JP2015204379A - Printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a rigid printed wiring board in which warpage of a resin insulating layer due to temperature rise is suppressed as much as possible when mounting an electronic component, while achieving the thinning of the printed wiring board.SOLUTION: On a first surface 11a of a resin insulating layer 11 having the first surface 11a and a second surface 11b on the opposite side of the first surface 11a, a first conductor layer 12 is embedded while exposing the one surface. On the second surface 11b of the resin insulating layer 11, a second conductor layer 14 is formed. A via conductor 15 connecting the first conductor layer 12 and the second conductor layer 14 is provided to penetrate the resin insulating layer 11. The resin insulating layer 11 is divided into a first resin insulating layer 111 and a second resin insulating layer 112, and a metal layer 113 is provided between the first resin insulating layer 111 and the second resin insulating layer 112. An opening 113a, through which the via conductor 15 penetrates, is formed in the metal layer 113.

Description

  The present invention relates to a printed wiring board on which electronic components are mounted and a method for manufacturing the same. More specifically, the present invention relates to a printed wiring board capable of suppressing warpage of the printed wiring board even when the printed wiring board is thinned in accordance with recent reductions in the size of electronic devices, and a method for manufacturing the printed wiring board.

  In recent years, printed circuit boards have been required to be thinner as electronic devices become lighter, thinner and shorter. Therefore, a coreless substrate is used for the resin insulation layer of the printed wiring board, and as shown in Patent Document 1, for example, a conductor layer on which a wiring pattern is formed is embedded in the resin insulation layer, and only one surface thereof is resin insulated. Structures that are exposed from the layer are known.

  Such a structure in which the conductor layer is embedded in the resin insulating layer is, for example, as shown in FIG. 4, in which a wiring 120a having a wiring pattern connected to an electronic component (not shown) is embedded in the resin insulating layer 110. Only the structure is exposed. In FIG. 4, reference numeral 140 denotes a conductor layer opposite to the resin insulating layer 110, 150 denotes a via conductor layer, and 160 denotes a solder resist layer.

Japanese Patent Laid-Open No. 10-173316

  As described above, in the printed wiring board on which the electronic component is mounted, as shown in FIG. 4, the area where the solder resist layer 160 is not formed is wide for mounting the electronic component (not shown), and the opposite surface is almost the entire surface. Since the solder resist layer 160 is provided on the surface, the amount of the solder resist layer 160 becomes non-uniform. Further, as described above, the wiring 120 is embedded in the resin insulating layer 110 from the viewpoint of the adhesion of the wiring to be thinned and extremely thinned. Since the solder resist layer is required to have a certain thickness or more from the surface of the conductor layer from the viewpoint of pressure resistance, on the side where the wiring 120a is embedded, the wiring on the opposite side is on the surface of the resin insulating layer 110. The solder resist layer 160 is thinner than the protruding side. Therefore, also from this point, the amount of the solder resist layer 160 decreases on the side where the wiring 120 is formed. Therefore, in addition to the decrease due to the area of the solder resist layer 160 due to the opening of the solder resist 160 where the electronic component is mounted, from the viewpoint of thickness, the amount of the solder resist layer 160 is the amount of the electronic component mounted. Less on the side. As a result, there is a problem that the thinned resin insulating layer 110 is likely to warp due to a rise in temperature.

  An object of the present invention is to provide a rigid printed wiring board in which warpage of a resin insulating layer due to a temperature rise when mounting an electronic component is suppressed as much as possible while achieving a thinner printed wiring board and a method for manufacturing the same. That is.

  The printed wiring board of the present invention is embedded in a resin insulating layer having a first surface and a second surface opposite to the first surface, and the first surface side of the resin insulating layer, and an uppermost surface is exposed. A first conductor layer, a second conductor layer formed on the second surface of the resin insulating layer, and provided through the resin insulating layer to connect the first conductor layer and the second conductor layer The printed wiring board includes a via conductor to be formed and a metal layer provided in the resin insulating layer, and an opening through which the via conductor penetrates is formed in the metal layer.

  The method for manufacturing a printed wiring board according to the present invention includes preparing a carrier with a carrier metal foil having a first metal foil on one surface of the carrier, and forming a first conductor layer having a predetermined pattern on the first metal foil. And a first resin insulation layer, a metal layer, a second resin insulation layer, and a second metal on the exposed surface of the first metal foil where the first conductor layer is not formed and on the first conductor layer. Laminating the foil so as to have an opening in a portion where the via conductor of the metal layer is formed, the second metal foil, the second resin insulating layer, the opening of the metal layer, and the first resin; Forming a conduction hole so as to penetrate the insulating layer and exposing the first conductor layer; forming a seed layer in the conduction hole and on the second metal foil; and Form a pattern of plating resist film on the layer Forming conductive vias and electroplated films by electroplating in the conductive holes and in the non-formed portions of the plated resist film pattern, removing the plated resist film, and removing the plated resist film Forming the second conductor layer having a predetermined pattern by removing the seed layer and the second metal foil which are exposed by being applied; and applying a solder resist on the second conductor layer; And exposing the first conductor layer by removing the carrier and the first metal foil.

  In this invention, since the metal layer is provided in the resin insulation layer of a printed wiring board, it is excellent in rigidity and can suppress the curvature of the printed wiring board by a temperature rise. On the other hand, the thickness of the metal layer is very thin, about 3 to 50 μm, and the thickness of the printed wiring board hardly causes an increase. As a result, it is possible to obtain a printed wiring board that is less likely to warp due to thermal expansion or the like while achieving a reduction in thickness.

Cross-sectional explanatory drawing of the printed wiring board of one Embodiment of this invention. Sectional explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Sectional explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Sectional explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Sectional explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Sectional explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Sectional explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Sectional explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Sectional explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Sectional explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Sectional explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Sectional explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Sectional explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Cross-sectional explanatory drawing of each process of the manufacturing method of the printed wiring board of other embodiment of this invention. Cross-sectional explanatory drawing of each process of the manufacturing method of the printed wiring board of other embodiment of this invention. Sectional explanatory drawing of the printed wiring board with which the conventional conductor layer was embedded.

  A printed wiring board according to an embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, the printed wiring board 1 of the present embodiment has a first surface 11a side of a resin insulating layer 11 having a first surface 11a and a second surface 11b opposite to the first surface 11a. A first conductor layer 12 whose surface is exposed is embedded. A second conductor layer 14 is formed on the second surface 11 b of the resin insulating layer 11. A via conductor 15 is provided through the resin insulating layer 11 to connect the first conductor layer 12 and the second conductor layer 14. A metal layer 113 is provided in the resin insulating layer 11. In the metal layer 113, an opening 113a through which the via conductor 15 passes is formed. Specifically, the resin insulation layer 11 is divided into a first resin insulation layer 111 and a second resin insulation layer 112, and a metal layer 113 is provided between the first resin insulation layer 111 and the second resin insulation layer 112. It has been.

  The resin insulating layer 11 is divided into a first resin insulating layer 111 and a second resin insulating layer 112, and a metal layer 113 is sandwiched therebetween. The first resin insulation layer 111 and the second resin insulation layer 112 are impregnated with a resin composition containing a filler in a core material (not shown) such as glass fiber, as used in the conventional resin insulation layer. It may be formed only with a resin composition containing a filler. However, the first resin insulating layer 111 and the second resin insulating layer 112 each have a film shape of about 15 to 50 μm, which is about half the conventional thickness. Each of the first resin insulating layer 111 and the second resin insulating layer 112 may be a single layer or may be formed of a plurality of insulating layers. If each of the first resin insulating layer 111 and the second resin insulating layer 112 is formed of a plurality of insulating layers, for example, the coefficient of thermal expansion, flexibility, and thickness can be easily adjusted. This material adjustment can also be performed between the first resin insulating layer 111 and the second resin insulating layer 112.

Examples of the resin insulating material include epoxy. Examples of the filler mixed with the resin include silica (SiO ₂ ), alumina (Al ₂ O ₃ ), titanium oxide (Ti ₂ O ₃ ), and the like. The total thickness of the first resin insulating layer 111, the second resin insulating layer 112, and the metal layer 113 is approximately the same as the thickness of one conventional resin insulating layer, and is exemplified by 25 to 100 μm. In the example shown in FIG. 1, the first surface 11a as the resin insulating layer 11 means the exposed surface (the surface opposite to the surface to be bonded) of the first resin insulating layer 111, and as described later, the first conductor One surface (upper surface) of each wiring 12a of the layer 12 is exposed. In the example shown in FIG. 1, the second surface of the resin insulating layer 11 means an exposed surface (a surface opposite to the surface to be bonded) of the second resin insulating layer 111, and will be described later on the second surface 11b. The second conductor layer 14 is formed on the exposed surface of the second surface 11b.

  As the metal layer 113, for example, a copper foil of about 3 to 5 μm is used. The material is not limited to copper foil, and foil such as nickel and titanium may be used. The thickness of the metal layer 113 is not limited to the aforementioned thickness. That is, about 3-50 micrometers is used. If it is too thin, rigidity cannot be obtained and resistance to bending cannot be obtained. On the other hand, if the thickness is too large, rigidity can be obtained, but it becomes impossible to reduce the thickness of the electronic component and increase the cost. Therefore, a particularly preferable thickness is about 5 to 30 μm.

  In the metal layer 113, an opening 113a is formed in advance at a place where the via conductor 15 is formed. After laminating the first resin insulation layer 111 and the metal layer 113, an opening may be formed by etching, and the second resin insulation layer 112 and the second metal foil 14a may be laminated. This is to prevent the via conductor 15 and the metal layer 113 that connect the first conductor layer 12 and the second conductor layer 14 described later from being in electrical contact. Therefore, the opening 113 a is formed with a larger hole than the via conductor 15 so as not to contact the via conductor 15. As described above, in principle, the opening 113a larger than the diameter of the via conductor 15 is formed in all the places where the via conductor 15 is formed.

  However, the via conductor 15 is not necessarily connected to a signal terminal or a power supply terminal, but may be connected to a ground (GND) terminal. If the via conductor is connected to such a ground terminal, the metal layer 113 and the via conductor 15 may be electrically connected to bring the metal layer 113 to the ground potential. By inserting the metal layer 113 having the ground potential into the resin insulating layer 11, there is an effect that noise can be blocked. Even in such a case, the opening 113a is formed in advance at the place where the via conductor 15 is formed. The via conductor 15 is formed to connect the first conductor layer 12 and the second conductor layer 14, and the conduction hole 11 d for forming the via conductor 15 includes the first resin insulating layer 111, the metal layer. It is necessary to be formed through the opening 113a of the 113 and the second resin insulating layer 112. As will be described later, this conduction hole 11d is processed by laser light. However, there is a difference in processing between the metal layer 113 and the resin layer, and the resin hole on the side opposite to the resin hole on the laser light irradiation side is different. This is because the size of the hole is too different. Therefore, it is preferable that a hole having a shape such that the metal layer 113 is exposed to the conduction hole 11d is formed in advance.

  As will be described later, the opening 113a of the metal layer 113 is formed by punching or the like in the form of a metal foil before being overlapped with the first and second resin insulation layers 111 and 112, and the first conductor layer. 12, the first resin insulating layer 111, the metal layer 113, the second resin insulating layer 112, and the second metal foil 14 a may be superposed and thermocompression bonded by a vacuum press. . In addition, the carrier 18 on which the first conductor layer 12 is formed, the first resin insulating layer 111 and the metal layer 113 having no opening are overlapped and thermocompression bonded by a vacuum press, and then the metal layer is patterned. An opening 113a may be formed in 113, and then the second resin insulating layer 112 and the second metal foil 14a may be further overlapped and thermocompression bonded by a vacuum press. An assembly of the first resin insulation layer 111, the metal layer 113, and the second resin insulation layer 112 formed by thermocompression bonding in this manner is described as the resin insulation layer 11 below.

  The first conductor layer 12 is a pattern embedded in the first surface 11a of the resin insulating layer 11 (exposed surface of the first resin insulating layer 111). The embedded first conductor layer 12 is exposed only on one surface (uppermost surface) of the wiring 12a and the other wiring 12b other than the wiring 12a to which the electronic component is connected substantially flush with the first surface 11a of the resin insulating layer 11. Yes. For this reason, the width of the wiring 12a is particularly narrow due to high density and fine pitch, and there is a risk of lowering the adhesion due to the use of the resin containing the core material as the resin insulating layer 11 becomes thinner. However, since the first conductor layer 12 is embedded in the resin insulating layer 11 in this way, it contributes to the improvement in the adhesion between the first conductor layer 12 and the resin insulating layer 11. On the other hand, as will be described later, when the first solder resist layer 16 and the second solder resist layer 17 that are not uniform are formed on the first surface 11a and the second surface 11b, the warp of the resin insulating layer 11 is caused. This is likely to occur, and there is a problem that a connection failure or the like is likely to occur when an electronic component (not shown) is mounted. However, as shown in FIG. 1, by embedding the metal layer 113 in the thin resin insulating layer 11, the rigidity of the resin insulating layer 11 is improved and such warpage is suppressed.

  The first conductor layer 12 may preferably be an electroplated film formed by electroplating. If the first conductor layer 12 is an electroplated film, there is an advantage that it is formed as a pure metal film. The material constituting the first conductor layer 12 is exemplified by copper. Copper is easy to electroplat, but has low resistance and is less likely to cause corrosion. As for the thickness of this 1st conductor layer 12, 3-20 micrometers is illustrated. The first conductor layer 12 includes a wiring 12a on which an electronic component is mounted and a wiring 12b other than that on which the electronic component is mounted. The electronic component is exposed from the opening 16a of the first solder resist layer 16. Since an electrode pad of an electronic component (not shown) is soldered to the exposed surface of the wiring 12a on which is mounted, surface treatment such as OSP, Ni / Au, Ni / Pd / Au, Sn is performed.

  The second conductor layer 14 is formed on the second surface 11 b of the resin insulating layer 11. Although the method of forming the 2nd conductor layer 14 is not specifically limited, For example, it forms by the electroplating method. The material constituting the second conductor layer 14 is exemplified by copper. As for the thickness of the 2nd conductor layer 14, 3-20 micrometers is illustrated. The second conductor layer 14 is shown as an example of one layer in FIG. 1, but may be formed of, for example, a metal foil and a plating film, as will be described later in the manufacturing method.

  The via conductor 15 penetrates through the resin insulating layer 11 including the metal layer 113 and electrically connects a part of the first conductor layer 12 and a part of the second conductor layer 14. The via conductor 15 is formed by filling a conductor in a conduction hole 11 d penetrating the second conductor layer 14 and the resin insulating layer 11. An example of the material of the via conductor 15 is copper, which is formed by electroplating, for example. Further, the cross-sectional shape of the via conductor 15 is not particularly limited. However, as shown in FIG. 1, the cross-sectional width of the via conductor 15 is smaller on the first conductor layer 12 side on which electronic components are mounted than on the second conductor layer 14 side. May be. This is because it is necessary to completely bury the via hole 15d in which the via conductor 15 is buried, and therefore it is preferable that the back side of the conduction hole 11d is small. The conduction hole 11d in which the via conductor 15 is formed can be formed in such a shape by being processed by laser light from the second conductor layer 14 side.

  As described above, an opening 113a larger than the diameter of the cross section of the via conductor 15 is previously formed in the metal layer 113 so that the metal layer 113 is not exposed in the conduction hole 11d in which the via conductor 15 is formed. In addition, the location where the via conductor 15 is formed and the opening 113a of the metal layer 113 are aligned. Therefore, the via conductor 15 and the metal layer 113 are electrically neutral without being in contact with each other.

  However, as described above, when the via conductor 15 is connected to the ground terminal, the via conductor 15 and the metal layer 113 may be electrically connected. In that case, the opening 113a formed in the metal layer 113 is formed so as to be exposed to the conduction hole 11d. The degree of exposure may be only exposed on the surface of the conduction hole 11d, or may be formed so as to protrude into the conduction hole 11d. Even in the small opening 113a of the metal layer 113 that slightly protrudes into the conduction hole 11d, since the conduction hole 11d is formed by the laser beam, the metal layer 113 is also melted. There is no hindrance. As a result, the via conductor 15 is formed in the conduction hole 11d by electroplating or the like, so that the via conductor 15 and the metal layer 113 are in electrical contact and become conductive. Since the metal layer connected to such a ground terminal is formed in the resin insulating layer 11, that is, below the first conductor layer 12 where the wiring pattern is formed, a circuit connected to the wiring pattern can be obtained. Even high-frequency circuits are less susceptible to noise and the like.

  On the other hand, even if the via conductor 15 is connected to the ground terminal, the via conductor 15 is not connected to the metal layer 113, and all the via conductors may not be connected to the metal layer 113. With such a structure, the metal layer 113 is a completely electrically neutral layer.

  The first solder resist layer 16 is on the first surface 11a side of the resin insulating layer 11, and the first surface 11a of the resin insulating layer 11 excluding the wiring pattern portion of the first conductor layer 12 to which the electrodes of the electronic component are connected. An opening 16a is formed so as to expose the electronic component of the first conductor layer 12 and the wiring 12a mounted thereon. Further, on the second surface 11b of the resin insulating layer 11, a second solder resist layer in which an opening 117a is formed so that the second conductor layer 14 exposes a wiring portion connected to another electronic component or a wiring board. 17 is provided. As described above, the second solder resist layer 17 is formed on the first surface 11a side as much as the second conductor layer 14 protrudes from the surface without being embedded in the resin insulating layer 11. It is formed thicker than the solder resist layer 16. The thickness of the first solder resist layer 16 on the first surface 11a side is about 10 to 20 μm, and the second solder resist layer 17 is about 20 to 30 μm. As a result, the sizes of the openings 16a and the openings 17a of the first and second solder resist layers 16 and 17 are different on the one surface 11a side and the second surface 11b side of the resin insulating layer 11, and the thicknesses are also different. . Therefore, bending stress acts on the resin insulating layer 11 based on the difference in coefficient of thermal expansion due to temperature change. However, according to this embodiment, since the metal layer 113 is inserted, such a problem does not occur.

  Next, an embodiment of a method for manufacturing the printed wiring board shown in FIG. 1 will be described with reference to FIGS.

  First, as shown in FIG. 2A, a carrier 18 provided with a first metal foil 13a is prepared. For example, a copper-clad support plate is used as the carrier 18, but the carrier 18 is not limited to this. In the example shown in FIG. 2A, a first metal foil with a carrier metal foil 18b in which, for example, a carrier metal foil 18b made of copper and a first metal foil 13a are attached to both surfaces of a support plate 18a made of prepreg, for example, with an adhesive. The carrier metal foil 18b side of 13a is attached to the support plate 18a by an adhesive or a thermocompression bonding method, so that the first metal foil 13a is attached to the support plate 18a and the carrier 18 made of, for example, the carrier metal foil 18b. Yes. The carrier 18 and the first metal foil 13a are removed and discarded later, and the material is not particularly limited. For example, copper, nickel or the like is used as the first metal foil 13a. Since the first metal foil 13a and the carrier metal foil 18b are separated later, the entire surface may be adhered by an easily separable adhesive such as a thermoplastic resin. By adhering with such an adhesive, the first metal foil 13a and the carrier 18 are easily separated by being peeled off by raising the temperature in a later step. Or, for example, it may be pasted only with a normal adhesive. This is because the surroundings are easily separated by cutting and removing. Since it is desirable that there is no difference in the coefficient of thermal expansion between the carrier 18 and the first metal foil 13a, if copper or nickel is used for the first metal foil 13a, the carrier metal foil is also carrier copper. The same material is preferred, such as consisting of foil or carrier nickel foil. In addition, a release layer may be appropriately provided on the surface of the carrier 18 on which the first metal foil 13a is provided.

  Moreover, in the example shown by FIG. 2A, the figure by which the 1st metal foil 13a with the carrier metal foil 18b was affixed on the both surfaces side of the support plate 18a is shown. Forming on both surfaces of the support plate 18a in this manner is preferable because the support plate 18a is removed and discarded, for effective use, and from the viewpoint of shortening the manufacturing process. However, it may be formed only on one side. Since the laminated body formed on both surfaces of the support plate 18a is formed in exactly the same process on both surfaces, the following description will be made with a structure having only one surface. The explanation of the following figures is also omitted in part, but the structures on both sides are exactly the same.

  Furthermore, in the example shown in FIG. 2A, an example is shown in which the first metal foil 13a is simply attached to the surface of the carrier metal foil 18b. However, the surface of the first metal foil 13a is further nickel-plated. May be given. By applying nickel plating, the first conductor layer 12 is formed on the surface in a later step, and finally the first metal foil 13a is removed by etching. Etching removal is facilitated by using a material different from copper as the material of the layer 12.

  Next, as shown in FIG. 2B, after the resist is formed on the entire surface, the resist is removed only at the portion where the wiring pattern of the first conductor layer 12 is formed by exposure and development photolithography techniques. Thus, a pattern of the resist mask 19 is formed.

  Thereafter, as shown in FIG. 2C, for example, the first metal foil 13a is used as one electrode, and is immersed in, for example, an electroplating solution of copper plating, and is energized between the other electrode in the electroplating solution. Thus, the electroplating film is formed only where the first metal foil 13a is exposed, and the patterned first conductor layer 12 is formed. On the first conductor layer 12, a wiring 12 a to which an electronic component (not shown) is mounted and connected, and the other wiring 12 b are patterned by the pattern of the resist mask 19.

  Thereafter, as shown in FIG. 2D, by removing the resist mask 19, only the wiring patterns 12a and 12b of the first conductor layer 12 are formed on the surface of the first metal foil 13a.

  Next, as shown in FIG. 2E, the first resin insulation layer 111 and the metal layer (foil) 113 are superimposed on the surface side of the first metal foil 13a on which the first conductor layer 12 is formed, and by vacuum press. They are laminated by thermocompression bonding. This metal layer 113 is a flat foil in which no opening is formed.

  Thereafter, as shown in FIG. 2F, an opening 113 a is formed at the position of the via conductor 15 in the metal layer 113. The opening 113a is formed by a method using a normal photolithography technique. A resist film (not shown) is formed, and is formed by etching using a resist film formed by exposure and development as a mask.

  Thereafter, as shown in FIG. 2G, the second metal foil 14a that becomes a part of the second resin insulating layer 112 and the second conductor layer 14 is superimposed on the metal layer 113 in which the opening 113a is formed, Bonding is again performed by a thermocompression bonding method using a vacuum press. As a result, as shown in FIG. 2G, a stacked structure in which the first resin insulating layer 111 and the second resin insulating layer 112 sandwich the metal layer 113 therebetween is formed.

Next, as shown in FIG. 2H, a conduction hole 11d is formed. As a method for forming the conduction hole 11d, a method is used in which the surface of the second metal foil 14a where the conduction hole 11 is formed is blackened and irradiated with laser light. That is, it is formed in a portion where the first conductor layer 12 and the second conductor layer 14 provided on both surfaces of the resin insulating layer 11 are connected, and the surface of the second metal foil 14a is irradiated with CO ₂ laser light or the like. It is processed by. At this time, the position of the opening 113a of the metal layer 113 may be specified by X-rays or the like, and the conduction hole 11d may be formed in accordance with the position of the opening.

  In the case of the conduction hole 11d in which the via conductor 15 connected to the metal layer 113 is formed, and the metal layer 113 is not exposed in the conduction hole 11d, the intensity of the laser beam is increased. The metal layer 113 is exposed. That is, by adjusting the intensity of the laser beam, exposure and non-exposure of the metal layer 113 to the conduction hole 11d are controlled.

  Next, as shown in FIG. 2I, a seed layer (metal coating) 14c such as an electroless plating film is formed in the conduction hole 11d and on the second metal foil 14a. The metal coating 14c may be formed not by electroless plating but by vacuum deposition or sputtering. This is because the metal film is provided even in a place where the metal film is not exposed on the surface as in the conduction hole 11d, and is used as a base for electroplating. Then, a pattern of the plating resist film 20 is formed on a metal film (hereinafter simply referred to as a metal film) 14c serving as a seed layer with the second metal foil 14a. Similarly to the description of FIG. 2B, the patterning of the plating resist film 20 is a portion where the pattern of the second conductor layer 14 is formed by exposure and development photolithography techniques after the resist is formed on the entire surface. By removing only the resist, the pattern of the plating resist film 20 is formed.

  Subsequently, as shown in FIG. 2J, the via conductor 15 is formed in the conduction hole 11d by, for example, electroplating, and the layer of the electroplating film 14b is formed on the exposed surface of the metal coating 14c. The Thereafter, the plating resist film 20 is removed, whereby the second conductor layer 14 patterned by the second metal foil 14a, the metal coating 14c, and the electroplating film 14b is formed.

  Next, as shown in FIG. 2K, the solder resist is applied and formed on the entire surface, and only the connection portion is removed by the same photolithography technique as described above, whereby the patterned second solder resist layer 17 is formed. It is formed.

  Thereafter, as shown in FIG. 2L, the carrier 18 is removed, and the first metal foil 13a is removed by etching. In addition, when the carrier 18 is removed in the state of FIG. 2K, two stacked bodies are obtained, but the upper and lower layers of FIG. 2K on the other hand are shown upside down. As described above, the carrier 18 (carrier metal foil 18b) and the first metal foil 13a are fixed by an adhesive that easily peels off, such as a thermoplastic resin, or an adhesive or the like only at the periphery. The contact surface of the first metal foil 13a with the carrier metal foil 18b can be easily separated by raising the temperature or by peeling off the surrounding adhesive portion. Is exposed. The first metal foil 13a is removed by, for example, wet or dry chemical etching. As a result, only one surface of the first conductor layer 12 made of an electroplated film embedded on the first surface 11a side in the resin insulating layer 11 is exposed.

  Thereafter, a solder resist is applied to the entire surface of the resin insulating layer 11 exposed by removing the first metal foil 13a, that is, the first surface 11a of the resin insulating layer 11 and the surface of the first conductor layer 12, and in the same manner as described above. The first solder resist film 16 having the opening 16a is formed by patterning so that the wiring 12a on which the electronic component is mounted is exposed. This state is shown in FIG.

  Although not shown, the exposed surface of each wiring 12a to which the electrode pads of electronic parts (not shown) of the first conductor layer 12 are connected is made of OSP, Ni / Au, Ni / Pd / Au, Sn, etc. Surface treatment is performed. This is to protect the surface and facilitate soldering.

  In the above example, after the first resin insulating layer 111 and the metal layer 113 are laminated, the opening 113a is formed in accordance with the position of the via conductor 15 of the metal layer 113, and the second resin insulating layer 112 and the like. The first resin insulating layer 111, the second resin insulating layer 112, and the second metal foil 13a may be stacked at once by forming the opening 113a in the metal layer 113 in advance. it can. An example is shown in FIGS.

  That is, it is formed in the same manner up to the step of forming the first conductor layer 12 on the carrier 18 described above. Therefore, the same view as FIG. 2D is shown as FIG. 3A.

  Thereafter, as shown in FIG. 3B, the first resin insulating layer 111, the metal layer (foil) 113, the second resin insulating layer 112, and the first resin insulating layer 112 are formed on the surface side of the first metal foil 13a on which the first conductor layer 12 is formed. The second metal foil 14a that becomes a part of the second conductor layer 14 is superposed in this order. In the metal layer 113, an opening 113a is formed with a diameter larger than the diameter of the via conductor 15 by a method such as punching in accordance with a location where the via conductor 15 is formed in advance. For this reason, the metal layer 113 is accurately positioned and overlapped so that the opening 113a of the metal layer 113 coincides with the formation position of the via conductor. Thereafter, they are laminated by being bonded by a thermocompression method using a vacuum press. This state is the same structure as that shown in FIG. 2G. Accordingly, in the subsequent steps, the printed wiring board 1 having the structure shown in FIG. 1 is obtained by performing the steps of FIGS. 2H to 2L in the same manner.

  According to this method, the first resin insulating layer 111, the metal layer 113, the second resin insulating layer 112, and the first resin insulating layer 111 are formed in the state in which the opening 113 a is accurately aligned in advance in the metal layer 113. Since the two metal foils 13a can be stacked and formed by thermocompression using a vacuum press at a time, the manufacturing process is greatly improved, which contributes to cost reduction.

  In the above embodiment, the printed wiring board in which a pair of conductor layers (the first conductor layer 12 and the second conductor layer 14) is formed via one resin insulating layer is exemplified. However, for example, until the state shown in FIG. 2J, a resin insulating layer 11 containing a metal layer 113 is formed on the exposed surfaces of the second conductor layer 14 and the resin insulating layer 11 as shown in FIG. A resin insulating layer of a normal prepreg that is not contained in the metal layer 113 may be laminated, and the same process may be repeated. By doing so, a printed wiring board having a three-layer structure with further improved rigidity can be obtained.

DESCRIPTION OF SYMBOLS 1 Printed wiring board 11 Resin insulation layer 11a 1st surface 11b 2nd surface 11d Conduction hole 111 1st resin insulation layer 112 2nd resin insulation layer 113 Metal layer 113a Opening part 12 1st conductor layer 12a An electronic component is mounted Wiring 12b Wiring other than mounting electronic components 13a First metal foil 14 Second conductor layer 14a Second metal foil 14b Electroplating film 14c Seed layer (metal coating)
DESCRIPTION OF SYMBOLS 15 Via conductor 16 1st soldering resist layer 16a Opening part 17 2nd soldering resist layer 17a Opening part 18 Carrier 19 Resist mask 20 Plating resist film

Claims (12)

A resin insulation layer having a first surface and a second surface opposite to the first surface;
A first conductor layer embedded on the first surface side of the resin insulating layer and exposing an uppermost surface;
A second conductor layer formed on the second surface of the resin insulation layer;
A via conductor provided through the resin insulation layer and connecting the first conductor layer and the second conductor layer;
A printed wiring board comprising:
A metal layer is provided in the resin insulating layer, and an opening through which the via conductor passes is formed in the metal layer. 2. The printed wiring board according to claim 1, wherein the resin insulating layer includes a first resin insulating layer and a second resin insulating layer, and the metal layer includes the first resin insulating layer and the second resin insulating layer. It is provided between the resin insulation layers. 3. The printed wiring board according to claim 1, wherein an opening portion of the metal layer is formed so that a via conductor electrically connected to a signal terminal of the via conductor does not contact the metal layer. Has been. It is a printed wiring board of any one of Claims 1-3, Comprising: The opening part of the said metal layer is formed so that all the said via conductors may not contact the said metal layer. The printed wiring board according to any one of claims 1 to 3, wherein, among the via conductors, the via conductor electrically connected to a ground terminal and the metal layer are connected. An opening of the metal layer is formed. It is a printed wiring board of any one of Claims 1-5, Comprising: The said metal layer is a copper foil with a thickness of 3-50 micrometers. 7. The printed wiring board according to claim 1, wherein a width of a cross-section of the via conductor is smaller on the first conductor layer side on which an electronic component is mounted than on the second conductor layer side. . A method of manufacturing a printed wiring board,
Preparing a carrier with a metal foil having a first metal foil on one side of the carrier;
Forming a first conductor layer having a predetermined pattern on the first metal foil;
On the exposed surface of the first metal foil where the first conductor layer is not formed and the first conductor layer, the first resin insulating layer, the metal layer, the second resin insulating layer, and the second metal foil, Laminating so as to have an opening in a portion through which the via conductor of the metal layer passes,
Passing through the second metal foil, the second resin insulation layer, the opening of the metal layer and the first resin insulation layer, and forming a conduction hole so that the first conductor layer is exposed;
Forming a seed layer in the conduction hole and on the second metal foil;
Forming a plating resist film pattern on the seed layer;
Forming conductive vias and electroplated films by electroplating in the hole for conduction and in the non-formation part of the pattern of the plating resist film;
Removing the plating resist film;
Forming the second conductor layer having a predetermined pattern by removing the seed layer and the second metal foil exposed by removing the plating resist film;
Applying a solder resist on the second conductor layer;
Removing the carrier and the first metal foil to expose the first conductor layer;
have. The method of manufacturing a printed wiring board according to claim 8, wherein the first resin insulating layer, the metal layer, the second resin insulating layer, and the second metal foil are laminated.
Laminating and bonding the first resin insulation layer and the metal layer;
Forming an opening in a portion of the metal layer through which the via conductor passes;
Laminating the second resin insulation layer and the second metal foil on the surface of the metal layer;
have. The method of manufacturing a printed wiring board according to claim 8, wherein the first resin insulating layer, the metal layer, the second resin insulating layer, and the second metal foil are laminated.
Forming an opening in advance in the portion of the metal layer through which the via conductor passes;
The first resin insulation layer, the metal layer, the second resin insulation layer, and the second metal foil;
have. It is a manufacturing method of the printed wiring board given in any 1 paragraph of Claims 8-10, and formation of the hole for conduction is performed by irradiation of a laser beam, and the intensity of the laser beam is adjusted, Exposure and non-exposure of the metal layer to the conduction hole are controlled. It is a manufacturing method of the printed wiring board of any one of Claims 8-11, Comprising: The position of the opening part of the said metal layer is specified by X-ray | X_line, The said hole for conduction | electrical_connection according to the position of this opening part Is formed.

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