JP2002305377A - Multilayer printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board which uses a laminated substrate of high external connection reliability, with no standing wave or reflection occurring at a through hole. SOLUTION: A through hole 66 of coaxial structure is used to prevent occurrence of standing wave and reflection, for a raised electric characteristics. A field via 160 is formed directly above the coaxial through hole 66, to shorten a wiring length and improve a high-frequency performance. Since a solder bump 76U is arranged on a flat field via, no void remains inside the solder bump, resulting in a higher reliability of the solder bump.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board in which the front and back sides are electrically connected to a laminated substrate of a core substrate and a resin layer via through holes, and more particularly, to a multilayer printed wiring board comprising a resin insulating layer and a conductive circuit layer. The present invention relates to a multilayer printed wiring board which is formed by building up alternately and can be suitably used for a package substrate on which electronic components such as IC chips are mounted.

[0002]

2. Description of the Related Art As the frequency of a signal is increased, the material of a printed wiring board is required to have a low dielectric constant and a low dielectric loss tangent. Therefore, the mainstream of printed wiring board materials is shifting from ceramics to resins.

A multilayer printed wiring board made of resin constituting such a package substrate is constituted by alternately laminating a wiring layer and an interlayer resin insulating layer on a core substrate, and an upper layer is formed by a through hole formed in the core substrate. Make a connection between the side and the lower side. The core substrate has a thickness of about 1 mm, and the interlayer resin insulating layer is formed to have a thickness of several tens of μm.

[0004] With the increase in the frequency of IC chips, package boards are required to reduce standing waves and reflections on signal lines. For this reason, in the case of a multilayer printed wiring board made of resin, as in the case of a ceramic laminated package substrate, the wiring between layers is made to have a microstrip line structure and a strip line structure so that electrical characteristics such as wiring impedance are matched. are doing.

On the other hand, since the above-mentioned strip line structure cannot be formed by a through hole penetrating a core substrate having a thickness of 1 mm instead of wiring, a standing wave or reflection is generated, and the operation tends to be unstable. In particular, in order to increase the degree of integration of a multilayer printed wiring board, if a configuration is adopted in which a wiring layer and an interlayer resin insulating layer are alternately laminated on a laminated substrate having resin layers provided on both sides of a core substrate, through-holes provided on the laminated substrate Since the length of the hole is longer by the thickness of the resin layer, standing waves and reflections are more likely to occur.

[0006]

For this reason, the present inventor has devised that the through hole provided in the laminated substrate is a through hole having a coaxial structure including an outer layer through hole and an inner layer through hole. The coaxial through-hole is
An outer layer through hole formed on the wall surface of the through hole of the laminated substrate;
It comprises an inner layer through hole formed by applying an outer layer resin filler in the outer layer through hole, a cover plating layer formed by plating just above the inner layer through hole, and an inner layer resin filler filled in the inner layer through hole. Then, a configuration was considered in which a via hole was provided immediately above the lid plating layer, and an external terminal connection portion such as a solder bump was provided in the via hole to reduce the wiring length.

However, when a via hole is provided on a through hole having a coaxial structure, stress tends to concentrate on the via hole due to thermal shrinkage of a substrate, and the connection reliability of solder bumps when a heat cycle is applied is low. Is expected. That is, since the core substrate has a low coefficient of thermal expansion, a large stress is not applied to the via holes arranged on the core substrate. On the other hand, the via hole on the coaxial through-hole is disposed on the resin filler filled in the inner layer through-hole via the cover plating film, and the coefficient of thermal expansion of the resin filler is larger than that of the core substrate. Stress is caused by the difference in thermal expansion between the filler and the core substrate. Here, it is considered that the stress causes an inward moment in the concave via hole, and the solder bump is peeled off.

In the via hole, when a solder bump is formed of a low melting point metal not containing Pb, there is a concern that a void may be involved in the manufacturing stage, peel off, and cracks may occur. That is, the solder is an alloy composed of Sn / Pb, and Pb contained in the solder adversely affects the environment. Therefore, it is required to use a low-melting metal that does not contain Pb. When a bump is formed using a low-melting-point metal that does not contain Pb, voids are generated in the concave portion of the via hole and in the vicinity of the concave portion when the low-melting point metal paste is filled in the opening of the via hole. Thereafter, even if reflow is performed, voids in the gaps between the via holes remain because the viscosity of the low melting point metal is high. The voids remaining in the via holes diffuse or expand due to heat generated during the operation of the IC chip. Due to the diffusion or expansion of the voids, the bumps or the conductive pads of the low melting point metal may be peeled off and cracks may occur to cause a failure. Therefore, when a bump is formed on a via hole using a low-melting-point metal that does not contain Pb, the reliability of connection with an IC chip is expected to be reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to prevent standing waves and reflection from being generated in a through hole and to improve the reliability of external connection. It is to propose a multilayer printed wiring board using a high laminated substrate.

[0010]

In order to solve the above-mentioned problems, a first aspect of the present invention is to provide an interlayer insulating layer and a conductive circuit on both sides of a laminated substrate having a resin layer disposed on a core substrate on which a conductive circuit is formed. In a multilayer printed wiring board, a coaxial through hole formed of an outer layer through hole formed on a wall surface of a through hole of the laminated substrate and an inner layer through hole formed by applying an outer layer resin filler in the outer layer through hole. A technical feature is that a hole is provided, and a filled via is arranged immediately above at least a part of the inner layer through hole.

According to the first aspect of the present invention, since the coaxial through-hole is provided, standing waves and reflection do not occur in the through-hole, and the electrical characteristics of the multilayer printed wiring board can be improved. Also, a filled via is formed on the inner layer through hole. That is, since the via hole can be formed directly above the through hole, the wiring length can be reduced, and the high frequency performance can be improved. Furthermore, since the solder bump is provided on the flat filled via, no void remains inside the solder bump, and the reliability of the solder bump can be improved. Further, electric characteristics can be improved.

A second aspect of the present invention is a multilayer printed wiring board in which an interlayer insulating layer and a conductor circuit are laminated on both sides of a laminate substrate in which a resin layer is disposed on a core substrate on which a conductor circuit is formed. An outer layer through hole formed on the wall surface of the through hole, an inner layer through hole formed by applying an outer layer resin filler in the outer layer through hole, a lid plating layer formed by plating directly on the inner layer through hole, It is a technical feature that a coaxial through-hole made of an inner resin filler filled in the inner through hole is provided, and a filled via is disposed immediately above at least a part of the cover plating layer.

According to the second aspect of the present invention, since the coaxial through-hole is provided, standing waves and reflection do not occur in the through-hole, and the electrical characteristics of the multilayer printed wiring board can be improved. Further, a lid plating layer is formed on the inner through hole, and a via hole is formed on the lid plating layer. That is, by providing a conductive lid plating layer on the inner through hole, a via hole can be formed immediately above the through hole, so that the wiring length can be reduced and the high frequency performance can be improved. Further, the filled via is disposed on the inner layer resin filler filled in the inner layer through hole via the lid plating layer, and even if stressed due to a difference in thermal expansion, the inside is filled with metal and can withstand the stress. Because of the strength, peeling of the solder bump does not occur. Furthermore, since the solder bump is provided on the flat filled via, no void remains inside the solder bump, and the reliability of the solder bump can be improved.
Further, electric characteristics can be improved. Further, since the substrate serving as the core is multilayered, the degree of freedom of wiring can be increased, and the number of interlayer resin insulating layers can be reduced.

A third aspect of the present invention is a multilayer printed wiring board in which an interlayer insulating layer and a conductive circuit are laminated on both sides of a laminated substrate in which a resin layer is disposed on a core substrate on which a conductive circuit is formed. Coaxial through-hole consisting of an outer layer through-hole formed on the wall surface of the through-hole of the laminated substrate, an inner layer through-hole formed by applying an outer layer resin filler in the outer layer through-hole, and a single shaft having no inner layer through-hole A technology is described in which a through hole is formed, a coaxial through hole is mainly disposed at a central portion of the laminated substrate, a uniaxial through hole is mainly disposed at an outer peripheral portion, and a filled via is disposed immediately above at least a part of the cover plating layer. Characteristic.

According to the third aspect of the present invention, since the coaxial through-hole is provided, standing waves and reflection do not occur in the through-hole, and the electrical characteristics of the multilayer printed wiring board can be improved. Further, a lid plating layer is formed on the inner through hole, and a via hole is formed on the lid plating layer. That is, by providing a conductive lid plating layer on the inner through hole, a via hole can be formed immediately above the through hole, so that the wiring length can be reduced and the high frequency performance can be improved. Further, the filled via is disposed on the inner layer resin filler filled in the inner layer through hole via the lid plating layer, and even if stressed due to a difference in thermal expansion, the inside is filled with metal and can withstand the stress. Because of the strength, peeling of the solder bump does not occur. Furthermore, since the solder bump is provided on the flat filled via, no void remains inside the solder bump, and the reliability of the solder bump can be improved.
Further, electric characteristics can be improved. On the other hand, since the coaxial through-holes are mainly arranged at the center of the core substrate and the uniaxial through-holes are mainly arranged at the outer periphery, the number of coaxial through-holes having low reliability and high manufacturing cost is achieved while achieving the required electric performance. , The reliability can be improved, and the device can be manufactured at low cost.

According to a fourth aspect of the present invention, in the filled via, a conductive resin is filled in the inside of the via hole, and preferably, a conductive lid is provided on an upper portion. For this reason, the upper portion of the filled via can be completely flat, and the solder bump is disposed on the completely flat filled via, so that no void remains inside the solder bump and the reliability of the solder bump is improved. Can be. Further, electric characteristics can be improved.

The conductive resin may be gold,
Use a conductive paste containing metal particles such as silver or copper, or a resin impregnated with metal particles and having no conductivity in the resin itself, for example, a thermosetting resin, a thermoplastic resin, or a photosensitive resin. Can be. In addition, a resin having conductivity can be used.

According to the fifth aspect, since filled vias are stacked and disposed directly above the coaxial through-holes, and wiring is not routed in a direction parallel to the printed wiring board, standing waves and reflections do not occur in the through-holes and the filled vias. The electrical characteristics of the multilayer printed wiring board can be improved.

According to the present invention, a filled via penetrating through a plurality of interlayer insulating layers is disposed immediately above the coaxial through hole, and the wiring is not routed in a direction parallel to the printed wiring board. The electrical characteristics of the multilayer printed wiring board can be improved without causing reflection or reflection. Further, the coaxial through-hole is connected to an external terminal such as a solder bump with one filled via, and there is no connection at the via holes of the plurality of interlayer resin insulating layers, so that no reflection occurs at the connection part.

In the present invention, the outer layer through-hole and the inner layer through-hole are formed by using a drill. That is, by using a drill, the through hole is prevented from being tapered, and the thickness of the outer resin filler forming the insulating layer between the outer through hole and the inner through hole can be made uniform. Therefore, a short circuit between the outer layer through-hole and the inner layer through-hole can be prevented, and the reliability is improved.

According to the eighth aspect of the present invention, the resin filler filled in the outer layer through-hole and the inner layer through-hole contains one or more inorganic particles.
0 to 80 vlo% is blended. By setting the blending amount of the inorganic particles to 10 vol% or more, the thermal expansion coefficient of the resin filler, the thermal expansion coefficient of the resin substrate forming the core substrate, and the thermal expansion coefficient of the resin film as the interlayer resin insulating layer And no stress is generated due to the difference in heat shrinkage even under the heat cycle condition. Therefore, it is possible to prevent the occurrence of cracks in the conductor portion near the boundary between the resin substrate and the resin film, and to improve electrical connectivity and reliability. The resin film constituting the interlayer resin insulation layer contains soluble particles that form a roughened surface by a roughening treatment.
By setting it to l% or less, it is possible to match the coefficient of thermal expansion.

In the ninth aspect, the low-melting point metal forming the solder bump on the filled via is Sn / Ag, Sn / Ag /
It is an alloy composed of Cu and Sn / Sb. That is, since it does not contain Pb, it does not adversely affect the environment. And Pb
When filling a via hole with a low-viscosity paste of a low melting point metal that does not contain slag, the formation of voids can be prevented by using a filled via having no concave portion, and the reliability of the solder bump can be improved.

In the present invention, when forming a filled via (a via hole in which the via hole opening is completely filled with metal and the upper surface of the via hole and the upper surface of the conductor circuit in the same layer are substantially in the same plane), By using an electrolytic plating solution containing a specific leveling agent and an additive consisting of a brightening agent at a specific ratio, the opening for the via hole is completely filled with metal. As a result, the upper surface of the via hole and the upper surface of the conductor circuit in the same layer are made substantially the same plane.

That is, the electrolytic plating solution of the present invention is an electrolytic plating solution used for manufacturing a multilayer printed wiring board in which a resin insulating layer and a conductor circuit are sequentially laminated on a substrate provided with a conductor circuit, 50-300 g / l copper sulfate, 30-2
00 g / l sulfuric acid, 25 to 90 mg / l chloride ions,
And 1 comprising at least a leveling agent and a brightening agent
It is characterized by containing up to 1000 mg / l of additives.

It is desirable to use at least one selected from the group consisting of polyethylene, derivatives thereof, gelatin and derivatives thereof as the leveling agent.
It is desirable to use at least one selected from the group consisting of hydrogen sulfide, its related compounds, and other sulfur compounds.

In the above electrolytic plating solution, if the concentration of copper sulfate is less than 50 g / l, a filled via cannot be formed,
If it exceeds 00 g / l, the variation in plating film thickness will be large. On the other hand, when the concentration of sulfuric acid is less than 30 g / l, the liquid resistance becomes large, so that the plating is difficult to be deposited.
If it exceeds 0 g / l, copper sulfate tends to be crystallized. If the chlorine ion concentration is less than 25 mg / l, the gloss of the plating film is reduced, and if it exceeds 90 mg / l, the anode is difficult to dissolve.

By using an electrolytic plating solution having such a composition, a filled via can be formed regardless of the opening diameter of the via hole, the material and thickness of the resin insulating layer, the presence or absence of the roughened surface of the resin insulating layer, and the like. Can be.

Further, when the above-mentioned electrolytic plating solution is used in producing a multilayer printed wiring board, since the electrolytic plating solution contains a high concentration of copper ions, the copper ions enter the via hole openings. Sufficiently supplied, the via hole opening can be plated at a plating speed of 40 to 100 μm / hour, and the speed of the electrolytic plating step can be increased.

Further, since the electrolytic plating solution contains sulfuric acid at a high concentration, the solution resistance during plating can be reduced. Therefore, the current density is increased, and the growth of the plated film in the via hole opening is not hindered, which is suitable for forming a filled via structure.

The desirable composition of the electrolytic plating solution is 10
0-250 g / l of copper sulfate, 50-150 g / l of sulfuric acid, 30-70 mg / l of chloride ion, and 1-600 mg / l of at least a leveling agent and a brightening agent
This is a composition containing 1 additive.

The above additives only need to be composed of at least a leveling agent and a brightening agent, and may contain other components.

As the leveling agent, for example, it is desirable to use at least one selected from the group consisting of polyethylene, derivatives thereof, gelatin and derivatives thereof.

The polyethylene derivative is not particularly limited, and examples thereof include polyethylene isophthalate, polyethylene imine, polyethylene oxide, polyethylene glycol, polyethylene glycol ester, polyethylene glycol ether, polyethylene sulfide, and polyether. Among these, it is desirable to use polyethylene glycol or gelatin. This is because the versatility is high and there is no damage to the resin insulating layer and the metal film.

As the brightener, it is desirable to use, for example, at least one selected from the group consisting of sulfur oxides, its related compounds, hydrogen sulfide, its related compounds, and other sulfur compounds.

The above-mentioned sulfur oxide and its related compounds are not particularly restricted but include, for example, sulfonic acid compounds, sulfone compounds, sulfite compounds and other sulfur oxide compounds.

The sulfonic acid compound is not particularly restricted but includes, for example, sulfobenzoic acid, sulfobenzoate,
Sulfoanthraquinone, sulfomethane, sulfoethane,
Sulfocarbamide, sulfosuccinic acid, sulfosuccinate, sulfoacetic acid, sulfosalicylic acid, sulfocyanuric acid, sulfocyanic acid, sulfocyanic acid ester, sulfonine, sulfovinic acid, sulfophthalic acid, sulfonamide, sulfonimide, etc., and sulfocarbanilide etc. And the like.

The sulfone compound is not particularly restricted but includes, for example, sulfonal, sulfonyldiacetate, sulfonyldiphenylmethane, sulfoxylic acid, sulfoxylate, sulfonamide, sulfonimide and the like;
Sulfonyl chloride compounds and the like can be mentioned.

The sulfite compound is not particularly limited, and examples thereof include sulfurous acid, ammonium sulfite, potassium sulfite, diethyl sulfite, dimethyl sulfite, sodium hydrogen sulfite, and sulfite compounds.

The above other sulfur oxide compounds are not particularly restricted but include, for example, sulfoxide.

The hydrogen sulfide and its related compounds are not particularly restricted but include, for example, sulfonium compounds and
Sulfonium salts and the like can be mentioned. The other sulfur compound is not particularly limited, and examples thereof include bisdisulfide.

When the electrolytic plating solution of the present invention further contains the above-mentioned brightening agent, the via hole opening can be completely filled with metal when manufacturing a multilayer printed wiring board, and the above-mentioned leveling agent By containing
The upper surface of the via hole and the upper surface of the conductor circuit in the same layer can be formed on substantially the same plane.

This is because the brightener activates a low current portion of the via hole opening, thereby accelerating plating deposition on the via hole opening, and adsorbing the leveling agent on the surface of the conductor circuit. This suppresses the deposition of plating on the surface of the conductor circuit.

The amount of the leveling agent is from 1 to 100.
0 mg / l is desirable, and the blending amount of the brightener is 0.1
-100 mg / l is desirable. The mixing ratio of the two is preferably 2: 1 to 10: 1.

If the amount of the leveling agent is too small, the amount of the leveling agent adsorbed on the surface of the conductor circuit is small,
Plating deposition on conductor circuits becomes faster. On the other hand, if the amount of the leveling agent is too large, the amount of the leveling agent adsorbed on the bottom of the via hole opening is large, and the deposition of plating on the via hole opening becomes slow.

On the other hand, if the amount of the brightener is too small, the bottom of the via hole opening cannot be activated, and the via hole opening cannot be completely filled with metal by plating. On the other hand, if the amount is too large, the deposition of the plating on the conductor circuit portion is accelerated, and a step occurs between the upper surface of the conductor circuit and the upper surface of the via hole.

The electrolytic plating method using the electrolytic plating solution having such a configuration is not particularly limited, and the following electrolytic plating method and the like can be used. That is, a DC electrolytic plating method (DC plating method), which is a general electrolytic plating method, or a method of controlling a current to a rectangular wave pulse current by alternately repeating supply and interruption of a cathode current (PC plating method). A pulse-reverse electroplating method (PR plating method) in which the supply of the cathode current and the supply of the anode current are alternately inverted and repeated to control the current using a periodic reversal wave; A method of alternately applying a pulse and a low-density current pulse can be used. Among them, the DC electrolytic plating method is preferable because it is suitable for forming a filled via when manufacturing a multilayer printed wiring board and does not require an expensive power supply device or control device.

As the resin constituting the resin composition for filling through holes of the present invention, a thermosetting resin or a thermoplastic resin can be used. As the thermosetting resin, at least one resin selected from an epoxy resin, a polyimide resin, and a phenol resin is preferable. As the thermoplastic resin, polytetrafluoroethylene (PTFE), tetrafluoroethylene hexafluoropropylene copolymer (FEP),
Polytetrafluoroethylene perfluoroalkoxy copolymer (PF
A) and other fluororesins, polyethylene terephthalate (P
ET), polysulfone (PSF), polyphenylene sulfide (PPS), thermoplastic polyphenylene ether (PPE), polyether sulfone (PES), polyetherimide (PEI), polyphenylene sulfone (PPES), polyethylene naphthalate (PEN) ,
At least one selected from polyetheretherketone (PEEK) and polyolefin-based resins is preferred.

In particular, as the optimum resin used for filling the through holes, at least one selected from bisphenol type epoxy resin and novolak type epoxy resin is preferable. The reason is that the viscosity of the bisphenol type epoxy resin can be adjusted without using a diluting solvent by appropriately selecting a resin such as A type or F type,
Also, the novolak type epoxy resin is high in strength, excellent in heat resistance and chemical resistance, and does not decompose and does not thermally decompose even in a strongly basic solution such as an electroless plating solution. As the bisphenol type epoxy resin, bisphenol A
It is desirable to use at least one selected from a type epoxy resin and a bisphenol F type epoxy resin. Among them, bisphenol F type epoxy resin is advantageous because it can be used with low viscosity and without solvent.
As the novolak type epoxy resin, it is desirable to use at least one selected from a phenol novolak type epoxy resin and a cresol novolak type epoxy resin. When a novolak type epoxy resin and a bisphenol type epoxy resin are blended and used in such a resin, the blending ratio is 1/1 to 1/1 by weight.
100 is preferred. The reason for this is that a remarkable increase in viscosity can be suppressed. The amount of the inorganic particles contained is preferably 10 to 80 vol%. More desirable is 20 to 70 vol%. It is preferable that at least one of an aluminum compound, a calcium compound, a potassium compound, a magnesium compound, and a silicon compound is blended in the contained inorganic particles.
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate, calcium hydroxide, and the like. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.
Examples of the silicon compound include silica and zeolite.

As the curing agent used in such a resin composition, an imidazole curing agent, an acid anhydride curing agent, and an amine curing agent are desirable. This is because curing shrinkage is small. By suppressing the curing shrinkage, the filler can be integrated with the conductor layer covering the filler to improve the adhesion.

Further, such a resin composition can be diluted with a solvent, if necessary. As this solvent,
NMP (normal methylpyrrolidone), DMDG (diethylene glycol dimethyl ether), glycerin,
Water, 1- or 2- or 3-cyclohexanol, cyclohexanone, methylcellosolve, methylcellosolve acetate, methanol, ethanol, butanol, propanol, and the like. More preferably, a solvent is not contained in the filling resin composition.

In the present invention, it is desirable that a roughened layer is formed on the inner wall conductor surface of the through hole filled with the filler. The reason for this is that the filler and the through hole are in close contact with each other via the roughened layer, and no gap is generated. If there is a gap between the filler and the through-hole, the conductor layer formed by electrolytic plating directly above it will not be flat, or the air in the gap will thermally expand, causing cracks and peeling. Or cause water to accumulate in the voids, causing migration or cracks.
In this regard, the formation of the roughened layer can prevent such defects from occurring.

In the present invention, it is advantageous that a roughened layer similar to the roughened layer formed on the conductor surface on the inner wall of the through hole is formed on the surface of the conductor layer covering the filler. The reason for this is that the roughened layer can improve the adhesion to the interlayer resin insulating layer and via holes.
In particular, if the roughened layer is formed on the side surface of the conductor layer, cracks generated toward the interlayer resin insulation layer starting from the interface due to insufficient adhesion between the conductor layer side surface and the interlayer resin insulation layer can be suppressed. Can be.

The thickness of the roughened layer formed on the inner wall of the through hole or the surface of the conductor layer is preferably 0.1 to 10 μm.
The reason for this is that if it is too thick, it causes interlayer short-circuit, and if it is too thin, the adhesion to the adherend decreases. The roughened layer is formed by subjecting the conductor on the inner wall of the through hole or the surface of the conductor layer to an oxidation (blackening) -reduction treatment, or a treatment formed with a mixed aqueous solution of an organic acid and a cupric complex. Alternatively, a material formed by plating a copper-nickel-phosphorus needle-like alloy is preferable.

Among these treatments, in the method by oxidation (blackening) -reduction treatment, NaOH (20 g / l), NaClO ₂ (50 g
/ L), Na ₃ PO ₄ (15.0 g / l) in an oxidation bath (blackening bath), Na
OH (2.7 g / l) and NaBH ₄ (1.0 g / l) are used as the reducing bath.

In the treatment using an aqueous solution of an organic acid-copper complex, the metal foil such as copper serving as a conductor circuit is dissolved under the coexisting conditions of oxygen such as spraying and bubbling as follows. Cu + [Cu (II) A] ⁿ → [2Cu (I) A] ^{n / 2} +
n / 4O ₂ + nAH (aeration) → [2Cu (I
I) A] ⁿ + n / 2H ₂ O A is a complexing agent (acting as a chelating agent), and n is a coordination number.

The cupric complex used in this treatment is preferably an azole cupric complex. The cupric complex of azoles acts as an oxidizing agent for oxidizing metallic copper and the like. As the azoles, diazole, triazole,
Tetrazole is preferred. Among them, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole and the like are preferable. The content of the cupric complex of azoles is preferably 1 to 15% by weight.
This is because, when it is in this range, solubility and stability are excellent.

The organic acid is added to dissolve copper oxide. Specific examples include formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, apple At least one selected from acids and sulfamic acids is preferred. The content of this organic acid is 0.1-30
% By weight is good. This is for maintaining the solubility of the oxidized copper and ensuring the solubility stability. The generated cuprous complex dissolves under the action of an acid and combines with oxygen to form a cupric complex, which again contributes to copper oxidation. Further, in addition to the organic acid, an inorganic acid such as borofluoric acid, hydrochloric acid, and sulfuric acid may be added.

In order to assist the dissolution of copper and the oxidizing action of azoles, a halogen ion, for example, a fluorine ion, a chlorine ion, a bromine ion or the like is added to the etching solution comprising the organic acid-cupric complex. Is also good. The halogen ions can be supplied by adding hydrochloric acid, sodium chloride, or the like. The amount of halogen ions is preferably 0.01 to 20% by weight. This is because if it is within this range, the adhesion between the formed roughened surface and the interlayer resin insulating layer will be excellent.

The etching solution comprising the organic acid-cupric complex is prepared by dissolving a cupric complex of an azole and an organic acid (halogen ion if necessary) in water.

In the plating of a needle-shaped alloy consisting of copper-nickel-phosphorus, copper sulfate 1-40 g / l, nickel sulfate 0.1-6.0 g / l, citric acid 10-20 g / l, hypophosphite 10-100 g / l, boric acid 10-40 g / l, surfactant
It is desirable to use a plating bath having a liquid composition of 0.01 to 10 g / l.

In the present invention, it is preferable that the interlayer resin insulating layer is formed using a thermosetting resin sheet. The thermosetting resin sheet contains a sparingly soluble resin, soluble particles, a curing agent, and other components. Each is described below.

In the thermosetting resin sheet used in the production method of the present invention, particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble particles”) are resins which are hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a hardly soluble resin). ). The terms “sparingly soluble” and “soluble” as used in the present invention, when immersed in a solution containing the same acid or oxidizing agent for the same time, have a relatively high dissolution rate and are called “soluble” for convenience. Those having a relatively low dissolution rate are referred to as "poorly soluble" for convenience.

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and acid or oxidizing agents. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

Further, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

The soluble inorganic particles include, for example, particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

The soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin film can be ensured, and thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed by using an acid or an oxidizing agent in the interlayer resin insulating layer. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, a via opening can be formed in the interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin,
Examples thereof include a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak epoxy resin, bisphenol A epoxy resin, bisphenol F epoxy resin, phenol novolak epoxy resin, alkylphenol novolak epoxy resin, biphenol F epoxy resin, and naphthalene epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin film used in the present invention, it is desirable that the soluble particles are substantially uniformly dispersed in the poorly soluble resin. A roughened surface having unevenness with a uniform roughness can be formed, and even when a via or a through hole is formed in a resin film, the adhesion of a metal layer of a conductive circuit formed thereon can be secured. Because. Alternatively, a resin film containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby, since the portions other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin film, the amount of the soluble particles dispersed in the poorly soluble resin is preferably 3 to 40% by weight based on the resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities. If the amount exceeds 40% by weight, the soluble particles may be dissolved using an acid or an oxidizing agent. In addition, there is a case where the resin film is melted to a deep portion of the resin film and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.

The resin film desirably contains a curing agent and other components in addition to the soluble particles and the hardly soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and microcapsules of these curing agents, and organic materials such as triphenylphosphine, tetraphenylphosphonium, and tetraphenylborate. Phosphine compounds and the like can be mentioned.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin film. 0.
If the amount is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidizing agent into the resin film is increased, and the insulating property of the resin film may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

Examples of the other components include fillers such as inorganic compounds and resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the printed wiring board can be improved by matching the thermal expansion coefficient, improving heat resistance and chemical resistance, and the like.

Further, the above resin film may contain a solvent. As the solvent, for example, acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Ethyl acetate, butyl acetate, cellosolve acetate, and aromatic hydrocarbons such as toluene and xylene. These may be used alone or in combination of two or more.

[0081]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment First, the structure of a multilayer printed wiring board used as a package substrate according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 10 is a sectional view of the package substrate 10 according to the first embodiment of the present invention. FIG. 11 is an explanatory diagram showing an enlarged view of the coaxial through hole 66 in FIG.
FIG. 12 is a sectional view taken along line XX of FIG.

As shown in FIG.
Has a build-up wiring layer 80A and a build-up wiring layer 80B formed on the front and back surfaces of the laminated substrate 30.
The laminated substrate 30 is a core substrate 2 on which the conductor circuit 22 is formed.
The resin layer 24 is formed on both sides of the “0”. In this embodiment, the resin layers 24 are formed on both surfaces of the core substrate 20, but may be formed on only one surface. Build-up wiring layer 80A,
The build-up wiring layer 80B includes an interlayer resin insulation layer 44 on which the conductor circuit 58 and the via hole 60 are formed, and an interlayer resin insulation layer 144 on which the conductor circuit 158 and the filled via 160 are formed. The front-side build-up wiring layer 80A and the back-side build-up wiring layer 80B have a coaxial through-hole 66 used as a signal line formed on the laminated substrate 30 and a conduction through-hole mainly used as a ground line / power supply line. It is connected via a hole 34. The solder resist layer 70 is formed on the interlayer resin insulating layer 144, and the conductor circuit 158 and the filled via 16 are formed through the opening 71 of the solder resist layer 70.
No. 0 has a solder bump 76U and a solder bump 76D. The solder bumps 76U on the front side are connected to the pads 92 of the IC chip 90. On the other hand, the solder bumps 76D on the back side are connected to the pads 96 of the daughter board 95.

As shown in FIG. 11, the coaxial through hole 6
6 is an outer layer through hole 36 and an inner layer through hole 62
Consists of As described above, the outer layer through-hole 36 and the inner layer through-hole 62 are
0A and the build-up wiring layer 80B on the back side. The outer layer through hole 36 is formed by forming a metal film 38 on the wall surface of the through hole 33 of the laminated substrate 30. An outer resin insulating layer (outer resin filler) 42 is formed inside the outer through hole 36. Outer resin insulation layer 4
An inner layer through hole 62 is formed inside 2.

A lid plating layer 94 is formed directly above the inner layer through hole 62, and the inner layer through hole 62 and the filled via 160 are connected via the lid plating layer 94. By interposing the cover plating layer 94, the inner layer through hole 62
And the upper layer filled via 160 have improved connectivity. Then, the inner plated through hole 62 is formed by the lid plating layer 94.
Since the filled via 160 can be provided directly above the wiring, the wiring length can be reduced, and the high-frequency performance can be improved.

Further, a filled via 160 is arranged on the inner resin filler 64 filled in the inner through hole 66 via the cover plating layer 94, and the difference in thermal expansion between the laminated substrate 30 and the inner resin filler 64 is caused. Even if it receives stress, it has a strength that can withstand the stress by filling the inside with metal,
No peeling of the solder bumps 76U, 76D occurs. Furthermore,
Solder bumps 76U, 7 on flat filled via 160
Since the 6D is provided, no void remains inside the solder bump, and the reliability of the solder bump can be improved.

The inner layer through hole 62 is composed of three layers: a metal layer 50, an electroless plating film 52, and an electrolytic plating film 56.
In addition, it is also possible to form with two layers. An inner resin insulating layer (inner resin filler) 64 is formed inside the inner through hole 62. By forming the through hole 66 used as a signal line to have the outer layer through hole 36 and the inner layer through hole 62 in a coaxial structure, it is possible to prevent standing waves and reflection from occurring in the through hole 66.

FIG. 12 shows a cross section taken along line XX of FIG. FIG.
Y-Y in FIG. 2 corresponds to the cut end face in FIG. In the present embodiment, the coaxial through-hole 66 is mainly disposed at the center of the laminated substrate 30, and the uniaxial through-hole (through-hole for conduction) 34 is mainly disposed at the outer peripheral part. That is, a coaxial through hole 66 capable of preventing reflection and standing wave from being generated is disposed as a high-frequency signal line (or power line) directly below the IC chip so that the distance between the IC chip and the daughter board is minimized. I do. On the other hand, since the distance between the IC chip and the daughter board is long in the outer peripheral portion, the through hole 34 for conduction is arranged, and the signal line of a relatively low frequency is arranged. Therefore, the number of coaxial through-holes 66 with low reliability and high manufacturing cost can be reduced while achieving the required electric performance, so that the reliability can be improved.
It can be manufactured at low cost.

The outer resin insulating layer 42 inside the outer through hole 36 and the inner resin insulating layer 64 inside the inner through hole 62 are filled with a resin containing a thermosetting resin, a curing agent, and inorganic particles. It is formed by filling an agent. This resin filler contains at least 10 inorganic particles.
Since it is blended in the range of ８０80 vol%, the thermal expansion coefficients of the outer resin insulating layer 42, the inner resin insulating layer 64, the laminated substrate 30, and the interlayer insulating layer 44 can be matched, and stress concentration due to thermal contraction can be prevented. Therefore, generation of cracks is prevented, and electrical connectivity and reliability can be improved.

As will be described later, in the package substrate 10 of the first embodiment, a through hole 33 having a vertical wall is formed in the laminated substrate 30 by using a drill to form an outer layer through hole 36. Then, the inner layer through-hole 62 is formed by using a smaller diameter drill. That is, by using a drill instead of a laser, the outer layer through-hole 36 and the inner layer through-hole 62 are prevented from being tapered, and an outer layer that forms an insulating layer between the outer layer through-hole 36 and the inner layer through-hole 62 is formed. Resin insulation layer (resin filler)
The thickness of 42 is made uniform. This prevents a short circuit between the outer layer through-hole 36 and the inner layer through-hole 62, thereby improving electrical connectivity and reliability.

In particular, in the first embodiment, the outer resin insulating layer (resin filler) 42 between the outer through-hole 36 and the inner through-hole 62 in order to prevent the occurrence of cracks inside due to the difference in thermal expansion coefficient. Contains 10% or more of inorganic particles. For this reason, migration is likely to occur due to transmission of the inorganic particles, and a short circuit is likely to occur. However, by making the thickness of the outer resin insulation layer (resin filler) 42 uniform, the outer layer through-hole 36 and the inner layer through-hole 62 are formed. To prevent short circuit between them.

Next, a method of manufacturing the package substrate 10 according to the first embodiment will be described with reference to FIGS. Here, first, A.I. used in the method of manufacturing the package substrate is described. The composition of the resin filler will be described.

A. Preparation of resin filler [Thermosetting resin] Bisphenol F type epoxy monomer (manufactured by Yuka Shell,
Molecular weight 310, YL983U) 100 parts by weight. [Curing agent] 6.5 parts by weight of imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals). [Inorganic particles] silica (Admatech, CRS 1101-C
E, where the silica used is SiO ₂ with an average particle size of 1.6 μm, the surface of which is coated with a silane coupling agent.
The size of the spherical particles and the maximum particles is not more than the thickness (15 μm) of the inner layer copper pattern described later.) 170 parts by weight. In the first embodiment, the amount of the inorganic particles added to the resin filler is set to 10 to 80 vol%, here, 50 vol%, as described above. By mixing 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) with the bisphenol F type epoxy monomer, imidazole curing agent and silica, the viscosity of the mixture is 5 to 30 Pa.s at 23 ± 1 ° C. Adjust to S. In the first embodiment, the viscosity is 5 Pa. S obtained by adjusting to S is used.

Manufacturing of package substrate (1) 0.8 mm thick glass epoxy resin or BT
Substrate 20 made of (bismaleimide-triazine) resin
The starting material is a copper-clad laminate 20A in which copper foils 21 of 12 μm are laminated on both sides of the substrate (FIG. 1A). Note that a base material impregnated with a reinforcing material such as FR4, FR5, or a glass epoxy resin can be used. A core substrate that has been multilayered in advance may be used.

(2) An inner layer copper pattern (metal film) 22 is formed on both surfaces of the substrate 30 by using a tenting method or a semi-additive method on the copper foil 21 (FIG. 1B).

(3) The core substrate 20 on which the inner layer copper pattern (metal film) 22 is formed is washed with water and dried. afterwards,
As an oxidation bath (blackening bath), NaOH (20 g / l), NaClO ₂
(50 g / l), Na ₃ PO ₄ (15 g / l), NaOH (2.7 g / l), NaBH ₄ (1.0 g / l)
A roughened layer 22α is provided on the surface of the inner layer copper pattern (metal film) 22 by oxidation-reduction treatment using
(C)). The roughened layer may be formed by plating, etching, or the like.

(4) A resin layer 24 made of a thermosetting resin is adhered to both surfaces of the core substrate 20 and the resin layer 24 is cured, so that a laminated substrate 30 composed of the core substrate 20 and the resin plate 30 is formed.
Is formed (FIG. 1D).

(5) After the surface of the resin layer 24 is roughened, an electroless copper plating film is formed, and an electroless copper plating film is formed on the electroless copper plating film. A metal film 31 made of an electrolytic copper plating film is formed (FIG. 1).
(E)).

(6) The laminated substrate 30 is drilled to form a through hole 32 for a conductive through hole having a diameter of 250 μm and a through hole 33 for an outer layer through hole having a diameter of 350 μm (FIG. 2A). Holes may be drilled using a laser, but it is preferable to use a drill to prevent tapering. In the present embodiment, since the coaxial through-hole and the normal through-hole are mixed, each is formed using a separate drill. Through hole 3 for outer layer through hole
The opening diameter of 3 is preferably 200 to 400 μm. Particularly desirable is 250 to 350 μm. The opening diameter of the through hole 32 for the conductive through hole is 50 to
The thickness is preferably 400 μm.

(7) Subsequently, the laminated substrate 30 is subjected to an electroless copper plating process to form a through hole 34 for conduction and an outer layer through hole 36 (FIG. 2B). Further, an inner copper pattern (metal film) 38 is formed on both surfaces of the substrate 30 by using a tenting method or a semi-additive method on the metal film 31 (FIG. 2C).

(8) The substrate 30 on which the inner layer copper pattern (metal film) 38, the conduction through hole 34, and the outer layer through hole 36 are formed is washed with water and dried. Then, NaOH (20 g / l), NaClO was used as an oxidation bath (blackening bath).
_Two (50 g / l), Na ₃ PO ₄ (15 g / l), NaOH (2.7 g / l), NaBH ₄ (1.0 g /
By the oxidation-reduction treatment using 1), the surface of the inner layer copper pattern (metal film) 38, the through hole 34 for conduction, and the outer layer through hole 36 is provided with a roughened layer 34α, a roughened layer 36α,
The roughened layer 38α is provided. (FIG. 2D) The roughened layer may be formed by plating, etching, or the like.

(9) The resin through-hole 34 and the outer layer through-hole 36 are filled with the resin filler 39 adjusted in the above A by printing (FIG. 3A). By filling the through hole 34 for conduction and the outer layer through hole 36 with the resin filler 39 adjusted in the above A, cracks are prevented from occurring, and electrical connectivity and reliability are improved. Here, based on a conventional filler (thermosetting resin, thermoplastic resin, or a resin composite thereof), an organic resin filler, an inorganic filler, a metal filler, etc. are blended to form a core substrate and an inner layer filler. Thermal expansion matching may be performed. At this time, the amount of the filler is preferably 10 to 80 vol%.

(10) Substrate 3 after completion of process (9)
The surface of the lower conductive circuit (inner copper pattern) 38 and the land 34 of the conductive through-hole 34 are polished on one side of
a, polishing is performed so that the resin filler 39 does not remain on the surface of the land 36a of the outer layer through hole 36. Next, buffing is performed to remove scratches caused by the belt sander polishing. This step is similarly performed on the other surface of the substrate. Then, the filled resin filler 39 is cured by heating to form the resin insulating layer 40 in the through hole 34 for conduction and the outer resin insulating layer 42 in the outer layer through hole 36 (FIG. 3B). Note that only buffing may be performed.

(11) Next, the surface of the lower conductive circuit 38 once flattened in the same manner as in (4) above and the through holes 34 for conduction are formed on both surfaces of the substrate 30 after the processing of (10) above.
And land 34a and land 36 of outer layer through hole 36
By performing an oxidation-reduction treatment on the surface a, a roughened surface 34β, a roughened surface 36β, and a roughened surface 38β are formed on the surface of the lower conductive circuit 38 and the surfaces of the lands 34a and 36a (FIG. 3C). ).

(12) Substrate 3 after step (11)
A thermosetting resin sheet containing a soluble filler having a thickness of 50 μm is vacuum-press-laminated at a pressure of 5 kg / cm ² while raising the temperature to a temperature of 50 to 150 ° C. on both surfaces of the resin resin layer 0 to provide an interlayer resin insulating layer 44 (FIG. 3). (D)). The interlayer resin insulating layer may be a resin made of a thermosetting resin or a thermoplastic resin, or a resin obtained by substituting a photosensitive group for them. Specific examples include resins used for printed wiring boards, such as epoxy resins, polyphenol resins, and polyimide resins. Further, a resin having a low dielectric constant in a high frequency region may be used. The degree of vacuum during vacuum compression of resin is
10 mmHg. Although the interlayer insulating layer is formed by attaching a resin film here, the interlayer insulating layer may be formed by applying a resin using a printing machine.

(13) Next, an opening 46 to be a via hole is formed in the interlayer resin insulating layer 44 (FIG. 4A). Here, a carbon dioxide (CO ₂ ) gas laser is used, and the beam diameter is 5 m.
A via hole opening 46 having a diameter of 80 μm is provided in the interlayer resin insulating layer 44 under the conditions of m, pulse width 15 μs, mask hole diameter 0.8 mm, and one shot.

(14) Using a drill having a diameter of 60 to 200 μm, the outer layer through hole 36 formed in the laminated substrate 30 is formed.
A through hole 48 for an inner layer through hole is formed to penetrate the outer resin insulating layer 42 and the interlayer resin insulating layer 44 of FIG.
(B)). In the first embodiment, a drill having a diameter of 145 μm with a diamond tip attached to the tip is rotated 16 times per minute to form a through hole 48 having a diameter of 150 μm. If necessary, the smear in the through hole 48 for the inner layer through hole is removed by a wet process such as permanganic acid or a dry etching process such as a plasma or corona treatment. It is preferable that the diameter of the through hole 48 for the inner layer through hole is 75 to 200 μm. Particularly desirable is 100-150
μm. In the first embodiment, since the through hole 48 for a through hole having a vertical wall is formed using a drill, it is possible to prevent the shape of the inner layer through hole from being tapered unlike a laser. Therefore, it is possible to prevent a short circuit from occurring between the inner layer through-hole and the outer layer through-hole formed in a step described later.

(15) Next, a roughened surface 44α of the interlayer resin insulating layer 44 is provided by dipping in an oxidizing agent such as chromic acid and permanganate (see FIG. 4C).
The roughened surface 44α is preferably formed in a range of 0.1 to 5 μm. As an example, a roughened surface 44α of 2-3 μm is provided by immersing in a sodium permanganate solution 50 g / l at a temperature of 60 ° C. for 5 to 25 minutes.
In addition to the above, plasma treatment is performed on the interlayer resin insulating layer 44 to roughen the surface layer of the interlayer resin insulating layer 44, and the roughened surface 44α
To form At this time, argon gas was used as an inert gas, power was 200 W, gas pressure was 0.6 Pa, and temperature was 7
Under the condition of 0 ° C (plasma equipment manufactured by Japan Vacuum Engineering Co., Ltd.
SV-4540) Perform plasma treatment for 2 minutes.

(16) Cu is sputtered into the surface layer of the interlayer resin insulation layer 44 and the through hole 48 for the through hole in the inner layer.
(Or Ni, P, Pd, Co, W) to form a metal layer 50 which targets an alloy (FIG. 4D). As the forming conditions, the pressure is 0.6 Pa, the temperature is 80 ° C., the electric power is 200 W, and the time is 5 minutes (the plasma apparatus SV-
4540). Thereby, the interlayer resin insulation layer 4
An alloy layer can be formed on the surface layer of No. 4 and the through-hole 48 for the inner layer through-hole. At this time, the thickness of the metal layer 50 is 0.2 μm. As the thickness of the metal layer 50,
0.1 to 2 μm is preferred. A plating layer may be formed without performing evaporation, sputtering, etc. other than sputtering.
Alternatively, these complexes may be used.

An example of plating will be described. The substrate 30 is conditioned, and the catalyst is applied in an alkaline catalyst solution for 5 minutes. The substrate 30 is activated, and a 0.5 μm-thick electroless plating film 5 is formed in a Rochelle salt type chemical copper plating bath.
2 (FIG. 5A). Plating conditions for chemical copper plating: CuSO ₄ .5H ₂ O 10 g / l HCHO 8 g / l NaOH 5 g / l Rochelle salt 45 g / l Additive 30 ml / l Temperature 30 ° C. Plating time 18 minutes

(17) A photosensitive film (dry film) having a thickness of 20 μm is stuck on the metal film 52, a mask is placed thereon, exposed at 100 mJ / cm ² , and developed with 0.8% sodium carbonate. And a 25 μm thick plating resist 5
4 (FIG. 5B).

(18) Next, electrolytic plating is performed on the non-formed portion of the plating resist 54 on the electroless plated film 52 under the following conditions to form an electrolytic plated film 56 (FIG. 5C). The thickness of the electrolytic plating film 56 is preferably 5 to 20 μm.

[Electroplating aqueous solution] Sulfuric acid 2.24 mol / L Copper sulfate 0.26 mol / L Additive 19.5 ml / L [Electroplating conditions] Current density 1 A / dm ² hours 65 minutes Temperature 22 ± 2 ° C

(19) Then, at 50 ° C., 40 g / l of N
The plating resist 54 is peeled off in an aOH aqueous solution.
Thereafter, the metal layer 50 and the electroless plating film 52 under the plating resist 54 are removed by etching using a sulfuric acid-hydrogen peroxide aqueous solution, and the conductor circuit 58 (including the via hole 60) is formed on the interlayer resin insulating layer 44. Is formed, and an inner layer through hole 62 is formed in the outer layer through hole 36. Thereafter, the surfaces of the conductor circuit 58, the via hole 60, and the inner layer through hole 62 are subjected to a roughening treatment (FIG. 5D).

(20) Next, similarly to the above-mentioned steps (8) to (10), the resin filler prepared in the above A is filled also in the inner through hole 62. Thereafter, the resin filler is polished. The polishing is performed using a nonwoven fabric containing an abrasive such as a buff on one side so that the resin filler does not remain on the surface of the land 62a of the inner layer through hole 62. This step is similarly performed on the other surface of the substrate. Then, the filled resin filler is cured by heating to form an inner resin insulating layer 64 in the inner through hole 62 (FIG. 6A). Thereby, the outer layer through hole 36 and the inner layer through hole 62
Is formed. In the first embodiment, the blending amount of the inorganic particles in the resin filler is 80 vol%.
Therefore, the polishing can be easily performed without performing mechanical polishing such as belt sander polishing, without damaging the interlayer insulating layer 44 and without losing the roughened surface of the interlayer insulating layer 44. It becomes possible to do.

Here, the inner layer through hole 62 is formed by filling a resin filler, but it may be formed by printing. In addition, based on a conventional filler (thermosetting resin, thermoplastic resin, or a resin composite thereof), an organic resin filler, an inorganic filler, and the like are blended to form a thermal expansion between the interlayer insulating layer and the outer layer filler. Matching may be performed. At this time, the compounding amount was 10 to 80 vol%, and the viscosity was 5 to 50 Pa. S is desirable. In addition, the outer resin insulating layer 4
2, inner resin insulation layer 64, laminated substrate 30 and interlayer insulation layer 4
4 can be matched with the coefficient of thermal expansion to prevent stress concentration due to thermal contraction. Therefore, generation of cracks is prevented, and electrical connectivity and reliability can be improved.

(21) After applying a catalyst for electroless plating to the substrate, electroless plating is performed to form an electroless plating film 68 (FIG. 6B). In the first embodiment, since the amount of the inorganic particles of the resin filler (inner-layer resin-filled layer) 64 filled in the inner-layer through-hole 62 is 80 vol% or less,
The electroless plating film 68 can be appropriately deposited by preventing a decrease in the amount of the applied catalyst and stopping the reaction of the electroless plating film.

(22) Next, after a plating resist 67 having a predetermined pattern is formed on the substrate, electrolytic plating is performed.
An electrolytic plating film 69 is formed (FIG. 6C). afterwards,
After the plating resist 67 is peeled off, the electroless plating film 68 under the plating resist 67 is removed by light etching to form a cover plating layer 94 composed of the electroless plating film 68 and the electrolytic plating film 69 on the inner through hole 62. (FIG. 6 (D)).

(23) Thereafter, after roughening the surface of the cover plating layer 94, an interlayer resin insulating layer 144 is formed as an upper layer, a via hole opening 146 is formed by laser, and a surface of the interlayer resin insulating layer 144 is formed. Is roughened (FIG. 7A).

(24) A metal film 152 is formed on the surface of the interlayer resin insulation layer 144 by electroless plating (FIG. 7).
(B)). The thickness of the metal film 152 is preferably formed in the range of 0.1 to 5 μm. As an example, [aqueous electroless plating solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α'-bipyridyl 100 mg / l polyethylene Glycol (PEG) 0.10 g / l Dipped at a liquid temperature of 34 ° C. for 40 minutes.

(25) On the metal film 152, a thickness of 20 μm
A photosensitive film (dry film) is affixed, a mask is placed, exposed at 100 mJ / cm ² , developed with 0.8% sodium carbonate, and a plating resist 154 having a thickness of 25 μm is provided. Then, electroplating is performed on the non-formation portion of the plating resist 154 on the electroless plating film 152 under the following conditions to form an electroplating film 156 (FIG. 7).
(C)). The thickness of the electrolytic plating film 156 is 5 to 2
0 μm is preferred. [Electrolytic plating solution] _{CuSO 4 · 5H 2 O 210g /} l sulfuric acid 150g / ^l Cl - 40mg / ^l reactive stabilizer 300 mg / l [electrolytic plating conditions] current density 1.0A / dm ² hours 35 minutes temperature 25 ° C.

(26) Then, at 50 ° C., 40 g / l of N
The plating resist 154 is peeled off in an aOH aqueous solution. Thereafter, the electroless plating film 1 under the plating resist 154 is etched by using a sulfuric acid-hydrogen peroxide aqueous solution.
52 is removed and the conductor circuit 1 is placed on the interlayer resin insulation layer 144.
58 (including via holes 157) (FIG. 7)
(D)).

(28) Since a recess is formed in the opening of the via hole 157, a conductive resin 159 is filled to fill the recess, and the surface is flattened (FIG. 8A )). Thereby, the via hole 157 and the upper surface of the conductor circuit 158 in the same layer are made substantially flush with each other.

As the conductive resin, a material that can be electrically connected can be used. As a result, the entire via hole can be electrically connected, and even if a large amount of current flows, it can be transmitted without generating a problem such as heat generation.

In the first embodiment, a conductive paste of copper particles having a particle size of 0.5 μm and an epoxy resin is used as the conductive resin. The compounding ratio of the particles to the epoxy resin is 7
5% by weight. Since the electrical characteristics were the same as those of the circuit formed because of the copper, peeling of the resin did not cause any problem.

The metal particles of the particulate material include copper, gold,
Silver, nickel, aluminum, titanium, chromium, tin,
Metals such as lead, palladium, and platinum can be used, and the structure may be formed of a single metal or an alloy of two or more types. The shape of the above-mentioned metal particles includes a spherical shape, a polyhedral shape, a hybrid of a spherical shape and a polyhedral shape, and the like.

As the inorganic particles of the particulate matter, silica,
Alumina, mullite, silicon carbide, or the like can be used. The shape of the aforementioned inorganic particles is spherical, polyhedral, porous,
There are hybrids of spherical and polyhedral shapes. By coating the surface with a conductive material such as a metal layer or a conductive resin, the resin particles have conductivity.

As the resin particles of the particulate matter, it is desirable to use at least one selected from an epoxy resin, a benzoguanamine resin and an amino resin.
Further, a conductive resin such as an anisotropic conductive resin may be used. By coating the surface with a conductive material such as a metal layer or a conductive resin, the resin particles have conductivity. In particular, it is preferable to use an epoxy resin. The reason is that the resin has good adhesion to the constituent resin and has a close linear expansion coefficient, so that the constituent resin does not crack.

Here, the diameter of the above-mentioned metal particles, inorganic particles or resin particles is preferably 0.1 to 50 μm. If the particle diameter is less than 1 μm, electrical continuity may not be obtained, and if the particle diameter exceeds 50 μm, the workability at the time of filling the openings is reduced.

Incidentally, the above-mentioned metal particles with respect to the total weight,
The packing ratio of inorganic particles or resin particles is 30 to 90.
% By weight is good. If the amount is less than 30% by weight, electrical connection may not be established. If the amount exceeds 90% by weight, the paste becomes hard and brittle.

A mixture of these particles and a resin can be used as the conductive resin. In particular, it is desirable to use a metal. Conductivity is obtained more reliably than other particles, alignment such as thermal expansion is easily achieved, and peeling is less likely to occur. As the resin, a thermosetting resin, a thermoplastic resin, or a photosensitive resin can be used. In particular, it is desirable to use a thermosetting resin. It is superior to other resins in terms of filling properties into via holes and uniformity of particles.

The thermosetting resin is preferably at least one resin selected from the group consisting of an epoxy resin, a polyimide resin, a polyester resin and a phenol resin. In the case of a thermosetting resin, after filling the opening by printing and potting, a protruding pin is inserted, and thermosetting is performed to join. In order to eliminate air, gaps, excess solvent, and the like in the resin, vacuum and reduced pressure defoaming may be performed, followed by heat curing.

After that, the surface of the via hole 157 is covered with a cover plating 16 by electroless plating of copper or electrolytic plating.
1 to form a filled via structure (FIG. 8B).

(29) On the other hand, 46.67 g of a photosensitizing oligomer (molecular weight 4000) obtained by acrylated 50% of epoxy groups of a 60% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG, 15.0 g of 80% by weight bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Chemicals, trade name: 2E4MZ-C)
N) 16 g, a photosensitive monomer polyvalent acrylic monomer (Nippon Kayaku, R604) 3 g, a polyvalent acrylic monomer (Kyoeisha Chemical, DPE6A) 1.5 g, and a dispersion defoaming agent (Sannopco, S -65) was mixed with 0.71 g, and 2 g of benzophenone (manufactured by Kanto Kagaku) as a photoinitiator and 0.2 g of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to the mixture to give a viscosity of 25. 2.0Pa at ℃
s is obtained. The viscosity was measured at 60 rpm using a B-type viscometer (Tokyo Keiki, DVL-B type).
For rotor No.4, for 6 rpm, rotor No.3.

(30) The solder resist composition was applied to both sides of the package substrate obtained in the above (27) by 20 μm.
Apply with a thickness of Next, after performing a drying process at 70 ° C. for 20 minutes and a temperature of 70 ° C. for 30 minutes, a 5 mm-thick photomask film on which a circular pattern (mask pattern) is drawn is placed in close contact, and is placed at 1000 mJ / cm ^2. Exposure with UV light, DM
Perform TG development. And then at 80 ° C for 1 hour at 100 ° C
For 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours to form a solder resist layer 70 (20 μm thick) having an opening 71 in a solder pad portion (including a via hole and its land portion). It is formed (FIG. 8C). The solder pads for forming the solder bumps for connecting the IC chip are preferably opened with an opening diameter of 100 to 170 μm. Further, it is preferable that the solder pads for disposing BGA / PGA for connecting external terminals are opened with an opening diameter of 300 to 650 μm.

(31) Then, nickel chloride 2.3 × 10
^-1 mol / l, sodium hypophosphite 2.8 × 10 ^-1 m
ol / l, sodium citrate 1.6 × 10 ⁻¹ mol /
1 is immersed for 20 minutes in an electroless nickel plating solution having a pH of 4.5 to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. Then, on the surface layer, potassium cyanide 7.6 × 10 ⁻³ mol / l, ammonium chloride 1.9 × 10 ⁻¹ mol / l, sodium citrate 1.2 ×
10 ^-1 mol / l, sodium hypophosphite 1.7 × 10 ^-1
The nickel plating layer 72 was immersed in an electroless gold plating solution of 80 mol / l at 80 ° C. for 7.5 minutes to a thickness of 0.5
A gold plating layer 74 of 03 μm is formed (FIG. 9A).

(32) The solder resist layer 70
The mask 98 in which the opening 98 a facing the opening 71 is formed is placed on the solder resist layer 70. Then
Sn / Ag (S) is applied to the opening 71 of the solder resist layer 70.
A paste 76α of a low melting point metal made of n / Ag / Cu or Sn / Sb) is filled (FIG. 9B). Since this low melting point metal uses an alloy containing no Pb, it does not adversely affect the environment. The opening 71 is formed on the filled via 160 whose surface is almost flat. Therefore, when filling the opening 71 with the paste 76α of the high-viscosity low-melting-point metal, no void is generated.

(33) Subsequently, paste 7 of low melting point metal
6α is reflowed to form solder bumps 76U and 76D (FIG. 9C). Even during this reflow, the depth of the recess of the filled via 160 is shallow (less than 10 μm, more preferably less than 5 μm), so that even if a void remains in the recess, it escapes to the outside.

The IC chip 90 is mounted by placing the pads 92 of the IC chip 90 on the solder bumps 76U of the completed package substrate 10 and performing reflow.
The package substrate 10 on which the IC chip 90 is mounted is
The reflow is performed by placing it on the daughter board 95 so as to correspond to the pad 96 on the daughter board 95 side (see FIG. 10). As a result, solder bumps are provided,
The package substrate 10 having the through-hole 66 in which the outer layer through-hole and the inner layer through-hole have a coaxial structure can be obtained. Here, the solder bumps 76D are provided also on the connection side with the daughter board, but a BGA may be provided instead.

By adding 10 to 80% of the inorganic particles to the resin filler filling the through holes 66 of the package substrate 10, it is possible to prevent the occurrence of stress due to heat shrinkage. Therefore, the occurrence of cracks in the conductor portion can be prevented, so that electrical connectivity and reliability can be improved.

In the method of manufacturing the package substrate 10 according to the first embodiment of the present invention, the case where solder bumps are provided has been exemplified. However, PGA may be provided as shown in FIG. The steps (1) to (31) are the same when the PGA is provided. The subsequent steps will be described.
First, a solder paste is printed as a conductive adhesive 78 in the opening 71 on the lower surface side (connection surface with the daughter board and the motherboard) of the substrate. Next, the conductive connection pin 97 is attached to and supported by an appropriate pin holding device, and the fixing portion 97A of the conductive connection pin 97 is fixed to the conductive adhesive 7 in the opening 71.
8 Then, reflow is performed to fix the conductive connection pins 97 to the conductive adhesive 78. In addition, as a method of attaching the conductive connection pin 97, the conductive adhesive 78
Into a shape of a ball or the like into the opening 71,
Alternatively, the conductive adhesive 78 may be joined to the fixing portion 97A to attach the conductive connection pin 97U, and then reflowed. The opening 71 on the upper surface is provided with a solder bump 76. As a result, the package substrate 10 having the through holes 66 in which the PGA is provided and the outer layer through holes and the inner layer through holes have a coaxial structure can be obtained. In the modified example, the flat filled via 16
Since the conductive connection pins 97 are mounted on the conductive adhesive 78 via the conductive adhesive 78, no void remains inside the conductive adhesive 78, and the connection reliability of the conductive connection pins 97 is high.

[Second Embodiment] In the second embodiment, as the conductive resin 159 to be filled in the via hole 157, a conductive resin of gold particles having a particle size of 0.2 μm and 0.5 μm and a phenol resin is used. Was used.

[Third Embodiment] In the third embodiment, silver particles and polyester resin are used as the conductive resin 159 to be filled in the via holes 157.

[Fourth Embodiment] In the fourth embodiment, as the conductive resin 159 to be filled in the via hole 157, an inorganic particle having a surface coated with copper and a polyester resin are used.

[Fifth Embodiment] In the fifth embodiment, as the conductive resin 159 to be filled into the via hole 157, epoxy resin particles whose surfaces are coated with copper and an epoxy resin are used.

Although the through holes 66 are coaxial in the above-described embodiment, the outer through holes 36 and the inner through holes 66 of the through holes 66 may be used as separate signal lines. In this case, the wiring density of the core substrate can be increased. In the above-described embodiment, the outer layer through-hole 36 and the inner layer through-hole 6
6, a coaxial structure is used, but a resin having a high dielectric constant may be provided as an outer layer resin filler between the outer layer through hole 36 and the inner layer through hole 66 to be used as a capacitor.

In the package substrates of the first to fifth embodiments, under the condition of high temperature and high humidity (85 ° C., humidity 85%),
The reliability was evaluated at 00 hours. No problem was caused in the electrical characteristics. The reason is that even if moisture enters between the solder bumps and the filled via, which is the metal layer under the bumps, it is in a filled state, and there is no place where moisture remains. It is considered that the electrical characteristics were secured without causing any problem in the characteristics.

[0147]

As described above, according to the present invention, since the coaxial through-hole is provided, standing waves and reflection are not generated in the through-hole, and the electrical characteristics of the multilayer printed wiring board can be improved. Further, the filled via is disposed on the inner layer resin filler filled in the inner layer through hole via the lid plating layer, and even if stressed due to a difference in thermal expansion, the inside is filled with metal and can withstand the stress. Because of the strength, peeling of the solder bump does not occur. Furthermore, since the solder bump is provided on the flat filled via, no void remains inside the solder bump, and the reliability of the solder bump can be improved. Further, electric characteristics can be improved.

On the other hand, since the coaxial through-hole is mainly disposed at the center of the core substrate and the uniaxial through-hole is mainly disposed at the outer periphery, the required electric performance is achieved while the coaxial through-hole having low reliability and high manufacturing cost is obtained. Since the number of holes can be reduced, reliability can be improved, and furthermore, it can be manufactured at low cost.

In particular, in the present invention, a through hole for a through hole having a vertical wall is formed by using a drill to prevent the through hole from being tapered, and the gap between the outer through hole and the inner through hole is prevented. The thickness of the outer layer resin filler forming the insulating layer can be made uniform. Therefore, a short circuit between the outer layer through-hole and the inner layer through-hole can be prevented, and the reliability is improved.

[Brief description of the drawings]

FIG. 1 (A), (B), (C), (D), (E)
It is a manufacturing process figure of the package board concerning a 1st embodiment of the present invention.

FIGS. 2A, 2B, 2C, and 2D are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIGS. 3A, 3B, 3C, and 3D are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIGS. 4A, 4B, 4C, and 4D are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIGS. 5A, 5B, 5C, and 5D are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIGS. 6A, 6B, 6C, and 6D are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIGS. 7A, 7B, 7C, and 7D are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIGS. 8A, 8B, and 8C are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIGS. 9A, 9B, and 9C are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a state in which an IC chip is mounted on a package substrate according to the first embodiment of the present invention and attached to a daughter board.

FIG. 11 is an explanatory diagram showing an enlarged configuration of a coaxial through hole in FIG. 10;

FIG. 12 is a sectional view of the package substrate taken along line XX of FIG. 10;

FIG. 13 is a sectional view of a package substrate according to a modification of the first embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 20 core substrate 22 conductive circuit 24 resin layer 30 laminated substrate 34 conduction through hole (single-axis through hole) 36 outer layer through hole 38 inner layer copper pattern 39 resin filler 40 resin insulation layer 42 outer layer resin insulation layer 44 interlayer resin insulation layer 48 Inner layer through hole through hole 50 Metal layer 52 Electroless plating film 56 Electrolytic plating film 58 Conductor circuit 60 Via hole 62 Inner layer through hole 64 Inner resin insulation layer 66 Coaxial through hole 70 Solder resist layer 71 Opening 72 Nickel plating layer 74 Gold Plating layer 76U, 76D Solder bump 78 Conductive adhesive 80A, 80B Build-up wiring layer 90 IC chip 92 Fixing part 94 Cover plating layer 97 Conductive connection pin 144 Interlayer resin insulation layer 158 Conductor circuit 160 Filled via

────────────────────────────────────────────────── ─── of the front page continued (51) Int.Cl. ⁷ identification mark FI theme Court Bu (reference) H01L 23/14 H01L 23/12 F H05K 3/00 P 23/14 R F -term (reference) 5E346 AA06 AA15 AA35 AA43 CC04 CC09 CC32 CC57 DD02 DD03 DD33 EE01 FF04 FF07 FF15 GG15 GG17 GG22 GG23 GG27 HH05 HH06 HH11

Claims (9)

[Claims] 1. A multilayer printed wiring board in which an interlayer insulating layer and a conductive circuit are laminated on both sides of a laminated substrate in which a resin layer is disposed on a core substrate on which a conductive circuit is formed. A coaxial through hole comprising an outer layer through hole formed in a wall surface and an inner layer through hole formed by applying an outer layer resin filler in the outer layer through hole, and a filled via is disposed immediately above at least a part of the inner layer through hole A multilayer printed wiring board characterized by the following. 2. A multilayer printed wiring board comprising an interlayer insulating layer and a conductive circuit laminated on both sides of a laminated substrate in which a resin layer is disposed on a core substrate on which a conductive circuit is formed. An outer layer through hole formed on a wall surface, an inner layer through hole formed by applying an outer layer resin filler in the outer layer through hole, a lid plating layer formed by plating directly on the inner layer through hole, and the inner layer through hole A multilayer printed wiring board, comprising: a coaxial through-hole made of an inner resin filler filled therein; and a filled via disposed immediately above at least a part of the cover plating layer. 3. A multilayer printed wiring board in which an interlayer insulating layer and a conductive circuit are laminated on both sides of a laminated substrate in which a resin layer is disposed on a core substrate on which a conductive circuit is formed. An outer layer through hole formed on the wall surface of the through hole, an inner layer through hole formed by applying an outer layer resin filler in the outer layer through hole, and a single axis through hole having no inner layer through hole. Is formed, mainly a coaxial through hole in the center of the laminated substrate,
A multilayer printed wiring board, wherein a uniaxial through hole is mainly disposed at an outer peripheral portion, and a filled via is disposed immediately above at least a part of the cover plating layer. 4. The multilayer printed wiring board according to claim 1, wherein the filled via is formed by filling a conductive resin into the inside of the via hole. 5. The multilayer printed wiring board according to claim 1, wherein a filled via is further stacked on the filled via immediately above the coaxial through hole. 6. The multilayer printed wiring board according to claim 1, wherein a filled via immediately above said coaxial through hole is formed to penetrate a plurality of interlayer insulating layers. 7. The multilayer printed wiring board according to claim 1, wherein the inner layer through hole and the outer layer through hole are formed in a through hole formed by a drill. 8. The outer layer resin filler and the inner layer resin filler include at least a thermosetting resin and a curing agent,
The multilayer printed wiring board according to claim 2 or 3, wherein 0 vol% of inorganic particles are blended. 9. At least a part of the filled via includes S
9. The multilayer printed wiring board according to claim 1, wherein a solder bump made of n / Ag, Sn / Ag / Cu, or Sn / Sb is arranged.