JP4753470B2 - Capacitor, multilayer printed wiring board, and method for manufacturing multilayer printed wiring board - Google Patents

Description

【０２０７】
【表２】

【０２０８】
表１に示したように、実施例１〜４で得られた多層プリント配線板について、１０００サイクルおよび２０００サイクルのヒートサイクル試験を行った場合、コンデンサと接着剤や層間樹脂絶縁層と間での剥離は発生しておらず、接着剤や層間樹脂絶縁層中にもクラックは発生していなかった。
また、短絡や断線、層間樹脂絶縁層の膨れも発生していなかった。
【０２０９】
一方、比較例１、２で得られた多層プリント配線板では、コンデンサと樹脂（接着剤層や層間樹脂絶縁層）との接触面を起点にクラックや剥離が発生していた。
【０２１０】
さらに、表２に示したように、実施例１〜４で基板に埋設したコンデンサは、信頼性試験の前後で静電容量に変化が少なく、導体回路−コンデンサの間においても、電気的接続による影響が殆どない。
一方、比較例１、２で得られた多層プリント配線板では、信頼性試験後の静電容量を測定することができず、断線が発生していることが明らかとなった。
【０２１１】
【発明の効果】
以上説明したように、本発明のコンデンサは、その表面の少なくとも一部にカップリング剤層が形成されているため、セラミックからなる誘電膜や金属からなる外部電極と接着剤や層間樹脂絶縁層との親和性が高く、コンデンサと層間樹脂絶縁層や接着剤との間で剥離が発生したり、層間樹脂絶縁層や接着剤にクラックが発生したりすることがない。
従って、本発明のコンデンサは、多層プリント配線板の内蔵用として適したものである。
【０２１２】
また、本発明の多層プリント配線板は、本発明のコンデンサが基板に内蔵されているため、コンデンサと層間樹脂絶縁層や接着剤との間で剥離が発生したり、該層間樹脂絶縁層や接着剤にクラックが発生したりすることがない。そのため、上記多層プリント配線板は、コンデンサの端子とバイアホールとの間の接続が遮断されたり、層間樹脂絶縁層にクラックや膨れが生じたりすることがなく、電気的接続性、信頼性に優れる。
【０２１３】
また、第一および第二の多層プリント配線板の製造方法では、本発明の多層プリント配線板、即ち、コンデンサと接着剤や層間樹脂絶縁層との間で剥離が発生したり、接着剤や層間樹脂絶縁層にクラックが発生したりすることがない多層プリント配線板を製造することができる。
【図面の簡単な説明】
【図１】（ａ）〜（ｄ）は、本発明のコンデンサの一例を模式的に示す断面部である。
【図２】本発明の多層プリント配線板の一例を模式的に示す断面図である。
【図３】図２に示す多層プリント配線板にＩＣチップを実装し、ドータボードに取り付けた状態を模式的に示す断面図である。
【図４】本発明の多層プリント配線板の一例を模式的に示す断面図である。
【図５】本発明の多層プリント配線板の一例を模式的に示す断面図である。
【図６】（ａ）〜（ｄ）は、本発明の多層プリント配線板の製造方法の一部を模式的に示す断面図である。
【図７】（ａ）〜（ｃ）は、本発明の多層プリント配線板の製造方法の一部を模式的に示す断面図である。
【図８】（ａ）〜（ｃ）は、本発明の多層プリント配線板の製造方法の一部を模式的に示す断面図である。
【図９】（ａ）〜（ｃ）は、本発明の多層プリント配線板の製造方法の一部を模式的に示す断面図である。
【図１０】（ａ）〜（ｃ）は、本発明の多層プリント配線板の製造方法の一部を模式的に示す断面図である。
【図１１】（ａ）〜（ｄ）は、本発明の多層プリント配線板の製造方法の一部を模式的に示す断面図である。
【図１２】（ａ）〜（ｃ）は、本発明の多層プリント配線板の製造方法の一部を模式的に示す断面図である。
【図１３】（ａ）〜（ｃ）は、本発明の多層プリント配線板の製造方法の一部を模式的に示す断面図である。
【図１４】（ａ）、（ｂ）は、従来の多層プリント配線板のループインダクタンスの説明図であり、（ｃ）は、本発明の多層プリント配線板のループインダクタンスの説明図である。
【図１５】（ａ）は、多数個取り用の裁断前のコンデンサを示し、（ｂ）は、（ａ）を裁断した後の本発明のコンデンサの１個を示す。
【図１６】（ａ）は、多数個取り用の裁断前のコンデンサを示し、（ｂ）は、（ａ）を裁断した後の本発明のコンデンサの１個を示す。
【図１７】本発明のコンデンサの一例を模式的に示す平面図である。
【図１８】（ａ）は、多数個取り用の裁断前のコンデンサを示し、（ｂ）は、（ａ）を裁断した後の本発明のコンデンサの１個を示す。
【符号の説明】
１０、１１０、２１０ 多層プリント配線板
２０、１２０、２２０、３２０ コンデンサ
２１ 第１電極
２２ 第２電極
２３ 誘電体
２４ 第１導電膜
２５ 第２導電膜
２６、２２６、３２６ 金属層
２７、２２７、３２７ 粗面
３０ 基板
４０、６０ 層間樹脂絶縁層
４６、６６ バイアホール
４８、６８ 導体回路
７０ ソルダーレジスト層
７６ 半田バンプ
９０ ＩＣチップ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a capacitor incorporated in a multilayer printed wiring board, a multilayer printed wiring board incorporating the capacitor, and a method of manufacturing the same.
[0002]
[Prior art]
Conventionally, in a printed wiring board for a package substrate, a chip capacitor is surface-mounted in order to reduce loop inductance from the power source to the power source / ground of the IC chip. That is, the loop inductance that becomes a transmission loss is the wiring length from the power supply terminal 192P of the IC chip 190 shown in FIG. 14A to the power supply via the power supply line in the printed wiring board 300 and the power supply to the printed wiring board 300. It is proportional to the wiring length between the ground terminals 192E of the IC chip 190 via the ground wire. For this reason, as shown in FIG. 14B, a chip capacitor 200 is surface-mounted on a printed wiring board 300, and the chip capacitor is interposed between the power supply and the power supply terminal / ground terminal of the IC chip. Can be shortened as shown by the solid line in the figure.
[0003]
However, since the reactance of the loop inductance depends on the frequency, even if the chip capacitor is mounted on the surface of the multilayer printed wiring board as the IC chip drive frequency increases, the loop inductance is sufficiently reduced. I can't do that.
[0004]
[Means for Solving the Problems]
Therefore, the present inventors have conducted extensive research to further reduce the loop inductance from the power source to the power source / ground of the IC chip, and as a result, have found that a capacitor may be built in the multilayer printed wiring board. First, an interlayer resin insulation layer and a conductor circuit are sequentially formed on a substrate in which a capacitor is built-in or housed (hereinafter also referred to simply as a built-in). We proposed a multilayer printed wiring board in which the conductor circuits are connected via via holes.
In such a multilayer printed wiring board, the distance between the IC chip and the capacitor is shorter than when the capacitor is mounted on the surface, and the loop inductance is sufficiently low even when the IC chip driven at a high frequency is mounted. .
[0005]
In the multilayer printed wiring board, a cavity for incorporating a capacitor such as a counterbore (concave portion) or a through-hole is provided in the substrate, and the capacitor is attached in the cavity via an adhesive. An interlayer resin insulation layer and a conductor circuit are formed on both surfaces of the substrate in which the capacitor is incorporated, and a via hole is provided between the capacitor connection terminal, the upper conductor circuit, and the upper and lower conductor circuits via the interlayer resin insulation layer. Connected through.
[0006]
However, conventional multilayer printed wiring board mounting capacitors are manufactured for surface mounting, and usually only one side of the capacitor contacts the surface of the multilayer printed wiring board. The form was not assumed. Therefore, the surface state of the capacitor is not uniform, and the capacitor surface is usually not exposed to a resin because the electrode made of metal or the dielectric film made of ceramic is exposed. Therefore, when the capacitor is built in the substrate, the capacitor and the interlayer resin insulation are caused by the non-uniform surface state and low affinity with the resin (interlayer resin insulation layer or adhesive). There is a problem that peeling occurs between the layers and the adhesive, or cracks occur in the interlayer resin insulation layer. In this case, the connection between the capacitor terminal and the via hole is interrupted, or the interlayer resin insulation layer is swollen, which causes a decrease in the electrical connectivity and reliability of the multilayer printed wiring board. It was.
[0007]
In addition to the above, other conventional techniques for embedding a capacitor in a substrate include JP-A-6-326472, JP-A-7-263619, JP-A-11-449555, JP-A-11-126978, and JP-A-1 -31868 publication.
[0008]
Japanese Patent Application Laid-Open No. 6-326472 discloses an invention in which a capacitor is embedded in a resin substrate made of glass epoxy, and by embedding the capacitor in the substrate in this way, noise of the power source is reduced, and a chip is provided. It is described that there is no need for a space for mounting a capacitor, and that the effect of reducing the size of the substrate can be obtained.
[0009]
Japanese Patent Application Laid-Open No. 7-263619 discloses an invention in which a capacitor is embedded in a substrate made of ceramic, alumina, or the like, and this capacitor is connected between a power supply layer and a ground layer. Thus, it is described that the effect that the length of the wiring can be shortened and the inductance can be reduced is obtained.
[0010]
However, even in a substrate in which the capacitor described in these publications is embedded, for example, when a reliability test is repeated 1000 times in a heat cycle, the electrical characteristics are deteriorated, cracks are generated in the substrate or the interlayer resin insulation layer, the capacitor There has been a problem that peeling occurs between the substrate and the substrate or the interlayer resin insulation layer.
[0011]
As a result of intensive studies to solve the above problems, the present inventors have formed a coupling agent layer on the capacitor surface, thereby achieving adhesion (affinity) between the capacitor surface and the interlayer resin insulation layer or adhesive. And the present invention has been completed by finding that peeling between the capacitor and the interlayer resin insulation layer and the adhesive is less likely to occur and cracks are less likely to occur in the interlayer resin insulation layer and the like.
[0012]
That is, the capacitor of the present invention is a capacitor that is built in or accommodated in a multilayer printed wiring board,
A coupling agent layer is formed on at least a part of the surface.And
External electrodes are formed in a laminate in which internal electrodes and dielectric films are alternately laminated. The external electrodes are composed of at least two layers, and the outermost layer is a plating layer.It is characterized by that.
[0013]
In the capacitor of the present invention, it is preferable that the coupling agent layer is formed using epoxy silane and / or imidosilane.
[0014]
MaThe topThe external electrode is preferably made of at least copper.
It is also desirable that the innermost layer of the external electrode is a conductive paste layer.
[0015]
The capacitor isthe aboveLaminated bodyOn the part including both end facesCapacitor with external electrodes formedIt is desirable that
The external electrode is preferably formed in a matrix.
[0016]
the aboveThe plating layer is preferably a copper plating layer.
[0017]
In the capacitor of the present invention, it is desirable that a metal coating layer is formed on at least a part of the surface of the external electrode.
[0018]
In the multilayer printed wiring board of the present invention, an interlayer resin insulation layer and a conductor circuit are sequentially formed on a substrate in which a capacitor is incorporated or accommodated, and the capacitor, the conductor circuit, and the upper and lower conductor circuits are via holes. A multilayer printed wiring board connected via
The capacitor is a capacitor according to the present invention.
[0019]
Further, in the method for producing a multilayer printed wiring board according to the first aspect of the present invention, an interlayer resin insulating layer and a conductor circuit are sequentially formed on a substrate in which a capacitor is built or housed. Is a method of manufacturing a multilayer printed wiring board in which the conductor circuit is connected through a via hole,
It includes at least the following steps (A) to (D).
(A) Capacitor attachment process for attaching the capacitor of the present invention to a resin film,
(B) A resin film crimping step for accommodating the capacitor in the recess or the through hole of the substrate in which the recess or the through hole is formed, and crimping the resin film to the substrate,
(C) an interlayer resin insulation layer forming step of forming an opening for a via hole in the resin film to form an interlayer resin insulation layer; and
(D) A conductor circuit forming step of forming a conductor circuit on the surface of the interlayer resin insulating layer including the wall surface of the via hole opening.
[0020]
Further, in the method for producing a multilayer printed wiring board according to the second aspect of the present invention, an interlayer resin insulation layer and a conductor circuit are sequentially formed on a substrate in which a capacitor is built or housed. Is a method of manufacturing a multilayer printed wiring board in which the conductor circuit is connected through a via hole,
The manufacturing method of the multilayer printed wiring board characterized by including the process of following (a)-(e) at least.
(A) a capacitor attaching step for attaching the capacitor of the present invention to the substrate A;
(B) A substrate stacking step of storing a capacitor in the through hole of the substrate B in which the through hole is formed, and stacking the substrate B in which the through hole is formed on the substrate A to which the capacitor is attached;
(C) a resin film crimping step for crimping a resin film to the side of the substrate B on which the through hole is formed, on which the capacitor is exposed,
(D) an interlayer resin insulation layer forming step of forming an opening for a via hole in the resin film to form an interlayer resin insulation layer; and
(E) A conductor circuit forming step of forming a conductor circuit on the surface of the interlayer resin insulation layer including the wall surface of the opening for the via hole.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
First, the capacitor of the present invention will be described.
The capacitor of the present invention is a capacitor built in or accommodated in a multilayer printed wiring board, and is characterized in that a coupling agent layer is formed on at least a part of the surface thereof.
[0022]
Since the coupling agent layer is formed on at least a part of the surface of the capacitor of the present invention, the affinity between the dielectric film made of ceramic or the external electrode made of metal and the adhesive or the interlayer resin insulation layer is high, Peeling does not occur between the capacitor and the interlayer resin insulation layer or adhesive, and cracks do not occur in the interlayer resin insulation layer or adhesive. Therefore, the capacitor of the present invention is suitable for use in a multilayer printed wiring board.
[0023]
The capacitor of the present invention has a coupling agent layer formed on at least a part of its surface.
The coupling agent layer can be formed using, for example, a silane-based, titanium-based, organic phosphoric acid-based, silyl peroxide-based coupling agent, or the like.
[0024]
Examples of the silane coupling agent include imide silane, epoxy silane, vinyltrichlorosilane, vinyltriethoxysilane, γ-methacryloxypropyltrimethoxysilane, γ-glycidoxypropyltrimethoxysilane, and γ-aminopropyltrimethyl. Examples include ethoxysilane, γ-chloropropyltrimethoxysilane, γ-mercaptopropyltrimethoxysilane, methyltrimethoxysilane, phenyltriethoxysilane, trifluoropropylmethyldimethoxysilane, and the like.
Trimethylsilyl isocyanate, dimethylsilyl diisocyanate, vinylsilyl triisocyanate, phenylsilyl triisocyanate and the like can also be used.
[0025]
Examples of titanium coupling agents include isopropyl triisostearoyl titanate, isopropyl tridecylbenzenesulfonyl titanate, isopropyl tris (dioctyl pyrophosphate) titanate, tetraisopropyl bis (dioctyl phosphite) titanate, tetra (2,2- Examples include diallyloxymethyl-1-butyl) bis (di-tridecyl) phosphite titanate, bisdioctylpyrophosphate) oxyacetate titanate, tris (dioctylpyrophosphate) ethylene titanate, and the like.
[0026]
Next, the shape of the capacitor of the present invention will be described with reference to the drawings.
Examples of the capacitor of the present invention include a capacitor in which an external electrode is formed on a portion including both end faces of a laminate in which internal electrodes and dielectric films are alternately laminated. Specifically, for example, FIG. Examples include capacitors having the shapes shown in (a) to (d). 1A to 1D are cross-sectional views schematically showing an example of the capacitor of the present invention.
The capacitor shown in FIG. 1B can be suitably used for a multilayer printed wiring board according to a third embodiment to be described later, and the multilayer printed wiring board shown in FIGS. It can be suitably used for the multilayer printed wiring board of the second and first embodiments. This will be described in detail later.
[0027]
As shown in FIGS. 1A to 1D, the capacitors 120, 320, 220, and 20 are connected to an external electrode including the first electrode 21 and the second electrode 22, and the first electrode 21 and the second electrode 22. The dielectric 23 includes a first conductive film (internal electrode) 24 connected to the first electrode 21 side and a second conductive film 22 connected to the second electrode 22 side. A plurality of two conductive films (internal electrodes) 25 are arranged to face each other.
[0028]
Moreover, the 1st electrode 21 and the 2nd electrode 22 may be comprised from 1 layer, as shown to Fig.1 (a), and are comprised from 2 layers, as shown in FIG.1 (b). Also good. Although not shown, it may be composed of three or more layers.
[0029]
The first electrode 21 and the second electrode 22 are preferably made of at least copper.
This is because copper is preferably used as the material for the conductor circuit that constitutes the multilayer printed wiring board, so that the use of copper as the external electrode of the capacitor makes it difficult for electrical problems to occur.
In addition, as will be described later, when the electrode and the via hole are connected using plating, if the first electrode and the second electrode are made of copper, the adhesion with the copper plating is excellent.
[0030]
Moreover, as shown in FIG.1 (b), when comprised from two layers, or when comprised from three or more layers, it consists of at least two layers including a conductive paste layer and a plating layer. It is desirable. Moreover, you may be comprised from the some electroconductive paste layer.
Capacitors as shown in FIGS. 1A to 1D are generally manufactured by alternately laminating dielectric films and conductive films (internal electrodes) and then forming external electrodes on portions including both end faces. . Here, it is advantageous to form the external electrode by applying a conductive paste because the electrode can be easily formed at low cost.
However, the electrodes formed using the conductive paste are soft, and various disadvantages occur when a capacitor is built in the substrate and a multilayer printed wiring board is manufactured. Therefore, it is desirable that the electrode of the capacitor of the present invention has a structure in which a plating layer is formed on the conductive paste layer. This reason will be described in detail later when the method for producing a multilayer printed wiring board of the present invention is described.
The plating layer is preferably a copper plating layer.
[0031]
Further, as shown in FIG. 1C, part of the surfaces (side surface and bottom surface) of the first electrode 21 and the second electrode 22 of the capacitor 220, and as shown in FIG. Metal coating layers 226 and 26 made of Sn or the like may be formed on the entire surfaces of the first electrode 21 and the second electrode 22.
Thus, by forming the metal coating layers 226 and 26, it is possible to improve rust prevention, solderability, and the like.
In addition, the formation part of the said metal coating layer is not limited to the part shown to FIG.1 (c) and (d), It may be formed in arbitrary parts, for example, it is formed only in the side surface, or a bottom face It may be formed only.
[0032]
The capacitor of the present invention may be a capacitor in which external electrodes are formed in a matrix. Specifically, for example, a capacitor having the shape shown in FIG.
FIG. 15A shows a capacitor before cutting for multi-piece cutting, and FIG. 15B shows one of the capacitors after cutting (a). In FIG. 15A, the alternate long and short dash line indicates a cutting line.
The capacitor 420 shown in FIG. 15 has the first electrode 21 and the second electrode 22 formed on the side edges thereof.
[0033]
FIG. 16 (a) shows a capacitor before cutting for multi-piece cutting, and FIG. 16 (b) shows one of the capacitors after cutting (a). In FIG. 16A, the alternate long and short dash line indicates a cutting line.
A capacitor 520 shown in FIG. 16 has a first electrode 21 and a second electrode 22 formed inside the side edge.
Capacitor 420 and capacitor 520 have a large capacity because the first electrode and the second electrode are formed inside the outer edge thereof.
[0034]
Further, the capacitor in which the external electrodes are formed in a matrix is not a small cut like the capacitor 420 or the capacitor 520, but may be a large-capacity large-sized capacitor 620 as shown in FIG. .
FIG. 17 is a plan view schematically showing an example of the capacitor of the present invention.
The capacitor 620 includes a first electrode 21, a second electrode 22, a dielectric, a first conductive film connected to the first electrode side, a second conductive film connected to the second electrode side, and a first conductive film. And a connection electrode 27 on the upper and lower surfaces of the substrate through a capacitor 620 not connected to the second conductive film.
In the multilayer printed wiring board of the present invention to be described later, when the large-sized capacitor 620 is formed as an inner layer, the capacity is large, and even under heat cycle conditions, the printed wiring board or the like is less likely to be warped.
[0035]
The capacitor in which the external electrodes are formed in a matrix may be a large-capacity large-sized capacitor 720 as shown in FIG.
FIG. 18A shows a capacitor before cutting for multi-piece taking, and FIG. 18B shows a capacitor built in or housed in the multilayer printed wiring board of the present invention after cutting (a). In FIG. 18A, the alternate long and short dash line indicates a cutting line.
The capacitor 720 is obtained by cutting a plurality of capacitors shown in FIG. 18A by cutting lines and then connecting a plurality (three in the example in the figure).
Such a capacitor 720 is also large and has a large capacity, and a multilayer printed wiring board incorporating the capacitor 720 is less likely to warp even under heat cycle conditions.
[0036]
Also in a capacitor in which these external electrodes are formed in a matrix, the external electrode may be composed of one layer or may be composed of two or more layers.
Furthermore, it is desirable that the matrix-like external electrode is made of at least copper, and when the matrix-like external electrode is composed of two or more layers, the external electrode has a plurality of conductive paste layers. It is desirable that the material comprises a material comprising a conductive paste layer and an innermost layer that is a conductive paste layer and an outermost layer that is a plating layer. In this case, the plating layer is preferably a copper plating layer.
Further, the matrix-like external electrode preferably has a metal coating layer formed on a part of its surface.
A capacitor in which such external electrodes are formed in a matrix can be suitably used as a capacitor built in a multilayer printed wiring board of the present invention described later.
[0037]
Since the coupling agent layer is formed on at least a part of the surface of the capacitor of the present invention, the capacitor of the present invention is excellent in adhesiveness (affinity) with an adhesive or an interlayer resin insulating layer. Therefore, the capacitor may be formed with a coupling agent layer on at least a part of the capacitor surface in consideration of adhesion with a required adhesive or the like, but the coupling agent layer is formed on the entire surface of the capacitor. It is desirable that it be formed.
[0038]
Further, it is desirable to form a coupling agent layer suitable for each part in consideration of the difference in material between the external electrode and the dielectric film, that is, the difference between metal and ceramic.
Specifically, it is desirable to form a coupling agent layer using imide silane on the surface of the external electrode, and it is desirable to form a coupling agent layer using epoxy silane on the surface of the dielectric film.
[0039]
It does not specifically limit as a method of forming the said coupling agent layer, What is necessary is just to select suitably according to the kind of coupling agent.
Specifically, for example, a method of immersing a capacitor in a 20 to 50 ° C. solution containing a coupling agent can be used. If the temperature of the solution is less than 20 ° C, the coupling agent is difficult to adhere to the surface of the capacitor. On the other hand, if the temperature exceeds 50 ° C, the coupling agent may be decomposed or the capacitor may be altered or deformed. May end up. A more preferable temperature is 25 to 35 ° C.
Moreover, it can replace with the method of immersing a capacitor | condenser in the solution containing a coupling agent, and can also use the method of spraying and apply | coating this solution on the capacitor | condenser surface.
[0040]
In addition, it is desirable that a portion on which the coupling agent layer is formed on the capacitor surface is previously subjected to pretreatment such as plasma treatment, cleaning treatment, and acid treatment.
This is because by performing such pretreatment, the surface state of the capacitor becomes uniform and becomes a state suitable for forming the coupling agent layer.
[0041]
Examples of the plasma treatment include a method using oxygen, nitrogen, carbon dioxide, carbon tetrachloride, and the like.
Among these, a method using oxygen is desirable. This is because the capacitor is not damaged and can be processed at low cost.
[0042]
In addition, the plasma radiation amount in the plasma treatment is desirably 200 to 1000 W, and the treatment time is desirably 1 to 20 minutes under vacuum. This is because if the treatment time is less than 1 minute, the surface state of the capacitor may not be sufficiently improved, while if it exceeds 20 minutes, the effect of improving the surface state is hardly changed.
Moreover, it is desirable to perform the said process under pressure reduction.
[0043]
Examples of the cleaning treatment include alkali cleaning, acid cleaning, and neutral cleaning.
In the cleaning treatment, the surface state of the capacitor can be brought into a desired state mainly by a degreasing action or a removing action of foreign matters such as an oxide film.
[0044]
The alkali cleaning may be performed by, for example, spraying a solution in which a salt such as caustic soda or alkaline silicic acid, carbonic acid, phosphoric acid or condensed phosphoric acid is added to an anionic surfactant and a nonionic surfactant. It can be carried out by immersing the capacitor inside. Moreover, it can also carry out by the electrolytic cleaning method which added surfactant.
[0045]
The acid cleaning can be performed, for example, by spraying a solution obtained by adding a cationic surfactant to an acid such as sulfuric acid or hydrochloric acid, or immersing a capacitor in the solution.
[0046]
Examples of the acid treatment include a method of immersing in a solution containing at least one acid selected from the group consisting of hydrochloric acid, nitric acid, sulfuric acid, hydrofluoric acid, and phosphoric acid.
In these, the process performed using a sulfuric acid and / or a hydrofluoric acid is desirable.
This is because the contact angle can be improved within the above range in a short time, and no residue remains on the capacitor surface after the treatment.
[0047]
In the acid treatment, the concentration of the acid in the solution is preferably 10% by weight or more.
This is because if the acid concentration is less than 10% by weight, it takes a long time to bring the surface state of the capacitor into a desired state, and as a result, the capacitor may be altered or deformed.
[0048]
Further, the immersion time in the acid solution may be appropriately selected in consideration of the type of acid to be used and its concentration, but it is usually preferably 1 to 15 minutes.
This is because if the immersion time is less than 1 minute, the surface condition of the capacitor may not be sufficiently improved, and if it exceeds 15 minutes, the surface condition of the capacitor hardly changes. The immersion time in the acid solution is more preferably 2 to 10 minutes. This is because the surface condition of the capacitor is improved and the damage to the metal or the like is small.
Moreover, as for the liquid temperature of the solution which consists of the said acid, 20-40 degreeC is desirable.
This is because if the temperature exceeds 40 ° C., the capacitor may be altered or deformed.
[0049]
Such a processing method may be used independently and may be used combining several processing methods. Therefore, each of the external electrode surface, the metal coating layer surface, and the dielectric surface may be treated by different methods.
[0050]
Next, the multilayer printed wiring board of the present invention will be described.
In the multilayer printed wiring board of the present invention, an interlayer resin insulating layer and a conductor circuit are sequentially formed on a substrate in which a capacitor is incorporated or accommodated, and the capacitor, the conductor circuit, and the upper and lower conductor circuits are connected via holes. A multilayer printed wiring board connected to each other,
The capacitor is a capacitor according to the present invention.
[0051]
In the multilayer printed wiring board of the present invention, since the capacitor of the present invention is built in the substrate, peeling occurs between the capacitor and the interlayer resin insulating layer or the adhesive, or the interlayer resin insulating layer or the adhesive is separated. No cracks are generated. Therefore, the multilayer printed wiring board has excellent electrical connectivity and reliability without disconnecting the connection between the capacitor terminal and the via hole or causing cracks or swelling in the interlayer resin insulation layer. .
[0052]
When a surface mounting capacitor is built in the substrate as it is, the capacitor and its peripheral resin (adhesive or interlayer resin insulation layer) However, since the coupling agent layer is formed on the surface, the capacitor of the present invention has excellent adhesion to the peripheral resin.
Therefore, in the multilayer printed wiring board of the present invention, the peripheral resin (interlayer resin insulating layer or adhesive) does not crack or peel off from the capacitor, and the capacitor does not shift.
[0053]
The multilayer printed wiring board of the present invention will be described below with reference to the drawings.
First, a first embodiment of the multilayer printed wiring board of the present invention will be described.
FIG. 2 is a cross-sectional view schematically showing an example of the multilayer printed wiring board of the present invention. FIG. 3 is a schematic view showing a state in which an IC chip is mounted on the multilayer printed wiring board shown in FIG. FIG.
[0054]
As shown in FIG. 2, the multilayer printed wiring board 10 is formed with a capacitor 20, a substrate 30 containing the capacitor 20, and interlayer resin insulation layers 40 and 60. A via hole 46 and a conductor circuit 48 are formed in the interlayer resin insulation layer 40, and a via hole 66 and a conductor circuit 68 are formed in the interlayer resin insulation layer 60. A through hole 36 is formed to connect the upper and lower conductor circuits via the substrate 30.
[0055]
Further, a solder resist layer 70 is disposed on the interlayer resin insulating layer 60, and a conductor circuit 68 (including the via hole 66) under the opening 71 of the solder resist layer 70 is provided with a daughter board, a mother board or the like. Solder bumps 76 for connecting to an external substrate are provided via a nickel plating layer and a gold plating layer.
[0056]
In the multilayer printed wiring board 10, the capacitor 20 is built in the substrate via the adhesive 32, and the capacitor 20 is the capacitor of the present invention. For this reason, the adhesiveness between the capacitor 20 and the adhesive 32 is high, and even under heat cycle conditions, peeling occurs on the contact surface between the capacitor 20 and the adhesive 32 or cracks occur in the adhesive. There is no. Therefore, the connection between the capacitor terminal and the via hole is not cut off, and the interlayer resin insulating layer is not cracked or swollen, and the multilayer printed wiring board 10 is excellent in electrical connectivity and reliability. .
[0057]
Further, as shown in FIG. 3, in the multilayer printed wiring board on which the IC chip 90 is mounted and attached to the daughter board, the bumps 76 formed in the openings 71 of the upper solder resist layer 70 and the IC chip 90 Pads 92S1, 92S2, 92P1, and 92P2 are connected. The bumps 76 formed in the openings 71 of the lower solder resist layer 70 are connected to the pads 96S1, 96S2, 96P1, and 96P2 of the daughter board 94.
[0058]
Also, the signal pad 92S2 of the IC chip 90 shown in FIG. 3 is a signal pad of the daughter board 94 via the bump 76-conductor circuit 68-via hole 66-through hole 36-via hole 66-bump 76. It is connected to 96S2. On the other hand, the signal pad 92S1 of the IC chip 90 is connected to the signal pad 96S1 of the daughter board 94 via the bump 76-via hole 66-through hole 36-via hole 66-bump 76.
[0059]
The power supply pad 92P1 of the IC chip 90 is connected to the first electrode 21 of the chip capacitor 20 via the bump 76-via hole 66-conductor circuit 48-via hole 46. On the other hand, the power supply pad 96P1 of the daughter board 94 is connected to the first electrode 21 of the chip capacitor 20 via the bump 76-via hole 66-through hole 36-conductor circuit 48-via hole 46.
[0060]
The power supply pad 92P2 of the IC chip 90 is connected to the second electrode 22 of the chip capacitor 20 via the bump 76, the via hole 66, the conductor circuit 48, and the via hole 46. On the other hand, the power supply pad 96P2 of the daughter board 94 is connected to the second electrode 22 of the chip capacitor 20 via the bump 76-via hole 66-through hole 36-conductor circuit 48-via hole 46.
[0061]
Therefore, in the multilayer printed wiring board of the present invention, as shown in FIG. 14C, by incorporating the capacitor 20 in the substrate, the capacitor 20 is arranged directly under the IC chip 90, and the capacitor 20 is interposed. The distance between the power supply and the power supply terminal 92E / earth terminal 92P of the IC chip 90, that is, the loop length that determines the loop inductance is further shortened as shown by the solid line in FIG.
As a result, even when the IC chip 90 that is driven at a high frequency is mounted, the loop inductance is sufficiently low, and power can be instantaneously supplied to the IC chip side.
[0062]
Further, by providing the through hole 36 between the capacitors 20, the signal line can be prevented from passing through the capacitor. Therefore, it is possible to prevent reflection due to impedance discontinuity due to the high dielectric material that occurs when the signal line passes through the capacitor, and signal propagation delay due to passage through the high dielectric material.
[0063]
Next, a second embodiment of the multilayer printed wiring board of the present invention will be described.
FIG. 4 is a cross-sectional view schematically showing an example of the multilayer printed wiring board of the present invention.
The multilayer printed wiring board 110 of the second embodiment shown in FIG. 4 is substantially the same as the multilayer printed wiring board 10 of the first embodiment.
However, the multilayer printed wiring board 110 differs in the method of incorporating the capacitor.
That is, in the first embodiment, the first electrode 21 and the second electrode 22 of the capacitor and the via hole 46 are electrically connected using an adhesive material 34 such as solder or conductive paste ( However, in the multilayer printed wiring board of the second embodiment, the first electrode 21 and the second electrode 22 are plated to electrically connect the via hole. Therefore, capacitors suitable for each built-in method are used.
[0064]
Therefore, the capacitors used in the first and second embodiments will be described.
In the capacitor 20 used in the first embodiment, as shown in FIG. 1 (d), a metal layer 26 made of Sn or the like is formed on the outer periphery of the first electrode 21 and the second electrode 22. This is because when the metal layer 26 made of Sn or the like is provided, solderability is improved and a rust prevention effect is provided.
Note that a capacitor used in the case of connecting the electrode and the via hole using an adhesive material such as solder or conductive paste preferably has no coupling agent layer formed on the contact portion of the adhesive material.
[0065]
On the other hand, as shown in FIG. 1C, the capacitor 220 used in the second embodiment has a metal layer 226 formed so that the upper surfaces of the first electrode and the second electrode are exposed.
This is because the exposed plating layer is suitable for connecting electrodes and via holes using plating. When connecting electrodes and via holes by plating, the connection resistance should be reduced. Because you can.
[0066]
Next, a third embodiment of the multilayer printed wiring board of the present invention will be described.
FIG. 5 is a sectional view schematically showing an example of the multilayer printed wiring board of the present invention.
The multilayer printed wiring board 210 of the third embodiment shown in FIG. 5 is substantially the same as the multilayer printed wiring board of the second embodiment.
However, the multilayer printed wiring board 210 differs in the method of incorporating a capacitor. That is, in the second embodiment, only the IC chip side (upper side) of the first electrode 21 and the second electrode 22 is electrically connected (see FIG. 4). However, in the present embodiment, the first electrode 21 is connected. The both sides of the second electrode 22 on the IC chip side (upper side) and the daughter board side (lower side) are electrically connected. In this embodiment, since the external electrode and the via hole are connected by plating, a capacitor having no metal coating layer formed on the outer periphery of the external electrode is used as shown in FIG. In the multilayer printed wiring board having such a configuration, the external electrodes 21 and 22 of the capacitor 320 have a so-called through-hole function, and the package structure can be simplified. it can.
[0067]
In addition, embodiment of the multilayer printed wiring board of this invention is not limited to the said 1st-3rd embodiment, For example, the form by which many capacitors were incorporated in one cavity in parallel may be sufficient. In the multilayer printed wiring board of such an embodiment, the shortage of the power supply voltage can be compensated, and malfunction of the IC can be eliminated. Therefore, such a multilayer printed wiring board can be suitably used for a flip chip.
Moreover, the embodiment of the multilayer printed wiring board of the present invention may have a form in which a capacitor having external electrodes formed in a matrix is incorporated as shown in FIGS.
[0068]
In such a multilayer printed wiring board, since the capacitor is built in the board, when the IC chip is mounted, the distance between the IC chip and the capacitor is short, and even when the IC chip driven at a high frequency is mounted. The loop inductance is sufficiently low. In addition, the capacitor built in the substrate is the capacitor of the present invention, and since the coupling agent layer is formed on the surface thereof, the adhesion between the capacitor and the peripheral resin is high, and even under heat cycle conditions, Peeling does not occur on the contact surface between the capacitor and the adhesive or interlayer resin insulation layer, and cracks do not occur in the adhesive or interlayer resin insulation layer. Accordingly, the connection between the external electrode of the capacitor and the via hole is not cut off, and the interlayer resin insulating layer is not swollen, and the electrical connectivity and reliability are excellent.
[0069]
Next, members other than the capacitor constituting the multilayer printed wiring board of the present invention will be described.
In the multilayer printed wiring board, an interlayer resin insulating layer and a conductor circuit are sequentially formed on a substrate in which a capacitor is incorporated or accommodated.
[0070]
The substrate is not particularly limited as long as it is generally used for printed wiring boards. For example, epoxy resin, bismaleimide / triazine (BT) resin, phenol resin, etc., reinforcing material such as glass cloth, or core material And a substrate formed by laminating a prepreg impregnated with an epoxy resin. Moreover, resin which does not impregnate a reinforcing material or a core material can also be used. A double-sided copper-clad laminate, a single-sided plate, a resin plate without a metal film, a resin film, or the like may be used.
[0071]
Moreover, although the capacitor | condenser is incorporated or accommodated in the said board | substrate, it is desirable here for the said capacitor | condenser to be incorporated or accommodated via the adhesive agent. This is because displacement of the capacitor is less likely to occur.
It does not specifically limit as said adhesive agent, For example, an epoxy resin, a phenol resin, etc. are mentioned.
[0072]
Moreover, as a material of the said interlayer resin insulation layer, what consists of resin composites, such as thermosetting resins, such as an epoxy resin, BT resin, a polyimide resin, an olefin resin, a thermosetting resin, etc., etc. Is mentioned. A photosensitive resin can also be used.
[0073]
Specific examples of the polyolefin resin include polyethylene, polypropylene, polyisobutylene, polybutadiene, polyisoprene, cycloolefin resin, and copolymers of these resins.
As a commercial item of the said polyolefin resin, the Sumitomo 3M brand name: 1592 etc. are mentioned, for example. Moreover, as a commercial item of thermoplastic polyolefin-type resin whose melting | fusing point is 200 degreeC or more, the brand name: TPX (melting | fusing point 240 degreeC) made by Mitsui Petrochemical Industry Co., Ltd. Melting point of 270 ° C.).
[0074]
Of these, cycloolefin resins are desirable.
Cycloolefin resin has a low dielectric constant, and even when high-frequency signals in the GHz band are used, signal delays and signal errors are less likely to occur, and mechanical properties, particularly high rigidity, make it a solid interlayer resin insulator. As a result, the connection reliability of the multilayer printed wiring board can be sufficiently ensured.
[0075]
In addition, since the cycloolefin resin is excellent in adhesion to the conductor circuit, the interlayer resin insulation layer can be prevented from peeling from the conductor circuit, and cracks in the interlayer resin insulation layer due to the peeling can be prevented. Occurrence and the like can also be prevented.
Furthermore, since the cycloolefin resin has a low water absorption rate, the electrical insulation between the conductor circuits is increased and the reliability is improved.
[0076]
The cycloolefin-based resin is preferably a homopolymer or copolymer of a monomer composed of 2-norbornene, 5-ethylidene-2-norbornene, or a derivative thereof. Examples of the derivative include those in which an amino group for forming a bridge, a maleic anhydride residue, or a maleic acid-modified one is bonded to a cycloolefin such as 2-norbornene.
Examples of the monomer for synthesizing the copolymer include ethylene and propylene.
[0077]
The cycloolefin-based resin may be a mixture of two or more of the above-described resins, or may include a resin other than the cycloolefin-based resin.
Moreover, when the said cycloolefin resin is a copolymer, a block copolymer may be sufficient and a random copolymer may be sufficient.
[0078]
The cycloolefin resin is preferably a thermosetting cycloolefin resin. This is because by heating to form a crosslink, the rigidity becomes higher and the mechanical properties are improved.
The glass transition temperature (Tg) of the cycloolefin resin is preferably 130 to 200 ° C.
[0079]
The cycloolefin-based resin may not contain a filler or the like, or may contain a flame retardant such as aluminum hydroxide, magnesium hydroxide, or phosphate ester.
[0080]
The resin composite includes a thermoplastic resin and a thermosetting resin.
Examples of the thermoplastic resin include polysulfone (PSF), polyether sulfone (PES), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenylene ether (PPE), polyetherimide (PI), phenoxy resin, A fluororesin etc. are mentioned.
Of these, polysulfone (PSF), polyethersulfone (PES), polyetherimide (PI) and / or phenoxy resin are desirable. This is because it is excellent in heat resistance and insulation and has a high toughness value, and is therefore particularly suitable for forming an interlayer resin insulation layer having excellent crack resistance and shape retention.
[0081]
As said thermosetting resin, an epoxy resin, a phenol resin, a polyimide resin etc. are mentioned, for example. Further, the thermosetting resin may be a sensitized resin, and specific examples thereof include those obtained by acrylate reaction of methacrylic acid, acrylic acid, and the like with a thermosetting group. In particular, an acrylated epoxy resin is desirable. Among these, an epoxy resin having two or more epoxy groups in one molecule is more desirable.
[0082]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0083]
The mixing ratio of the thermoplastic resin and the thermosetting resin in the resin composite is preferably thermosetting resin / thermoplastic resin = 95/5 to 50/50. This is because a high toughness value can be ensured without impairing heat resistance.
[0084]
Specific examples of the resin composite include, for example, coarse particles in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are dispersed in a resin that is hardly soluble in an acid or oxidizing agent (hereinafter referred to as a poorly soluble resin). Examples thereof include a resin composition for forming a chemical surface.
As used herein, the terms “slightly soluble” and “soluble” refer to those having a relatively high dissolution rate as “soluble” for convenience when immersed in the same roughening solution for the same time. The slow one is called “slightly soluble” for convenience.
[0085]
Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
[0086]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0087]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the present specification, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0088]
The soluble resin particle is not particularly limited as long as it has a higher dissolution rate than the hardly soluble resin when immersed in a solution comprising an acid or an oxidizing agent. Specific examples thereof include, for example, an epoxy resin, Examples include phenol resins, phenoxy resins, polyimide resins, polyphenylene resins, polyolefin resins, fluororesins, amino resins (melamine resins, urea resins, guanamine resins), and the like. It may be a mixture of two or more resins.
[0089]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified various modified polybutadiene rubber, carboxyl group-containing (meth) acrylonitrile-butadiene rubber, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acids can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface. As described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.
[0090]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0091]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate. Examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0092]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0093]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Since both have low conductivity, insulation between the upper and lower conductor circuits can be ensured, and thermal expansion can be easily adjusted with the hardly soluble resin, and no cracks are generated in the interlayer resin insulation layer. This is because no peeling occurs between the resin insulating layer and the conductor circuit.
[0094]
The hardly soluble resin may be any resin that can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulating layer. The thermoplastic resin and the thermosetting resin may be used. Mixtures with functional resins can be used.
[0095]
When the roughened surface forming resin composition is used as the resin composite, the soluble particles are desirably dispersed almost uniformly in the hardly soluble resin. This is because a roughened surface having unevenness with uniform roughness can be formed, and adhesion with a conductor circuit including a via hole can be secured.
Moreover, you may use the film containing a soluble particle only in the surface layer part which forms a roughening surface. In this case, since the portions other than the surface layer portion of the film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits through the interlayer resin insulation layer is reliably maintained.
[0096]
The mixing weight ratio of the soluble particles is preferably 5 to 50% by weight, more preferably 10 to 40% by weight, based on the solid content of the hardly soluble resin.
When the mixing weight ratio of the soluble particles is less than 5% by weight, a roughened surface with sufficient roughness may not be formed. When the mixing weight ratio exceeds 50% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. When the roughened surface is formed, it melts to the deep part of the interlayer resin insulation layer, and insulation between the upper and lower conductor circuits through the resin insulation layer cannot be secured, causing a short circuit. There is.
[0097]
The roughened surface-forming resin composition preferably contains a curing agent, other components, and the like in addition to the thermoplastic resin and the thermosetting resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0098]
As for content of the said hardening | curing agent, it is desirable that it is 0.05 to 10 weight% with respect to the resin composition for roughening surface formation. If it is less than 0.05% by weight, the resin composite is not sufficiently cured when the interlayer resin insulation layer is formed, and a roughened surface is formed on the surface of the interlayer resin insulation layer by using an acid or an oxidant. May increase the degree of penetration of the resin film, and the insulating properties of the interlayer resin insulation layer may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may change the composition of the resin, which may lead to a decrease in reliability.
[0099]
Examples of the other components include fillers such as inorganic compounds and resins that do not affect the formation of the roughened surface.
Examples of the inorganic compound include silica, alumina, and dolomite. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By containing these fillers, the thermal expansion coefficient is matched, heat resistance and chemical resistance are improved, and the performance of the multilayer printed wiring board can be further improved.
[0100]
Moreover, the said resin composition for roughening surface formation may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more.
[0101]
Moreover, as a material of the said conductor circuit, tin, zinc, copper, nickel, cobalt, thallium, lead etc. are mentioned, for example. Among these, those made of copper, copper and nickel are desirable from the viewpoint of excellent electrical characteristics, economical efficiency, and the like.
Moreover, the said conductor circuit may be a single layer, may be composed of two or more layers, and is preferably composed of two layers of an electroless copper plating layer and an electrolytic copper plating layer.
[0102]
In the multilayer printed wiring board, the capacitor, the conductor circuit, and the upper and lower conductor circuits are connected to each other through a via hole.
Examples of the material of the via hole include the same materials as the conductor circuit. Further, the via hole may be a single layer or may be composed of two or more layers.
The multilayer printed wiring board of this invention which consists of such a structure can be manufactured, for example using the manufacturing method of the multilayer printed wiring board of the 1st or 2nd this invention mentioned later.
[0103]
Next, the manufacturing method of the multilayer printed wiring board of 1st this invention is demonstrated.
In the method for producing a multilayer printed wiring board according to the first aspect of the present invention, an interlayer resin insulation layer and a conductor circuit are sequentially formed on a substrate in which a capacitor is incorporated or accommodated, and the capacitor, the conductor circuit, and the upper and lower conductors A method of manufacturing a multilayer printed wiring board in which a circuit is connected via a via hole,
It includes at least the following steps (A) to (D).
(A) Capacitor attachment process for attaching the capacitor of the present invention to a resin film,
(B) A resin film crimping step for accommodating the capacitor in the recess or the through hole of the substrate in which the recess or the through hole is formed, and crimping the resin film to the substrate,
(C) an interlayer resin insulation layer forming step of forming an opening for a via hole in the resin film to form an interlayer resin insulation layer; and
(D) A conductor circuit forming step of forming a conductor circuit on the surface of the interlayer resin insulating layer including the wall surface of the via hole opening.
[0104]
In the method for producing a multilayer printed wiring board according to the first aspect of the present invention, peeling occurs between the multilayer printed wiring board of the present invention, that is, the capacitor and the adhesive or interlayer resin insulation layer, or the adhesive or interlayer resin insulation. A multilayer printed wiring board in which no cracks are generated in the layer can be produced.
Here, the steps (A) to (D) will be described first, and all manufacturing steps of the multilayer printed wiring board including the steps (A) to (D) will be described in detail later.
[0105]
In the step (A), that is, the capacitor attaching step, the capacitor of the present invention is attached to the resin film.
Here, a conductor layer is formed in advance on a part of the surface of the resin film, and a capacitor is attached to the conductor layer via an adhesive material such as a solder paste. In addition, since the capacitor is attached via solder paste or the like, it is desirable to use a capacitor having a metal coating layer made of Sn.
Moreover, you may attach a capacitor | condenser directly to a resin film, without forming a conductor layer in a resin film. In this case, it is desirable to attach the capacitor via an adhesive such as an epoxy resin or a phenol resin.
[0106]
As a method of forming the conductor layer on a part of the surface of the resin film, for example, after forming the conductor film on the entire surface of the resin film by performing electroless plating, sputtering, or attaching a metal foil A method of performing pattern etching can be used.
Moreover, after forming a conductor film on the entire surface of the resin film by electroless plating or the like, the thickness of the conductor film may be adjusted by performing electrolytic plating.
In addition, the resin film which attaches a capacitor at this process becomes an interlayer resin insulation layer of the multilayer printed wiring board manufactured by the present invention.
[0107]
In the step (B), that is, the resin film crimping step, a capacitor is housed in the recess or the through hole of the substrate in which the recess or the through hole is formed, and the resin film is crimped to the substrate.
Therefore, in this step, a substrate having a recess or a through hole is prepared separately from the resin film to which the capacitor is attached.
The substrate on which the concave portion is formed can be formed, for example, by bonding a prepreg having a through hole or a concave portion and a prepreg having no through hole or the like, or by injection molding.
In addition, the substrate on which the through hole is formed can be obtained by forming a through hole in the substrate with a drill or the like, injection molding or the like.
[0108]
At this time, by previously applying an adhesive to the inner wall surface of the recess and the through hole and / or the capacitor surface, the capacitor can be adhered to the inner wall surface of the recess and the through hole via the adhesive.
The capacitor used here is the capacitor according to the present invention, and the coupling agent layer is formed on the surface thereof, so that the adhesiveness with the adhesive is excellent. This is because the coupling agent layer has affinity with both the capacitor and the adhesive.
At this time, the resin film may be pressure-bonded to the surface opposite to the surface to which the resin film to which the capacitor of the substrate is attached is bonded. This is because an interlayer resin insulation layer is formed on both sides of the substrate. In particular, when a resin film is pressure-bonded to a substrate in which through holes are formed, it is desirable to pressure-bond the resin film on both surfaces of the substrate. Moreover, the cured layer of a resin film is formed by heat-curing as needed after this. Specifically, when a resin film made of a thermosetting resin or a resin composite is used, heat curing is performed to form a cured layer of the resin film.
In the present specification, hereinafter, a resin film layer formed by press-bonding a resin film made of a thermoplastic resin is also referred to as a cured layer of the resin film.
[0109]
In the resin film press-bonding step, when a substrate having a through hole is used, a multilayer printed wiring board in which the external electrode of the capacitor has a function as a so-called through hole can be preferably manufactured.
[0110]
Further, the step (C), that is, the interlayer resin insulation layer forming step is performed to form a via hole opening in the resin film to form an interlayer resin insulation layer.
The formation of the via hole opening can be performed using, for example, laser processing. At this time, examples of the laser to be used include a carbon dioxide laser, an ultraviolet laser, and an excimer laser. Among these, an excimer laser and a short pulse carbon dioxide laser are desirable.
[0111]
As will be described later, the excimer laser can form a large number of via hole openings at a time by using a mask or the like in which a through hole is formed in a portion where a via hole opening is formed. This is because the pulse carbon dioxide laser has a small amount of resin remaining in the via hole opening, and damage to the resin around the laser irradiation site is particularly small.
[0112]
When the via hole opening is formed in this step, the external electrode of the capacitor is formed on the bottom surface of the via hole opening if a resin film directly attached with a capacitor without using a conductor layer is used in the step (A). It will be exposed.
Here, when the external electrode of the capacitor is composed only of the conductive paste, the following inconvenience occurs due to the soft conductive paste.
That is, when the cured film of the resin film is irradiated with a laser, since the conductive paste existing under the cured layer of the resin film is soft, the cured layer of the resin film is pushed into the conductive paste layer, As a result, a resin residue may be generated in the conductive paste layer at the end of the laser treatment. Such a resin residue causes a connection failure when a via hole is formed, leading to a decrease in reliability of the multilayer printed wiring board.
[0113]
However, in the case of using a capacitor in which the external electrode is composed of at least two layers, the innermost layer is a conductive paste layer, and the outermost layer is a plating layer, the capacitor is exposed on the bottom surface of the via hole opening. Is a plating layer, and since this plating layer is harder than the conductive paste layer, the above-mentioned inconvenience is hardly generated, and a multilayer printed wiring board having higher reliability can be manufactured.
In some cases, the external electrode may be composed only of a conductive paste. In this case, the conductive paste desirably contains Ni, Cu, Ag, and Pd, and may contain Cu. More desirable. This is because the via hole is usually formed using copper, so that the electrical characteristics are hardly deteriorated and peeling between the via hole and the external electrode hardly occurs. Similarly, peeling is unlikely to occur even under heat cycle conditions.
[0114]
When forming an opening for a via hole using an excimer laser, it is desirable to use a hologram type excimer laser. The hologram method is a method of irradiating a target object with laser light through a hologram, a condensing lens, a laser mask, a transfer lens, and the like. Can be formed efficiently.
[0115]
When a carbon dioxide laser is used, the pulse interval is 10^-Four-10^-8It is desirable to be seconds. In addition, the time for irradiating the laser for forming the opening is desirably 10 to 500 μm seconds.
Further, the through-hole of the mask in which the through-hole is formed in the portion forming the opening for the via hole needs to be a perfect circle in order to make the spot shape of the laser light a perfect circle, and the diameter of the through-hole is About 0.1 to 2 mm is desirable.
[0116]
In addition, by irradiating laser light through an optical system lens and a mask, a large number of openings for via holes can be formed at one time. This is because laser light having the same intensity and the same irradiation intensity can be irradiated to a plurality of portions through the optical system lens and the mask.
[0117]
Further, when the resin film is made of a photosensitive resin, the via hole opening may be formed by exposure and development processing.
In this case, it is desirable that the resin film is laminated on the substrate, pressed, and then subjected to exposure / development processing before heat curing.
This is because a completely cured layer is not suitable for forming an opening by exposure / development processing, and an opening having a desired shape cannot be formed.
[0118]
In addition, even when the via hole opening is formed using exposure and development processing, if the external electrode of the capacitor is exposed on the bottom surface of the via hole opening, the capacitor is composed of at least two layers. It is desirable that the innermost layer is a conductive paste layer and the outermost layer is a plating layer.
The conductive paste usually contains conductive particles such as a spherical shape and a crushed shape, and there is a gap between the conductive particles. Therefore, when the resin film is laminated on the substrate and pressed, the resin film also enters the gaps between the conductive particles. As described above, the resin film that has entered the gaps between the conductive particles is difficult to remove by exposure and development, and as a result, a resin residue is generated in the conductive paste layer when the via hole opening is formed. There is.
However, such inconveniences are unlikely to occur in a plating layer that is harder than the conductive paste.
[0119]
Further, when the via hole opening is formed using the exposure and development process, if the external electrode is exposed on the bottom surface of the via hole opening, the coupling agent layer is not formed on the exposed surface of the external electrode. It is desirable to use a capacitor. In the exposure and development process, the coupling agent layer cannot be removed, and if a via hole is formed while the coupling agent layer is present, a conduction failure may occur between the external electrode and the via hole, or between the two. This is because peeling may occur.
However, when the via hole opening is formed by laser processing, a capacitor in which a coupling agent layer is formed on the exposed surface of the external electrode may be used. This is because the coupling agent layer can also be removed during the laser treatment.
[0120]
Moreover, after forming the opening for via holes, a desmear process is performed as needed. The desmear treatment can be carried out using an oxidizing agent comprising an aqueous solution such as chromic acid or permanganate. Also oxygen plasma, CF_Four You may process by the mixed plasma of oxygen and oxygen, corona discharge, etc. Further, the surface can be modified by irradiating with ultraviolet rays using a low-pressure mercury lamp.
[0121]
Further, if necessary, a roughened surface may be formed on the surface of the interlayer resin insulating layer (including the inner wall surface of the via hole opening).
By forming the roughened surface, the adhesion with a conductor circuit (including via holes) formed on the interlayer resin insulating layer in a later step is further improved.
As a method for forming the roughened surface, for example, when the polyolefin-based resin is used as a material for an interlayer resin insulating layer, the roughened surface can be formed by plasma treatment. When the resin composition for use is used, a roughened surface can be formed using an acid or an oxidizing agent.
[0122]
After completing the via hole opening forming step, through holes for through holes are formed in a substrate having an interlayer resin insulating layer formed on both sides thereof, and the through hole for through holes are simultaneously performed when performing the conductor circuit forming step described below. A conductor layer may also be formed on the wall surface to form a through hole.
The through hole for the through hole can be formed by drilling, laser processing, or the like. When a substrate made of a resin impregnated with a reinforcing material or a core material is used, it is desirable to use drilling.
The diameter of the through hole for the through hole is preferably 50 to 500 μm.
When the through-hole through hole is formed, a desmear process or a roughened surface forming process may be performed before the conductor layer is formed on the wall surface of the through-hole through hole.
[0123]
Furthermore, the process of said (D), ie, a conductor circuit formation process, is performed, and a conductor circuit is formed in the surface of the resin film containing the wall surface of the said opening for via holes.
Through this step, a conductor circuit can be formed on the interlayer resin insulation layer, and a via hole for electrically connecting the conductor circuit and the capacitor can be formed.
[0124]
Hereinafter, this conductor circuit forming step will be described in detail.
First, a thin film conductor layer is formed on the surface of the interlayer resin insulation layer (including the via hole opening and the inner wall surface of the through hole through hole) by electroless plating, sputtering or the like. The thin film conductor layer may be a single layer or may be composed of two or more layers.
The thin film conductor layer can be formed by, for example, electroless plating or sputtering.
In addition, when forming a thin film conductor layer by electroless plating, it is desirable to provide a catalyst nucleus such as a palladium catalyst on the surface of the interlayer resin insulation layer in advance.
[0125]
The thickness of the thin film conductor layer is preferably 0.6 to 1.2 μm when the thin film conductor layer is formed by electroless plating, and 0.1 to 1.0 μm when formed by sputtering. Is desirable.
[0126]
Next, a plating resist is formed on a part of the interlayer resin insulation layer on which the thin film conductor layer is formed by using a dry film, and then electrolytic plating is performed using the thin film conductor layer as a plating lead, and the plating resist non-forming portion is formed. An electrolytic plating layer is deposited.
At this time, the via hole opening may be filled with electrolytic plating to form a field via structure. After filling the via hole opening with a conductive paste, a lid plating layer is formed thereon to form a field via structure. Also good. By forming the field via structure, a via hole can be provided immediately above the via hole.
[0127]
Next, after removing the plating resist, the thin film conductor layer existing under the plating resist is dissolved and removed by etching, and a conductor circuit (including via holes and through holes) composed of the thin film conductor layer and the electrolytic plating layer is formed. Form.
In addition, when a thin film conductor layer is formed by electroless plating after depositing the catalyst, the catalyst on the interlayer resin insulating layer may be removed using an acid or an oxidizing agent. By removing the catalyst, it is possible to prevent a reduction in electrical characteristics.
[0128]
In addition, after forming a thin film conductor layer as described above, a plating resist is formed, and a conductive circuit is formed using the following method instead of a method of forming a conductive circuit by performing electrolytic plating treatment and etching treatment. May be.
[0129]
That is, first, a thin film conductor layer is formed using the same method as described above. Next, using this thin film conductor layer as a plating lead, an electrolytic plating layer is formed on the entire surface of the thin film conductor layer, and further, an etching resist is formed on the electrolytic plating layer using a dry film. The conductor circuit may be formed by etching away the layer and the electroless plating layer.
Through the steps (A) to (D), the interlayer resin insulating layer and the conductor circuit can be formed on the substrate containing the capacitor.
[0130]
Next, after all the manufacturing steps of the manufacturing method of the multilayer printed wiring board of the present invention including the steps (A) to (D), that is, after the steps (A) to (D), the multilayer printed wiring board is obtained. The entire manufacturing process until the process is completed will be described in the order of processes.
[0131]
(1) After the steps (A) to (D), a roughened surface is formed on the surfaces of the conductor circuit, the via hole, and the through hole, if necessary.
The roughened surface can be formed by etching, blackening reduction, plating, or the like.
[0132]
The said etching process can be performed using the etching liquid containing an organic acid and a cupric complex, for example.
Examples of the organic acid include formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, Examples include lactic acid, malic acid and sulfamic acid.
These may be used alone or in combination of two or more. In the mixed solution, the content of the organic acid is preferably 0.1 to 30% by weight. This is because the solubility of oxidized copper can be maintained and catalyst stability can be ensured.
[0133]
The cupric complex is preferably an azole cupric complex. This cupric complex of azoles acts as an oxidizing agent that oxidizes metallic copper and the like. Examples of azoles include diazole, triazole, tetrazole and the like. Among these, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, and 2-undecylimidazole are desirable. In the etching solution, the content of the cupric complex is preferably 1 to 15% by weight. This is because it is excellent in solubility and stability and can also dissolve noble metals such as Pd constituting the catalyst nucleus.
[0134]
Specific methods of the blackening reduction treatment include NaOH (10 g / l), NaClO.₂ (40 g / l), Na_Three PO_Four A blackening treatment using an aqueous solution containing (6 g / l), and NaOH (10 g / l), NaBH_Four And a method of performing a reduction treatment using an aqueous solution containing (6 g / l) as a reduction bath.
[0135]
Specific methods of the plating treatment include copper sulfate (1-40 g / l), nickel sulfate (0.1-6.0 g / l), citric acid (10-20 g / l), sodium hypophosphite. (= 10-100 g / l), boric acid (10-40 g / l) and surfactant (manufactured by Nissin Chemical Industry Co., Surfinol 465) (0.01-10 g / l), electroless at pH = 9 The method etc. which perform electroless plating with a plating bath are mentioned.
[0136]
(2) Next, when a through hole is formed in the step (D), the inside of the through hole is filled with a resin filler, and a resin film is pasted on both sides of the substrate on which the conductor circuit is formed. The
As the resin filler, there can be used a non-conductive resin whose main component is a resin such as an epoxy resin, a conductive resin containing a metal paste such as copper, and the like. Moreover, you may use the resin filler which mix | blended inorganic fillers, such as a silica, with the thermosetting epoxy resin, and matched the thermal expansion coefficient with the interlayer resin insulation layer and the board | substrate.
Moreover, as a resin film, the thing similar to a resin film can be used.
[0137]
(3) Next, if necessary, after curing the resin film, the steps (c) and (d) and the steps (1) and (2) are repeated to further increase the interlayer A resin insulating layer and a conductor circuit (including via holes) are formed.
In this step, the through hole for the through hole may or may not be formed.
[0138]
(4) Next, a solder resist layer having an opening is formed on the substrate surface including the outermost conductor circuit. As said soldering resist layer, what consists of a polyphenylene ether resin, polyolefin resin, a fluorine resin, a thermoplastic elastomer, a soldering resist resin composition etc. is mentioned, for example.
The solder resist layer is formed by applying an uncured resin (solder resist resin composition) by a roll coater method, or by thermocompression bonding an uncured resin film, and then opening it by laser processing, exposure / development processing, or the like. It forms by performing a process and also performing a hardening process etc.
[0139]
Examples of the solder resist resin composition include (meth) acrylates of novolak-type epoxy resins, imidazole curing agents, bifunctional (meth) acrylate monomers, and heavy (meth) acrylate esters having a molecular weight of about 500 to 5,000. Examples include thermosetting resins composed of coalesced bisphenol-type epoxy resins, photosensitive monomers such as polyvalent acrylic monomers, paste-like fluids containing glycol ether solvents, and the like. It is desirable that the pressure is adjusted to 10 Pa · s.
[0140]
Examples of the (meth) acrylate of the novolak type epoxy resin include an epoxy resin obtained by reacting a glycidyl ether of phenol novolak or cresol novolak with acrylic acid or methacrylic acid.
Moreover, it does not specifically limit as said bifunctional (meth) acrylic acid ester monomer, For example, various diols, ester of acrylic acid, methacrylic acid, etc. are mentioned.
The opening is formed by exposure, development processing, laser processing, or the like.
[0141]
(5) Thereafter, a solder pad is provided by forming a nickel plating layer, a gold plating layer, etc. on the conductor circuit in the opening of the solder resist layer, and a solder paste is printed on the solder pad. A solder bump is formed by reflowing at ℃. Thereby, a multilayer printed wiring board having an IC chip built in the substrate and having solder bumps can be obtained.
Also, after solder paste is printed in the opening of the solder resist layer, a conductive pin is placed in the opening and reflowed at 230 ° C., thereby connecting to an external terminal PGA (Pin Grid Array) It is good also as a multilayer printed wiring board by which is arranged.
[0142]
Next, the manufacturing method of the multilayer printed wiring board of 2nd this invention is demonstrated.
In the method for producing a multilayer printed wiring board according to the second aspect of the present invention, an interlayer resin insulation layer and a conductor circuit are sequentially formed on a substrate in which a capacitor is incorporated or accommodated, and the capacitor, the conductor circuit, and the upper and lower conductors are formed. A method of manufacturing a multilayer printed wiring board in which a circuit is connected via a via hole,
It includes at least the following steps (a) to (e).
(A) a capacitor attaching step for attaching the capacitor of the present invention to the substrate A;
(B) A substrate stacking step of storing a capacitor in the through hole of the substrate B in which the through hole is formed, and stacking the substrate B in which the through hole is formed on the substrate A to which the capacitor is attached;
(C) a resin film crimping step for crimping a resin film to the side of the substrate B on which the through hole is formed, on which the capacitor is exposed,
(D) an interlayer resin insulation layer forming step of forming an opening for a via hole in the resin film to form an interlayer resin insulation layer; and
(E) A conductor circuit forming step of forming a conductor circuit on the surface of the resin film including the wall surface of the via hole opening.
[0143]
In the method for producing a multilayer printed wiring board according to the second aspect of the present invention, peeling occurs between the multilayer printed wiring board of the present invention, that is, the capacitor and the adhesive or interlayer resin insulation layer, or the adhesive or interlayer resin insulation. A multilayer printed wiring board in which no cracks are generated in the layer can be produced.
[0144]
The method for producing a multilayer printed wiring board according to the second aspect of the present invention is a process of (a) to (e), that is, a capacitor is accommodated in a substrate, compared with the method for producing a multilayer printed wiring board according to the first aspect of the present invention. Furthermore, since only the steps of forming the interlayer resin insulation layer and the conductor circuit are different, only the steps (a) to (e) will be described here, and the manufacturing method of the second invention will be described. A description of the entire manufacturing process will be omitted.
[0145]
In the step (a), that is, the capacitor attaching step, the capacitor of the present invention is attached to the substrate A.
In this step, a capacitor is usually attached to the substrate A via an adhesive.
The capacitor used here is the capacitor according to the present invention, and the coupling agent layer is formed on the surface thereof, so that the adhesiveness with the adhesive is excellent. This is because the coupling agent layer has affinity with both the capacitor and the adhesive.
[0146]
In the step (b), that is, the substrate lamination step, the capacitor is stored in the through hole of the substrate B in which the through hole is formed, and the substrate B in which the through hole is formed in the substrate A to which the capacitor is attached. Laminate.
Therefore, in this step, a substrate B having a through hole is prepared separately. The formation of the through hole is desirably performed using, for example, laser processing or drilling. When a substrate including a reinforcing material such as glass cloth is used as the substrate B, it is desirable to perform drilling.
Moreover, the material of the board | substrate B in which the said through-hole was formed is not specifically limited, The material of the board | substrate A which attached the capacitor | condenser at the process of said (a) may be may be different.
[0147]
In addition, when the substrate B having the through holes is laminated on the substrate A to which the capacitors are attached in this step, the surface of the substrate A to which the capacitors are attached and the through holes are formed in advance. It is desirable to apply an adhesive to the wall surface of the through hole of the substrate B and the surface facing the substrate A.
This is because the substrates can be firmly bonded to each other, and the capacitor having the coupling agent layer formed on the surface thereof can be firmly fixed in the through hole via the adhesive.
When applying the adhesive, it is desirable to select a method of applying the adhesive to the capacitor-attached surface of the substrate A to which the capacitor is attached. Compared with the method of applying an adhesive to the wall surface of the through hole, the operation is easy, and when a sufficient amount of adhesive is applied to the surface to which the capacitor is attached, the adhesive has fluidity, so that the substrate A This is because when the substrate B is laminated, the adhesive also enters between the capacitor and the wall surface of the through hole, so that the capacitor can be firmly fixed.
A capacitor built-in substrate can be formed through the steps (a) and (b).
[0148]
In the step (c), that is, the resin film press-bonding step, the resin film is pressure-bonded to the side of the substrate B on which the through-hole is formed where the capacitor is exposed.
In this step, after the resin film is pressure-bonded, a cured layer of the resin film can be formed by performing heat curing as necessary.
In addition, when performing heat curing, you may perform heat curing after forming the opening for via holes in the process of the following (d).
The resin film to be pressure-bonded in this step becomes an interlayer resin insulating layer of the multilayer printed wiring board manufactured by the manufacturing method of the present invention.
Note that when the resin film is pressure-bonded, the resin film may be pressure-bonded to the surface of the substrate A to which the capacitor is mounted on the side opposite to the surface to which the capacitor is mounted.
[0149]
In the step (d), that is, the interlayer resin insulation layer forming step, a via hole opening is formed in the resin film to form an interlayer resin insulation layer.
In this step, an interlayer resin insulation layer can be formed by forming a via hole opening in the resin film.
The formation of the via hole opening can be performed using, for example, laser processing. At this time, examples of the laser used include those similar to the laser used in the manufacturing method of the first aspect of the present invention.
In the step (c), when a resin film made of a photosensitive resin is used, a via hole opening may be formed by exposure and development.
[0150]
Similarly to the manufacturing method of the first aspect of the present invention, when the via hole opening is formed by exposure and development processing, if the external electrode is exposed on the bottom surface of the via hole opening, the external electrode is exposed. It is desirable to use a capacitor in which a coupling agent layer is not formed on the surface. However, when the via hole opening is formed by laser processing, a capacitor in which a coupling agent layer is formed on the exposed surface of the external electrode may be used.
[0151]
After forming the opening for the via hole, a desmear treatment may be performed as necessary.
The desmear treatment can be carried out using an oxidizing agent comprising an aqueous solution such as chromic acid or permanganate. Also oxygen plasma, CF_Four You may process by the mixed plasma of oxygen and oxygen, corona discharge, etc. Further, the surface can be modified by irradiating with ultraviolet rays using a low-pressure mercury lamp.
Further, if necessary, a roughened surface may be formed on the surface of the interlayer resin insulation layer (including the inner wall surface of the via hole opening).
[0152]
Furthermore, the process of said (e), ie, a conductor circuit formation process, is performed, and a conductor layer is formed in the surface of the resin film containing the wall surface of the said opening for via holes.
Through this step, a conductor circuit can be formed on the interlayer resin insulation layer, and a via hole for electrically connecting the conductor circuit and the capacitor can be formed.
[0153]
Before performing this step, through-holes for through holes are formed in the substrate on which the interlayer resin insulating layer is formed, and when performing the above-described conductor circuit forming step, a conductor layer is simultaneously formed on the through-hole wall surface, It may be a through hole.
[0154]
As a specific method for performing the above-mentioned conductor circuit forming step, a specific method performed by the method for producing a multilayer printed wiring board according to the first aspect of the present invention, that is, after forming a thin film conductor layer, a plating resist is provided, and electrolysis is performed. Examples include a method of forming a conductor circuit by performing plating and etching, and a method of forming a conductor circuit by performing electrolytic plating after forming a thin-film conductor layer and providing an etching resist after etching. .
Through the steps (a) to (e), the interlayer resin insulation layer and the conductor circuit can be formed on the substrate containing the capacitor.
[0155]
By using such a method for producing a multilayer printed wiring board of the first or second aspect of the present invention, the multilayer printed wiring board of the present invention can be suitably produced.
In addition, the multilayer printed wiring board of this invention can be manufactured also using methods other than the manufacturing method of the 1st or 2nd this invention.
[0156]
Specifically, for example, the steps (a) and (b) in the method for producing a multilayer printed wiring board according to the first aspect of the present invention, that is, a resin film to which a capacitor is attached are formed with through holes or the like in advance. In place of the step of forming a capacitor built-in substrate and a cured layer of a resin film, the following steps (1) and (2) are performed, and the other steps are the same as the manufacturing method of the first invention. The multilayer printed wiring board of the present invention can also be produced by carrying out the same method.
[0157]
(1) First, a through hole is formed in the substrate. The through hole is formed by, for example, drilling or laser processing.
Further, the capacitor of the present invention is built in the through hole of the substrate. Here, an adhesive is applied in advance to the inner wall surface of the through hole and / or the side surface of the capacitor, and the capacitor is accommodated in the through hole.
[0158]
(2) Next, a resin film is pressure-bonded to both surfaces of the substrate having the capacitor built therein, and thereafter, a capacitor built-in substrate and a cured layer of the resin film are formed by performing heat curing as necessary.
The multilayer printed wiring board of the present invention can also be produced by a method for producing a multilayer printed wiring board that undergoes such steps.
[0159]
【Example】
Hereinafter, the present invention will be described in more detail.
Example 1
(1) An epoxy resin film 40α in which a metal film 41 made of copper is laminated on one side is used as a starting material (see FIG. 6A).
First, a predetermined circuit pattern 42 was formed by pattern-etching the metal film 41 (see FIG. 6B).
[0160]
(2) Next, the capacitor 20 was attached to the circuit pattern 42 formed on the resin film 40α via the solder 34 (see FIG. 6C).
As the capacitor 20, a capacitor having a coupling agent layer formed on the entire surface of a commercially available chip capacitor (manufactured by Murata Manufacturing Co., Ltd., LL0612) by the following method was used. As the capacitor, a capacitor in which a metal coating layer made of Cu was formed on the entire surface of the external electrode was used (see FIG. 1D).
The external electrode in this case is made of only a conductive paste, or made of a conductive paste and a plating film.
[0161]
The coupling agent layer was formed as follows. That is, a silane coupling agent (manufactured by Shin-Etsu Chemical Co., Ltd., BKM573) was slowly added to an acetic acid aqueous solution previously adjusted to pH 4.0 at room temperature, and stirred for 1 hour.
After immersing the chip capacitor in the coupling agent solution for 1 minute, the coupling agent layer was formed by drying at 110 ° C. for 30 minutes.
The coupling agent layer may be formed by applying the above coupling agent solution on the surface of the chip capacitor and then drying under the above conditions.
[0162]
(3) Separately from the above, a substrate 30α having a recess 31 for containing the capacitor 20 is prepared.
Next, after applying an adhesive to the inner wall of the recess 31, the resin film 40α to which the capacitor 20 was attached, the substrate 30α having the recess 31 formed therein, and another resin film 40α were stacked and pressed ( (Refer to Drawing 6 (c) and (d)).
An epoxy resin was used as the adhesive.
[0163]
(4) Next, a heat curing process was performed to form a substrate 30 containing the capacitor 20 and a cured layer 40β of a resin film (see FIG. 7A). In FIG. 7A, reference numeral 32 denotes an adhesive layer.
Subsequently, CO 2 having a wavelength of 10.4 μm is passed through a mask having a through-hole formed on the cured layer 40β of the resin film.₂ For via holes with a gas diameter of 4.0 μm, top hat mode, pulse width of 8.0 μsec, mask through-hole diameter of 1.0 mm, and a two-shot cured layer of resin film 40β with a diameter of 60 μm An opening 43 was formed to form an interlayer resin insulation layer 40 (see FIG. 7B). Thereafter, desmear treatment was performed using oxygen plasma.
[0164]
(5) Next, through-holes for through holes 33 having a diameter of 100 μm were formed by drilling in the substrate 30 on which the interlayer resin insulating layer 50 was formed (see FIG. 7C).
Further, a palladium catalyst (manufactured by Atotech) is applied to the surface of the interlayer resin insulation layer 40 (including the inner wall surfaces of the via hole opening 43 and the through-hole through hole 33), whereby the surface of the interlayer resin insulation layer 40 is obtained. The catalyst nuclei were attached to.
[0165]
(6) Next, the substrate is immersed in an electroless copper plating aqueous solution having the following composition, and a thin film having a thickness of 0.6 to 0.9 μm is formed on the entire surface of the interlayer resin insulating layer 40 and the through hole 33 for the through hole. A conductor layer (electroless copper plating layer) 44 was formed (see FIG. 8A).
[Electroless plating aqueous solution]
NiSO_Four               0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 40 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at 35 ° C liquid temperature
[0166]
(7) Next, a commercially available photosensitive dry film is attached to the electroless copper plating 44, and a mask is placed thereon, and 100 mJ / cm.² Then, a plating resist 51 was provided by developing with 0.8% sodium carbonate aqueous solution.
Further, the substrate is washed and degreased with water at 50 ° C., washed with water at 25 ° C., washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions. 45 was formed (see FIG. 8B).
[0167]
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 1.95 ml / l
(Manufactured by Atotech Japan, Kaparaside GL)
[Electrolytic plating conditions]
Current density 1 A / dm²
65 minutes
Temperature 22 ± 2 ° C
[0168]
(8) Next, after removing the plating resist 51 with 5% KOH, the electroless plating layer 44 under the plating resist 51 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the interlayer resin insulation is removed. A conductive circuit 48 and a via hole 46 were formed in the layer 40, and a through hole 36 was formed in the substrate 30 (see FIG. 8C).
[0169]
(9) Next, the surfaces of the conductor circuit 48, the via hole 46, and the through hole 36 are etched using an etchant composed of an organic acid salt and a cupric complex, thereby roughening the surface. (Not shown) was formed.
Further, the substrate on which the conductor circuit 48 and the like are formed is immersed in a 70 ° C. solution containing 800 g / l of chromic acid for 3 minutes, and the surface of the interlayer resin insulation layer 40 between the conductor circuits located in the conductor circuit non-formation portion. Was etched by 1 μm to remove the palladium catalyst remaining on the surface.
[0170]
Furthermore, the resin filler layer 38 was formed by filling the through hole 36 with a resin filler using a squeegee and drying at 100 ° C. for 20 minutes.
The resin filler is 100 parts by weight of a bisphenol F-type epoxy monomer (manufactured by Yuka Shell Co., Ltd., molecular weight: 310, YL983U), the average particle diameter coated with a silane coupling agent is 1.6 μm, and the maximum SiO whose particle size is 15 μm or less₂ 72 parts by weight of spherical particles (manufactured by Adtech, CRS 1101-CE) and 1.5 parts by weight of a leveling agent (Perenol S4, manufactured by San Nopco) are placed in a container and mixed by stirring. The one prepared to 60 Pa · s was used. Here, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) was used as the curing agent.
[0171]
Thereafter, the resin film 60α was attached to both surfaces of the substrate (see FIG. 9A). A resin film made of an epoxy resin was used as the resin film 60α.
[0172]
(10) By further repeating the steps (4) to (8) (excluding the step of forming a through hole for a through hole), an upper conductor circuit 68 (including a via hole 66) is formed, and then By etching the surface of the conductor circuit 66 to form a roughened surface (not shown), a multilayer wiring board having a conductor circuit formed on the outermost layer was obtained (FIGS. 9B to 10B). )reference).
[0173]
(11) Next, a photosensitizing agent obtained by acrylating 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, trade name: Epicoat 1001), 15 parts by weight of imidazole curing agent (manufactured by Shikoku Chemicals) , Trade name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) which is a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product) Name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.7 A weight part is put into a container, and a mixed composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator and Michler's ketone as a photosensitizer for the mixed composition. (Kanto Chemical Co., Ltd.) 0.2 parts by weight was added to obtain a solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity measurement was performed using a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.). In the case of 4 or 6 rpm, the rotor No. 3 according.
[0174]
(12) Next, the above-mentioned solder resist composition is applied to a multilayer wiring board in a thickness of 20 μm and dried at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes. A photomask having a thickness of 5 mm on which the pattern of the portion is drawn is brought into close contact with the solder resist layer 70 to 1000 mJ / cm² Were exposed to UV light and developed with DMTG solution to form openings 71 having a diameter of 200 μm (see FIG. 10C).
[0175]
(13) Next, the substrate on which the solder resist layer 70 is formed is nickel chloride (2.3 × 10^-1mol / l), sodium hypophosphite (2.8 × 10^-1mol / l), sodium citrate (1.6 × 10^-1A nickel plating layer (not shown) having a thickness of 5 μm was formed in the opening 71 by immersing in an electroless nickel plating solution containing 0.5 mol / l) of pH = 4.5. Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (1.7 × 10^-1mol / l) is immersed in an electroless plating solution at 80 ° C. for 7.5 minutes to form a gold plating layer (not shown) having a thickness of 0.03 μm on the nickel plating layer. Solder pads were formed on the circuit 68 and the like.
[0176]
(14) Thereafter, solder bumps 76 were formed by printing solder paste in the openings 71 of the solder resist layer 70 and reflowing at 200 ° C. As a result, the multilayer printed wiring board 10 including the capacitor 20 and having the solder bumps 76 was obtained (see FIG. 2).
[0177]
(Example 2)
(1) A laminate 30β obtained by laminating two prepregs 35 impregnated with an epoxy resin was used as a starting material. First, a capacitor 220 was attached to this laminate 30β with an adhesive (thermosetting resin) interposed (see FIG. 11A).
[0178]
As the capacitor 220, a capacitor in which a coupling agent layer was formed on the entire surface of a commercially available chip capacitor (Murata Manufacturing Co., Ltd., LL0612) by the following method was used. In addition, as a capacitor | condenser, the metal coating layer 26 which consists of Sn was formed only in the side surface and bottom face of an external electrode, and the external electrode used the copper plating layer on the upper surface (refer FIG.1 (c)). .
[0179]
The coupling agent layer was formed as follows. That is, a silane coupling agent (manufactured by Shin-Etsu Chemical Co., Ltd., BKM573) was slowly added to an acetic acid aqueous solution previously adjusted to pH 4.0 at room temperature, and stirred for 1 hour.
After immersing the chip capacitor in the coupling agent solution for 1 minute, the coupling agent layer was formed by drying at 110 ° C. for 30 minutes.
[0180]
(2) Separately from the above, a laminated plate 30α is prepared by laminating four prepregs 35 and forming a through hole 37 for accommodating a capacitor, and the laminated plate 30α and the laminated plate 30β to which the capacitor 220 is attached are prepared. Laminating and pasting were performed to obtain a substrate 30 containing a capacitor 220 (see FIG. 11B). At this time, an adhesive was previously applied to the surface of the laminated plate 30β on which the capacitor was attached. As a result, the adhesive flowed when the laminated plate 30α and the laminated plate 30β were attached, and an adhesive layer was formed between the wall surface of the capacitor 220 and the wall surface of the through hole 37.
[0181]
(3) Next, the resin film 40α is laminated and pressed on the upper and lower sides of the substrate 30 containing the capacitor 220, and then heat-cured, and a cured layer 40β of resin film is formed on both surfaces of the substrate containing the capacitor 220. It formed (refer FIG.11 (c) and (d)).
As the resin film 40α, a resin film made of a thermosetting cycloolefin resin was used.
[0182]
(4) Next, through-holes 33 for through holes having a diameter of 100 μm were formed by drilling on the substrate 30 on which the cured layer 40β of the resin film was formed (see FIG. 12A).
[0183]
Subsequently, CO 2 having a wavelength of 10.4 μm is passed through a mask having a through-hole formed on the cured layer 40β of the resin film.₂ For via holes with a diameter of 60 μm on the resin film cured layer 40β under the conditions of a gas laser with a beam diameter of 4.0 mm, a dopp-hat mode, a pulse width of 8.0 μs, a mask through-hole diameter of 1.0 mm, and two shots. An opening 43 was formed to form an interlayer resin insulation layer 40 (see FIG. 12B). Thereafter, desmear treatment was performed using oxygen plasma.
[0184]
(5) Next, plasma treatment was performed using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd., and a roughened surface (not shown) was formed on the surface of the interlayer resin insulation layer 40. At this time, argon gas was used as the inert gas, and plasma treatment was performed for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, and temperature 70 ° C.
[0185]
(6) Next, using the same apparatus and using the internal argon gas, sputtering with a Ni—Cu alloy as a target was performed under the conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, and time 5 minutes, A thin film conductor layer 44 made of a Ni—Cu alloy and having a thickness of 0.2 μm was formed on the surface of the interlayer resin insulation layer 40 and the through hole 33 (see FIG. 12C).
[0186]
(7) Next, a commercially available photosensitive dry film is attached to the electroless copper plating 44, and a mask is placed thereon, and 100 mJ / cm.² Then, a plating resist 51 was provided by developing with a 0.8% aqueous sodium carbonate solution (see FIG. 13A).
Further, the substrate is washed and degreased with water at 50 ° C., washed with water at 25 ° C., washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions. 45 was formed (see FIG. 13B).
[0187]
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 1.95 ml / l
(Manufactured by Atotech Japan, Kaparaside GL)
[Electrolytic plating conditions]
Current density 1 A / dm²
65 minutes
Temperature 22 ± 2 ° C
[0188]
(8) Next, after removing the plating resist 51 with 5% KOH, the electroless plating layer 44 under the plating resist 51 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the interlayer resin insulation is removed. Conductor circuits 48 and via holes 46 were formed in the layer 40, and through holes 36 were formed in the substrate 30 (see FIG. 13C).
[0189]
(9) Next, the surfaces of the conductor circuit 48, the via hole 46, and the through hole 36 are etched using an etchant composed of an organic acid salt and a cupric complex, thereby roughening the surface. (Not shown) was formed.
Further, the substrate on which the conductor circuit 48 and the like are formed is immersed in a 70 ° C. solution containing 800 g / l of chromic acid for 3 minutes, and the surface of the interlayer resin insulation layer 40 between the conductor circuits located in the conductor circuit non-formation portion. Was etched by 1 μm to remove the palladium catalyst remaining on the surface.
[0190]
Further, the resin filler was filled in the through hole 36 using a squeegee and dried at 100 ° C. for 20 minutes to form a resin filler layer.
In addition, as a resin filler, the thing similar to the resin filler used in Example 1 was used.
[0191]
Thereafter, a resin film 60α was attached to both surfaces of the substrate. The resin film 60α is the same as the resin film 40α.
[0192]
(10) By repeating the steps (4) to (8) above, a further upper conductor circuit 68 (including the via hole 66) is formed, and then the surface of the conductor circuit 66 is etched to roughen the surface. By forming the conversion surface, a multilayer wiring board having a conductor circuit formed on the outermost layer was obtained.
[0193]
(11) In the same manner as (11) to (14) in Example 1, the multilayer printed wiring board 110 having the capacitor 120 and having the solder bumps 76 was obtained (see FIG. 4).
[0194]
(Example 3)
As the capacitor, a capacitor having a coupling agent layer formed on the entire surface of a commercially available chip capacitor (manufactured by Murata Manufacturing Co., Ltd., LL0612) in the same manner as in Example 2 is used. A multilayer printed wiring board was produced in the same manner as in Example 2 except that the following steps (1) to (2) were performed instead of the above step. In addition, as a capacitor | condenser, the whole surface of an external electrode used what consists of a copper plating layer (refer FIG.1 (b)).
[0195]
(1) Palladium catalyst (manufactured by Atotech) is applied to the surface of the interlayer resin insulation layer (including the opening for via holes and the inner wall surface of the through hole for through holes) to thereby form catalyst nuclei on the surface of interlayer resin insulation layer Was attached.
[0196]
(2) Next, the substrate is immersed in an electroless copper plating aqueous solution having the following composition, and a thin film having a thickness of 0.6 to 0.9 μm is formed on the entire surface of the interlayer resin insulating layer 40 and the through hole 33 for the through hole. A conductor layer (electroless copper plating layer) 44 was formed (see FIG. 8A).
[Electroless plating aqueous solution]
NiSO_Four               0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 40 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at 35 ° C liquid temperature
[0197]
Example 4
In the process of Example 1 (2), multilayer printing is performed in the same manner as in Example 1 except that a capacitor in which the external electrode is formed in a matrix and the entire surface of the external electrode is made of copper is used. A wiring board was manufactured.
[0198]
(Comparative Example 1)
A multilayer printed wiring board was produced in the same manner as in Example 1 except that in the step (2) of Example 1, a capacitor having no coupling agent layer formed thereon was used.
[0199]
(Comparative Example 2)
A multilayer printed wiring board was produced in the same manner as in Example 2 except that in the step (2) of Example 2, a capacitor having no coupling agent layer formed thereon was used.
[0200]
For the multilayer printed wiring boards obtained in Examples 1 to 4 and Comparative Examples 1 and 2, after performing a heat cycle test under the following conditions, capacitors and adhesives or interlayer resin insulation layers were evaluated by the following evaluation methods. The presence or absence of delamination between them, the presence or absence of cracks in the adhesive or the interlayer resin insulation layer, the presence or absence of short circuit or disconnection, and the presence or absence of swelling of the interlayer resin insulation layer were evaluated. The results are shown in Table 1.
[0201]
Heat cycle test (reliability test)
The obtained multilayer printed wiring board was maintained in an atmosphere at 130 ° C. for 3 minutes, and then a cycle in which the multilayer printed wiring board was maintained in an atmosphere at −65 ° C. for 3 minutes was repeated 1000 times and 2000 times.
[0202]
Evaluation methods
(1) Presence or absence of peeling between the capacitor and the adhesive or interlayer resin insulation layer
The multilayer printed wiring board was cut with a cutter, and the cut section was observed with a microscope. Here, the multilayer printed wiring board was cut so as to cut the capacitor. The results are shown in Table 1 below.
[0203]
(2) Presence or absence of cracks in the adhesive or interlayer resin insulation layer
The multilayer printed wiring board was cut in the same manner as in (1) above, and the cross section was observed with a microscope. The results are shown in Table 1 below.
[0204]
(3) Presence or absence of short circuit or disconnection
After mounting the IC chip on the multilayer printed wiring board, a continuity test was performed, and the continuity state was evaluated from the results displayed on the monitor. The results are shown in Table 1 below.
(4) Interstitial resin insulation layer presence or absence of swelling
The multilayer printed wiring board was cut in the same manner as in (1) above, and the cross section was observed with a microscope. The results are shown in Table 1 below.
[0205]
(5) Capacitance measurement before and after reliability test
The capacitance of the capacitor was measured before and after the reliability test using a picoammeter. The results are shown in Table 2 below.
[0206]
[Table 1]

[0207]
[Table 2]

[0208]
As shown in Table 1, when the heat cycle test of 1000 cycles and 2000 cycles was performed for the multilayer printed wiring boards obtained in Examples 1 to 4, between the capacitor and the adhesive or the interlayer resin insulation layer No peeling occurred, and no cracks occurred in the adhesive or the interlayer resin insulation layer.
Further, no short circuit, disconnection, or swelling of the interlayer resin insulation layer occurred.
[0209]
On the other hand, in the multilayer printed wiring boards obtained in Comparative Examples 1 and 2, cracks and peeling occurred starting from the contact surface between the capacitor and the resin (adhesive layer or interlayer resin insulating layer).
[0210]
Furthermore, as shown in Table 2, the capacitors embedded in the substrates in Examples 1 to 4 have little change in capacitance before and after the reliability test, and the electrical connection is also made between the conductor circuit and the capacitor. There is almost no influence.
On the other hand, in the multilayer printed wiring boards obtained in Comparative Examples 1 and 2, the capacitance after the reliability test could not be measured, and it was revealed that disconnection occurred.
[0211]
【The invention's effect】
As described above, since the coupling agent layer is formed on at least a part of the surface of the capacitor of the present invention, the dielectric film made of ceramic, the external electrode made of metal, the adhesive, the interlayer resin insulating layer, Therefore, no separation occurs between the capacitor and the interlayer resin insulation layer or the adhesive, and no crack occurs in the interlayer resin insulation layer or the adhesive.
Therefore, the capacitor of the present invention is suitable for use in a multilayer printed wiring board.
[0212]
In the multilayer printed wiring board of the present invention, since the capacitor of the present invention is built in the substrate, peeling occurs between the capacitor and the interlayer resin insulation layer or the adhesive, No cracks occur in the agent. Therefore, the multilayer printed wiring board has excellent electrical connectivity and reliability without disconnecting the connection between the capacitor terminal and the via hole or causing cracks or swelling in the interlayer resin insulation layer. .
[0213]
In the first and second multilayer printed wiring board manufacturing methods, the multilayer printed wiring board of the present invention, that is, peeling occurs between the capacitor and the adhesive or interlayer resin insulating layer, or the adhesive or interlayer A multilayer printed wiring board in which no cracks are generated in the resin insulating layer can be manufactured.
[Brief description of the drawings]
FIGS. 1A to 1D are cross-sectional views schematically showing an example of a capacitor of the present invention.
FIG. 2 is a cross-sectional view schematically showing an example of a multilayer printed wiring board according to the present invention.
3 is a cross-sectional view schematically showing a state in which an IC chip is mounted on the multilayer printed wiring board shown in FIG. 2 and attached to a daughter board.
FIG. 4 is a cross-sectional view schematically showing an example of a multilayer printed wiring board according to the present invention.
FIG. 5 is a cross-sectional view schematically showing an example of the multilayer printed wiring board of the present invention.
6A to 6D are cross-sectional views schematically showing a part of the method for manufacturing a multilayer printed wiring board according to the present invention.
7A to 7C are cross-sectional views schematically showing a part of the method for manufacturing a multilayer printed wiring board according to the present invention.
8A to 8C are cross-sectional views schematically showing a part of the method for producing a multilayer printed wiring board according to the present invention.
9A to 9C are cross-sectional views schematically showing a part of the method for manufacturing a multilayer printed wiring board according to the present invention.
10A to 10C are cross-sectional views schematically showing a part of the method for manufacturing a multilayer printed wiring board according to the present invention.
11A to 11D are cross-sectional views schematically showing a part of the method for manufacturing a multilayer printed wiring board according to the present invention.
12A to 12C are cross-sectional views schematically showing a part of the method for manufacturing a multilayer printed wiring board according to the present invention.
FIGS. 13A to 13C are cross-sectional views schematically showing a part of the method for producing a multilayer printed wiring board according to the present invention.
14A and 14B are explanatory diagrams of loop inductance of a conventional multilayer printed wiring board, and FIG. 14C is an explanatory diagram of loop inductance of the multilayer printed wiring board of the present invention.
FIG. 15A shows a capacitor before cutting for multi-piece cutting, and FIG. 15B shows one of the capacitors of the present invention after cutting (a).
16 (a) shows a capacitor before cutting for multi-piece cutting, and FIG. 16 (b) shows one of the capacitors of the present invention after cutting (a).
FIG. 17 is a plan view schematically showing an example of the capacitor of the present invention.
FIG. 18A shows a capacitor before cutting for multi-piece cutting, and FIG. 18B shows one of the capacitors of the present invention after cutting (a).
[Explanation of symbols]
10, 110, 210 Multilayer printed wiring board
20, 120, 220, 320 capacitors
21 First electrode
22 Second electrode
23 Dielectric
24 First conductive film
25 Second conductive film
26, 226, 326 metal layer
27, 227, 327 Rough surface
30 substrates
40, 60 interlayer resin insulation layer
46, 66 Via hole
48, 68 conductor circuit
70 Solder resist layer
76 Solder bump
90 IC chip

Claims (10)

A multilayer printed wiring board in which an interlayer resin insulation layer and a conductor circuit are sequentially formed on a substrate in which a capacitor is built-in or accommodated, and the capacitor, the conductor circuit, and the upper and lower conductor circuits are connected via via holes. Because
The capacitor has a coupling agent layer formed on the entire surface thereof, an external electrode is formed on a laminate in which internal electrodes and dielectric films are alternately laminated, and the external electrode is composed of at least two layers. The outermost layer is a plating layer,
A multilayer printed wiring board, wherein openings for via holes are formed in a coupling agent layer formed on the entire surface of the capacitor . The multilayer printed wiring board according to claim 1, wherein the coupling agent layer is formed using epoxysilane and / or imidosilane. The multilayer printed wiring board according to claim 1, wherein the external electrode is made of at least copper. The multilayer printed wiring board according to claim 1, wherein the innermost layer of the external electrode is a conductive paste layer. The multilayer printed wiring board according to any one of claims 1 to 4, wherein the capacitor is a capacitor in which external electrodes are formed on portions including both end faces of the laminate. The multilayer printed wiring board according to claim 1, wherein the external electrodes are formed in a matrix. The multilayer printed wiring board according to claim 1, wherein the plating layer is a copper plating layer. The multilayer printed wiring board of any one of Claims 1-7 in which the metal coating layer is formed in at least one part of the surface of the said external electrode. A multilayer printed wiring board in which an interlayer resin insulation layer and a conductor circuit are sequentially formed on a substrate in which a capacitor is built-in or accommodated, and the capacitor, the conductor circuit, and the upper and lower conductor circuits are connected via via holes. A manufacturing method of
The manufacturing method of the multilayer printed wiring board characterized by including the process of following (A)-(D) at least.
(A) Capacitor attaching step for attaching a capacitor used in the multilayer printed wiring board according to any one of claims 1 to 8 to the resin film,
(B) A resin film crimping step of accommodating a capacitor in the recess or the through hole of the substrate in which the recess or the through hole is formed, and crimping the resin film to the substrate;
(C) a coupling agent layer formed on the capacitor surface, an interlayer resin insulation layer forming step of forming an opening for a via hole in the resin film to form an interlayer resin insulation layer, and
(D) A conductor circuit forming step of forming a conductor circuit on the surface of the interlayer resin insulating layer including the wall surface of the via hole opening. A multilayer printed wiring board in which an interlayer resin insulation layer and a conductor circuit are sequentially formed on a substrate in which a capacitor is built-in or accommodated, and the capacitor, the conductor circuit, and the upper and lower conductor circuits are connected via via holes. A manufacturing method of
The manufacturing method of the multilayer printed wiring board characterized by including the process of following (a)-(e) at least.
(A) a capacitor attaching step for attaching the capacitor used in the multilayer printed wiring board according to any one of claims 1 to 8 to the substrate A;
(B) A substrate stacking step of storing a capacitor in the through hole of the substrate B in which the through hole is formed, and stacking the substrate B in which the through hole is formed on the substrate A to which the capacitor is attached,
(C) a resin film crimping step of crimping a resin film on the side of the substrate B on which the through hole is formed, the capacitor being exposed;
(D) a coupling agent layer formed on the capacitor surface, and an interlayer resin insulation layer forming step of forming an opening for a via hole in the resin film to form an interlayer resin insulation layer; and
(E) A conductor circuit forming step of forming a conductor circuit on the surface of the interlayer resin insulating layer including the wall surface of the via hole opening.

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