JP2001007526A - Multilayer buildup wiring board and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer buildup wiring board in which length of wiring can be shortened. SOLUTION: In this multilayer buildup wiring board, a via hole 160b piercing through a lower interlayer resin insulation layer 50 and an upper interlayer resin insulation layer 150 conducts electricity from solder bumps 76U and 76D in an upper layer of the interlayer resin insulation layer 150 to a conductor layer (conductor circuit) 34 formed on a core board 30. Further, a through hole 39 piercing through the core board 30 and the interlayer resin insulation layer 150 formed over the core board 30 connects a via hole (conductor layer) 160a over the interlayer resin insulation layer 50. As a result, length of wiring is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer build-up wiring board in which interlayer resin insulation layers and conductor layers are alternately laminated on both surfaces of a core substrate.

[0002]

2. Description of the Related Art A multilayer build-up wiring board is, for example, shown in FIG.
0, the through hole 236 and the conductor circuit 234
Are formed on the core substrate 230 on which the lower layer is formed, and a lower interlayer resin insulating layer 350 and a conductor layer 358 are further provided. The conductor layer 358 and the via hole are provided. 360 is provided with solder bumps 376 for external connection. The conductor circuit 234 on the core substrate 230 and the lower conductor layer 258 are connected by a via hole 260 formed in the lower interlayer resin insulation layer 250, and the lower conductor circuit 258 and the upper conductor circuit 358 are connected.
Are formed by via holes 360 formed in the upper interlayer resin insulation layer 350.

[0003]

However, in the conventional multi-layer build-up wiring board, via holes are formed in each interlayer resin insulation layer to route the wiring. For this reason, the wiring length becomes long, and when the multilayer build-up wiring board is used as a package substrate for mounting an IC chip, the signal transmission speed is reduced and the heat generation in the multilayer build-up wiring board is caused. Had become.

The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a multilayer build-up wiring board capable of shortening a wiring length.

[0005]

In order to achieve the above-mentioned object, a first aspect of the present invention is to alternately laminate an interlayer resin insulation layer and a conductor layer, and connect the conductor layers above and below the interlayer resin insulation layer by via holes. A technical feature of the multilayer build-up wiring board according to the present invention is that a via hole penetrating through the interlayer resin insulating layer below the conductor layer and the interlayer resin insulating layer above is formed.

According to a second aspect of the present invention, in the first aspect, the multilayer build-up wiring board has a core substrate.
A technical feature is that at least a through hole penetrating the core substrate and a via hole penetrating the lower and upper interlayer resin insulating layers are connected.

According to the first and second aspects of the present invention, since the upper and lower conductor layers are electrically connected by the via holes penetrating the lower interlayer resin insulation layer and the upper interlayer resin insulation layer, the wiring length is reduced. can do.

A third aspect of the present invention is a multilayer build-up wiring in which interlayer resin insulation layers and conductor layers are alternately laminated on both surfaces of a core substrate, and the upper and lower conductor layers of the interlayer resin insulation layer are connected by via holes. In the board, a technical feature is that a conductor layer on the interlayer resin insulating layer on the core substrate is connected by a through hole penetrating the core substrate and the interlayer resin insulating layer formed on the core substrate. And

According to the third aspect of the present invention, the conductor layer on the interlayer resin insulating layer on the core substrate is connected by a through hole penetrating the core substrate and the interlayer resin insulating layer formed on the core substrate. Therefore, the wiring length can be reduced.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a multilayer build-up wiring board comprising at least the steps (A) to (C): (A) formed on a lower interlayer resin insulating layer. Forming an upper interlayer resin insulation layer on the conductor layer; (B) forming a through hole by laser in the lower interlayer resin insulation layer and the upper interlayer resin insulation layer; and (C) forming a through hole in the through hole. Forming a conductor layer to be a via hole;

According to the fourth aspect of the present invention, a through hole is formed in the lower interlayer resin insulation layer and the upper interlayer resin insulation layer by a laser to form a via hole. It becomes possible and the wiring length can be shortened.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a multilayer build-up wiring board, comprising at least the steps (A) to (C): (A) forming a conductive layer on a core substrate; Forming an interlayer resin insulation layer, (B) forming a through hole in the core substrate and the interlayer resin insulation layer by laser,
(C) forming a conductor layer in the through hole;

According to the fifth aspect of the present invention, a through hole is formed in the core substrate and the interlayer resin insulating layer by using carbonic acid, excimer, YAG, and UV laser, and the conductor layer is formed. Wiring can be provided, and the wiring length can be reduced.

In the present invention, it is desirable to use an adhesive for electroless plating as the interlayer resin insulating layer. The most suitable adhesive for electroless plating is one in which heat-resistant resin particles soluble in a cured acid or oxidizing agent are dispersed in an uncured heat-resistant resin hardly soluble in an acid or oxidizing agent. is there. By treating with an acid or an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus-shaped anchor can be formed on the surface.

In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles which have been particularly hardened include a heat-resistant resin powder having an average particle diameter of 10 μm or less, and an average particle diameter of 2 μm.
Aggregated particles obtained by aggregating the following heat-resistant resin powder, a heat-resistant powder resin powder having an average particle size of 2 to 10 μm and an average particle size of 2 μm
m and a mixture with a heat-resistant resin powder having a mean particle size of 2 or less.
Pseudo particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 μm or less to the surface of a 10 μm heat-resistant resin powder, and an average particle diameter of 0.1 to
0.8μm heat resistant resin powder and average particle size 0.8μ
m, and a mixture with a heat-resistant resin powder of less than 2 μm,
It is desirable to use a heat-resistant resin powder having an average particle size of 0.1 to 1.0 μm. This is because they can form more complex anchors.

The depth of the roughened surface is Rmax = 0.01 to 2
0 μm is preferred. This is to ensure adhesion. Particularly, in the semi-additive method, the thickness is preferably 0.1 to 5 μm. This is because the electroless plating film can be removed while ensuring adhesion.

The heat-resistant resin hardly soluble in an acid or an oxidizing agent is selected from a “resin composite composed of a thermosetting resin and a thermoplastic resin” or a “resin composite composed of a photosensitive resin and a thermoplastic resin”. It is desirable to become. This is because the former has high heat resistance, and the latter can form an opening for a via hole by photolithography.

As the thermosetting resin, epoxy resin, phenol resin, polyimide resin and the like can be used. In the case of photosensitization, methacrylic acid, acrylic acid, or the like is reacted with a thermosetting group for acrylation. Particularly, acrylate of epoxy resin is most suitable. As the epoxy resin, a novolak type epoxy resin such as a phenol novolak type and a cresol novolak type, and an alicyclic epoxy resin modified with dicyclopentadiene can be used.

As the thermoplastic resin, polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PP
E), polyetherimide (PI) and the like can be used.
The mixing ratio of the thermosetting resin (photosensitive resin) and the thermoplastic resin is: thermosetting resin (photosensitive resin) / thermoplastic resin = 95
/ 5 to 50/50 is preferred. This is because a high toughness value can be secured without impairing the heat resistance.

The mixing weight ratio of the heat-resistant resin particles is 5 to 50% by weight based on the solid content of the heat-resistant resin matrix.
Desirably, the content is 10 to 40% by weight. As the heat-resistant resin particles, amino resin (melamine resin, urea resin, guanamine resin), epoxy resin and the like are preferable. The adhesive may be composed of two layers having different compositions.

As the solder resist layer to be added to the surface of the multilayer build-up wiring board, various resins can be used. For example, bisphenol A epoxy resin, acrylate of bisphenol A epoxy resin, novolak epoxy resin, novolak A resin obtained by curing an acrylate of a type epoxy resin with an amine curing agent or an imidazole curing agent can be used.

On the other hand, such a solder resist layer is
Since it is composed of a resin having a rigid skeleton, peeling may occur. Therefore, the provision of the reinforcing layer can also prevent the solder resist layer from peeling off.

Here, as the acrylate of the novolak type epoxy resin, an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolak with acrylic acid, methacrylic acid or the like can be used.

The above-mentioned imidazole curing agent is desirably liquid at 25 ° C. This is because a liquid can be uniformly mixed. As such a liquid imidazole curing agent,
1-benzyl-2-methylimidazole (product name: 1B2MZ),
1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN) and 4-methyl-2-ethylimidazole (product name: 2E4MZ) can be used.

The amount of the imidazole curing agent is desirably 1 to 10% by weight based on the total solid content of the solder resist composition. The reason for this is that if the added amount is within this range, uniform mixing is easy.

The composition before curing of the solder resist is as follows:
It is desirable to use a glycol ether-based solvent as the solvent. The solder resist layer using such a composition does not generate free acid and does not oxidize the copper pad surface. It is also less harmful to the human body.

As such a glycol ether-based solvent, one having the following structural formula, particularly preferably at least one selected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG) is used. This is because these solvents can completely dissolve benzophenone and Michler's ketone as reaction initiators by heating at about 30 to 50 ° C. CH ₃ O-(CH ₂ CH _{2 O) n -CH 3 (n =} 1~
5) The amount of the glycol ether solvent is preferably 10 to 70% by weight based on the total weight of the solder resist composition.

In addition to the solder resist composition described above, various antifoaming agents and leveling agents, thermosetting resins for improving heat resistance and base resistance and imparting flexibility,
A photosensitive monomer or the like can be added to improve the resolution. For example, as the leveling agent, one made of a polymer of an acrylate ester is preferable. The initiator is preferably Irgacure I907 manufactured by Ciba-Geigy, and the photosensitizer is DETX-S manufactured by Nippon Kayaku. further,
A dye or pigment may be added to the solder resist composition. This is because the wiring pattern can be hidden. It is desirable to use phthalocyanine green as this dye.

As the thermosetting resin as an additional component, a bisphenol type epoxy resin can be used. This bisphenol type epoxy resin includes a bisphenol A type epoxy resin and a bisphenol F type epoxy resin, and when importance is attached to base resistance, the former is required to reduce viscosity (when importance is attached to coating properties). The latter is better.

As the photosensitive monomer as an additive component, a polyvalent acrylic monomer can be used.
This is because the polyacrylic monomer can improve the resolution. For example, Nippon Kayaku's DPE-6A and Kyoeisha Chemical's R-
604 can be used. Further, these solder resist compositions have a pressure of 0.5 to 10 Pa · s at 25 ° C., preferably 1 to 10 Pa · s. This is because the viscosity is easy to apply with a roll coater.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer build-up wiring board according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings. First, the configuration of the multilayer build-up wiring board 10 according to the first embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIG. 8 (Z) is a cross-sectional view of the multilayer build-up wiring board 10 before mounting the IC chip, and FIG. 9 shows an IC chip 90 mounted on the multilayer build-up wiring board 10 shown in FIG. 8 (Z). The state where it was attached to the daughter board 94 is shown.

As shown in FIG. 9, in the multilayer build-up wiring board 10, through holes 36 are formed in the core substrate 30, and conductor circuits 34 are formed on both surfaces of the core substrate 30. A lower interlayer resin insulation layer (50) is provided on the core substrate (30). The lower interlayer resin insulation layer (50) has conductive paths (39) passing through the lower interlayer resin insulation layer (50) and the core substrate (30). And a wiring pattern 58 are formed. On the lower interlayer resin insulation layer 50, an upper interlayer resin insulation layer 150 is disposed.
Via hole 160 penetrating through interlayer resin insulation layer 150
a, a via hole 160b penetrating through the upper interlayer resin insulation layer 150 and the lower interlayer resin insulation layer 50, and a wiring pattern 158 are formed.

On the upper surface side of the multilayer build-up wiring board 10, solder bumps 76U for connection to the lands 92 of the IC chip 90 are provided. The solder bump 76U is
The via hole 160b is connected to the through-hole 36, and the via hole 160a is connected to the through-hole 39. On the other hand, a solder bump 76D for connection to the land 96 of the daughter board 94 is provided on the lower surface side. The solder bump 76D is connected to the via hole 160b.
Through hole 36 and via hole 16
Oa is connected to the through path 39.

The multilayer build-up wiring board 10 of the present embodiment
In the above, via holes 160b penetrating through the lower interlayer resin insulation layer 50 and the upper interlayer resin insulation layer 150, the upper solder bumps 76U of the interlayer resin insulation layer 150,
The conduction between 76D and the conductor layer (conductor circuit) 34 formed on the core substrate 30 is established. Also, via holes (conductor layers) 160a on interlayer resin insulating layer 50 on the IC chip side and daughter board are formed by through paths 39 penetrating core substrate 30 and interlayer resin insulating layer 150 formed on core substrate 30. Side via hole 160a. Therefore, the wiring length can be shortened, the signal transmission speed from the IC chip 90 to the daughter boat can be improved, and the heat generation in the multilayer build-up wiring board can be reduced.

Next, a method of manufacturing the multilayer build-up wiring board according to the first embodiment will be described with reference to the drawings. Here, A.E. used in the method for manufacturing a multilayer build-up wiring board of the first embodiment is described. Adhesive for electroless plating, B. Interlayer resin insulation, C.I. Resin filler, D.I. The composition of the solder resist composition will be described.

A. Raw material composition for preparation of adhesive for electroless plating (adhesive for upper layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
35% by weight of a resin solution dissolved in DMDG at a concentration of 3.15% and a photosensitive monomer (Toa Gosei Co., Aronix M315) 3.15
Parts by weight, 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, S-65)
3.6 parts by weight of NMP were obtained by stirring and mixing.

[Resin Composition] 12 parts by weight of polyether sulfone (PES), epoxy resin particles (manufactured by Sanyo Chemical Co., Ltd.)
After mixing 7.2 parts by weight of a polymer pole having an average particle size of 1.0 μm and 3.09 parts by weight of a polymer pole having an average particle size of 0.5 μm, 30 parts by weight of NMP was further added, followed by stirring and mixing with a bead mill.

[Curing Agent Composition] 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of a photoinitiator (Irgacure I-907, manufactured by Ciba Geigy), and a photosensitizer (manufactured by Nippon Kayaku) , DETX-S) 0.2 parts by weight and NMP 1.5 parts by weight.

B. Raw material composition for preparing interlayer resin insulation agent (adhesive for lower layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
% Of a resin solution dissolved in DMDG at a concentration of 35%, 4 parts by weight of a photosensitive monomer (Alonix M315, manufactured by Toagosei Co., Ltd.), 0.5 parts by weight of an antifoaming agent (S-65, manufactured by San Nopco), N
3.6 parts by weight of MP were obtained by stirring and mixing.

[Resin composition] 12 parts by weight of polyether sulfone (PES), epoxy resin particles (manufactured by Sanyo Chemical Co., Ltd.)
After mixing 14.49 parts by weight of a polymer pole having an average particle size of 0.5 μm, 30 parts by weight of NMP were further added,
It was obtained by stirring and mixing with a bead mill.

[Curing agent composition] 2 parts by weight of imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of photoinitiator (Irgacure I-907, manufactured by Ciba Geigy), photosensitizer (manufactured by Nippon Kayaku) , DETX-S) 0.2 parts by weight and NMP 1.5 parts by weight with stirring.

C. Raw material composition for resin filler preparation [Resin composition] 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U), having an average particle diameter of 1.6 μm coated with a silane coupling agent on the surface SiO ₂ spherical particles (Admatech, CRS
1101-CE, where the maximum particle size is 170 parts by weight of the inner layer copper pattern described below (15 μm or less) and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) by stirring and mixing. The viscosity of the mixture is 23 ±
It was obtained by adjusting to 45,000 to 49,000 cps at 1 ° C. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN) 6.5 parts by weight.

D. Solder resist composition 60% by weight of cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in DMDG was sensitized with 50% of epoxy groups of acrylated oligomer (molecular weight 4000).
6.67 g, 15.0 g of 80 wt% bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Chemicals,
2E4MZ-CN) 1.6 g, photosensitive acrylic monomer (Nippon Kayaku, R604) 3 g, polyvalent acrylic monomer (Kyoeisha Chemical, DPE6A) 1.5 g, dispersion defoamer (Sannopco) , S-65), and 2 g of benzophenone (Kanto Chemical) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Chemical) as a photosensitizer were added to the mixture. 2.0P at 25 ° C
A solder resist composition adjusted to a · s was obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type).
Rotor No.4 for 60rpm, rotor for 6rpm
No.3.

Next, a manufacturing process of the multilayer build-up wiring board according to the first embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. In the first embodiment, a multilayer build-up wiring board is formed by a semi-additive method.

(1) As shown in FIG. 1A, an 18 μm copper foil 3 is formed on both sides of a substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm.
2 was used as a starting material. First, the copper clad laminate 30A is drilled,
A through hole 36 is formed by performing an electroless plating process (FIG. 1B), and a conductor circuit 34 is provided by etching in a pattern to form the core substrate 30 shown in FIG. 1C. I do.

(2) Conductor circuit 34 and through hole 36
After the substrate 30 on which is formed is washed with water and dried, NaOH (10 g / l), NaClO ₂ (40
g / l), Na ₃ PO ₄ (6 g / l), as a reducing bath,
The oxidation-reduction treatment using NaOH (10 g / l) and NaBH ₄ (6 g / l) allows the conductor circuit 34 and the through-hole 3 to be formed.
6 was provided with a roughened layer 38 (see FIG. 1D).

(3) The raw material composition for preparing the resin filler C was mixed and kneaded to obtain a resin filler.

(4) By applying the resin filler 40 obtained in the above (3) to both surfaces of the substrate 30 using a roll coater within 24 hours after the preparation, the conductor circuit 34 and the conductor circuit 34
And the inside of the through hole 36 is dried at 70 ° C. for 20 minutes, and the other surface is similarly filled between the conductor circuits 34 and 34 or the through hole 36.
The inside was filled with a resin filler 40 and dried by heating at 70 ° C. for 20 minutes (see FIG. 2E).

(5) One surface of the substrate 30 after the processing of (4) is subjected to belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku) to form the surface of the conductor circuit 34 and the through holes 36. Polishing was performed so that the resin filler 40 did not remain on the surface of the land 36a, and then buffing was performed to remove scratches due to the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate (see FIG. 2F). Then at 120 ° C for 1 hour at 100 ° C
For 3 hours, at 150 ° C. for 1 hour, and at 180 ° C. for 7 hours to cure the resin filler 40.

In this way, the surface layer of the resin filler 40 filled in the through-holes 36 and the like and the roughened layer 38 on the upper surface of the conductor circuit 34 are removed to smooth both surfaces of the substrate 30, and then the resin filler 40 is removed. 40 and the side of the conductor circuit 34 are roughened layers 3
8, and a wiring board in which the inner wall surface of the through hole 36 and the resin filler 40 were firmly adhered through the roughened layer 38 was obtained. That is, by this step, the surface of the resin filler 40 and the surface of the conductor circuit 34 are flush with each other.

(6) The substrate 30 on which the conductor circuit 34 is formed is alkali-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst and activate the catalyst. After the conversion, copper sulfate 3.2 ×
10 ⁻² mol / l, nickel sulfate 3.9 × 10 ⁻³ m
ol / l, complexing agent 5.4 × 10 ⁻² mol / l, sodium hypophosphite 3.3 × 10 ⁻¹ mol / l, boric acid 5.0 × 10 ⁻¹ mol / l, surfactant (Surfiel 465, manufactured by Nissin Chemical Industry Co., Ltd.) Immersion in an electroless plating solution consisting of 0.1 g / l, PH = 9, 1 minute after immersion, vertical and horizontal vibrations once every 4 seconds Then, the surface of the land 36a of the conductor circuit 34 and the through hole 36 is
A coating layer of a needle-like alloy made of -Ni-P and a roughened layer 42 were provided (see FIG. 2G).

Further, tin borofluoride 0.1 mol /
1, thiourea 1.0 mol / l, temperature 35 ° C., PH =
A Cu—Sn substitution reaction was performed under the conditions of 1.2, and a 0.3 μm-thick Sn layer (not shown) was provided on the surface of the roughened layer 42.

(7) The raw material composition for preparing the interlayer resin insulating agent of B was stirred and mixed, and the viscosity was adjusted to 1.5 Pa · s to obtain an interlayer resin insulating agent (for lower layer). Next, the raw material composition for preparing the adhesive for electroless plating of A was stirred and mixed, and the viscosity was adjusted to 7 Pa · s to obtain an adhesive solution for electroless plating (for the upper layer).

(8) The interlayer resin insulating material (for lower layer) having a viscosity of 1.5 Pa · s obtained in the above (7) is applied on both surfaces of the substrate of the above (6).
4 was coated with a roll coater within 24 hours after preparation, left in a horizontal state for 20 minutes, dried at 60 ° C. for 30 minutes (prebaked), and then the viscosity of 7 Pa · obtained in the above (7) was obtained. s
Of the photosensitive adhesive solution (for upper layer) 46 is applied within 24 hours after preparation, and left in a horizontal state for 20 minutes.
Then, the adhesive layer 50α having a thickness of 35 μm was formed (see FIG. 2H).

(9) The substrate 30 on which the adhesive layer 50α is formed in the above (8) is placed at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and then
After performing a heat treatment (post-bake) at 150 ° C. for 3 hours to form an interlayer resin insulating layer (two-layer structure) 50, a carbon dioxide gas laser (Mitsubishi Electric ML605GTL) is used to obtain 30 mJ, 52 × 10 −6. Laser irradiation was performed under a pulse condition of 15 seconds under a condition of 15 shots to form a through-hole 37 having a diameter of 130 μm (see FIG. 3 (L)). Here, a tin plating layer (not shown) was partially exposed in the through hole 37.

In the present embodiment, the through hole 37 is formed in the portion of the core substrate 30 where the conductor circuit 34 is not provided. However, when forming the through hole in the portion where the conductor circuit 34 is provided, It is desirable that the surface of the circuit 34 be subjected to a blackening treatment. Thereby, a through hole can be easily formed in the conductor circuit 34 and the core substrate 30 by the laser. In this embodiment, a carbon dioxide laser is used as a laser, but various lasers such as an excimer, a YAG, and a UV laser can be used.

(10) The substrate 30 in which the through hole 37 is formed is
By immersing in chromic acid for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulation layer 50,
The surface of the interlayer resin insulating layer 50 was roughened (see FIG. 3 (J)), and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water.

(11) By applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate 30 whose surface has been roughened in the step (10), catalyst nuclei are added to the surfaces of the interlayer resin insulating layer 50 and the through holes 37. Attached. Thereafter, the substrate 30 is immersed in an electroless copper plating aqueous solution having the following composition to form an electroless plating film 52 having a thickness of 0.6 μm as a whole (FIG. 3).
(K)). [Electroless plating aqueous solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. 30 minutes at liquid temperature

(12) A commercially available photosensitive dry film (not shown) is adhered on the electroless copper plating film 52 formed in the above (11), and a mask (not shown) on which a predetermined pattern is drawn.
Was placed and exposed at 100 mJ / cm ² , and then developed with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 15 μm (see FIG. 3 (L)).

(13) Then, by passing an electric current through the electroless copper plating film 52, the portion where the resist is not formed is subjected to electrolytic copper plating under the following conditions, and the electrolytic copper plating film 5 having a thickness of 15 μm is formed.
6 was formed (see FIG. 4 (M)). [Electroplating aqueous solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (captoside GL, manufactured by Atotech Japan) 1 ml / l [Electroplating conditions] Current density 1 A / dm ² hours 30 minutes Temperature Room temperature

(14) First, the plating resist 54 is made 5% KO
Remove with H. Thereafter, the electroless plating film 52 under the plating resist is dissolved (removed) by etching (light etching) with a mixed solution of sulfuric acid and hydrogen peroxide, and a thickness of 15 μm including the electroless copper plating film 52 and the electrolytic copper plating film 56 is formed.
The wiring pattern 58 and the through path 39 of FIG.
(N)).

(15) By performing the same processing as in (6), a roughened surface 62 made of Cu-Ni-P was formed on the surface of the wiring pattern 58 and the through-passage 39, and the surface was further substituted with Sn. (FIG. 5
(O)).

(16) In the same manner as in (8) above, an interlayer resin insulating agent (for lower layer) 44 and an adhesive solution (for upper layer) 4
6 and left in a horizontal state for 20 minutes, followed by pre-baking and post-baking to obtain an interlayer resin insulating layer (2
A layer structure) 150 was formed (FIG. 4 (P)).

(17) Thereafter, a carbon dioxide laser (Mitsubishi Electric Corporation)
ML605GTL), 30 mJ, 52 × 10 -6
Laser irradiation was performed under the condition of five shots under pulse conditions of seconds, and through holes 148a and 148b having a diameter of 130 μm were provided (see FIG. 5 (Q)). Here, a through hole 148 penetrating through the interlayer resin insulating layer 150 is provided at a position where the conductive pattern 58 is provided below the upper interlayer resin insulating layer 150.
a is drilled. On the other hand, at a position where the conductor pattern 58 is not provided under the interlayer resin insulation layer 150, the interlayer resin insulation layer 15 extending to the conductor circuit 34 on the surface of the core substrate 30 is provided.
0 and a through hole 148b penetrating through the interlayer resin insulation layer 50.

(18) Then, as in the above (10), the substrate 30
Is immersed in chromic acid to roughen the surface of the interlayer resin insulation layer 150 (see FIG. 5 (R)), and the electroless plating film 152 having a thickness of 0.6 μm as a whole is obtained in the same manner as in the above (11). Is formed (see FIG. 5 (S)). Then, similarly to the above (12), after a plating resist 154 having a thickness of 15 μm is provided (see FIG. 6 (T)), a current flows through the electroless copper plating film 152 as in the above (13). Thus, an electrolytic copper plating film 156 having a thickness of 15 μm was formed (see FIG. 6 (U)). the above
Similarly to (14), after the plating resist 154 is peeled off and removed, the electroless plating film 152 under the plating resist is dissolved and removed by light etching, and the thickness of the electroless copper plating film 152 and the electrolytic copper plating film 156 is formed. A 15 μm wiring pattern 158 and via holes 160a and 160b were formed (FIG. 6 (V)). Thereafter, a roughened layer 162 is formed in the wiring pattern 158 and the via holes 160a and 160b in the same manner as in (15), thereby completing a multilayer build-up wiring board (see FIG. 7 (W)). In the step of forming the upper wiring pattern and the via hole,
No Sn substitution was performed.

(19) Then, solder bumps are formed on the multilayer build-up wiring board described above. On both surfaces of the substrate 30 obtained in the above (18), Is applied in a thickness of 45 μm. Then 70
After performing a drying process at 20 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a 5 mm-thick photomask film (not shown) on which a circular pattern (mask pattern) is drawn is placed in close contact,
It is exposed to ultraviolet rays of 00 mJ / cm ² and subjected to DMTG development processing. Further, heat treatment is performed at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours. A solder resist layer (thickness: 20 μm) 70 having a diameter (200 μm) 71 is formed (see FIG. 7 (X)).

(20) Next, nickel chloride 2.31 × 10 ^-1 mo
1 / l, sodium hypophosphite 2.8 × 10 ^-1 mol /
1 and 1.85 × 10 ⁻¹ mol / l of sodium citrate, and the substrate 3 was placed in an electroless nickel plating solution having a pH of 4.5.
0 was immersed for 20 minutes to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. Further, the substrate was treated with potassium cyanide 4.1 × 10 ⁻² mol / l, ammonium chloride 1.87 × 10 ⁻¹ mol / l, sodium citrate 1.
16 × 10 ⁻¹ mol / l, sodium hypophosphite 1.7 × 10
Immersion in an electroless gold plating solution of ^-1 mol / l at 80 ° C. for 7 minutes and 20 seconds to form a film having a thickness of 0.2 mm on the nickel plating layer.
By forming a gold plating layer 74 of 03 μm, solder pads 75 are formed in the via holes 160a and 160b (see FIG. 8 (Y)). After that, the reinforcing layer 78 of the solder resist layer 70 is covered.

(21) Then, solder paste is printed in the opening 71 of the solder resist layer 70 and reflowed at 200 ° C., so that the solder bumps (solder bodies) 76U, 76D
Was formed to complete the multilayer build-up wiring board 10 (see FIG. 8 (Z)).

The IC chip 90 is mounted on the solder bumps 76U of the completed multilayer build-up wiring board 10 such that the pads 92 of the IC chip 90 correspond to the solder bumps 76U and reflow is performed. After that, the multilayer build-up wiring board 10 on which the IC chip 90 is mounted is placed so as to correspond to the bumps 96 on the daughter board 94 side, reflowed, and attached to the daughter board 94. (See FIG. 9).

In the present embodiment, in a multilayer build-up wiring board having two interlayer resin insulating layers formed on one side,
A via hole 160b penetrating the two layers was formed.
In a multilayer build-up wiring board having at least two interlayer resin insulation layers, via holes can be formed so as to penetrate two or more interlayer resin insulation layers. Further, in the above-described embodiment, the multilayer build-up wiring board in which the core substrate and the interlayer resin insulating layer immediately above the core substrate are pierced by one layer is exemplified. However, a through-path can be formed in any number of interlayer resin insulating layers together with the core substrate. Needless to say.

[Brief description of the drawings]

1 (A), 1 (B), 1 (C), 1
(D) is a manufacturing process diagram of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIG. 2 (E), FIG. 2 (F), FIG. 2 (G), FIG.
(H) is a manufacturing process diagram of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIG. 3 (I), FIG. 3 (J), FIG. 3 (K), FIG.
(L) is a manufacturing process diagram of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIGS. 4 (M), 4 (N), 4 (O), 4
(P) is a manufacturing process diagram of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIGS. 5 (Q), 5 (R), and 5 (S) are manufacturing process diagrams of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIGS. 6 (T), 6 (U), and 6 (V) are cross-sectional views of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIGS. 7 (W) and 7 (X) are cross-sectional views of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIGS. 8 (Y) and 8 (Z) are cross-sectional views of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIG. 9 is a sectional view of the multilayer build-up wiring board according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view of a multilayer build-up wiring board according to the related art.

[Explanation of symbols]

 Reference Signs List 30 core substrate 36 via hole 37 through hole 39 through path 50 interlayer resin insulating layer 58 wiring pattern (conductor layer) 148a, 148b through hole 150 interlayer resin insulating layer 158 wiring pattern (conductor layer) 160a, 160b via hole (conductor layer)

Claims (5)

[Claims] 1. A multilayer build-up wiring board in which interlayer resin insulation layers and conductor layers are alternately laminated, and upper and lower conductor layers of the interlayer resin insulation layer are connected by via holes. A multilayer build-up wiring board, wherein a via hole penetrating an insulating layer and an upper interlayer resin insulating layer is formed. 2. The multilayer build-up wiring board has a core substrate, and at least a through hole penetrating the core substrate is connected to a via hole penetrating the lower and upper interlayer resin insulation layers. The multilayer build-up wiring board according to claim 1, wherein 3. A multilayer build-up wiring board in which interlayer resin insulation layers and conductor layers are alternately laminated on both surfaces of a core substrate, and upper and lower conductor layers of the interlayer resin insulation layer are connected by via holes. A multilayer build-up wiring board, wherein a conductor layer on an interlayer resin insulating layer on the core substrate is connected by a through hole penetrating the substrate and an interlayer resin insulating layer formed on the core substrate. . 4. A method for manufacturing a multilayer build-up wiring board, comprising at least steps (A) to (C): (A) forming a conductive layer on a lower interlayer resin insulating layer; Forming an upper interlayer resin insulation layer, (B) forming a through hole in the lower interlayer resin insulation layer and the upper interlayer resin insulation layer with a laser, and (C) forming a via hole in the through hole. Forming a layer; 5. A method for manufacturing a multilayer build-up wiring board, comprising at least steps (A) to (C): (A) forming an interlayer resin insulating layer on a core substrate on which a conductor layer is formed; Forming; (B) forming a through-hole by laser in the core substrate and the interlayer resin insulating layer;
(C) forming a conductor layer in the through hole;