JP2000307225A - Mask for solder printing and print wiring board and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a print wiring board with excellent connectability and reliability and a method for manufacturing this by holding the shape of a solder bump at the time of solder printing. SOLUTION: Soldering paste is packed, and reflow is carried out by using a mask for solder printing formed by making equal the open areas of through- holes so that solder bumps 76U can be formed. Afterwards, heating, pressurization, or heating/pressurization is carried out so that the top parts of the solder bumps 76U can be flattened. The height is arranged so that the connectability with an IC chip can be improved. Also, the solder quantity is made uniform so that the propagating speeds of signals in the solder bump 76U on a via hole 160 and the solder bump 76U on a conductive circuit 158 can be made uniform.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board having solder bumps for connection to pads of electronic components such as IC chips, a method of manufacturing the printed wiring board, and a solder for filling a solder paste to be solder bumps. It also relates to a print forming mask.

[0002]

2. Description of the Related Art Conventionally, build-up multilayer printed wiring boards have been manufactured, for example, by the method disclosed in Japanese Patent Application Laid-Open No. Hei 9-130050. That is, a roughened layer is formed on the surface of the conductor circuit of the build-up multilayer printed wiring board by electroless plating or etching. Then, an interlayer insulating resin is applied by a roll coater or printing, and then exposed and developed to form a via hole opening for interlayer conduction, and UV curing and main curing to form an interlayer resin insulating layer. . Further, the interlayer insulating layer is subjected to a roughening treatment with an acid or an oxidizing agent to form a roughened surface, and a catalyst such as palladium is applied to the roughened surface to form a thin electroless plating film.
A pattern is formed on the plating film with a dry film, and after thickening by electrolytic plating, the dry film is peeled off with an alkali and etched to form a conductor circuit. By repeating this, a build-up multilayer printed wiring board is obtained.

Further, a solder resist layer is applied to the outermost layer of the printed wiring board in order to protect the conductor circuit. When forming the solder bumps, a part of the solder resist layer is opened for connection with the conductor circuit, the solder circuit is printed on the exposed conductor circuit, and the solder bump is formed by reflow. Is formed.

[0004]

However, in a printed wiring board in which solder bumps are provided on via holes having depressions and on smoothly formed conductor circuits, the height and shape of the solder bumps are not uniform. There were challenges.
That is, when the solder paste is filled into the opening of the solder resist layer using a mask for solder printing, the opening of the solder resist layer formed on the via hole having a depression,
Since the amount of the solder paste filled with the opening of the solder resist layer formed on the conductor circuit formed smoothly is the same, the solder bump on the via hole is compared with the solder bump of the smooth conductor circuit. The diameter of the hemisphere tended to decrease and the height also tended to decrease. Here, if the height of the solder bumps is not uniform, it may not be possible to join the IC chip. Further, if the shape (diameter of a hemisphere) is not uniform, the solder bumps may not fit into the bumps of an electronic component such as an IC chip, and the IC chip may be tilted after the mounting, resulting in disconnection.

For this reason, the present inventor has devised that the filling amount of the solder paste is changed by changing the diameter of the through hole of the solder printing mask for printing the solder paste. That is, the idea was that the diameter of the through hole for filling the via hole with the solder paste was larger than the diameter of the through hole for filling the smooth conductive circuit.

However, it has been found that when the amount of the solder bumps to be formed is made different, the transmission speed of the signal from the IC chip becomes different. That is, with the increase in the speed of the electric signal of the IC chip, the difference in the transmission speed is caused even by a minute difference in the amount of solder formed on the solder bump.

An object of the present invention is to propose a printed wiring board which retains the shape of a solder bump in solder printing and has excellent connectivity and reliability, a method of manufacturing the same, and a mask for solder printing used in the manufacturing method. It is in.

[0008]

As a result of the inventor's intensive research, the diameter of the through-hole of the printing mask filled with the solder paste is adjusted (the opening area is set to 1.0 to 2 times the opening area of the solder pad).
It has been found that setting the ratio to 0) makes it easier to make the shape and height of the solder bumps uniform. This magnification is particularly suitable when the thickness of the solder resist is in the range of 5 to 70 μm. Also, this magnification is equal to the opening area of the solder pad.
When solder bumps are formed in openings each having the same opening area of 075 mm ² or less, circuits exposed from the solder resist layer are formed as via holes (all the following descriptions are referred to as via-on) and via holes such as smooth conductor circuits. It is better to form the solder bumps using a mask formed with the same opening area regardless of the other (all the following descriptions are described as via-off). As a result, it was found that the solder paste bleeds during printing and flows out onto the solder resist layer after reflow, so that a short circuit between the solder bumps can be prevented.

The gap of the through hole of the solder printing mask is 20.
It was also found that if it was not less than μm, there was no insufficient filling of the solder paste and no solder bumps were not formed due to no filling even with the same opening area. That is, when the gap is less than 20 μm, unfilled solder paste occurs at the same opening area of the solder pad and the same opening diameter of the mask, and there is no margin for misalignment due to the narrow pitch, so that solder bumps cannot be formed. is there.

The through holes in the solder printing mask are as follows:
The taper may be straight toward the solder resist layer on the printed wiring board side, or may be tapered to gradually increase in diameter. The taper is such that the difference between the radius of the opening of the printing mask with respect to the printed wiring board on the solder resist side and the radius of the opening on the side filled with the solder paste is zero.
It is good that it is 〜25 μm. Particularly, a taper width of 5 to 15 μm is desirable. By providing such a taper,
Since the removal of the solder paste from the mask is improved, the filling of the solder pads is improved. Thereby, the shape and size of the formed solder bump can be maintained uniformly. In particular, it is possible to improve the filling property of the via hole, eliminate the gap due to insufficient filling of the bottom portion of the via hole, and improve the performance and quality of the printed wiring board.

The material of the mask used in the present invention is as follows.
For example, there are a metal mask such as a nickel alloy and a nickel-cobalt alloy, and a plastic mask such as an epoxy resin and a polyimide resin. However, the material of the mask is not particularly limited, and all materials used for a print mask for manufacturing a printed wiring board and other print masks can be used. Etching, additive processing, laser processing, etc., can be used as a method of forming the through holes of the mask.
In particular, additive processing is preferable.

The thickness of the mask is desirably 20 to 70 μm. In particular, those having a thickness of 35 to 50 μm are preferable. The reason for this is that there is little problem with the removability of the openings of the solder paste and the filling of the via holes. Therefore, it is easy to change the solder paste and change the mask design such as the opening diameter in the viscosity. If the mask thickness is less than 20 μm, the height of the formed bump is difficult to be uniform, and it is difficult to form a taper having a desired width. Further, the mask itself is easily damaged, and the working efficiency is reduced. On the other hand, when the thickness of the mask is 70 μm
If it exceeds, the removability of the solder paste will decrease,
Since the paste remains in the opening, the shape and height of the solder bump may not be uniform. For this reason,
As the density becomes higher and finer, solder bumps cannot be formed.

As the solder paste used for forming the solder bumps of the present invention, any solder paste generally used in the manufacture of printed wiring boards can be used. As an example of a solder paste, Sn: Pb = 6
3:37, Sn: Pb: Ag = 62: 36: 2, Sn:
Ag = 96.5: 3.5. In particular, it is preferable to use those having Sn: Pb in the range of 9: 1 to 4: 6. A solder paste having a particle diameter of 5 to 40 μm is used.
It is better to use s. The reason is that 100 Pa. s, the shape of the solder bump cannot be maintained, and 400 Pa.s. If it is higher than s, the solder paste cannot be efficiently filled into the openings on the solder resist layer.

Further, in a preferred embodiment of the present invention, a solder printing mask having the same size as the opening area of the through hole for printing in the opening of the via hole and the opening area of the through hole for printing on the circuit. Then, a solder paste is filled into the opening by using the method, and reflow is performed to form a solder bump. Thereafter, the top of the solder bump can be flattened by heating, pressing, or heating and pressing. In other words, the height is made uniform by flattening the tops of the solder bumps,
In addition to improving the connectivity with an IC chip or the like, the amount of solder is made uniform and the signal propagation speed is made uniform between the solder bumps on the via holes and the solder bumps on the conductor circuit. As a result, the flat area at the top of the solder bump on the smooth formed circuit is larger than the flat area at the top of the solder bump formed on the via hole.

In a preferred aspect of the present invention, a roughened layer is formed on a conductor circuit provided on a surface layer of a printed wiring board. The roughened layer to be formed is desirably a roughened surface of copper formed by an etching process, a polishing process, an oxidation process, or an oxidation-reduction process or a roughened surface formed by a plating film.

Next, a solder-resist layer is formed on the conductor circuit. The thickness of the solder resist layer in the present invention is preferably 5 to 40 μm. If it is too thin, it will not function as a solder dam, and if it is too thick, it will not be easy to open, and it will cause cracks in the solder body due to contact with the solder body. As the solder resist layer, various resins can be used. For example, bisphenol A type epoxy resin, acrylate of bisphenol A type epoxy resin, novolak type epoxy resin, acrylate of novolak type epoxy resin may be used as an amine curing agent or an imidazole curing agent. Can be used. In particular, when an opening is provided in the solder resist layer to form a solder bump, it is preferable that the solder bump be formed of "novolak-type epoxy resin or acrylate of novolak-type epoxy resin" and include "imidazole curing agent" as a curing agent.

The solder resist layer having such a structure is
There is an advantage that migration of lead (phenomenon in which lead ions diffuse in the solder resist layer) is small. Moreover, this solder resist layer is a resin layer obtained by curing an acrylate of a novolak type epoxy resin with an imidazole curing agent, has excellent heat resistance and alkali resistance, does not deteriorate even at a temperature at which the solder melts (around 200 ° C.), It is not decomposed by a strongly basic plating solution such as plating or gold plating.

However, since such a solder resist layer is formed of a resin having a rigid skeleton, peeling is likely to occur. The roughened layer formed on the conductor circuit is effective for preventing such peeling.

Here, as the acrylate of the novolak type epoxy resin, an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolak with acrylic acid or methacrylic acid can be used. The imidazole curing agent is desirably liquid at 25 ° C. This is because a liquid can be uniformly mixed. As such a liquid imidazole curing agent, 1-benzyl-2-methylimidazole (product name: 1B2MZ
), 1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN), and 4-methyl-2-ethylimidazole (product name: 2E4MZ).

The amount of the imidazole curing agent to be added is preferably 1 to 10% by weight based on the total solid content of the solder resist composition. The reason for this is that if the added amount is within this range, uniform mixing is easy. In the composition before curing of the solder resist, it is desirable to use a glycol ether-based solvent as a solvent. The solder resist layer using such a composition does not generate free oxygen and does not oxidize the copper pad surface. It is also less harmful to the human body.

As such a glycol ether-based solvent, one having the following structural formula, particularly preferably at least one selected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG) is used. This is because these solvents can completely dissolve benzophenone and Michler's ketone as reaction initiators by heating at about 30 to 50 ° C. CH ₃ O— (CH ₂ CH ₂ O) _n —CH ₃ (n = 1 to 5) The glycol ether solvent is preferably 10 to 40% by weight based on the total weight of the solder resist composition. In addition to the solder resist composition described above, various defoaming agents and leveling agents, a thermosetting resin for improving heat resistance and base resistance and imparting flexibility, and a photosensitive resin for improving resolution. A functional monomer or the like can be added. For example, as the leveling agent, one made of a polymer of an acrylate ester is preferable. The initiator is preferably Irgacure I907 manufactured by Ciba-Geigy, and the photosensitizer is DETX-S manufactured by Nippon Kayaku. Further, a dye or a pigment may be added to the solder resist composition. This is because the wiring pattern can be hidden. It is desirable to use phthalocyanine green as this dye.

As the thermosetting resin as an additional component, a bisphenol type epoxy resin can be used. This bisphenol type epoxy resin includes a bisphenol A type epoxy resin and a bisphenol F type epoxy resin, and when importance is attached to base resistance, the former is required to reduce viscosity (when importance is attached to coating properties). The latter is better.

As the photosensitive monomer as an additional component, a polyacrylic monomer can be used.
This is because the polyvalent acrylic monomer can improve the resolution. For example, Nippon Kayaku DPE-6
A, a polyvalent acrylic monomer having a structure such as R-604 manufactured by Kyoeisha Chemical is desirable.

These solder resist compositions may be used at a temperature of 25 ° C. in a range of 0.5 to 10 Pa · s, more preferably, 1 to 10 Pa · s.
-10 Pa · s is preferred. This is because the viscosity is easy to apply with a roll coater. After the formation of the solder resist, an opening is formed. The opening is formed by exposure and development processing.

Then, after the formation of the solder-resist layer, a nickel plating layer is formed on the opening by electroless plating.
Nickel sulfate 4.5 as an example of the composition of the nickel plating solution
g / l, sodium hypophosphite 25 g / l, sodium citrate 40 g / l, boric acid 12 g / l, thiourea 0.1 g.
There is 1 g / l (PH = 11). The opening and the surface of the solder-resist layer are washed with a degreasing solution, a catalyst such as palladium is applied to a conductor portion exposed to the opening, activated, and then immersed in a plating solution to form a nickel plating layer. .

The thickness of the nickel plating layer is 0.5 to 20.
In particular, a thickness of 3 to 10 μm is desirable. 0.5μ
If it is less than m, it is difficult to make a connection between the solder bump and the nickel plating layer. If it exceeds 20 μm, the solder bump formed in the opening cannot be completely accommodated and peels off.

After forming the nickel plating layer, a gold plating layer is formed by gold plating. The thickness is 0.03 μm.
Although two metal layers such as nickel and gold are formed, a single layer, three or more metal layers may be formed, or solder bumps may be formed directly on a conductor circuit.

In a method of forming solder bumps, a solder paste is filled into through holes of a mask using a squeegee. There is no particular limitation on the shape, hardness, material, etc. of the squeegee used. The selection is based on the paste, such as the composition of the solder paste, the viscosity, and the particle size, the thickness and material of the solder resist layer, the opening area of the through hole, the pitch of the through hole and the material of the mask,
It varies depending on factors other than the paste such as hardness.
Alternatively, a press-fit type or roller type closed squeegee may be used.

The diameters of via-on and via-off are equal,
In addition, a solder bump is formed using a solder printing mask having a through hole set to be 1.0 to 2.0 times the opening area of the solder pad. The formed solder bumps are formed by via-on and via-off and have different heights. Via-on solder bumps are higher than via-off solder bumps. The difference in height is 3 to 10 μm, particularly 5 to 7 μm
It is good to be in the range. By providing the height difference, it is also possible to arbitrarily provide the height difference to bumps of electronic components such as IC chips to be connected. For example, the bumps connected to the via-off solder bumps can be higher than those connected to the via-on solder bumps. As a result, a structure in which the electronic component and the solder bump of the substrate are fitted to each other is provided, so that during the mounting, the stress is relieved, so that the solder bump can be prevented from peeling and cracking, and can be easily determined even if the displacement occurs. .

The height of the solder bump is 5 to 70 μm from the upper surface of the solder resist layer. Particularly preferably, the height is 10 to 40 μm. This is because the solder bumps can easily be uniform in the range and can be held. If the height of the solder bumps is less than 5 μm, the solder bumps cannot be bonded to the bumps of electronic components such as IC chips. Conversely, if the height of the solder bumps exceeds 70 μm, the solder will flow out during solder reflow. This may cause a short circuit at the solder bump. The gap of the formed solder bump is 2
It is better to be 0 μm or more. If the thickness is less than 20 μm, insufficient filling of the solder paste occurs, the bump shape is not uniform, the height is too low, and connection with an electronic component such as an IC chip cannot be obtained. In addition, the solder bump may be accommodated in the opening of the solder resist layer, or may be formed along the periphery of the opening.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. In this embodiment, a multilayer printed wiring board will be described as a printed wiring board. FIG. 7 is a sectional view of the multilayer printed wiring board 10, and FIG. 8 shows a state in which an IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG. As shown in FIG. 7, in the multilayer printed wiring board 10,
Conductive circuits 34, 34 are formed on the front and back surfaces of the core substrate 30, and build-up wiring layers 80A, 80B are formed on the conductive circuits 34, 34. The built-up layers 80A and 80B include an interlayer resin insulation layer 50 having via holes 60 and conductor circuits 58 formed therein, and an interlayer resin insulation layer 150 having via holes 160 and conductor circuits 158 formed therein. A solder resist 70 is formed on the upper layer of the via hole 160 and the conductor circuit 158, and is formed through an opening 71 of the solder resist 70.
Solder bump 7 in via hole 160 and conductive circuit 158
6U and 76D are formed.

As shown in FIG. 8, the solder bumps 76U on the upper surface of the multilayer printed wiring board 10 are connected to the lands 92 of the IC chip 90. On the other hand, the lower solder bump 76
D is connected to a land of a daughter board (not shown). Here, the multilayer printed wiring board 10 and the IC chip 90
Is filled with an underfill 88 and sealed with a resin.

Next, a solder printing mask for forming the solder bump 76U on the IC chip connection side will be described with reference to FIG. FIG. 9A is a plan view of a solder printing mask (metal mask) 20, and FIG.
FIG. 10B shows a BB cross section of FIG. The mask 20 for solder printing is made of a thin film of a nickel alloy having a thickness of 50 μm, and has openings 71 for filling the solder paste in openings 71 of the solder resist layer 70. here,
The through-hole 22 is a via hole 160 having a depression shown in FIG.
A through-hole (via-on through-hole) for forming the solder bump 76U thereon and a through-hole (via-off through-hole) for forming the solder bump 76U on the smooth conductor circuit 158 shown in FIG. 165 μm (open area 0.021
mm ² ), and has a diameter of 175 μm on the bottom surface (the side in contact with the multilayer printed wiring board) and is tapered to a width of 5 μm. The gap between the through holes 22 is 50
It is set to μm.

The solder printing mask 20 has a thickness of 50 μm.
The tapered through-hole 22 is formed by subjecting the nickel alloy thin film of m to the additive processing from the bottom side or the laser processing of the SUS thin film.

FIG. 9C shows a solder printing mask 320 according to another embodiment. This solder printing mask 320
In this example, a through hole 322 having a diameter of 170 μm and having no taper is formed by laser processing.

Next, a method of manufacturing the multilayer printed wiring board 10 will be described. Here, first, A. A. used in the method of manufacturing the multilayer printed wiring board of the first embodiment is described. Adhesive for electroless plating, B. Interlayer resin insulation, C.I. Resin filler, D.I. The composition of the solder resist raw material composition will be described.

A. Raw material composition for preparation of adhesive for electroless plating (adhesive for upper layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
35% by weight of a resin solution dissolved in DMDG at a concentration of 3.15% and a photosensitive monomer (Toa Gosei Co., Aronix M315) 3.15
Parts by weight, 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, S-65)
3.6 parts by weight of NMP were obtained by stirring and mixing. [Resin composition] Polyether sulfone (PES) 12
Parts by weight, epoxy resin particles (manufactured by Sanyo Chemical Industries, polymer pole) with an average particle size of 1.0 μm, 7.2 parts by weight, average particle size
After mixing 0.59 μm of 3.09 parts by weight,
30 parts by weight of MP was added, and the mixture was stirred and mixed with a bead mill to obtain. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN), 2 parts by weight of a photoinitiator (Circa Geigy, Irgacure I-907), 0.2 parts by weight of a photosensitizer (Nippon Kayaku, DETX-S), and 1.5 parts by weight of NMP are stirred and mixed. I got it.

B. Raw material composition for preparing interlayer resin insulation agent (adhesive for lower layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
% Of a resin solution dissolved in DMDG at a concentration of 35%, 4 parts by weight of a photosensitive monomer (Alonix M315, manufactured by Toagosei Co., Ltd.), 0.5 parts by weight of an antifoaming agent (S-65, manufactured by San Nopco), N
3.6 parts by weight of MP were obtained by stirring and mixing. [Resin composition] Polyether sulfone (PES) 12
After mixing 14.49 parts by weight of an epoxy resin particle (manufactured by Sanyo Chemical Industries, polymer pole) having an average particle size of 0.5 μm, 30 parts by weight of NMP was further added, and the mixture was stirred and mixed with a bead mill. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN), 2 parts by weight of a photoinitiator (Circa Geigy, Irgacure I-907), 0.2 parts by weight of a photosensitizer (Nippon Kayaku, DETX-S), 1.5 parts by weight of NMP I got it.

C. Raw material composition for resin filler preparation [Resin composition] 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U), having an average particle diameter of 1.6 μm coated with a silane coupling agent on the surface SiO ₂ spherical particles (Admatech, CRS
1101-CE, where the maximum particle size is 170 parts by weight of the inner layer copper pattern described below (15 μm or less) and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) by stirring and mixing. The viscosity of the mixture is 23 ±
It was obtained by adjusting to 45,000 to 49,000 cps at 1 ° C. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN) 6.5 parts by weight.

D. Raw Material Composition of Solder Resist A 60% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in DMDG was sensitized with an oligomer (molecular weight 4000) having a 50% epoxy group acrylated.
6.67 g, 15.0 g of 80 wt% bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Chemicals,
2E4MZ-CN) 1.6 g, photosensitive acrylic monomer (Nippon Kayaku, R604) 3 g, polyvalent acrylic monomer (Kyoeisha Chemical, DPE6A) 1.5 g, dispersion defoamer (Sannopco) , S-65), and 2 g of benzophenone (Kanto Chemical) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Chemical) as a photosensitizer were added to the mixture. 2.0P at 25 ° C
A solder resist composition adjusted to a · s was obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type).
Rotor No.4 for 60rpm, rotor for 6rpm
No.3.

Manufacture of Printed Wiring Board (1) Both sides of a substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm
copper-clad laminate 30 on which copper foil 32 of μm is laminated
A was used as a starting material (step (A) in FIG. 1). First, this copper clad laminate is drilled and subjected to electroless plating.
The inner layer copper pattern 34 and the through-hole 36 were formed on both surfaces of the substrate by etching in a pattern (step (B)).

(2) The substrate 30 on which the inner layer copper pattern 34 and the through hole 36 are formed is washed with water, dried, and then used as an oxidation bath (blackening bath) as NaOH (10 g / l) and NaClO _2.
(40 g / l), Na ₃ PO ₄ (6 g / l), and an oxidation-reduction treatment using NaOH (10 g / l) and NaBH ₄ (6 g / l) as a reducing bath to form the inner layer copper pattern 34 and the through hole. A roughened layer 38 was provided on the surface of Step 36 (Step (C)).

(3) The raw material composition for preparing the resin filler C was mixed and kneaded to obtain a resin filler.

(4) After preparing the resin filler obtained in the above (3),
The coating and filling were performed between the conductor circuits or in the through holes 36 within 24 hours. The coating was performed by a printing method using a squeegee. In the first printing application, the inside of the through hole 36 was mainly filled and dried at 100 ° C. in a drying furnace for 20 minutes. In the second printing application, the recess formed mainly by the formation of the conductor circuit (inner layer copper pattern) 34 is filled, and the resin filler 40 is filled between the conductor circuit 34 and the conductor circuit 34 and in the through hole 36. After that, it was dried under the above-mentioned drying conditions (step (D)).

(5) The surface of the inner layer copper pattern 34 and the through holes 36 are polished on one side of the substrate 30 after the treatment of the above (4) by belt sanding using # 600 belt polishing paper (manufactured by Sankyo Rikagaku). Was polished so that the resin filler did not remain on the surface of the land 36a, and then buffed to remove the scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate (step (E) in FIG. 2). Then at 100 ° C for 1 hour, 1
Heat treatment was performed at 50 ° C. for 1 hour to cure the resin filler 40.

In this manner, the surface layer portion of the resin filler 40 filled in the through holes 36 and the like and the inner layer conductor circuit 3
(4) The roughened layer 38 on the upper surface is removed to smooth both surfaces of the substrate, and the resin filler 40 and the side surfaces of the inner conductor circuit 34 are roughened.
To obtain a wiring board in which the inner wall surface of the through-hole 36 and the resin filler 40 are firmly adhered to each other through the roughened layer 38. That is, by this step, the surface of the resin filler 40 and the surface of the inner layer copper pattern 34 are flush with each other.

(6) The substrate 30 on which the conductor circuit 34 is formed is alkali-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst and activate the catalyst. 3.9x copper sulfate
10 ⁻² mol / l, nickel sulfate 3.8 × 10 ⁻³ m
ol / l, sodium citrate 7.8 × 10 ⁻³ mol
/ L, sodium hypophosphite 2.3 × 10 ^-1 mol /
l, surfactant (Surfir 46, manufactured by Nissin Chemical Industry Co., Ltd.)
5) Immersion in an electroless plating solution consisting of 1.1 × 10 ⁻⁴ mol / l, PH = 9, 1 minute after immersion, vertical and horizontal vibrations once every 4 seconds, and A coating layer of a needle-like alloy made of Cu-Ni-P and a roughened layer 42 were provided on the surface of the land of the circuit and the through hole (step (F)). Furthermore, tin borofluoride 0.1 mol / l,
Thiourea 1.0 mol / l, temperature 35 ° C, PH = 1.2
Under the conditions described above, a 0.3 μm thick Sn layer (not shown) was provided on the surface of the roughened layer.

(7) The raw material composition for preparing the interlayer resin insulating agent B was stirred and mixed, and the viscosity was adjusted to 1.5 Pa · s to obtain an interlayer resin insulating agent (for lower layer). Next, the raw material composition for preparing the adhesive for electroless plating of A was stirred and mixed, and the viscosity was adjusted to 7 Pa · s to obtain an adhesive solution for electroless plating (for the upper layer).

(8) On both surfaces of the substrate 30 of (6),
The interlayer resin insulating agent (for lower layer) 44 having a viscosity of 1.5 Pa · s obtained in (7) was applied by a roll coater within 24 hours after preparation,
After standing for 20 minutes in a horizontal state, drying (prebaking) was performed at 60 ° C. for 30 minutes.
After preparing a Pa · s photosensitive adhesive solution (for upper layer) 46
Apply within 20 hours, leave it horizontal for 20 minutes, then
Drying (prebaking) was performed at 30 ° C. for 30 minutes to form an adhesive layer 50α having a thickness of 35 μm (step (G)).

(9) The substrate 3 on which the adhesive layer was formed in the above (8)
A photomask film 51 having a black circle 51a of 85 μmφ printed thereon is brought into close contact with both sides of
Exposure was performed at 00 mJ / cm ² (step (H)). This is DMT
G solution, and then exposed the substrate to 3000 mJ / cm ² with an ultra-high pressure mercury lamp,
Heat treatment (post-bake) at 120 ° C. for 1 hour and then at 150 ° C. for 3 hours to obtain an 85 μmφ opening (via hole forming opening) 48 with excellent dimensional accuracy equivalent to a photomask film A 35 μm interlayer resin insulating layer (two-layer structure) 50 was formed (step (I) in FIG. 3). Note that a tin plating layer (not shown) was partially exposed in the opening 48 serving as a via hole.

(10) The substrate 30 in which the opening 48 is formed is immersed in chromic acid for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer, thereby forming the interlayer resin insulating layer 50. The surface was roughened, and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water (step (J)). Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate subjected to the surface roughening treatment (roughening depth: 6 μm), the catalyst is formed on the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via hole opening 48. Attach a nucleus.

(11) The substrate is immersed in an aqueous electroless copper plating solution having the following composition, and a thickness of 0.6 to 1.2 μm
Was formed (step (K)). [Electroless plating aqueous solution] EDTA 0.08 mol / l Copper sulfate 0.03 mol / l HCHO 0.05 mol / l NaOH 0.05 mol / l α, α'-bipyridyl 80 mg / l PEG 0.10 g / l [Electroless plating conditions] 65 ° C 20 minutes at liquid temperature

(12) A commercially available photosensitive dry film is stuck on the electroless copper plating film 52 formed in the above (11), a mask is placed on the film, exposed at 100 mJ / cm ² , and exposed to 0.8% sodium carbonate. Developed, 15μm thick plating resist 54
Was provided (step (L)).

(13) Next, electrolytic copper plating was performed on the non-resist-formed portion under the following conditions to form an electrolytic copper plating film 56 having a thickness of 15 μm (step (M) in FIG. 4). [Aqueous electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (captoside HL, manufactured by Atotech Japan) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm ² hours 65 minutes Temperature 22 ± 2 ° C

(14) After the plating resist 54 is peeled off with 5% KOH, it is etched with a mixed solution of sulfuric acid and hydrogen peroxide.
Dissolve and remove the electroless plating film 52 under the plating resist,
A conductor circuit 58 and a via hole 60 each having a thickness of 18 μm (10 to 30 μm) composed of the electroless plating 52 and the electrolytic copper plating film 56 were obtained (step (N)).

The adhesive layer 5 for electroless plating between the conductor circuits 58 was immersed in chromic acid of 80 g / L at 70 ° C. for 3 minutes.
The surface of No. 0 was etched at 1 μm to remove the palladium catalyst on the surface.

(15) The same processing as in (6) is performed, and the conductor circuit 5
A roughened surface 62 made of Cu—Ni—P was formed on the surfaces of the via holes 60 and via holes 60, and the surfaces thereof were further substituted with Sn (step (O)).

(16) By repeating the steps (7) to (14), an upper interlayer resin insulating layer 160, a via hole 160 and a conductor circuit 158 are further formed. Further, the roughened layer 16 is formed on the surface of the via hole 160 and the conductive circuit 158.
2 to complete a multilayer printed wiring board (step (P)). Note that, in the step of forming the upper conductive circuit, Sn substitution was not performed.

(17) The multilayer printed wiring board described above
To form solder bumps. Substrate 3 obtained in (16) above
0 on both sides. Solder resist composition explained in
The object 70α was applied in a thickness of 20 μm (step of FIG. 5).
(Q)). Then dry at 70 ° C for 20 minutes and 70 ° C for 30 minutes
After processing, a circular pattern (mask pattern) is drawn
5mm thick photomask film (not shown)
Placed in close contact, 1000mJ / cm ²Exposure with ultraviolet light
DMTG development processing was performed. And then at 80 ° C for 1 hour, 100
1 hour at 120 ° C, 1 hour at 120 ° C, 3 hours at 150 ° C
Heat the solder pad (via hole and its
Opening 71 (including the chip part) (top side (IC chip side)
Sol with an opening diameter of 130 μm and an opening diameter of the bottom side of 600 μm)
A dark resist layer (thickness: 20 μm) 70 was formed (step
(R)).

(18) Then, nickel chloride 2.3 × 10 ^-1 m
ol / l, sodium hypophosphite 2.8 × 10 ⁻¹ mol /
l, sodium citrate 1.6 × 10 ⁻¹ mol / l, was immersed in an electroless nickel plating solution having a pH of 4.5 for 20 minutes to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. . Further, the substrate was washed with 7.6 × 10 ⁻³ mol / l of potassium potassium cyanide and 1.9 × 10 ³ ammonium chloride.
10 ^-1 mol / l, sodium citrate 1.2 × 10 ^-1 m
ol / l, sodium hypophosphite 1.7 × 10 ^-1 mol /
Then, the substrate was immersed in an electroless gold plating solution composed of 1 for 7.5 minutes at 80 ° C. to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72 (step (S)).

(19) The opening 71 of the solder resist layer 70 is filled with a solder paste. Here, FIG.
The solder printing mask 20 described above with reference to (A) is mounted on the multilayer printed wiring board 10 (step (T) in FIG. 6).
The solder printing mask 20 has through holes (opening area 0.021 mm ² (opening diameter 165 μm)) 2 for printing solder paste on the via holes 160 and the conductor circuits 158.
2 are provided. And viscosity 100Pa. s solder paste 75 was filled in the opening 71 using a rubber squeegee having a hardness of 75 ° (step (U)). FIG. 6 (W) is an enlarged view of the opening 71 on the upper side (IC chip side).

(20) Thereafter, the solder filled in the opening 71 of the solder resist layer 70 is reflowed at 200 ° C., thereby forming solder bumps (solder bodies) 76U and 76D (see FIG. 7). In the first embodiment, by adjusting the diameter of the through hole 22 of the solder printing mask 20, the solder bump 76U on the via hole 160 has a height H1 (35 μm).
In addition, the solder bump 76U on the conductor circuit 158 has a height H2.
(40 μm), that is, the difference in height is 5 μm.

(21) After cleaning the flux, the substrate is divided into pieces of an appropriate size using a device having a router, and then subjected to a checker process for inspecting a printed circuit board for short-circuit and disconnection.
The desired corresponding printed wiring board was obtained.

(22) Thereafter, by using a suitable mounting device,
Using the target mark (not shown) of the multilayer printed wiring board, the solder bumps 76U on the printed wiring board side are aligned with the bumps 92 of the corresponding type of IC chip 90 after flux application, and reflow is performed. The solder bump 76U and the bump 92 are joined. Thereafter, flux cleaning was performed to fill an underfill 88 between the IC chip 90 and the multilayer printed wiring board 10. As a result, a printed wiring board on which the IC chip was mounted was obtained (see FIG. 8).

FIG. 10 shows printing of a solder paste according to a modification of the first embodiment. In the first embodiment, FIG.
As described above with reference to (W), the solder paste 75 was printed so as not to protrude to the periphery of the opening 71 of the solder resist layer 71. Instead, as shown in FIG. 10A, a solder paste 75 is used to cover the periphery of the opening 71 using a solder printing mask having a larger diameter through hole.
Is printed, the solder bumps 76U having a larger diameter can be formed by reflow as shown in FIG. 10B.

Next, a printed wiring board according to a second embodiment of the present invention will be described. In the printed wiring board 210 of the second embodiment, as shown in FIG.
The top is flattened to make the heights of 76U and 276D uniform.

A method of manufacturing a printed wiring board according to the second embodiment will be described with reference to FIG. Similarly to the first embodiment, the solder paste is printed using the solder printing mask 20 having the through holes 22 having the uniform diameter described above with reference to FIG. 9, and the solder bumps are formed by reflow.

After the formation of the solder bumps, the tops of the solder bumps 276U are flattened by heating and pressing as shown in FIG. The pressure stage 11 includes a heater (not shown)
And heated to 100 ° C. First, FIG.
As shown in (B), the substrate 30 is placed on the pressing stage 11 with the solder bumps 276U facing upward, and the top of the solder bumps 276U is vertically moved by the pressing head 12 as shown by an arrow while heating. Pressurized. In the present embodiment, a heater is also provided in the pressure head 12, and the heating is performed also from the solder bump 276U side. The pressure at the time of pressurization is 100kgf
/ Cm ² and the heating time was 5 seconds.

As shown in FIG. 11, each of the solder bumps 276
U height H3 (part exposed from solder resist layer)
Was adjusted to 20 μm. Here, the solder bumps 76 on the conductor circuit 158 formed in a relatively large hemispherical shape are used.
A flat surface 77 having a large area is formed on the top of U, and a flat surface having a small area is formed on the solder bump 76U on the via hole 160 formed in a small hemisphere.

In the second embodiment, the height is adjusted to 20 μm by flattening the top of the solder bump 276U.
The solder bumps 276U on the via holes 160 and the solder bumps 276 on the conductor circuits 158 improve the connectivity with the C chip and the like, make the amount of solder uniform, and increase the signal propagation speed.
Make uniform with U. Therefore, it is suitable for mounting an IC chip driven at a high frequency. In addition, the printed wiring board 2
In order to securely attach 10 to the daughter board, the top of solder bump 276D on the attachment side to the daughter board may be flat. The method may be the same as the method of flattening the solder bump 276U on the IC chip mounting side. The pressing stage is heated, and the solder bump 276D on the other surface is flattened simultaneously with the heating and pressing of the solder bump 276U. Alternatively, before or after flattening the top of the solder bump 276U, the substrate on the pressing stage may be turned upside down and pressed.

(Comparative Example 1) Almost the same as the first embodiment, except that the opening area of the mask is 0.011 mm ² (the opening diameter is 12
A solder bump was formed using a mask formed at 0 μm).

(Comparative Example 2) Almost the same as the first embodiment, except that the opening area of the mask was 0.027 mm ² (the opening diameter was 18
A solder bump was formed using a mask formed at 5 μm).

[0073]

As described above, for the printed wiring boards manufactured in the first and second embodiments and Comparative Examples 1 and 2, the solder bump height, the shape of the solder bump, and the state of the solder bump (contamination of the solder resist layer). And a connection test with the IC chip, a continuity test after the formation of solder bumps, and a continuity test after completion of the reliability test. The results are shown in FIGS.

As shown in FIG. 13, in the printed wiring board 10 according to the manufacturing method of the first embodiment, the height difference between the solder bumps formed on the via-on and via-off is uniform at around 5 μm, and All also retained hemispherical. No problems occurred during subsequent mounting and inspection. Further, continuous printing was also possible. Further, there was no connection with the IC chip, and no problems occurred in the continuity test and the reliability test.

As shown in FIG. 14, in the printed wiring board 210 according to the manufacturing method of the second embodiment, the height of the solder bump formed on the via-on and via-off was uniform at 20 μm. And the test result was good as in the first example.

In the printed wiring boards manufactured in Comparative Examples 1 and 2, the height of via-off solder bumps was not uniform.
This caused unconnection at the time of IC connection. In Comparative Example 1,
Due to the small amount of solder paste filled in vias, the height of the solder bumps is low, and there are places where connection is not possible,
When the continuity test was performed, disconnection occurred. When a high-temperature and high-humidity reliability test was performed, the condition was significantly deteriorated. In Comparative Example 2, the solder paste overflowed from the solder resist layer after the reflow flow and the contamination was caused because the via-on was filled with too much solder, and a short circuit occurred at the solder bump. The situation was further degraded when a high-temperature and high-humidity reliability test was performed.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a multilayer printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.

8 is a cross-sectional view showing a state where an IC chip is mounted on the multilayer printed wiring board shown in FIG.

9A is a plan view of a mask for solder printing, FIG. 9B is a cross-sectional view taken along line BB of FIG. 9A, and FIG. 9C.
FIG. 9 is a cross-sectional view of a solder printing mask of a modified example.

FIGS. 10A and 10B are manufacturing process diagrams of a printed wiring board according to a modification of the first embodiment.

FIG. 11 is a sectional view of a multilayer printed wiring board according to a second embodiment of the present invention.

FIGS. 12A and 12B are explanatory views of a manufacturing process of a printed wiring board according to the second embodiment.

FIG. 13 is a table showing the results of tests on the multilayer printed wiring boards according to the first example and Comparative Examples 1 and 2.

FIG. 14 is a table showing the results of testing the multilayer printed wiring board according to the second example.

[Explanation of symbols]

 Reference Signs List 20 solder printing mask 22 through hole 30 core substrate 34 conductive circuit 36 through hole 50 interlayer resin insulation layer 58 conductive circuit 60 via hole 70 solder resist 71 opening 72 nickel plating layer 74 gold plating layer 75 solder paste 76U, 76D solder bump 150 interlayer resin insulation layer 158 conductive circuit 160 via hole

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 3/46 H01L 23/12 L

Claims (8)

[Claims] 1. A printed circuit board in which a part of a solder resist layer is opened to expose a via hole and a smoothly formed circuit, a solder bump is formed in the opened via hole and the circuit. A solder printing mask having a through hole for filling with a solder paste, wherein the opening area of the through hole is formed in a range of 1.0 to 2.0 times the area of the opening of the solder resist. A mask for solder printing, characterized in that: 2. An opening area of a through hole for printing on the opening of the via hole and an opening area of a through hole for printing on the flat formed circuit. 2. The solder printing mask according to 1. 3. The solder printing mask according to claim 1, wherein a thickness of the solder resist of the printed wiring board is in a range of 5 to 70 μm. 4. The solder printing mask according to claim 1, wherein the thickness is 20 to 70 μm. 5. A method for manufacturing a printed wiring board, comprising using the mask for solder printing according to claim 1. Description: 6. A method for manufacturing a printed wiring board, comprising: at least the following steps (A) to (D): (A) a method for manufacturing a printed circuit board on which a via hole and a smoothly formed circuit are formed; Forming a solder resist layer so as to open a part of the via hole and a part of the circuit; and (B) a solder printing mask having a through hole, wherein printing is performed on the opening of the via hole. Filling a solder paste into the opening using a solder printing mask having the same size as the opening area of the through hole for printing and the opening area of the through hole for printing on the circuit, and (C) performing reflow. By that
Forming a solder bump; and (D) flattening the top of the solder bump by performing heating, pressing, or heating and pressing. 7. A printed wiring board in which a solder bump is formed on a via hole and a smoothly formed circuit through an opening in a solder resist layer, wherein a top portion of at least a part of the solder bump is flattened, and A printed wiring board, wherein a flat area at a top of a solder bump on a formed circuit is larger than a flat area at a top of a solder bump formed on a via hole. 8. The printed wiring board according to claim 7, wherein the solder bump covers a peripheral portion of an opening of the solder resist layer.