JP2001217543A - Multilayer circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer circuit board advantageous for increasing the wiring density and mounting electronic components including semiconductor chips such as LSIs at higher densities. SOLUTION: This multilayer circuit board has layer resin insulation layers and conductor layers alternately laminated on both surfaces of a multilayer core board having conductor circuits in inner layers and buildup wiring layers having conductor layers interconnected through vias. The multilayer core board is formed by laminating through adhesive layers and heating and pressing en bloc a plurality of circuit boards each having conductor circuits on one or both surfaces of an insulative hard base and vias composed of a conductive substance filled in holes piercing the insulative hard base to reach the conductor circuits, solder bumps are provided on the surface of the outermost conductor layer constituting one buildup wiring layer, and conductive pins or conductive balls are disposed on the surface of the outermost conductor layer constituting the other buildup wiring layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer circuit board having a multi-layered core substrate, and more particularly to a multi-layered core substrate in which a plurality of single-sided or double-sided circuit boards having filled via holes are laminated and bonded. The electrical connection between the conductor circuit in the multilayer core substrate and the build-up wiring layer formed on the multilayer core substrate is performed by batch heating and pressing via an agent. It can be secured via via holes in the build-up wiring layer formed directly above, and is directly connected to the outermost conductor circuits of the build-up wiring layer to electronic components including semiconductor chips such as LSI and motherboards. A multi-layer circuit board having conductive bumps, conductive pins, or conductive balls that can be used and that is advantageous for ultrahigh-density wiring is proposed.

[0002]

2. Description of the Related Art In recent years, package substrates on which electronic components including semiconductor chips such as LSIs are mounted have been adapted to miniaturization or high-speed of electronic devices accompanying the progress of the electronics industry. Is required. As such a package substrate, 19
“Surface mounting technology” in January 1997 discloses a multilayer core substrate in which build-up multilayer wiring layers are formed on both surfaces.

However, in the above-described conventional package substrate, the connection between the conductor layer in the multilayer core substrate and the build-up wiring layer is performed by providing inner layer pads wired from through holes on the surface of the multilayer core substrate. A via hole is connected to the inner layer pad. For this reason, the land shape of the through-hole becomes a Dharma shape or an iron array shape, and the area of the inner layer pad hinders an improvement in the arrangement density of the through-holes, and there is a certain limit to the number of through-holes formed. Therefore, when the core substrate is multilayered in order to increase the wiring density, there is a problem that the outer build-up wiring layer cannot secure sufficient electrical connection with the conductor layers in the multilayer core substrate. Was.

[0004] Regarding such a problem, the present inventors have previously described Japanese Patent Application No. 10-15346 (Japanese Patent Application Laid-Open No.
No. 1-214846), and proposed an improvement method.
The multilayer circuit board according to such an improvement proposal is a build-up wiring in which an interlayer resin insulating layer and a conductor layer are alternately laminated on a multilayer core substrate having a conductor layer in an inner layer, and each conductor layer is connected by a via hole. In the multilayer circuit board having the layers formed therein, a through hole is formed in the multilayer core substrate, the through hole is filled with a filler, and the conductor layer covers the exposed surface of the filler from the through hole. Is formed, and via holes are connected to the conductor layer, thereby increasing the arrangement density of the through holes, and connecting with the conductor circuit in the multilayered core substrate through the densified through holes. Can be secured.

[0005]

However, a through hole in a multilayer circuit board having such a structure is formed by drilling a through hole in a multilayered core board with a drill or the like, and electroless plating is applied to the wall surface of the through hole and the board surface. In consideration of the opening properties and economical efficiency, the lower limit of the through hole opening diameter that can be formed is about 300 μm, realizing ultra-high-density wiring that satisfies the current requirements of the electronics industry. In order to achieve this, it is desired to develop a technology for obtaining a smaller opening diameter of about 50 to 250 μm and a narrower through-hole land pitch.

Accordingly, the present inventors have developed a circuit board having a conductor circuit on one or both sides of a core material made of a hard material, and forming a filled via hole that penetrates the core material from one surface to reach the conductor circuit. If a multilayer core substrate is formed by laminating a plurality of sheets to each other and hot-pressing collectively via an adhesive, without providing through holes in the multilayer core substrate, conductor circuits in the multilayer core substrate, and The electrical connection between the conductor circuit in the multilayer core substrate and the build-up wiring layer formed on the multilayer core substrate is based on the filling via hole formed on the multilayer core substrate and the via hole in the build-up wiring layer formed immediately above the filled via hole. And that a part of the outermost conductor circuit of one of the build-up wiring layers is formed on the solder pad, and the solder pad is formed. A conductive bump for connecting an electronic component including a semiconductor chip such as an LSI, and a part of the outermost conductive circuit of the other build-up wiring layer is formed on a solder pad. It has been found that by providing conductive pins or conductive balls that can be directly connected to the motherboard with respect to the solder pads, high-density wiring and high-density mounting of electronic components can be realized. An object of the present invention is to provide a multilayer circuit board that is advantageous for such high-density wiring and high-density mounting of electronic components.

[0007]

Means for Solving the Problems The inventors of the present invention have intensively studied for realizing the above-mentioned object, and as a result, have arrived at an invention having the following content as a gist configuration. That is, (1) the multilayer circuit board of the present invention is a build-up in which interlayer resin insulation layers and conductor layers are alternately laminated on a multilayer core board having a conductor circuit in an inner layer, and each conductor layer is connected by a via hole. In the multilayer circuit board in which the up wiring layer is formed, the multilayer core substrate has a conductor circuit on one or both surfaces of an insulating hard base material, and reaches the conductor circuit through the insulating hard base material. A plurality of circuit boards each having a via hole filled with a conductive substance in the hole are formed by laminating via an adhesive layer, and hot pressing all together.

(2) In the multilayer circuit board of the present invention, an interlayer resin insulation layer and a conductor layer are alternately laminated on both sides of a multilayer core board having a conductor circuit in an inner layer, and a via hole is provided between each conductor layer. In the multilayer circuit board formed with the build-up wiring layer connected by the above, the multilayer core board has a conductor circuit on one or both sides of the insulating hard base material, penetrates the insulating hard base material In the hole reaching the conductor circuit, a plurality of circuit boards having via holes filled with a conductive substance are laminated via an adhesive layer, and formed by being heated and pressed collectively, A solder bump is provided on the surface of the outermost conductor layer forming one of the build-up wiring layers, and a conductive pin is formed on the surface of the outermost conductor layer forming the other of the build-up wiring layer. Or conductive ball is characterized in that it is arranged.

The conductive substance filled in the via hole of each circuit board constituting the multilayer core board of the above (1) or (2) may be formed of metal plating or conductive paste formed by electrolytic plating. Desirably, electrolytic copper plating is more preferable as metal plating, and conductive paste containing metal particles and a thermosetting or thermoplastic resin is more preferable.

In the above-mentioned multilayer circuit board, it is preferable that each circuit board constituting the above-mentioned multilayer core board has a projecting conductor electrically connected to the via hole corresponding to the position of the via hole. Preferably, the protruding conductor is formed from a conductive paste.
Part of the via hole of the build-up wiring layer is located immediately above the via hole formed in the multilayer core substrate,
It is desirable to be directly connected to the via hole.

In the above multilayer circuit board, the insulating base of each circuit board constituting the multilayer core board is a glass cloth epoxy resin base, a glass cloth bismaleimide triazine resin base, a glass cloth polyphenylene ether resin base, an aramid It is desirable to be formed from any hard base material selected from nonwoven fabric-epoxy resin base material and aramid nonwoven fabric-polyimide resin base material.

The insulating substrate of each circuit board constituting the multilayer core substrate is formed of a glass cloth epoxy resin substrate having a thickness of 20 to 600 μm, and the filled via hole diameter is 50 to 250 μm. Is desirable.

Further, the filled via hole has a pulse energy of 0.5 to 100 mJ and a pulse width of 1 to 100 mJ.
μs, pulse interval 0.5 ms or more, shot number 3 ~
It is preferable that the opening is formed for the carbon dioxide laser opening under the condition of 50.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION A multilayer circuit board according to the present invention comprises a multilayer core board having a build-up wiring layer formed on a multilayer core board. A plurality of circuit boards each having a circuit and being filled with a conductive substance such as electrolytic plating or a conductive paste in a through hole penetrating the insulating hard base material and reaching the conductor circuit via an adhesive layer. It is characterized in that it is formed by laminating each other and hot pressing all together.

According to such a configuration, it is not necessary to provide a through hole in the core substrate, so that the degree of freedom in arranging pads such as lands is improved. As a result, filled via holes can be provided at a high density, and via the densified via holes, the outer build-up wiring layer can ensure a sufficient connection with the conductor circuit in the multilayer core substrate. And high density wiring becomes possible. Also,
Even in the multilayer core substrate, the density of the wiring can be further increased.

Further, the multilayer circuit board according to the present invention is a multilayer circuit board formed by laminating a plurality of circuit boards having conductor circuits on one or both sides of a hard insulating base material via an adhesive and collectively forming them by hot pressing. Solder bumps are provided on the surface of the outermost conductor layer that constitutes one of the build-up wiring layers formed on the front and back surfaces of the core substrate, and the outermost conductor that constitutes the other of the build-up wiring layers is provided. A conductive pin or conductive ball is provided on the surface of the conductive layer.

According to this structure, via holes are provided in the build-up wiring layer at a high density, and the via holes formed in the outermost interlayer resin insulating layer are exposed from the via holes having the high density. The conductive bumps, the conductive pins or the conductive balls are disposed on the conductive pads, and the build-up wiring layer in the multilayer circuit board includes the conductive bumps, the conductive pins or the conductive balls. Through this, it is connected to an electronic component including a semiconductor chip such as an LSI or a mother board with the shortest wiring length, and high-density wiring and high-density mounting of the electronic component become possible.

In the present invention, each of the circuit boards constituting the multilayer core board is not formed of a semi-cured prepreg as in the prior art, but is formed of an insulating resin base material formed of a completely cured hard resin material. Is desirable.

Such insulating base materials include glass cloth epoxy resin base material, glass cloth bismaleimide triazine resin base material, glass cloth polyphenylene ether resin base material,
Aramid non-woven fabric-epoxy resin substrate, aramid non-woven fabric-
A rigid (hard) laminated substrate selected from polyimide resin substrates is used, and a glass cloth epoxy resin substrate is most desirable.

In the case where a conductor circuit is formed on the insulating base material, in the step of pressing a copper foil on the insulating base material by hot pressing, the final thickness variation of the insulating base material due to the pressing pressure Therefore, the positional deviation of the via hole can be suppressed to the minimum, the via land diameter can be reduced, and as a result, the wiring pitch can be reduced and the wiring density can be improved.

Further, since the cured resin base material is used as the insulating base material, the thickness of the base material can be kept substantially constant, and the setting of the laser processing conditions when forming the opening for forming a via hole can be achieved. Becomes easier.

The thickness of the insulating substrate is 20 to 600 μm.
m is desirable. The reason is to ensure insulation. If the thickness is less than 20 μm, the strength is reduced and handling becomes difficult, and the reliability with respect to electrical insulation is reduced. If the thickness is more than 600 μm, a fine via hole forming opening becomes difficult, and the substrate itself becomes thick. It is because it becomes.

The opening for forming a via hole formed on a glass epoxy substrate having a thickness in the above range has a pulse energy of 0.5 to 100 mJ and a pulse width of 1 to 1 m.
00μs, pulse interval 0.5ms or more, shot number 3
It is preferably formed by a carbon dioxide laser irradiated under the conditions of 50 to 50, and the opening diameter is 50 to 250 μm.
m is desirable. The reason is 50 μm
If it is less than 250 μm, it is difficult to fill the opening with a conductive substance, and the connection reliability is low. If it exceeds 250 μm, it is difficult to increase the density.

Before the opening is formed by the carbon dioxide gas laser, a resin film is adhered to the surface of the insulating substrate opposite to the surface on which the conductive circuit is formed, or if necessary, a resin adhesive layer in a semi-cured state. Stick the resin film through
It is desirable to perform laser irradiation from above the resin film. In the former method, a non-through hole is formed by irradiating a laser from the opposite side to the copper foil on an insulating base material on which copper foil is pasted on one side in advance, and the copper foil is used as a plating lead in the non-through hole. When a single-sided circuit board is manufactured by etching after filling the plating layer, or a single-sided copper-clad laminate is etched to form a non-through hole by laser irradiation on an insulative base material with a conductor circuit formed in advance. It is adopted when a single-sided circuit board is manufactured by filling an electrolytic plating layer with a copper foil as a plating lead in the non-through hole, and the latter is provided with a through hole in advance by laser irradiation on an insulating base material. This method is used when a double-sided circuit board is manufactured by filling a through hole with a conductive paste, attaching copper foil to both surfaces of an insulating base material, and performing an etching process. This resin adhesive is for bonding a copper foil to the surface of an insulating substrate, and is formed of, for example, a bisphenol A type epoxy resin and has a thickness of 10 to 50.
The range of μm is preferred.

The resin film adhered on the insulating base material or on the resin adhesive layer formed on the insulating base material forms a via hole by filling an electrolytic plating in a via hole forming opening. As a protective film when doing
Alternatively, a conductive paste is filled in the opening to form a via hole and a projecting conductor, or a conductive paste is filled on the electrolytic plating layer to form a projecting conductor (bump) immediately above the electrolytic plating layer. It has a pressure-sensitive adhesive layer that functions as a printing mask when performing the process, and that is separated from the insulating base material or the adhesive layer after filling with the conductive substance. This resin film has, for example, a pressure-sensitive adhesive layer having a thickness of 1 to 20 μm.
m and the thickness of the film itself is preferably from 10 to 50 μm.

The reason is that the height of a projecting conductor described later is determined depending on the thickness of the PET film.
If the thickness is less than this, the protruding conductor is too low, and connection failure tends to occur. Conversely, if the thickness exceeds 50 μm, the protruding conductor spreads too much at the connection interface, so that a fine pattern cannot be formed.

As the conductive substance to be filled in the opening formed in the insulating substrate, metal plating or conductive paste formed by electrolytic plating is preferable. The conductive paste is preferable in that the process is simplified, the production cost is reduced, and the yield is improved.
Metal plating is more preferable from the viewpoint of connection reliability. As the conductive paste, a conductive paste composed of at least one or more metal particles selected from silver, copper, gold, nickel and solder can be used.

As the above-mentioned metal particles, those obtained by coating the surface of metal particles with a dissimilar metal can also be used. Specifically, metal particles in which the surface of copper particles is coated with a noble metal selected from gold and silver can be used. As such a conductive paste, an organic conductive paste obtained by adding a thermosetting resin such as an epoxy resin or a phenol resin to a metal particle and a thermoplastic resin such as polyphenylene sulfide (PPS) is desirable.

The conductor circuit formed on one or both sides of the insulating base material is formed by hot pressing a copper foil having a thickness of 5 to 18 μm through a resin adhesive layer held in a semi-cured state, It is preferably formed by performing an etching process. Such hot pressing is performed under appropriate temperature and pressure. More preferably, it is performed under reduced pressure, and by curing only the resin adhesive layer in a semi-cured state, the copper foil can be firmly adhered to the insulating base material. The manufacturing time is shortened as compared with the case of FIG.

A circuit board in which such a conductive circuit is formed on both sides of an insulating substrate is suitable as a core of a multilayer core board. It is preferable that the via land (pad) as a part is formed in a range of 50 to 250 μm in diameter.

A circuit board in which a conductive circuit is formed on one side of an insulating base material can be formed not only as a multilayer board by laminating a plurality of these boards sequentially, but also as a core using a double-sided circuit board as a core. It is suitable as a circuit board for lamination to be laminated on both sides thereof, and it is preferable that a projecting conductor is formed just above the position of the conductive material filled in the via hole.

The projecting conductor is preferably formed of a conductive paste or a low-melting metal. In the step of laminating the circuit boards and hot-pressing them collectively, the conductive paste or the low-melting metal is heated. Due to the deformation, the variation in height of the conductive material filled in the via hole can be absorbed, and therefore, a connection failure can be prevented and a multilayer core substrate excellent in connection reliability can be obtained. Further, such a protruding conductor can be formed of the same material as the conductive paste filled in the via hole, and can be formed by the same filling step.

Further, when the build-up wiring layer formed on the multilayer core substrate is formed by applying and curing a resin as described later, the surface of the conductor circuit provided on the surface of the multilayer core substrate is roughened. Advantageously, a layer is formed. The reason is that it is possible to improve the adhesion to the interlayer resin insulating layer and the via hole in the build-up wiring layer laminated on the multilayer core substrate. In particular, when a roughened layer is formed on the side surface of the conductor circuit, cracks generated toward the interlayer resin insulation layer from these interfaces due to insufficient adhesion between the side surface of the conductor circuit and the interlayer resin insulation layer are suppressed. be able to.

On the other hand, when the build-up wiring layer is formed by laminating a resin film and curing by heating and pressing as described later, the formation of a roughened layer is not always necessary.

The thickness of the roughened layer formed on the surface of such a conductor circuit is preferably 0.1 to 10 μm. The reason for this is that if it is too thick, it causes interlayer short-circuit, and if it is too thin, the adhesion to the adherend decreases. The roughened layer may be formed by treating with a mixed aqueous solution of an organic acid and a cupric complex, or may be formed by plating a copper-nickel-phosphorus needle-like alloy.

Among these roughening treatments, the treatment using a mixed aqueous solution of an organic acid and a cupric complex works as follows under the coexistence condition of oxygen such as spraying and bubbling, and the conductor circuit such as copper is used. Dissolve the metal foil. _{Cu + Cu (II) A n} → 2Cu (I) A n / 2 2Cu (I) A n / 2 + n / 4O 2 + nAH ( _{aeration) → 2Cu (II) A n} + n / 2H 2 O A complexing agent (chelate N) is the coordination number.

The cupric complex used in this treatment is preferably an azole cupric complex. The cupric complex of azoles acts as an oxidizing agent for oxidizing metallic copper and the like. As the azoles, diazole, triazole,
Tetrazole is preferred. Among them, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole and the like are preferable. The content of the cupric complex of azoles is preferably 1 to 15% by weight. This is because, when it is in this range, solubility and stability are excellent.

The organic acid is added to dissolve copper oxide. Specific examples include formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, apple At least one selected from acids and sulfamic acids is preferred. The content of this organic acid is 0.1 to
30% by weight is good. This is for maintaining the solubility of the oxidized copper and ensuring the solubility stability. The generated cuprous complex dissolves under the action of an acid and combines with oxygen to form a cupric complex, which again contributes to copper oxidation. Further, in addition to the organic acid, an inorganic acid such as borofluoric acid, hydrochloric acid, and sulfuric acid may be added.

To the etching solution comprising the organic acid-cupric complex, a halogen ion, for example, a fluorine ion, a chlorine ion, a bromine ion or the like is added to assist in dissolving copper and oxidizing azoles. Is also good. The halogen ions can be supplied by adding hydrochloric acid, sodium chloride, or the like. The amount of halogen ions is preferably 0.01 to 20% by weight. This is because if it is within this range, the formed roughened layer has excellent adhesion to the interlayer resin insulating layer. The etching solution composed of the organic acid-cupric complex contains a copper complex of azoles and an organic acid (halogen ion as required),
Prepare by dissolving in water.

In the plating of a needle-shaped alloy comprising copper-nickel-phosphorus, copper sulfate 1-40 g / l, nickel sulfate 0.1-6.0 g / l, citric acid 10-20 g / l,
Hypophosphite 10 to 100 g / l, boric acid 10 to 40
It is desirable to use a plating bath having a liquid composition of g / l and a surfactant of 001 to 10 g / l.

In the present invention, the multi-layer core substrate is formed by laminating a plurality of the single-sided circuit boards and heating and pressing them all at once. As the interlayer resin insulating layer constituting the up wiring layer, a thermosetting resin, a thermoplastic resin, or a composite of a thermosetting resin and a thermoplastic resin can be used.

As the thermosetting resin, epoxy resin, polyimide resin, phenol resin, thermosetting polyphenylene ether (PPE) and the like can be used. Examples of the thermoplastic resin include a phenoxy resin, a fluororesin such as polytetrafluoroethylene (PTFE), polyethylene terephthalate (PET), polysulfone (PSF), polyphenylene sulfide (PPS), thermoplastic polyphenylene ether (PPE), and polyether. Sulfone (PE
S), polyetherimide (PEI), polyphenylene sulfone (PPES), tetrafluoroethylene hexafluoropropylene copolymer (FEP), tetrafluoroethylene perfluoroalkoxy copolymer (PFA), polyethylene naphthalate (PEN) ), Polyetheretherketone (P
EEK), polyolefin-based resins and the like can be used. As a composite of a thermosetting resin and a thermoplastic resin, epoxy resin-PES, epoxy resin-PSF, epoxy resin-
PPS, epoxy resin-PPES, epoxy resin-phenoxy resin, phenol resin-phenoxy resin and the like can be used.

In the present invention, the interlayer resin insulating layer constituting the build-up wiring layer is formed by laminating a desired number of resin films such as a polyolefin resin, heating and pressing, and then thermosetting to integrate. be able to.
The thickness of the polyolefin-based resin layer is desirably in the range of 5 to 200 μm. The reason is that if it is less than 5 μm, it is difficult to secure interlayer insulation, and if it exceeds 200 μm, it becomes difficult to form an opening by laser processing.

In the present invention, an adhesive for electroless plating can be used as the interlayer resin insulating layer constituting the build-up wiring layer. As the adhesive for electroless plating, heat-resistant resin particles that are soluble in a cured acid or oxidizing agent are dispersed in an uncured heat-resistant resin that becomes hardly soluble in an acid or an oxidizing agent by the curing treatment. Is best. The reason for this is that by treating with an acid or an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus pot-shaped anchor can be formed on the surface. The depth of the roughened surface is preferably 0.1 to 20 μm. This is to ensure adhesion. In the semi-additive process, the thickness is preferably 0.1 to 5 μm. This is because the electroless plating film can be removed while ensuring adhesion.

In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles particularly subjected to the curing treatment include a heat-resistant resin powder having an average particle diameter of 10 μm or less, and an average particle diameter of 2 μm.
agglomerated particles obtained by aggregating a heat-resistant resin powder having a particle diameter of 2 m or less, and a heat-resistant resin powder having an average particle diameter of 2 to 10 μm and an average particle diameter of 2 μm
m and a mixture with a heat-resistant resin powder having a mean particle size of 2 or less.
Pseudo particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 μm or less to the surface of a 10 μm heat-resistant resin powder, and an average particle diameter of 0.1 μm.
~ 0.8μm heat resistant resin powder and average particle size 0.8μ
It is desirable to use at least one selected from a mixture with a heat-resistant resin powder having a particle size exceeding m and less than 2 μm and a heat-resistant resin powder having an average particle diameter of 0.1 to 10 μm. Further, metal particles or inorganic particles may be used in place of the above resin particles, and a plurality of types thereof may be appropriately mixed and used. This is because a more complicated anchor can be formed. As the heat-resistant resin used in the adhesive for electroless plating, the aforementioned thermosetting resin, thermoplastic resin, or a composite of the thermosetting resin and the thermoplastic resin can be used.

In the present invention, the electrical connection between the conductor circuit formed on the multilayer core substrate and the conductor circuit in the build-up wiring layer can be made by a via hole formed in the interlayer resin insulation layer. In this case, the via hole may be filled with a plating film or a filler.

Hereinafter, an example of manufacturing a multilayer circuit board according to the present invention will be specifically described with reference to the accompanying drawings.
In the method described below, the build-up wiring layer is formed on the multilayer core substrate by a semi-additive method, but a full-additive method, a multi-lamination method, or a pin lamination method can also be adopted.

(A) Formation of Multilayer Core Board (1) In manufacturing a multilayer circuit board according to the present invention, a circuit board constituting a multilayer core board as a base includes:
A material in which a copper foil 12 is adhered to one surface of an insulating substrate 10 is used as a starting material. The insulating base material 10 is, for example, a glass cloth epoxy resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, an aramid nonwoven fabric-epoxy resin base material, an aramid nonwoven fabric-polyimide resin base material. A rigid laminated substrate of choice may be used, but glass cloth epoxy resin substrates are most preferred.

The thickness of the insulating substrate 10 is 20 to 60.
0 μm is desirable. The reason for this is that if the thickness is less than 20 μm, the strength is reduced and handling becomes difficult, and the reliability with respect to electrical insulation is reduced. If the thickness exceeds 600 μm, fine via holes are formed and the conductive paste is filled. And the thickness of the substrate itself is increased.

The thickness of the copper foil 12 is preferably 5 to 18 μm. The reason for this is that the opening (non-through hole) for forming a via hole is formed in the insulating base material by using laser processing as described below.
This is because, when forming, a conductor circuit pattern having a fine line width is difficult to be formed by etching if the thickness is too small.

As the insulating base material 10 and the copper foil 12, in particular, epoxy resin is impregnated in
It is preferable to use a single-sided copper-clad laminate obtained by laminating a prepreg as a stage and a copper foil and pressing the laminate under heat. The reason is that the positions of the wiring patterns and the via holes do not shift during handling after the copper foil 12 is etched as described later, and the positional accuracy is excellent.

(2) First, when manufacturing a circuit board having conductor circuits formed on both surfaces, such an insulating substrate 10
A protective film 14 is attached to the surface opposite to the surface to which the copper foil 12 is attached (see FIG. 1A).

The protective film 14 is used as a mask for printing a conductive paste for forming a projecting conductor described later. For example, a polyethylene terephthalate (PET) film having an adhesive layer on the surface can be used. The PET film 14 has a pressure-sensitive adhesive layer having a thickness of 1 to 20 μm.
m, a film having a thickness of 10 to 50 μm is used.

(3) Then, a carbon dioxide laser is irradiated from above the PET film 14 attached to the insulating base material 10 to penetrate the PET film 14 and
An opening 16 reaching the copper foil 12 from the surface of FIG.
(b)). This laser processing is performed by a pulse oscillation type carbon dioxide laser processing apparatus, and the processing conditions are as follows: pulse energy is 0.5 to 100 mJ, and pulse width is 1 to 1.
It is desirable that the pulse width is 100 μs, the pulse interval is 0.5 ms or more, and the number of shots is in the range of 3 to 50. The via diameter that can be formed under such processing conditions is 50 to 25.
Desirably, it is 0 μm.

(4) In order to remove resin residues remaining on the side and bottom surfaces of the opening 16 formed in the step (3),
Perform desmear processing. This desmear treatment is performed by oxygen plasma discharge treatment, corona discharge treatment, ultraviolet laser treatment, excimer laser treatment, or the like. In particular, desmearing by irradiating the opening with an ultraviolet laser or an excimer laser is desirable from the viewpoint of ensuring connection reliability.

When the desmear treatment is performed by, for example, ultraviolet laser irradiation using the third harmonic of YAG, the laser irradiation conditions are: a transmission frequency of 3 to 15 KHz, a pulse energy of 0.1 to 5 mJ, and a shot number of 10 ~ 3
A range of 0 is desirable.

(5) Next, for the desmeared substrate
The copper foil 12 is used as a plating lead under the following conditions.
Applying electrolytic copper plating, electrolytic copper plating in the opening 16
18 to form a filled via hole 20 (FIG. 1).
(C)). By this plating process, the upper part of the opening 16 is formed.
Is filled with a conductive paste 22 as described below.
Is filled with electrolytic copper plating 18 leaving a slight gap
You. [Aqueous electrolytic copper plating solution] Copper sulfate pentahydrate: 65 g / l Leveling agent (manufactured by Atotech, HL): 20 ml / l Sulfuric acid: 220 g / l Brightener (manufactured by Atotech, UV): 0.5 ml / l chloride ion : 40 ppm [Electroplating conditions] Bubbling: 3.0 L / min Current density: 0.5 A / dm²  Set current value: 0.18 A Plating time: 130 minutes

(6) After filling the conductive paste 22 with the protective film 14 as a printing mask, fill a slight gap or dent above the opening 18 where the electrolytic copper plating 20 was not filled in the above (5). Then, a conductor portion 24 (hereinafter, referred to as a “projecting conductor”) protruding from the surface of the insulating substrate 10 by an amount corresponding to the thickness of the protective film 14 is formed (see FIG. 1D).

(7) Next, after the protective film 14 is peeled off, an adhesive layer 26 is formed on the surface of the insulating substrate 10 including the protruding conductor 24 (see FIG. 1E). The adhesive 26 is in a semi-cured state, that is, a B-stage adhesive, for bonding a copper foil on which a conductive circuit pattern is to be formed. For example, an epoxy resin varnish is used. It is preferably in the range of 50 μm.

(8) A copper foil 28 is pressed on the surface of the insulating base material 10 provided with the adhesive layer 26 in the step (7) by a hot press to cure the adhesive layer 26 (FIG. 1). (f)). At this time, the copper foil 28 is bonded to the insulating base material 10 via the cured adhesive layer 26, and the projecting conductor 24 and the copper foil 2
8 are electrically connected. The thickness of the copper foil 28 is 5
１８18 μm is desirable.

(9) Next, an etching protection film is stuck on each of the copper foils 12 and 28 stuck on both sides of the insulating base material 10, and after being covered with a mask having a predetermined circuit pattern, the etching process is performed. Go to the conductor circuit 30
And 32 (including via lands) (FIG. 1 (g)
reference).

In this processing step, first, the copper foil 12
And after applying a photosensitive dry film resist on the surface of 28 and exposing and developing along a predetermined circuit pattern to form an etching resist, etching the metal layer of the etching resist non-formed portion, including via lands The conductor circuit patterns 30 and 32 are formed. As the etchant, at least one selected from aqueous solutions of sulfuric acid and hydrogen peroxide, persulfate, cupric chloride, and ferric chloride.
An aqueous solution of the seed is desirable.

As a pretreatment for forming the conductor circuits 30 and 32 by etching the copper foils 12 and 28, in order to easily form a fine pattern, the entire surface of the copper foil is previously etched to a thickness of 1 to The thickness can be reduced to 10 μm, more preferably to about 2 to 8 μm. The via land as a part of the conductor circuit has an inner diameter substantially similar to the via hole diameter, but has an outer diameter of 50.
It is preferable that the film is formed in a range of about 250 μm.

(10) Next, the surfaces of the conductor circuits 30 and 32 formed in the step (8) are subjected to a roughening treatment as necessary (the indication of the roughened layer is omitted), and the double-sided circuit board is omitted. 34 are formed. This roughening treatment is for improving adhesion to the adhesive layer and preventing peeling (delamination) when forming a multilayer. Roughening methods include, for example, soft etching, blackening (oxidation) and one-reduction treatment, formation of a copper-nickel-phosphorus needle-like alloy plating (manufactured by Ebara Uzilite; trade name: Interplate), manufactured by MEC Corporation. Surface roughening by an etching solution called "Mech etch bond".

In this embodiment, the roughened layer is preferably formed by using an etching solution.
For example, it can be formed by etching the surface of a conductor circuit from a mixed aqueous solution of a cupric complex and an organic acid using an etchant. Such an etchant can dissolve the copper conductor circuit pattern under oxygen-existing conditions such as spraying and bubbling, and the reaction is presumed to proceed as follows. Cu + Cu (II) A _n → 2Cu (I) _{An / 2} 2Cu (I) _{An / 2} + n / 4O ₂ + nAH (aeration) → 2Cu (II) A _n + n / 2H ₂ O In the formula, A is a complex. Agent (acting as a chelating agent), n represents the coordination number.

As shown in the above formula, the generated cuprous complex dissolves under the action of an acid and combines with oxygen to form a cupric complex, which again contributes to copper oxidation. The cupric complex used in the present invention is preferably a cupric complex of azoles.
The etching solution comprising the organic acid-cupric complex can be prepared by dissolving a cupric complex of an azole and an organic acid (halogen ion as required) in water. Such an etchant is, for example, imidazole copper
(II) It is formed from an aqueous solution in which 10 parts by weight of a complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride are mixed. The double-sided circuit board constituting the multilayered board which is the base of the multilayer circuit board according to the present invention is manufactured according to the above-mentioned steps (1) to (10).

(11) Next, a single-sided circuit board to be laminated on the front and back surfaces of such a double-sided circuit board is manufactured. First, a process of manufacturing the double-sided circuit board 34
(1) to (6), a non-through hole is provided by laser irradiation from the surface opposite to the copper foil 12 attached to one surface of the insulating base material 10, and the non-through hole is formed in the non-through hole. After the via hole 20 is formed by filling the electrolytic copper plating layer 18, the conductive paste 22 is filled in a slight gap above the via hole to form the projecting conductor 44 (FIGS. 2A to 2).
(D)).

The insulating substrate 1 of such a projecting conductor 44
The protruding height from the surface 0 is almost equal to the thickness of the protective film 14, and is preferably in the range of 5 to 30 μm. The reason for this is that if it is less than 5 μm, poor connection is likely to occur, and 30 μm
If the ratio exceeds, the resistance value increases, and when the protruding conductor 44 is thermally deformed in the hot pressing step, it spreads too much along the surface of the insulating substrate, so that a fine pattern cannot be formed. Further, the protrusion-like conductor 44
Is preferably pre-cured. The reason is that the protruding conductor 44 is hard even in a semi-cured state, and is capable of making electrical contact with a conductor circuit (conductor pad) of another circuit board to be laminated before the adhesive layer is softened at the stage of lamination pressing. Because it becomes. Such a projecting conductor 44 is deformed at the time of hot pressing to increase the contact area, so that the conduction resistance can be reduced and the variation in the height of the projecting conductor 44 is corrected.

(12) Next, the protection film 14 opened by the laser irradiation is covered with the etching protection film 2.
After sticking No. 5, after covering with a mask of a predetermined circuit pattern, an etching process is performed to form a conductor circuit 40 (including a via land) (see FIG. 2E). In this processing step, first, a photosensitive dry film resist is attached to the surface of the copper foil 12, and then exposed and developed according to a predetermined circuit pattern to form an etching resist.
The metal layer in the portion where the etching resist is not formed is etched to form the conductor circuit pattern 40 including the via land.

As the etchant, at least one aqueous solution selected from aqueous solutions of sulfuric acid and hydrogen peroxide, persulfate, cupric chloride and ferric chloride is desirable. The above copper foil 1
As a pretreatment for forming the conductor circuit 40 by etching the copper foil 2, in order to easily form a fine pattern, the entire surface of the copper foil is etched in advance to reduce the thickness to 1 to 10 mm.
μm, more preferably about 2 to 8 μm.

(13) Conductor circuit 40 is provided on one side of insulating base material 10.
Is formed, the protective film 14 and the etching protective film 25 are peeled off to expose the protruding conductors 44, whereby the single-sided circuit board 50 can be obtained, and the protruding portions exposed from the surface of the insulating base material 10 can be obtained. An adhesive layer 46 is formed to cover the conductor 44 (see FIG. 2F). Such a resin adhesive can be applied not only to the entire surface of the insulating base material 10 including the protruding conductors 44 but also to a surface not including the protruding conductors 24, and the resin adhesive in a dried state can be used. It is formed as an adhesive layer 46 made of an uncured resin. The adhesive layer 46 is preferably precured for easy handling, and its thickness is preferably in the range of 5 to 50 μm.

The adhesive layer 46 is preferably made of an organic adhesive. Examples of the organic adhesive include an epoxy resin, a polyimide resin, a thermosetting polyphenolene ether (PPE), and an epoxy resin and a thermoplastic resin. Composite resin with epoxy resin and silicone resin, B
Desirably, the resin is at least one resin selected from T resins. As a method of applying the uncured resin which is an organic adhesive, a curtain coater, a spin coater, a roll coater, a spray coat, a screen printing, or the like can be used. Further, the formation of the adhesive layer can also be performed by laminating an adhesive sheet.

The single-sided circuit board 50 formed according to the above steps (11) to (13) has the conductor circuit 40 on one surface of the insulating base material 10 and the filled via hole 2 on the other surface.
0 has a protruding conductor 44 formed by exposing a part of the conductive paste, and further has an adhesive layer 46 on the surface of the insulating substrate 10 including the protruding conductor 44. The multi-layer substrate is formed by laminating and adhering a plurality of these to each other or by laminating to a double-sided circuit board 34 manufactured in advance, and the resin adhesive 46 is used in such a laminating step. Preferably.

(B) Multilayering of Laminating Circuit Boards As shown in FIG. 3, three single-sided circuit boards 50 and 52 are provided on both sides of the double-sided circuit board 34 manufactured according to the processing step (1). The four-layer substrate formed by laminating 54 has a heating temperature of 150 to 200 ° C. and a pressure of 1 M to 4 MPa
Under the conditions (1) and (2), the multi-layer substrate 60 is integrated by a single press molding (see FIG. 4). Under the above-described conditions, the adhesive layer 46 of each single-sided circuit board is cured by heating at the same time as pressurizing, and strong bonding is performed between adjacent single-sided circuit boards. It is preferable to use a vacuum heat press as the heating press. In the above-described embodiment, a single-layer double-sided circuit board and a three-layer single-sided circuit board are used to form a multilayer of four layers.
It can also be applied to multi-layering exceeding layers.

(C) Formation of Build-up Wiring Layer Build-up wiring layers are formed on both surfaces of the multilayer core substrate 60 formed by the steps (1) and (2). FIG.
In FIG. 5, all of the double-sided and single-sided circuit boards constituting the multilayer core board 60 are omitted for the purpose of simplification (see FIG. 5A).

(1) First, a roughened layer 6 made of copper-nickel-phosphorus is formed on the surface of the conductor circuit 52 on the surface of the multilayer core substrate 60.
2 is formed (see FIG. 5B). This roughened layer 62
It is formed by electroless plating. The liquid composition of the electroless plating aqueous solution has a copper ion concentration, a nickel ion concentration and a hypophosphite ion concentration of 2.2 × 10 ⁻² to 2.2 × 10 ⁻² , respectively.
4.1 × 10 ⁻² mol / l, 2.2 × 10 ⁻³ to
4.1 × 10 ⁻³ mol / l, 0.20 to 0.25 m
ol / l is desirable. This is because the crystalline structure of the film deposited in this range has a needle-like structure, and thus has an excellent anchor effect. A complexing agent or an additive may be added to the electroless plating aqueous solution in addition to the above compounds. As a method of forming the roughened layer, as described above, a roughened surface is formed by a treatment using copper-nickel-phosphorus needle-like alloy plating, an oxidation-reduction treatment, and a treatment for etching the copper surface along grain boundaries. There are methods.

(2) Next, an interlayer resin insulating layer 64 is formed on the multilayer core substrate 60 having the roughened layer prepared in the above (1) (FIG. 5C). In particular, in the present invention, it is desirable to use an adhesive for electroless plating using a composite of a thermosetting resin and a thermoplastic resin as a resin matrix as an interlayer resin insulating material for forming a via hole 70 described later.

(3) After the adhesive layer for electroless plating formed in the above (2) is dried, an opening 65 for forming a via hole is provided (FIG. 5D). In the case of a photosensitive resin, exposure and development are performed followed by thermosetting, and in the case of a thermosetting resin, thermosetting and then laser processing are performed to form an opening for forming a via hole in the adhesive layer 64. Part 65
Is provided.

(4) Next, the epoxy resin particles present on the surface of the cured adhesive layer 64 are removed by decomposition or dissolution with an acid or an oxidizing agent, and the surface of the adhesive layer is subjected to a roughening treatment so as to be roughened. The surface 66 is shown in FIG. 5 (e). Here, examples of the acid include phosphoric acid, hydrochloric acid, sulfuric acid, and organic acids such as formic acid and acetic acid, and it is particularly preferable to use an organic acid. This is because it is difficult to corrode the metal conductor layer exposed from the via hole when the roughening treatment is performed. On the other hand, it is desirable to use chromic acid and permanganate (such as potassium permanganate) as the oxidizing agent.

(5) Next, the roughened surface 66 of the surface of the adhesive layer 64
To a catalyst core. It is desirable to use a noble metal ion or a noble metal colloid for providing the catalyst nucleus, and generally, palladium chloride or a palladium colloid is used. Note that it is desirable to perform a heat treatment to fix the catalyst core. Palladium is preferred as such a catalyst core.

(6) Further, the surface of the adhesive layer 64 (for electroless plating) is subjected to electroless plating, and an electroless plating film 67 is formed so as to follow the entire roughened surface (FIG. 5).
(F)). At this time, the thickness of the electroless plating film 67 is
The range is preferably from 0.1 to 5 μm, more preferably
0.5 to 3 μm. Next, a plating resist 68 is formed on the electroless plating film 67 (FIG. 6A). As the plating resist composition, it is particularly desirable to use a composition comprising an acrylate of a cresol novolak type epoxy resin or an acrylate of a phenol novolak type epoxy resin and an imidazole curing agent. Alternatively, a commercially available dry film may be used.

(7) Further, a portion where the plating resist is not formed on the electroless plating film 67 is subjected to electrolytic plating to provide a conductor layer on which the upper conductor circuit 72 is to be formed, and to fill the inside of the opening 65 with the electrolytic plating film 69. Then, a via hole 70 is formed (FIG. 6B). At this time, the thickness of the electrolytic plating film 9 exposed outside the opening 5 is preferably 5 to 30 μm. Here, it is desirable to use copper plating as the electrolytic plating.

(8) Further, after removing the plating resist 68, a mixed solution of sulfuric acid and hydrogen peroxide, sodium persulfate,
The electroless plating film under the plating resist is dissolved and removed with an etching solution such as ammonium persulfate to form an independent upper conductor circuit 72 and a filled via hole 70.

(9) Next, the surface of the upper conductor circuit 72 is roughened.
A layer 74 is formed. As a method for forming the roughened layer 74,
Etching, polishing, oxidation-reduction and plating
is there. Of these treatments, the oxidation-reduction treatment is NaOH
(20 g / l), NaClO _Two(50 g / l), NaP
O₄(15.0 g / l) as an oxidation bath (blackening bath)
OH (2.7 g / l), NaBH₄(1.0 g / l)
Use as a reducing bath. In addition, the copper-nickel-phosphorus alloy layer
Roughened layer is formed by deposition by electroless plating.
It is.

The electroless plating solution for this alloy was prepared as follows: copper sulfate 1 to 40 g / l, nickel sulfate 0.1 to 6.0 g / l
l, citric acid 10-20 g / l, hypophosphite 10-1
00g / l, boric acid 10-40g / l, surfactant 0.
It is desirable to use a plating bath having a liquid composition of from 01 to 10 g / l. Further, the surface of the roughened layer 74 is covered with a layer of a metal or a noble metal whose ionization tendency is greater than copper and equal to or less than titanium. In the case of tin, tin borofluoride-thiourea or tin chloride-thiourea liquid is used. At this time, an Sn layer having a thickness of about 0.1 to 2 μm is formed by the substitution reaction of Cu—Sn. In the case of a noble metal, a method such as sputtering or vapor deposition can be adopted.

(10) Next, an adhesive layer 76 for electroless plating is formed on the substrate as an interlayer resin insulating layer. (11) Further, by repeating the above steps (3) to (9), another via hole 80 is provided directly above the via hole 70 and the upper conductor circuit 8 is further disposed outside the upper conductor circuit 72.
2 and a roughened layer 84 are provided (see FIG. 6C). The surface of the via hole 80 is formed as a conductor pad functioning as a solder pad.

(12) Next, a solder resist composition 90 is applied to the outer surface of the wiring substrate thus obtained, and the coating film is dried. Then, a photomask film having an opening drawn thereon is applied to the coating film. An opening 91 exposing a solder pad (including a conductor pad and a via hole) in the conductor layer is formed by mounting, exposing, and developing (see FIG. 7A). Here, the diameter of the exposed opening is
The diameter may be larger than the diameter of the solder pad, and the solder pad may be completely exposed. Conversely, the opening diameter of the opening can be smaller than the diameter of the solder pad, and the periphery of the solder pad can be covered with the solder resist layer 90. In this case, the solder pads can be suppressed by the solder resist layer 90, and peeling of the solder pads can be prevented.

(13) Further, the solder resist layer 9
A metal layer made of “nickel-gold” is formed on the solder pad exposed from the opening 91 of the “0”. The thickness of the nickel layer 92 is preferably 1 to 7 μm, and the thickness of the gold layer is 0.01 to 0.1 μm.
06 μm is preferred. The reason for this is that if the nickel layer 92 is too thick, it causes an increase in the resistance value, and if it is too thin, it is easy to peel off. On the other hand, if the gold layer 94 is too thick, the cost increases, and if it is too thin, the effect of adhering to the solder body is reduced.

(14) Further, the solder exposed from the opening 91 (opening located above) in one of the solder resist layers located on the outermost side of the build-up wiring layer formed on both sides of the multilayer core substrate. Gold layer 94 of pad part
On the upper side, a solder body is supplied to form a solder bump 96 and is exposed from an opening 91 (an opening located below) formed in the other of the solder resist layer located on the outermost side of the build-up wiring layer. A multi-layer circuit board is manufactured by supplying a solder body also on the gold layer 94 of the solder pad portion to form the T pin 96 or the solder ball 100 (see FIG. 7B).

As a method for supplying the solder body, a solder transfer method or a printing method can be used. Here, in the solder transfer method, a solder foil is bonded to a prepreg, and the solder foil is etched leaving only a portion corresponding to an opening, thereby forming a solder pattern to form a solder carrier film. This is a method of applying a flux to a solder resist opening portion of a substrate, laminating a film so that a solder pattern is in contact with a pad, and heating and transferring the film. On the other hand, the printing method is a method in which a printing mask (metal mask) having a through-hole provided in a portion corresponding to a pad is placed on a substrate, and a solder paste is printed and heat-treated. As the solder, tin-silver, tin-indium, tin-zinc, tin-bismuth and the like can be used.

As a solder body for forming the conductive bumps 62, tin / lead solder (melting point: 183 ° C.) or tin / silver solder (melting point: 220 ° C.) having a relatively low melting point is used.
As a solder body for connecting the conductive pins 64 and the conductive balls 66, tin / antimony solder, tin / silver solder, tin / silver / copper solder having a relatively high melting point of 230 ° C. to 270 ° C. may be used. preferable.

[0092]

EXAMPLES (Example 1) (1) A single-sided copper-clad laminate obtained by laminating a prepreg in which epoxy resin is impregnated in a glass cloth into a B stage and a copper foil and pressing the laminate with heat is used as a substrate. To manufacture a double-sided circuit board. The thickness of the insulating base material 10 was 75 μm, and the thickness of the copper foil 12 was 12 μm. On the surface of the laminate opposite to the surface on which the copper foil is formed, a pressure-sensitive adhesive layer having a thickness of 10 μm is provided.
A μm PET film 14 is laminated.

(2) Next, a non-through hole 16 for forming a via hole reaching the copper foil 12 is formed by irradiating a pulse oscillation type carbon dioxide laser from above the PET film 14, and further, the copper foil 12 is used as a plating lead for electrolytic copper plating. By performing the treatment, the interior of the non-through hole is filled with electrolytic copper plating 18 leaving a slight gap above the non-through hole 16 to form a filled via hole 20. In this example, a non-through hole for forming a via hole was formed using a high peak short pulse oscillation type carbon dioxide laser processing machine manufactured by Mitsubishi Electric, and a 22 μm thick PET film was laminated on the resin surface as a whole. , A glass cloth epoxy resin base material with a base material thickness of 75 μm,
The mask film method was used to irradiate a laser beam from the PET film side to form an opening for forming a 150 μmφ via hole at a speed of 100 holes / second.

(3) Using the PET film 14 as a printing mask, the conductive paste 22 is passed from the opening formed by laser irradiation to the gap remaining above the filled via hole 20.
Was charged.

(4) Insulating PET film 14 with insulating substrate 1
0, on the surface of the insulating substrate 10 on the side of the via hole 20, the projecting conductor 2 just above the via hole 20.
4 are formed. Further, an epoxy resin adhesive is applied to the entire surface on the protruding conductor side, and dried at 100 ° C. for 30 minutes to form an adhesive layer 26 having a thickness of 20 μm.
A 2 μm copper foil 28 is heated at 180 ° C. for a heating time of 70
Then, under the conditions of a pressure of 2 MPa and a degree of vacuum of 2.5 × 10 ³ Pa, hot pressing is performed on the adhesive layer 26.

(5) Thereafter, the copper foils 12 and 28 on both sides of the substrate were subjected to an appropriate etching treatment to form conductor circuits 30 and 32 (including via lands), thereby producing a core double-sided circuit board 34.

(6) Next, a single-sided circuit board for lamination is manufactured. This circuit board uses a single-sided copper-clad laminate as a substrate, like the double-sided circuit board. The thickness of the insulating substrate 10 is 7
5 μm, and the thickness of the copper foil 12 is 12 μm. On the surface of the laminate opposite to the surface on which the copper foil is formed, a PET film having a 10 μm-thick pressure-sensitive adhesive layer and a 12 μm-thick film itself is used.
The film 14 is laminated.

(7) Next, the conductive paste 22 is filled in the small gaps between the filled via holes 20 by performing the processing according to the steps (2) and (3) to form the projecting conductors 44. .

(8) Covering the PET film 14,
22μm thick PET as etching protection film
After attaching the film 25, the copper foil 12 attached to the surface of the insulating substrate 10 opposite to the filling via hole 20 is subjected to an appropriate etching treatment to form the conductor circuit 40.

(9) Thereafter, when the PET films 14 and 25 are all peeled off from the insulating base material 10, the projecting conductors 44 are formed on the surface of the insulating base material 10 on the via hole 20 side directly above the via holes 20. You. Further, an epoxy resin adhesive is applied to the entire surface of the projecting conductor side and precured to form an adhesive layer 46 for multilayering. Three such single-sided circuit boards for lamination are manufactured.

(10) The single-layer double-sided circuit board 34 formed by the processes (1) to (9) is used as a core.
Three-layered single-sided circuit boards 50, 52 and 54 are stacked on predetermined positions on both sides thereof (see FIG. 3), and laminated and pressed at a temperature of 180 ° C. using a vacuum hot press so that all the layers are I-shaped.
A multilayer core substrate 60 having a VH structure was created (see FIG. 4). In the multilayer core substrate 60 manufactured as described above, L / S = 75 μm / 75 μm, and the land diameter is 250 μm.
m, via hole diameter is 150 μm, and conductor layer thickness is 12
μm, and the thickness of the insulating layer was 75 μm.

(11) Next, the multilayer core substrate 60 (see FIG. 5 (a)) having the conductor circuits 40 formed on both surfaces is replaced with 8 g of copper sulfate.
/ L, nickel sulfate 0.6g, citric acid 15g / l, sodium hypophosphite 29g / l, boric acid 31g / l, surfactant 0.1g / l, immersed in electroless plating solution of pH = 9 Then, a roughened layer 62 made of copper-nickel-phosphorus having a thickness of 3 μm was formed on the surface of the conductor circuit 40. Next, the substrate was washed with water and immersed in an electroless tin displacement plating bath composed of a 0.1 mol / l tin borofluoride-1.0 mol / l thiourea solution at 50 ° C. for 1 hour to prepare the roughened layer 63.
(See FIG. 5 (b), but the tin layer is not shown).

(12) The compositions obtained in (1) and (2) were mixed and stirred to prepare an adhesive for electroless plating. Cresol novolak epoxy resin (Nippon Kayaku,
35 parts by weight (solid content: 80%) of a 25% acrylate having a molecular weight of 2500), 4 parts by weight of a photosensitive monomer (Aronix M315, manufactured by Toa Gosei), an antifoaming agent (S-65, manufactured by San Nopco)
0.5 parts by weight and 3.6 parts by weight of NMP were mixed with stirring. After mixing 8 parts by weight of polyether sulfone (PES) and 7.245 parts by weight of an epoxy resin particle (manufactured by Sanyo Kasei Co., Ltd., polymer pole) having an average particle size of 0.5 μm, 20 parts by weight of NMP were further added and stirred. Mixed. 2 parts by weight of imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals)
Photoinitiator (Ciba Geigy, Irgacure I-907)
2 parts by weight, 0.2 parts by weight of a photosensitizer (DETX-S, manufactured by Nippon Kayaku) and 1.5 parts by weight of NMP were mixed with stirring.

(13) The adhesive for electroless plating prepared in the above (12) is applied to the substrate 60 treated in the above (11) (see FIG. 5 (c)), and dried to form an adhesive layer. A photomask film on which a black circle of 85 μmφ was printed was brought into close contact with both surfaces of the formed substrate 60, and was exposed at 500 mJ / cm ² by an ultra-high pressure mercury lamp. This is DMDG
By performing spray development with a (diethylene glycol dimethyl ether) solution, an opening 65 serving as a 85 μmφ via hole was formed in the adhesive layer. Further, the substrate was exposed to 3000 mJ / cm ² by an ultra-high pressure mercury lamp,
By performing a heat treatment at 00 ° C. for 1 hour and then at 150 ° C. for 5 hours, a 35 μm-thick interlayer insulating material layer 64 (adhesive layer) having openings with excellent dimensional accuracy corresponding to a photomask film is formed. (See FIG. 5D). The tin plating layer was partially exposed in the opening 65 serving as a via hole.

(14) The substrate on which the via hole forming openings 65 are formed is immersed in chromic acid for 20 minutes to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer. The surface was roughened to a depth of about 1 to 5 μm to form a roughened surface 66, which was then immersed in a neutralizing solution (manufactured by Shipley), and then washed with water.

(15) By applying a palladium catalyst (manufactured by Atotech) to the roughened layer 66 (roughened depth 3.5 μm) on the surface of the adhesive layer, the adhesive layer 64 and the opening 65 for forming a via hole are formed. Catalyst nuclei were provided on the surface.

(16) The substrate was immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 67 having a thickness of 0.6 μm on the entire roughened surface (see FIG. 5F). . At this time, since the electroless plating film 67 was thin, irregularities following the roughened surface 66 of the adhesive layer 64 were observed on the film surface. [Electroless plating solution] NiSO _4: 0.003 mol / l tartaric acid: 0.20 mol / l copper sulfate: 0.03mol / l HCHO: 0.05mol / l NaOH: 0.10mol / l α, α'- bipyridyl: 40 mg / l polyethylene glycol (PEG): 0.1 g / l [Electroless plating conditions] Liquid temperature of 33 ° C

(17) A commercially available photosensitive dry film is stuck on the electroless copper plating film 67 formed in the above (16), a mask is placed, and exposure is performed at 100 mJ / cm ² .
It was developed with 0.8% sodium carbonate to provide a plating resist 68 having a thickness of 15 μm (see FIG. 6A).

(18) Next, plating is performed under the following conditions.
Electroless plating is applied to the non-resist area, and the thickness is 20μm
To form an upper conductor circuit 72
At the same time that the conductor layer to be provided is provided, the plating film 69 is formed in the opening.
To form a via hole 70 (see FIG. 6B).
See). [Aqueous electrolytic plating solution] Copper sulfate pentahydrate: 60 g / l Leveling agent (manufactured by Atotech, HL): 40 ml / l Sulfuric acid: 190 g / l Brightening agent (manufactured by Atotech, UV): 0.5 ml / l chloride ion : 40 ppm [Electroplating conditions] Bubbling: 3.0 l / min Current density: 0.5 A / dm²  Set current value: 0.18 A Plating time: 130 minutes

(19) After the plating resist 68 is peeled off and removed, the electroless plating film 67 under the plating resist is dissolved and removed with a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate and ammonium persulfate. And a thickness of about 2 composed of the electroless plating film 67 and the electrolytic copper plating film 69.
0 μm, L / S = 25 μm / 25 μm Upper layer conductor circuit 7
2 was formed. At this time, the surface of the via hole 70 was flat, and the level of the conductor circuit surface was the same as that of the via hole surface.

(20) A roughened layer 84 is formed on the substrate in the same manner as in the above (11).
By repeating the procedure of 9), the upper interlayer resin insulation layer 76 and the conductor circuit 82 (including the via hole 80) are further laminated by one layer to obtain a build-up wiring layer having three layers on one side and six layers on both sides (FIG. 7). (A)). Here, a roughened layer 84 made of copper-nickel-phosphorus is provided on the surface of the conductor circuit 82, but no tin-substituted plating layer is formed on the surface of the roughened layer 84.

(21) On the other hand, 60 dissolved in DMDG
Of cresol nopolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) of 50% by weight, and sensitized oligomer (molecular weight 4000) obtained by acrylated 50% of the epoxy group.
80% by weight bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, Epicoat 1)
001) 14.121 parts by weight, imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals) 1.6 parts by weight, polyvalent acrylic monomer which is a photosensitive monomer (Nippon Kayaku, R6
04) 1.5 parts by weight, 30 parts by weight of a polyvalent acrylic monomer (manufactured by Kyoeisha Chemical, DPE6A) and 0.36 parts by weight of a leveling agent made of an acrylate ester polymer (manufactured by Kyoeisha, Polyflow No. 75) were also mixed. Penzophenone (Kanto Chemical) as a photoinitiator for this mixture
20 parts by weight, 0.2 parts by weight of EAB (manufactured by Hodogaya Chemical) as a photosensitizer, 10 parts by weight of DMDG (diethylene glycol dimethyl ether) were added, and the viscosity was 1.4 ± 0.3 pa · s was obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type) at 60 rpm.
In the case of No. 4, rotor No. 4 was used, and in the case of 6 rpm, rotor No. 3 was used.

(22) The solder resist composition obtained in (21) was applied to both sides of the build-up wiring layer obtained in (20) in a thickness of 20 μm. Then
After drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a 5 mm thick soda lime glass substrate on which a circular pattern (mask pattern) of a solder resist opening is drawn by a chromium layer is placed on a chrome layer. The side on which was formed was brought into close contact with the solder resist layer, exposed to ultraviolet light of 1000 mJ / cm ² , and subjected to DMTG development treatment. In addition, 80
1 hour at 100 ° C, 1 hour at 100 ° C, 1 hour at 120 ° C,
Heat treatment was performed at 50 ° C. for 3 hours to form a solder resist layer 90 (thickness: 20 μm) with an opening in the pad portion (opening diameter: 200 μm).

(23) Next, the substrate on which the solder resist layer 90 was formed was replaced with nickel chloride 30 g / 1, sodium hypophosphite 10 g / 1, sodium citrate 10 g / 1.
Immersed in an electroless nickel plating solution having a pH of 5 for 20 minutes to form a nickel plating layer 92 having a thickness of 5 μm on the opening.
Was formed. Further, the substrate was placed on an electroless gold plating solution composed of gold cyanide 2 g / 1, ammonium chloride 75 g / 1, sodium citrate 50 g / 1, and sodium hypophosphite 10 g / 1 at 93 ° C. for 23 hours. By immersion for 2 seconds, a gold plating layer 94 having a thickness of 0.03 μm was formed on the nickel plating layer 92.

(24) Then, a solder paste made of tin / antimony solder having a melting point of 230 ° C. is printed on the gold plating layer 94 exposed in the opening of the solder resist layer 90 below the build-up wiring layer. The T pin 98 or the solder ball 100 is fixed on the solder pad by reflowing at a nearby ambient temperature, and on the gold plating layer 94 (solder pad) exposed from the opening of the solder resist layer 90 above the build-up wiring layer. Has a melting point of 1
A solder paste made of tin / lead solder at 83 ° C. was printed and reflowed at an ambient temperature near the melting point, thereby forming solder bumps 96 on the solder pads to produce a multilayer circuit board (see FIG. 7B). ).

In the multilayer circuit board manufactured in this manner, the land shape of the via hole of the multilayer core substrate can be made a perfect circle, and the land pitch can be set to about 600 μm. Densification can be easily achieved. Moreover, since the number of via holes in the core substrate can be increased, it is possible to sufficiently secure electrical connection between the conductor circuits in the multilayer core substrate and the conductor circuits in the build-up wiring layer. Also, it is connected to an electronic component including a semiconductor chip such as an LSI via a solder bump 96 formed on a gold plating layer 94 (solder pad) exposed from an opening of the solder resist layer 90 provided above the build-up wiring layer, Conductive pins 98 provided on the gold plating layer 94 (solder pad) exposed from the opening of the solder resist layer 90 provided below the build-up sub-layer.
Alternatively, since it is connected to a connection terminal or the like on the motherboard via the conductive ball 100, high-density mounting of electronic components becomes possible.

(Example 2) A non-through hole for forming a via hole of a double-sided circuit board and a single-sided circuit board constituting a multilayer core substrate is filled with a conductive paste to form a via hole, and the same process as that for forming the via hole is performed. A multilayer circuit board was manufactured in the same manner as in Example 1, except that a conductive paste was filled on the via hole to form a projecting conductor.

Example 3 An interlayer resin insulating layer having a thickness of 20
An epoxy resin film having a diameter of 60 μm is formed by thermocompression bonding of an epoxy resin film having a diameter of 60 μm, and an opening for forming a via hole having a diameter of 60 μm is provided. A multilayer circuit board was manufactured in the same manner as in Example 1 except that the roughening treatment was performed. The epoxy resin film is preferably a resin composite with a phenoxy resin, and contains particles for forming a roughened layer.

Example 4 A non-through hole for forming a via hole of a double-sided circuit board and a single-sided circuit board constituting a multilayer core board is filled with a conductive paste to form a via hole, and the same process as that for forming the via hole is performed. A multilayer circuit board was manufactured in the same manner as in Example 3, except that a conductive paste was filled on the via hole to form a projecting conductor.

Example 5 The interlayer resin insulating layer was formed to a thickness of 20 μm.
m is formed by thermocompression bonding of a polyolefin resin film, and an opening for forming a via hole having a diameter of 60 μm is provided by irradiating a carbon dioxide laser, and then, instead of forming an electroless plating film, without performing a roughening treatment. A 0.1 μm thick Cu sputtered film or Cu—N film on the surface of the interlayer resin insulating layer including the inner wall surface of the opening by sputtering.
A multilayer circuit board was manufactured in the same manner as in Example 1 except that an i-sputtered film was formed.

(Example 6) A non-through hole for forming a via hole of a double-sided circuit board and a single-sided circuit board constituting a multilayer core board is filled with a conductive paste to form a via hole, and the same process as that for forming the via hole is performed. A multilayer circuit board was manufactured in the same manner as in Example 5, except that a conductive paste was filled in the via hole to form a projecting conductor.

(Comparative Example) (1) An insulating substrate made of a double-sided copper-clad laminate having a thickness of 0.8 μm was used as a core substrate, and a through-hole having a diameter of 300 μm was drilled in the core substrate. Conducting plating and electrolytic plating to form a conductor layer including through-holes, further providing a roughened layer on the entire surface of the conductor layer including through-holes, and filling the through-holes with a non-conductive filling material for filling holes. And dried and cured. (2) Next, the filler protruding from the through-hole is removed and flattened, and the surface thereof is subjected to electroless plating and electrolytic plating to be thickened to cover the conductor circuit and the conductor covering the filler filled in the through-hole. A layer portion was formed. (3) An etching resist is formed on the surface of the substrate on which a portion serving as a conductive layer covering the conductive circuit and the filler filled in the through holes is formed, and the plating film in a portion where the etching resist is not formed is removed by etching. The etching resist was peeled off to form a conductor layer covering the independent conductor circuit and the filler. Further, a multilayer circuit board was manufactured according to the same steps as (11) to (23) of Example 1.

For the above Examples 1 to 6 and Comparative Example,
The wiring length from the IC chip to the solder bumps, BGA (ball grid array) or PGA (pin grid array) and the number of core lands formed were checked.
It was possible to reduce the number of core lands per unit area (cm ² ) by 10 to 30% by reducing the number of core lands by 0 to 25%.

[0124]

As described above, according to the multilayer circuit board of the present invention, a multilayer core board is formed by laminating a large number of circuit boards having fine filled via holes and conductive circuits formed by laser processing, and performing batch heat treatment. Since it was formed by pressing, it is possible to increase the density of wiring in the multilayer core substrate, and without providing through holes unlike the conventional one,
Electrical connection with the build-up wiring layer can be sufficiently ensured via the filled via hole.

Further, a conductive bump, a conductive pin or a conductive ball is formed on a conductive pad exposed in an opening provided in a solder resist layer located on the outermost side of the build-up wiring layer, ie, a solder pad immediately above a via hole. Is provided, the wiring layer in the build-up wiring layer can be connected to electronic components including a semiconductor chip such as an LSI or a motherboard via such conductive bumps, conductive pins or conductive balls. The connection is made with the wiring length, which enables high-density wiring and high-density mounting of electronic components.

Further, since a single-sided or double-sided circuit board is formed of the same material and is laminated, cracks and peeling at the interface originating from thermal expansion hardly occur.
Therefore, the reliability for the temperature cycle test is also improved. In addition, when a multilayer circuit board is configured using only a single-sided circuit board, the effect that warpage hardly occurs regardless of the presence or absence of wiring formation is also obtained.

[Brief description of the drawings]

FIGS. 1A to 1F are views showing a part of a manufacturing process of a double-sided circuit board constituting a multilayer core board serving as a base of a multilayer circuit board according to the present invention.

FIGS. 2A to 2E are diagrams illustrating a part of a manufacturing process of a single-sided circuit board constituting a multilayer core board serving as a base of the multilayer circuit board according to the present invention.

FIG. 3 is a view showing a part of a manufacturing process of a multilayer core substrate as a base of the multilayer circuit board according to the present invention.

FIG. 4 is a view showing a multilayer core substrate as a base of the multilayer circuit board according to the present invention.

FIGS. 5A to 5F are views showing a part of the manufacturing process of the multilayer circuit board according to the present invention.

6 (a) to 6 (c) are views showing a part of a manufacturing process of the multilayer circuit board according to the present invention.

FIGS. 7A and 7B are diagrams illustrating a part of the manufacturing process of the multilayer circuit board according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Insulating base material 12 Adhesive 14 Protective film 16 Via hole forming opening 18 Conductive paste 20 Via hole 22 Copper foil 24 Conductive circuit 30 Double-sided circuit board 32, 34, 36 Single-sided circuit board 40 Insulating base material 42 Copper foil 44 PET Film 46 via hole forming opening 48 conductive paste 49 via hole 50 etching protection film 52 conductive circuit 53 projecting conductor 54 adhesive layer 60 multilayer core substrate 62 roughening layer 64 electroless plating adhesive layer 65 via hole forming opening 66 rough Layer 67 Electroless plating film 68 Plating resist 69 Electroplating film 70 Via hole 72 Conductor circuit 74 Roughening layer 76 Adhesive layer for electroless plating 80 Via hole 82 Conductor circuit 84 Roughening layer 90 Solder resist layer 92 Nickel plating layer 94 Gold Plating layer 96 Solder bump 98 T pin 100 Solder ball

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 3/46 H05K 3/46 X H01L 23/12 1/03 610L H05K 1/03 610 610N 1/11 N 1/11 3/00 N 3/00 H01L 23/12 NF term (reference) 5E317 AA24 BB01 BB02 BB03 BB11 CC25 CC33 CC53 CD32 GG14 5E346 AA04 AA05 AA06 AA12 AA22 AA32 AA43 AA51 BB15 BB16 CC02 CC04 CC09 CC32 DD02 DD25 DD33 DD44 EE06 EE09 EE13 EE15 EE19 EE33 EE38 FF06 FF07 FF09 FF10 FF12 FF18 FF24 FF35 FF45 GG15 GG17 GG18 GG19 GG22 GG25 GG27 GG28 HH11 HH22 HH25

Claims (10)

[Claims] 1. A build-up wiring layer in which interlayer resin insulating layers and conductive layers are alternately laminated on a multilayer core substrate having a conductive circuit in an inner layer, and each conductive layer is connected by a via hole. In the multilayer circuit board, the multilayer core substrate has a conductive circuit on one or both sides of an insulating hard base material, and a hole penetrating the insulating hard base material and reaching the conductive circuit is filled with a conductive substance. A multilayer circuit board, comprising: a plurality of circuit boards each having a via hole formed by laminating the circuit boards via an adhesive layer; 2. A build-up wiring layer in which interlayer resin insulating layers and conductive layers are alternately laminated on both surfaces of a multilayer core substrate having a conductive circuit in an inner layer, and each conductive layer is connected by a via hole. In the multilayer circuit board, the multilayer core substrate has a conductive circuit on one or both sides of an insulating hard base material, and a conductive circuit is formed in a hole penetrating through the insulating hard base material and reaching the conductive circuit. A plurality of circuit boards each having a via hole filled with a substance are formed by laminating via an adhesive layer and hot-pressing collectively, and further, an outermost layer constituting one of the build-up wiring layers A solder bump is provided on the surface of the conductor layer of
A multilayer circuit board, wherein a conductive pin or a conductive ball is disposed on a surface of an outermost conductor layer forming the other of the build-up wiring layers. 3. The multilayer circuit board according to claim 1, wherein the conductive material is metal plating formed by an electrolytic plating process. 4. The multilayer circuit board according to claim 1, wherein the conductive substance is a conductive paste composed of metal particles and a thermosetting resin or a thermoplastic resin. 5. Each of the circuit boards constituting the multilayer core substrate has a projecting conductor electrically connected to the via hole corresponding to the position of the via hole. 5. The multilayer circuit board according to any one of 4. 6. The multilayer circuit board according to claim 5, wherein the projecting conductor is formed from a conductive paste. 7. A method according to claim 1, wherein a portion of the via hole of the build-up wiring layer is located immediately above the via hole formed in the multilayer core substrate and is directly connected to the via hole. 7. The multilayer circuit board according to any one of 6. 8. The insulating substrate of each circuit board constituting said multilayer core substrate is a glass cloth epoxy resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, an aramid non-woven epoxy resin. The multilayer circuit board according to any one of claims 1 to 7, wherein the multilayer circuit board is formed from any one of a hard base material selected from a resin base material and an aramid nonwoven fabric-polyimide resin base material. 9. The insulating substrate of each circuit board constituting the multilayer core substrate is formed of a glass cloth epoxy resin substrate having a thickness of 20 to 100 μm, and the filled via hole diameter is 50 to 250 μm. The multilayer circuit board according to claim 8, wherein: 10. A via hole of each circuit board constituting said multilayer core board has a pulse energy of 0.5 to 100.
mJ, pulse width 1 to 100 μs, pulse interval 0.5
10. The method according to claim 9, wherein the number of shots is not less than ms, and the number of shots is 3 to 50. Multilayer circuit board.