JP2002271027A - Multi-layer printed board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board which is reliable since a conductor circuit has a short wiring distance and a high degree of freedom of design and an inter-layer resin insulating layer near the via hole hardly cracks. SOLUTION: A multi-layer printed wiring board has conductor circuits and an inter-layer resin insulating layer laminated on a in order, so that the conductor circuits on both sides of the inter-layer resin layer are connected through via holed. Via holes of different layers among the via holes are formed in stack via structure, and at least one of the via holes of the different layers has a different land diameter from other via holes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a multilayer printed wiring board.

[0002]

2. Description of the Related Art A multilayer printed wiring board called a so-called multilayer build-up wiring board is manufactured by a semi-additive method or the like.
m on a resin substrate reinforced with glass cloth, etc.
It is manufactured by alternately laminating a conductor circuit made of copper or the like and an interlayer resin insulating layer. The connection between the conductor circuits via the interlayer resin insulation layer of the multilayer printed wiring board is performed by via holes.

Conventionally, build-up multilayer printed wiring boards have been manufactured by a method disclosed in, for example, Japanese Patent Application Laid-Open No. 9-130050. That is, first, a through hole is formed in the copper-clad laminate to which the copper foil is attached, and then a through hole is formed by performing an electroless copper plating process. Subsequently, the surface of the substrate is etched into a conductor pattern using a photolithography technique to form a conductor circuit. Next, on the surface of the formed conductor circuit,
After forming a roughened surface by electroless plating or etching, forming an insulating resin layer on the conductor circuit having the roughened surface, performing exposure and development processing to form a via hole opening, and then UV After curing and main curing, an interlayer resin insulating layer is formed.

Further, after performing a roughening treatment on the interlayer resin insulating layer with an acid or an oxidizing agent, a thin electroless plating film is formed, a plating resist is formed on the electroless plating film, and then an electrolytic plating is performed. Then, etching is performed after the plating resist is stripped to form a conductive circuit connected to the lower conductive circuit by a via hole. After repeating this, finally form a solder resist layer to protect the conductor circuit, apply plating etc. to the exposed part for connection with electronic components such as IC chip and motherboard etc. and solder After the pad for bump formation, IC
A build-up multilayer printed wiring board is manufactured by printing solder paste on an electronic component side such as a chip to form solder bumps. Further, if necessary, solder bumps are formed on the motherboard.

[0005]

In recent years, with the increase in the frequency of IC chips, the speed of multilayer printed wiring boards has been increased.
High density is required, and as a multilayer printed wiring board corresponding to this, a multilayer printed wiring board having a via hole of a stacked via structure (a structure in which a via hole is formed immediately above a via hole) has been proposed. (See FIG. 19). However, in a multilayer printed wiring board having a via hole having such a stacked via structure, cracks may occur in the interlayer resin insulating layer near the via hole. In particular, when a multilayer printed wiring board is left for a certain period of time under heat cycle conditions, cracks often occur, and further, due to the cracks, peeling or disconnection occurs in the conductor circuit around the via hole. There was something.

This is a conventional multi-layer printed wiring board 600 having via holes of a stacked via structure (FIG. 19).
In (a) and (b)), the via hole 1 is usually used.
071 to 1073 have substantially the same land diameter, and the outermost via hole 1071 and the adjacent conductor circuit 105
a in the lower region of the conductor circuit non-forming portion (FIG. 19, A
Region), no conductor circuit exists, and the interlayer resin insulation layer 10
In addition, since the interlayer resin insulating layer does not contain a reinforcing material such as glass fiber, the mechanical strength of the region A is not sufficient, and cracks and the like occur. It is considered easy.

[0007]

The inventors of the present invention have made intensive studies to make the land diameter of at least one of the via holes having a stacked via structure different from the other land diameters. As a result, it has been found that the problem of cracks or the like occurring in the interlayer resin insulating layer near the via hole can be solved, and the present invention has the following features.

That is, the printed wiring board of the first invention is
A multilayer printed wiring board in which a conductor circuit and an interlayer resin insulation layer are sequentially laminated on a substrate, and the conductor circuits sandwiching the interlayer resin insulation layer are connected via via holes,
Among the via holes, via holes having different layers are formed so as to have a stacked via structure, and at least one of the via holes having different layers has a land diameter of a land of another via hole. It is characterized by being different from the diameter.

In the multilayer printed wiring board according to the second aspect of the present invention, a conductor circuit and an interlayer resin insulation layer are sequentially laminated on a substrate, and the conductor circuits sandwiching the interlayer resin insulation layer are interposed via holes. Connected, a multilayer printed wiring board in which the conductor circuits sandwiching the substrate are connected via through holes, and a via hole having a stack via structure is formed immediately above the through holes, and At least one of the via holes having the stacked via structure has a land diameter different from that of the other via holes.

In the third multilayer printed wiring board, a conductor circuit and an interlayer resin insulation layer are sequentially laminated on a substrate, and the conductor circuits sandwiching the interlayer resin insulation layer are connected via via holes. Also, a multilayer printed wiring board in which the conductor circuits sandwiching the substrate and the interlayer resin insulating layer are connected via through holes, and directly above the through holes,
A via hole having a stacked via structure is formed, and at least one of the via holes having the stacked via structure has a land diameter different from that of another via hole.

[0011] In the first to third multilayer printed wiring boards, at least one of the via holes includes:
It is desirable that the shape be a field via shape.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION In a printed wiring board according to the first aspect of the present invention, a conductive circuit and an interlayer resin insulating layer are sequentially laminated on a substrate, and a via hole is formed between the conductive circuits sandwiching the interlayer resin insulating layer. A plurality of via holes having different levels among the via holes are formed to have a stacked via structure, and at least one of the via holes having different levels is different from each other. First, the land diameter is different from the land diameters of other via holes.

In the first multilayer printed wiring board of the present invention,
Via holes of different levels are formed so as to form a stacked via structure. As described above, when the via hole is formed so as to have a stacked via structure, the wiring distance is shortened, so that the signal transmission time can be shortened and the degree of freedom in designing the conductor circuit is improved. High density wiring makes it easier to respond.

In the above-mentioned multilayer printed wiring board,
At least one of the via holes at different levels
The land diameter is different from the land diameters of other via holes.
When the via hole has such a configuration, the via hole having a large land diameter serves as a reinforcing material for the interlayer resin insulating layer, and the mechanical strength of the interlayer resin insulating layer is improved. Cracks are less likely to occur in the interlayer resin insulation layer. This will be described below with reference to the drawings. 1 to 3 respectively
(A) is a partial sectional view schematically showing a part of an embodiment of the first multilayer printed wiring board of the present invention, and (b) is a via hole of the multilayer printed wiring board shown in (a). FIG. 3 is a perspective view schematically showing only a.

In the first multilayer printed wiring board of the present invention,
At least one of the via holes at different levels is
The land diameter is different from the land diameters of other via holes. Specifically, for example, as shown in FIGS. 1A and 1B, the land diameter of the via hole 1072 in the inner layer is configured to be larger than the land diameter of the via hole 1071 in the outermost layer. In this case, each via hole of each layer is formed so that the shape when viewed in plan is circular and concentric. For example, as shown in FIGS. 2A and 2B, the land diameter of the lowermost via hole 1073 may be larger than the land diameter of the outermost via hole 1071. Also in this case, each via hole of each layer has a circular shape when viewed in plan,
And it is formed so that it may become concentric.

Further, as shown in FIGS. 3A and 3B, the land diameter of the via hole 1072 of the inner layer and a part of the land diameter of the via hole 1073 of the lowermost layer are respectively changed to the via holes 1071 of the outermost layer. And a conductor circuit 105a adjacent to the conductor circuit 105a may be configured to have a larger diameter than the land diameter of the outermost via hole 1071 in a different portion (region A in the drawing) below the conductor circuit non-formed portion. Good. In this case, each via hole of each layer has a circular shape when viewed in plan, but the center is at a different position, that is, the center of the inner layer via hole and the center of the lowermost via hole are: It is formed at a position opposite to the center of the outermost via hole. The center of the via hole of the inner layer and the center of the via hole of the lowermost layer when the via hole is viewed in plan may be located at a position other than the position opposite to the center of the via hole of the outermost layer.

In the case where a via hole having a stacked via structure having such a structure is formed, one of the regions (A region) below the conductor circuit non-formed portion between the outermost via hole and the conductor circuit adjacent thereto is formed. In addition to the interlayer resin insulation layer 102, the land portions 1072a,
73a will be present. In this case, since the land portion serves as a reinforcing material for the interlayer resin insulation layer, A
The mechanical strength of the region is improved, and the occurrence of cracks and the occurrence of peeling between the conductive circuit or via hole and the interlayer resin insulating layer can be prevented. In addition, in FIGS.
101 is a substrate, 114 is a solder resist layer, and 117 is a solder bump.

The shape of the via hole is not limited to the shape shown in FIGS. 1 to 3 and is not shown. For example, the land diameter of the inner via hole 1072 and the via hole 1073 of the lowermost layer are not shown. May be configured to be larger than the land diameter of the outermost via hole. Further, the land diameter of the via hole in each layer may be different from each other. In addition, in the above-described example, the shape when the via holes of each layer are viewed in plan is circular, but the shape when the via holes are viewed in plan is not limited to this. It may be rectangular or the like.

In the multilayer printed wiring board of the first aspect of the present invention, the number of via holes having a stacked via structure is not particularly limited as long as it is two or more. It may be a layer, two or four or more layers. In the present specification, the land diameter of the via hole refers to a distance from the outer edge of the via hole opening to the outer edge of the via hole, for example, the distance L shown in FIG.

The land diameter of the via hole is desirably such that at least one land portion is present in at least a half region of the region A on the via hole side. More preferably, the length is such that at least one land portion is present.

In addition, as described above, in the multilayer printed wiring board, among the via holes, via holes having different levels are formed so as to have a stacked via structure. Therefore, in order to obtain a more reliable via hole, it is desirable that the shape of the lower via hole (the via hole in which another via hole is formed immediately above) be a field via shape. This is because, in the case of a field via shape, the upper surface of the via hole is substantially flat, so that it is suitable for forming a via hole immediately above.

The via hole is usually formed by plating, as described later. When the via hole is formed in a field via shape, the via hole may be formed in a field via shape by plating, or may be formed once. After forming a via hole having a depression on the upper surface, the depression may be filled with a conductive paste or the like to form a field via shape. The plating solution used for forming a via hole having a field via shape by plating will be described later in detail. Also, without forming the via hole into a field via shape, after forming a via hole having a depression on the upper surface, filling the depression with a resin filler or the like, and then forming a lid plating layer covering the resin filler, The upper surface of the via hole may be flat. When the via hole has a field via shape or a lid plating layer is formed on the via hole, the upper surface preferably has an average roughness Ra of 5 μm or less. This is because it is suitable for forming a via hole having a stacked via structure, and has excellent connection reliability of the formed via hole having the stacked via structure.

Next, a method of manufacturing the multilayer printed wiring board according to the first aspect of the present invention will be described in the order of steps. (1) First, a conductor circuit is formed on a glass epoxy substrate, a polyimide substrate, a bismaleimide-triazine resin (BT resin) substrate, a resin substrate such as a fluororesin substrate, a copper-clad laminate, or the like as a starting material. Specifically, for example, after forming a solid conductor layer by performing electroless plating or the like on both surfaces of the substrate, an etching resist corresponding to the conductor circuit pattern is formed on the conductor layer,
It may be formed by performing etching. Further, a copper-clad laminate may be used as a substrate on which a solid conductor layer is formed.

When performing the above electroless plating, a through hole is formed in advance on the insulating substrate, and the electroless plating is also performed on the wall surface of the through hole.
A through hole is provided to electrically connect the conductor circuits sandwiching the substrate. After the through holes are formed, it is desirable to fill the through holes with a resin filler.
At this time, it is desirable that the resin-filling material is also filled in the non-conductor-circuit-formed portion. Examples of the resin filler include a resin composition containing an epoxy resin, a curing agent, and inorganic particles.

(2) Next, if necessary, the surface of the conductor circuit is subjected to a roughening treatment. As a roughening treatment method, for example,
A blackening (oxidation) -reduction treatment, an etching treatment using a mixed solution containing an organic acid and a cupric complex, a treatment by Cu-Ni-P needle-like alloy plating, and the like can be used.

(3) Next, an uncured resin layer made of a thermosetting resin or a resin composite is formed on the conductor circuit, or a resin layer made of a thermoplastic resin is formed. The uncured resin layer may be formed by applying an uncured resin with a roll coater, a curtain coater, or the like, or may be formed by thermocompression bonding of an uncured (semi-cured) resin film. . Further, a resin film in which a metal layer such as a copper foil is formed on one surface of an uncured resin film may be attached. The resin layer made of a thermoplastic resin is desirably formed by thermocompression bonding a resin molded body formed into a film.

When applying the uncured resin, a heat treatment is applied after the resin is applied. By performing the heat treatment, the uncured resin can be thermally cured. The heat curing may be performed after forming a via hole opening described later.

Specific examples of the thermosetting resin used in forming such a resin layer include, for example, epoxy resin, phenol resin, polyimide resin, polyester resin, bismaleimide resin, polyolefin resin, polyphenylene ether resin and the like. No.

Examples of the epoxy resin include cresol novolak epoxy resin, bisphenol A epoxy resin, bisphenol F epoxy resin, phenol novolak epoxy resin, alkylphenol novolak epoxy resin, biphenol F epoxy resin, and naphthalene epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

Examples of the polyolefin resin include polyethylene, polystyrene, polypropylene, polyisobutylene, polybutadiene, polyisoprene, cycloolefin resin, and copolymers of these resins.

Examples of the thermoplastic resin include phenoxy resin, polyethersulfone, and polysulfone. Further, the composite of the thermosetting resin and the thermoplastic resin (resin composite) is not particularly limited as long as it contains a thermosetting resin and a thermoplastic resin, and specific examples thereof include, for example, And a resin composition for forming a roughened surface.

As the resin composition for forming a roughened surface, for example, an uncured heat-resistant resin matrix which is hardly soluble in a roughening solution comprising at least one selected from an acid, an alkali and an oxidizing agent may be used. Examples thereof include those in which a substance soluble in a roughening liquid comprising at least one selected from an acid, an alkali, and an oxidizing agent is dispersed. Note that the terms "sparingly soluble" and "soluble" are referred to as "soluble" for convenience when a substance having a relatively high dissolution rate is immersed in the same roughening solution for the same time, and the relative dissolution rate is relatively low. The slower one is called "poorly soluble" for convenience.

The heat-resistant resin matrix is preferably a matrix capable of maintaining the shape of the roughened surface when the roughened surface is formed on the interlayer resin insulating layer using the roughening solution. , Thermoplastic resins, and composites thereof. Further, a photosensitive resin may be used. This is because, in a step of forming a via hole opening described later, the opening can be formed by exposure and development processing.

The thermosetting resin includes, for example, epoxy resin, phenol resin, polyimide resin, polyolefin resin, fluororesin and the like. Alternatively, a resin obtained by imparting photosensitivity to these thermosetting resins, that is, a resin obtained by subjecting a thermosetting group to a (meth) acrylation reaction using methacrylic acid, acrylic acid, or the like may be used. Specifically, a (meth) acrylate of an epoxy resin is desirable, and an epoxy resin having two or more epoxy groups in one molecule is more desirable.

Examples of the thermoplastic resin include phenoxy resin, polyether sulfone, polysulfone, polyphenylene sulfone, polyphenylene sulfide, polyphenyl ether, polyether imide and the like. These may be used alone or in combination of two or more.

Examples of the soluble substance include inorganic particles, resin particles, metal particles, rubber particles, liquid resin, liquid rubber, and the like. These may be used alone or in combination of two or more.

Examples of the inorganic particles include aluminum compounds such as alumina and aluminum hydroxide; calcium compounds such as calcium carbonate and calcium hydroxide;
Potassium compounds such as potassium carbonate; magnesium compounds such as magnesia, dolomite, basic magnesium carbonate and talc; silicon compounds such as silica and zeolite. These may be used alone or in combination of two or more. The alumina particles can be dissolved and removed with hydrofluoric acid, and the calcium carbonate can be dissolved and removed with hydrochloric acid. Further, sodium-containing silica and dolomite can be dissolved and removed with an alkaline aqueous solution.

Examples of the resin particles include those made of a thermosetting resin, a thermoplastic resin and the like. When immersed in a roughening liquid comprising at least one selected from acids, alkalis and oxidizing agents, There is no particular limitation as long as the dissolution rate is faster than the heat-resistant resin matrix,
Specifically, for example, amino resin (melamine resin, urea resin, guanamine resin, etc.), epoxy resin, phenol resin, phenoxy resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, bismaleimide-triazine resin and the like can be mentioned. Can be These may be used alone or in combination of two or more. It is necessary that the resin particles have been previously cured.
If not cured, the resin particles will dissolve in the solvent that dissolves the resin matrix, so they will be uniformly mixed, and it will not be possible to selectively dissolve and remove only the resin particles with an acid or oxidizing agent. is there.

Examples of the metal particles include gold, silver,
Examples include copper, tin, zinc, stainless steel, aluminum, nickel, iron, lead, and the like. These may be used alone or in combination of two or more. The metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

(4) Next, when forming an interlayer resin insulating layer using a thermosetting resin or a resin composite as the material, an uncured resin layer is subjected to a curing treatment and a via hole opening is formed. To form an interlayer resin insulation layer. The via hole opening is desirably formed by laser processing. The laser processing may be performed before the curing processing or may be performed after the curing processing. When an interlayer resin insulating layer made of a photosensitive resin is formed, exposure,
By performing a developing process, an opening for a via hole may be provided. In this case, the exposure and development processes are performed before the above-described curing process.

When forming an interlayer resin insulation layer using a thermoplastic resin as the material, an opening for a via hole is formed in the resin layer made of the thermoplastic resin by laser processing to form an interlayer resin insulation layer. be able to.

At this time, as a laser to be used, for example, a carbon dioxide gas laser, an excimer laser, a UV laser,
An AG laser and the like can be mentioned. These may be properly used in consideration of the shape of the via hole opening to be formed.

When the via hole opening is formed,
By irradiating laser light with a hologram excimer laser through a mask, a large number of via hole openings can be formed at once. Further, when the via hole opening is formed using a short-pulse carbon dioxide laser, the amount of resin remaining in the opening is small, and the damage to the resin at the periphery of the opening is small.

When irradiating a laser beam through an optical lens and a mask, a large number of via hole openings can be formed at one time. This is because a plurality of portions can be simultaneously irradiated with laser light having the same intensity and the same irradiation angle through the optical lens and the mask.

The thickness of the interlayer resin insulating layer is not particularly limited, but is usually preferably 5 to 50 μm. Also,
The opening diameter of the via hole opening is not particularly limited, but is usually preferably 40 to 200 μm.

(5) Next, a roughened surface is formed on the surface of the interlayer resin insulating layer including the inner wall of the via hole opening, if necessary, using an acid or an oxidizing agent. The roughened surface is formed in order to enhance the adhesion between the interlayer resin insulating layer and the thin film conductor layer formed thereon. In the case where there is a property, it may not be formed.

Examples of the acid include sulfuric acid, nitric acid, hydrochloric acid, phosphoric acid, and formic acid. Examples of the oxidizing agent include chromic acid, chromic sulfuric acid, and permanganates such as sodium permanganate. After forming the roughened surface, it is desirable to neutralize the surface of the interlayer resin insulating layer using an aqueous solution of an alkali or a neutralizing solution. This is because the next step can be prevented from being affected by an acid or an oxidizing agent. Further, the formation of the roughened surface may be performed by using a plasma treatment or the like.

(6) Next, a thin film conductor layer is formed on the surface of the interlayer resin insulating layer provided with the via hole opening. The thin film conductor layer can be formed using a method such as electroless plating, sputtering, or vapor deposition. In addition, when the roughened surface is not formed on the surface of the interlayer resin insulating layer, it is preferable that the thin film conductor layer is formed by sputtering. When the thin film conductor layer is formed by electroless plating, a catalyst is previously applied to the surface to be plated. Examples of the catalyst include palladium chloride.

The thickness of the thin film conductor layer is not particularly limited, but is preferably 0.6 to 1.2 μm when the thin film conductor layer is formed by electroless plating, and is preferably 0 to 1.2 μm when formed by sputtering. 0.1 to 1.0 μm is desirable. The material of the thin film conductor layer is, for example, C
u, Ni, P, Pd, Co, W and the like. Among these, Cu and Ni are desirable.

(7) Next, a plating resist is formed on a part of the thin film conductor layer using a dry film, and thereafter, electrolytic plating is performed using the thin film conductor layer as a plating lead, and the plating resist non-formed portion is formed. To form an electrolytic plating layer. Here, a plating resist is formed so that a via hole having a desired land diameter can be formed. That is, if a via hole having a large land diameter is formed in this layer, the width of the plating resist non-formed portion may be increased.

In this step, the via hole opening may be filled with electrolytic plating to form a field via structure. A via hole having a recess on the upper surface is formed once, and then a conductive paste is filled in the recess. It may be filled to form a field via structure. Alternatively, after forming a via hole having a depression on the upper surface, the depression may be filled with a resin filler or the like, and a lid plating layer may be formed thereon to form a via hole having a flat upper surface.

When a via hole having a filled via structure is formed at the time of electrolytic plating, for example, electrolytic plating may be performed using an electrolytic plating solution having the following composition. That is, 50-300 g / l copper sulfate, 30-200 g / l
g / l sulfuric acid, 25 to 90 mg / l chloride ions, and 1 to 1 comprising at least a leveling agent and a brightening agent.
Electroplating treatment may be performed using an electrolytic plating solution containing 000 mg / l of an additive.

With the electrolytic plating solution having such a composition, a via hole having a field via structure can be formed regardless of the opening diameter of the via hole, the material and thickness of the resin insulating layer, the presence or absence of a roughened surface of the interlayer resin insulating layer, and the like. Can be formed. In addition, since this electrolytic plating solution contains a high concentration of copper ions, it sufficiently supplies copper ions to the via hole openings,
Plating speed 40 ~ 100μm /
The plating can be performed in a short time, which leads to an increase in the speed of the electrolytic plating process.

The electrolytic plating solution is 100 to 25
0 g / l copper sulfate, 50-150 g / l sulfuric acid, 30-
Desirably, the composition contains 70 mg / l of chloride ion and 1 to 600 mg / l of an additive composed of at least a leveling agent and a brightening agent.

In the electrolytic plating solution, the additive only needs to be at least composed of a leveling agent and a brightener, and may contain other components.
Here, examples of the leveling agent include polyethylene, gelatin, and derivatives thereof. Examples of the brightener include sulfur oxide and its related compounds, hydrogen sulfide and its related compounds, and other sulfur compounds.

The amount of the leveling agent is from 1 to
The amount of the brightener is preferably 1000 mg / l.
0.1-100 mg / l is desirable. The mixing ratio of the two is preferably 2: 1 to 10: 1.

(8) Next, the plating resist is peeled off, and the thin film conductor layer existing under the plating resist is removed by etching to form an independent conductor circuit. Examples of the etchant include a sulfuric acid-hydrogen peroxide aqueous solution, an aqueous solution of a persulfate such as ammonium persulfate, ferric chloride, cupric chloride, and hydrochloric acid. Further, a mixed solution containing the above-described cupric complex and an organic acid may be used as an etching solution.

Further, a conductor circuit may be formed by using the following method instead of the method described in the above (7) and (8). That is, after forming an electrolytic plating layer on the entire surface of the thin film conductor layer, an etching resist is formed using a dry film on a part of the electrolytic plating layer, and thereafter, an electrolytic plating layer under an etching resist non-formed portion and An independent conductor circuit may be formed by removing the thin-film conductor layer by etching and then removing the etching resist.

(9) Thereafter, the above steps (3) to (8) are repeated one or more times to produce a substrate having the uppermost conductive circuit formed on the interlayer resin insulating layer. Note that the number of times the above steps (3) to (8) are repeated may be appropriately selected according to the design of the multilayer printed wiring board. Here, the via hole is formed immediately above the via hole so that the via hole has a stacked via structure. Further, as described above, the land diameter of the via hole can be adjusted by adjusting the size of the plating resist non-formed portion when forming the plating resist.

(10) Next, a solder resist layer having a plurality of openings for forming solder bumps is formed on the substrate including the uppermost conductive circuit. Specifically, after the uncured solder resist composition is applied by a roll coater or a curtain coater, or the solder resist composition formed into a film is pressed, the solder bumps are formed by laser processing or exposure and development processing. Openings are formed and, if necessary, a curing treatment is performed to form a solder resist layer.

The above solder resist layer can be formed using a solder resist composition containing, for example, a polyphenylene ether resin, a polyolefin resin, a fluororesin, a thermoplastic elastomer, an epoxy resin, a polyimide resin and the like.

Examples of the solder resist composition other than those described above include, for example, a novolak-type epoxy resin (meth) acrylate, an imidazole curing agent, a bifunctional (meth) acrylate monomer, and a molecular weight of 500 to 50.
A paste-like fluid containing a polymer of about 00 (meth) acrylate, a thermosetting resin such as a bisphenol-type epoxy resin, a photosensitive monomer such as a polyvalent acrylic monomer, a glycol ether-based solvent, and the like. It is desirable that the viscosity is adjusted to 1 to 10 Pa · s at 25 ° C. Further, the solder resist composition may contain an elastomer or an inorganic filler. A commercially available solder resist composition may be used as the solder resist composition.

The laser used for forming the opening for forming the solder bump may be the same as the laser used for forming the opening for the via hole.

Next, a solder pad is formed on the surface of the conductor circuit exposed at the bottom surface of the opening for forming a solder bump, if necessary. The solder pad can be formed by coating the surface of the conductor circuit with a corrosion-resistant metal such as nickel, palladium, gold, silver, and platinum. Specifically, it is desirable to form with metal, such as nickel-gold, nickel-silver, nickel-palladium, and nickel-palladium-gold. Further, the solder pad is, for example,
It can be formed using a method such as plating, vapor deposition, electrodeposition, etc. Among them, plating is preferable because of excellent uniformity of the coating layer.

(11) Next, the above-mentioned solder bump forming opening is filled with a solder paste and subjected to a reflow treatment, or after the solder paste is filled, a conductive pin is attached, and further a reflow treatment is carried out. Bump or B
A GA (Ball Grid Array) and a PGA (Pin Grid Array) are formed. In addition, a plasma treatment with oxygen, carbon tetrachloride, or the like may be performed as needed for a character printing process for forming a product recognition character or the like or for modifying a solder resist layer.
Through such steps, the multilayer printed wiring board of the first present invention can be manufactured.

Next, the multilayer printed wiring board according to the second embodiment of the present invention will be described. The multilayer printed wiring board according to the second aspect of the present invention, on a substrate, a conductor circuit and an interlayer resin insulation layer are sequentially laminated, and the conductor circuits sandwiching the interlayer resin insulation layer are connected via via holes, A multilayer printed wiring board in which conductive circuits sandwiching a substrate are connected via through holes, wherein via holes having a stacked via structure are formed immediately above the through holes, and the stacked via structures are provided. At least one of the via holes has a land diameter different from that of the other via holes. Therefore, the multilayer printed wiring board of the second present invention is characterized in that a via hole having a stack via structure is formed immediately above a through hole.
The configuration is different from the multilayer printed wiring board of the first invention.

FIG. 4 is a partial sectional view schematically showing a part of an embodiment of the second multilayer printed wiring board of the present invention. In the multilayer printed wiring board 400, through holes 109 for connecting conductor circuits sandwiching the substrate are formed, and via holes 1071 to 1073 having a stacked via structure are formed immediately above the through holes.
Further, a lid plating layer 118 is formed on the through hole 109 to form a via hole having a stacked via structure. Further, a resin filler layer 110 is formed in the through hole 109.

In the multilayer printed wiring board having such a configuration, since the via hole having the stacked via structure is formed immediately above the through hole, the wiring distance of the conductor circuit sandwiching the substrate is reduced, and the signal transmission time is reduced. Can be shortened, and the degree of freedom in designing the conductor circuit is improved.

In the multilayer printed wiring board according to the second aspect of the present invention, the land diameter of at least one of the via holes having the stacked via structure is different from the land diameter of the other via holes. Specifically, for example, the same configuration or the like as the multilayer printed wiring board of the first present invention may be used. That is, as in the multilayer printed wiring board 400 shown in FIG. 4, the land diameter of the via hole 1072 in the inner layer is larger than the land diameter of the via hole 1071 in the outermost layer, and the land portion 1072a of the via hole 1072 exists in the A region. The configuration, the land diameter of the via hole of the lowermost layer is larger than the land diameter of the via hole of the outermost layer, and the land portion of the via hole exists in the region A, the land diameter of the via hole of the inner layer, and the via hole of the outermost layer. May have a configuration in which a part of the land diameter is larger than the land diameter of the via hole of the outermost layer in a different portion of the region A.
Further, the land diameter of the via hole in the inner layer and the land diameter of the via hole in the lowermost layer may both be larger than the land diameter of the via hole in the outermost layer. The above A
The region is a region composed only of the interlayer resin insulating layer near the via hole.In the second aspect of the present invention, 1) a lower region between the outermost via hole and a conductor circuit adjacent thereto, Or, 2) means a narrower area of the upper area between the conductor circuit and the through hole, assuming that the conductor circuit adjacent to the outermost via hole is translated to the same level as the through hole. In the multilayer printed wiring board illustrated in FIG. 4, the area 2) is the area A.

In the case where the via hole has such a structure, the via hole having a large land diameter functions as a reinforcing material for the interlayer resin insulating layer, similarly to the multilayer printed wiring board of the first invention. In addition, the mechanical strength of the interlayer resin insulating layer is improved, and cracks are less likely to occur particularly in the interlayer resin insulating layer near the via hole. This means that the land portion of the via hole exists in a part of a region (region A in FIG. 4) below the conductor circuit non-formed portion between the outermost via hole and the conductor circuit adjacent thereto, This is because this portion functions as a reinforcing material for the interlayer resin insulating layer. In the multilayer printed wiring board according to the second aspect of the present invention, the number of via holes having a stacked via structure is not particularly limited as long as it is two or more. There may be
Two or four or more layers may be used. Further, the land diameter of the via hole is such that at least one land portion is present in at least a half region of the region A on the via hole side, as in the multilayer printed wiring board of the first invention. It is more preferable that the length be such that at least one land portion penetrating through the region A exists.

In the multilayer printed wiring board according to the second aspect of the present invention, since the via holes are formed so as to have a stacked via structure, the shape of the lower via holes is preferably a field via shape.

In the multilayer printed wiring board according to the second aspect of the present invention, a via hole having a stacked via structure is formed immediately above the through hole, so that a multilayer printed wiring board having more excellent connection reliability is formed. It is desirable that a lid plating layer is formed in the hole. The lid plating layer is
This is because the surface is flat and suitable for forming a via hole. Further, the lid plating layer has
It may be composed of layers, or may be composed of two or more layers. It is desirable that a resin filler layer is formed in the through hole. This is because filling the through holes with a resin filler is suitable for forming the cover plating layer.

Next, a method of manufacturing the multilayer printed wiring board according to the second embodiment of the present invention will be described. The multilayer printed wiring board according to the second aspect of the present invention is different from the multilayer printed wiring board according to the first aspect in that, as described above, a via hole having a stacked via structure is formed immediately above the through hole.
The configuration is different. Therefore, the multilayer printed wiring board of the second present invention can be manufactured by the same method as the method of manufacturing the multilayer printed wiring board of the first present invention, except that a via hole is formed immediately above a through hole. it can.

More specifically, for example, in the steps (1) and (2) of the method for manufacturing the multilayer printed wiring board of the first invention, through holes are formed to connect conductor circuits sandwiching the substrate. Further, if necessary, after forming a resin filler layer and performing a roughening treatment on the surface of the conductor circuit, a lid plating layer is formed on the through-hole, and the multilayer printed wiring board of the first present invention is formed. In the step (4) of the manufacturing method, the multilayer printed wiring board according to the first aspect of the present invention is manufactured except that the opening for the via hole is formed on the cover plating layer when the opening for the via hole is formed. It can be manufactured by the same method as the above method.

The cover plating layer can be formed, for example, through the following steps (a) to (c). (A) After forming a through hole in a substrate and forming a resin filler layer in the through hole, the surface of the substrate including the exposed surface of the resin filler layer is subjected to electroless plating, sputtering, or the like. To form a thin film conductor layer. When using electroless plating, a catalyst is previously applied to the surface to be plated. (B) Next, a plating resist is formed on portions other than the through holes (including the resin filler layer), and electrolytic plating is performed using the thin film conductor layer as a plating lead. (C) Next, after the completion of the electrolytic plating, the lid plating layer composed of the thin film conductor layer and the electrolytic plating layer is formed by removing the plating resist and removing the thin film conductor layer under the plating resist. Can be. The steps (a) to (c), from the application of the catalyst to the removal of the thin film conductor layer, are performed in the steps (6) to (6) of the multilayer printed wiring board of the first invention.
It can be performed using the same method as (8).

In the case of forming a lid plating layer consisting of one layer, for example, after applying a catalyst to the surface of the substrate including the exposed surface of the resin filler layer, a plating resist is applied to portions other than on the through holes. After that, an electroless plating process and a removal of the plating resist may be performed.

Next, the multilayer printed wiring board according to the third embodiment of the present invention will be described. The multilayer printed wiring board according to the third aspect of the present invention, on a substrate, a conductor circuit and an interlayer resin insulation layer are sequentially laminated, and the conductor circuits sandwiching the interlayer resin insulation layer are connected via via holes, A multilayer printed wiring board in which a conductive circuit sandwiching a substrate and an interlayer resin insulating layer is connected via a through hole, and a via hole having a stack via structure is formed immediately above the through hole. At least one of the via holes having the stacked via structure has a land diameter different from that of the other via holes. Therefore, the multilayer printed wiring board according to the third aspect of the present invention is different from the multilayer printed wiring board in that a via hole having a stack via structure is formed immediately above a through hole connecting between a substrate and a conductor circuit sandwiching an interlayer resin insulating layer. The structure is different from that of the multilayer printed wiring board of the present invention.

FIG. 5 is a partial sectional view schematically showing a part of an embodiment of the third multilayer printed wiring board of the present invention. In the multilayer printed wiring board 500, a through hole 109 for connecting between a substrate and a conductor circuit sandwiching an interlayer resin insulating layer is formed, and via holes 1071 to 107 having a stacked via structure are provided immediately above the through holes.
2 are formed. Further, in order to form a via hole having a stacked via structure,
A cover plating layer 118 is formed. Further, a resin filler layer 110 is formed in the through hole 109.

In the multilayer printed wiring board having such a structure, since the via hole having the stacked via structure is formed immediately above the through hole, the wiring distance of the conductor circuit sandwiching the substrate and the interlayer resin insulating layer is short. In addition, the signal transmission time can be shortened, and the degree of freedom in designing the conductor circuit is improved.

In the multilayer printed wiring board according to the third aspect of the present invention, at least one of the via holes having the stacked via structure has a land diameter different from that of the other via holes. Specifically, for example, as in a multilayer printed wiring board 500 shown in FIG. 5, the land diameter of the inner-layer via hole 1072 is smaller than the outer-layer via hole 107.
1 is larger than the land diameter, and the via hole 10
For example, a configuration in which 72 land portions 1072a are present is exemplified.

The multilayer printed wiring board 50 shown in FIG.
In the multilayer printed wiring board according to the third aspect of the present invention, three or more via holes may be formed in a stacked via structure, or a three-layer via hole may be formed. Is formed in a stacked via structure, for example, may have a configuration similar to that of the multilayer printed wiring board of the first present invention. That is, the land diameter of the via hole of the inner layer is larger than the land diameter of the via hole of the outermost layer, and the land portion of the via hole exists in the region A, or the land diameter of the via hole of the lowermost layer is the via hole of the outermost layer. The land diameter of the inner-layer via hole and the land diameter of the outer-layer via hole are partly larger than the land diameter of the outer-layer via hole at different portions of the region A. I just need. Further, the land diameter of the via hole in the inner layer and the land diameter of the via hole in the lowermost layer may both be larger than the land diameter of the via hole in the outermost layer. The region A is a region composed only of the interlayer resin insulating layer near the via hole, and has the same meaning as the region A in the multilayer printed wiring board according to the second aspect of the present invention.

In the case where the via hole has such a structure, the via hole having a large land diameter functions as a reinforcing material for the interlayer resin insulating layer, similarly to the multilayer printed wiring board of the first invention. In addition, the mechanical strength of the interlayer resin insulating layer is improved, and cracks are less likely to occur particularly in the interlayer resin insulating layer near the via hole. This means that the land portion of the via hole exists in a part of a region (A region in FIG. 5) below the portion where the conductor circuit is not formed between the outermost via hole and the conductor circuit adjacent thereto. This is because this portion functions as a reinforcing material for the interlayer resin insulating layer. In the multilayer printed wiring board of the third aspect of the present invention, the number of via holes having a stacked via structure is not particularly limited as long as it is two or more. Or three or more layers. Further, the land diameter of the via hole is such that at least one land portion is present in at least a half region of the region A on the via hole side, as in the multilayer printed wiring board of the first invention. It is more preferable that the length be such that at least one land portion penetrating through the region A exists.

In the multilayer printed wiring board according to the third aspect of the present invention, since the via holes are formed so as to have a stacked via structure, the shape of the lower via holes is preferably a field via shape.

In the multilayer printed wiring board according to the third aspect of the present invention, a via hole having a stacked via structure is formed immediately above the through hole, so that a multilayer printed wiring board having more excellent connection reliability is formed. It is desirable that a lid plating layer is formed in the hole. The lid plating layer is
This is because the surface is flat and suitable for forming a via hole. Also, in the through hole,
It is desirable that a resin filler layer be formed. This is because filling the through holes with a resin filler is suitable for forming the cover plating layer.

Next, a method for manufacturing the multilayer printed wiring board according to the third aspect of the present invention will be described in the order of steps. (1) First, a conductor circuit is formed on a substrate in the same manner as in the step (1) of the method for manufacturing a multilayer printed wiring board according to the first invention. Further, the multilayer printed wiring board according to the third aspect of the present invention has a through hole for connecting between the substrate and the conductor circuit sandwiching the interlayer resin insulating layer. In this step, it is not necessary to form a through-hole, unlike the method of manufacturing a semiconductor device. However, the multilayer printed wiring board according to the third aspect of the present invention does not exclude connecting conductor circuits sandwiching only the substrate with through holes. A through-hole for electrically connecting the circuits may be formed. After forming the conductor circuit, if necessary, a roughened surface is formed on the surface of the conductor circuit by using the same method as the step (2) of the method for manufacturing a multilayer printed wiring board according to the first aspect of the present invention. May be.

(2) Next, using a method similar to the steps (3) and (4) of the first method for producing a multilayer printed wiring board of the present invention, a thermosetting resin or resin An uncured resin layer made of a composite or a resin layer made of a thermoplastic resin is formed, and an opening for a via hole is formed to form an interlayer resin insulating layer. Further, after forming the interlayer resin insulating layer, a through hole penetrating the interlayer resin insulating layer and the substrate is formed. The through holes can be formed by using drilling, laser processing, or the like.

(3) Next, a roughened surface is formed on the surface of the interlayer resin insulating layer including the inner wall of the via hole opening and the inner wall of the through hole by using an acid or an oxidizing agent as necessary. The roughened surface is formed in order to enhance the adhesion between the interlayer resin insulating layer and the thin film conductor layer formed in a later step, and a sufficient adhesion is provided between the interlayer resin insulating layer and the thin film conductor layer. In the case where there is a property, it may not be formed. The acid and the oxidizing agent may be the same as those used in the step (5) of the first method for producing a multilayer printed wiring board of the present invention.

(4) Next, a thin film conductor layer is formed on the surface of the interlayer resin insulating layer provided with the opening for the via hole and on the inner wall surface of the through hole. The thin film conductor layer is formed by the same method as the method used in the step (6) of the method for manufacturing a multilayer printed wiring board of the first invention, that is, by a method such as electroless plating, sputtering, or vapor deposition. Can be formed. Also, it is desirable to form a thin film conductor layer also in the through hole and make it a through hole, and then fill the inside of the through hole with a resin filler, and then cover the resin filler on the through hole. It is desirable to form a layer. This is because forming a cover plating layer is suitable for forming a via hole having a stacked via structure immediately above.

The through-holes formed through this process are formed on both surfaces of the two-layer conductor circuit and the substrate, as well as connecting the conductor circuit sandwiching the substrate and the interlayer resin insulation layer. It may be a circuit connecting between a total of four layers of conductor circuits including two layers of conductor circuits.

(5) Next, a plating resist is formed on a part of the thin film conductor layer by using a dry film, and thereafter, electroplating is performed using the thin film conductor layer as a plating lead, and the plating resist non-formed portion is formed. To form an electrolytic plating layer. Here, an electrolytic plating layer may be formed also on the thin film conductor layer formed on the wall surface of the through hole, and the thickness of the through hole may be increased.

(6) After the formation of the electrolytic plating layer, the plating resist is peeled off, and the thin film conductor layer made of a metal existing under the plating resist is removed by etching to form an independent conductor circuit. As the etchant, an etchant similar to the etchant used in the step (8) of the method for manufacturing a multilayer printed wiring board according to the first aspect of the present invention can be used. In the conductor circuit formed here,
Conductive circuits sandwiching the substrate and the interlayer resin insulating layer are connected by through holes.

Further, a conductor circuit may be formed by using the following method instead of the methods described in the above (5) and (6). That is, after forming an electrolytic plating layer on the entire surface of the thin film conductor layer, an etching resist is formed using a dry film on a part of the electrolytic plating layer, and thereafter, an electrolytic plating layer under an etching resist non-formed portion and An independent conductor circuit may be formed by removing the thin-film conductor layer by etching and then removing the etching resist.

As described above, after the conductor circuit is formed, the through hole is filled with a resin filler, and thereafter, a lid plating layer is formed on the through hole (including the resin filler layer). Is desirable. The lid plating layer can be formed, for example, through the following steps (a) to (c). That is, (a) forming a through hole penetrating the substrate and the interlayer resin insulating layer, forming a resin filler layer in the through hole, and forming a through hole on the surface of the wiring board including the exposed surface of the resin filler layer; A thin-film conductor layer is formed by using an electroless plating process, sputtering, or the like. When using electroless plating, a catalyst is applied in advance to the surface to be plated. (B) Next, a plating resist is formed on portions other than the through holes (including the resin filler layer), and electrolytic plating is performed using the thin film conductor layer as a plating lead. (C) Then, after the completion of the electrolytic plating, the plating resist is peeled off and the thin film conductor layer under the plating resist is removed to form a lid plating layer composed of a thin film conductor layer and an electrolytic plating layer. Can be. The steps (a) to (c), from the application of the catalyst to the removal of the thin film conductor layer, are performed in the steps (6) to (6) of the multilayer printed wiring board of the first invention.
It can be performed using the same method as (8). Also,
The cover plating layer may be formed of a single layer as in the multilayer printed wiring board of the second aspect of the present invention.

(7) Thereafter, the steps (2) to (6) are repeated once or twice or more to produce a substrate having the uppermost conductive circuit formed on the interlayer resin insulating layer. How many times the above steps (2) to (6) are repeated may be appropriately selected according to the design of the multilayer printed wiring board. Here, when forming the plating resist, the plating resist is formed so that the via hole can be formed immediately above the through hole. Further, a plating resist is formed so that a via hole having a desired land diameter can be formed. That is, if a via hole having a large land diameter is formed in this layer, the width of the plating resist non-formed portion may be increased.

In forming a via hole, it is desirable that the via hole has a field via structure. Specifically, the via hole opening may be filled with electrolytic plating to form a field via structure, and a via hole having a recess is formed on the upper surface thereof, and then the recess is filled with a conductive paste to form a field via structure. A via structure may be used. Alternatively, after forming a via hole having a depression on the upper surface, the depression may be filled with a resin filler or the like, and a lid plating layer may be formed thereon to form a via hole having a flat upper surface.

When a via hole having a filled via structure is formed at the time of electrolytic plating, the same electrolytic plating as the electrolytic plating solution used in the step (7) of the first method for producing a multilayer printed wiring board of the present invention should be used. Is desirable.

(8) Next, a solder resist layer is formed by the same method as the steps (10) and (11) of the first method for manufacturing a multilayer printed wiring board of the present invention, A multilayer printed wiring board is formed by forming bumps, BGA, PGA, and the like.

[0098]

The present invention will be described in more detail below. Example 1 A. Preparation of Resin Film for Interlayer Resin Insulation Layer Bisphenol A type epoxy resin (Epoxy equivalent 46
9. Yuka Shell Epoxy Epicoat 1001) 30
Parts by weight, 40 parts by weight of a cresol novolak type epoxy resin (epoxy equivalent: 215, Epicron N-673 manufactured by Dainippon Ink and Chemicals, Inc.) Light KA-705
2) 30 parts by weight were dissolved by heating in 20 parts by weight of ethyl diglycol acetate and 20 parts by weight of solvent naphtha while stirring, and epoxidized polybutadiene rubber (Denalex R-45EPT manufactured by Nagase Kasei Kogyo Co., Ltd.) was added thereto.
15 parts by weight, 1.5 parts by weight of a crushed product of 2-phenyl-4,5-bis (hydroxymethyl) imidazole, 2 parts by weight of finely divided silica, and 0.5 part by weight of a silicon-based antifoaming agent are added, and an epoxy resin composition is added. Was prepared. The resulting epoxy resin composition is applied on a 38 μm-thick PET film using a roll coater so that the thickness after drying becomes 50 μm, and then dried at 80 to 120 ° C. for 10 minutes to form an interlayer resin. A resin film for an insulating layer was produced.

B. Preparation of resin filler 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell Co., molecular weight: 310, YL983U), the average particle diameter of which is coated with a silane coupling agent on the surface is 1.6 μm, and the diameter of the largest particle Is less than 15 μm
iO ₂ spherical particles (CRS 1101- manufactured by Adtech Co., Ltd.)
CE) 72 parts by weight and 1.5 parts by weight of a leveling agent (Perenol S4 manufactured by San Nopco Co.) are placed in a container, and the mixture is stirred and mixed to have a viscosity of 30 to 80 at 25 ± 1 ° C.
A Pa · s resin filler was prepared. In addition, as a curing agent, an imidazole curing agent (2E4MZ- manufactured by Shikoku Chemicals Co., Ltd.)
6.5 parts by weight (CN).

C. Method for manufacturing printed wiring board (1) 0.8 mm thick glass epoxy resin or BT
A starting material was a copper-clad laminate in which 18 μm copper foils 8 were laminated on both sides of a substrate 1 made of (bismaleimide triazine) resin (see FIG. 6A). First, the copper-clad laminate was drilled, subjected to an electroless plating treatment, and etched in a pattern to form a lower conductor circuit 4 and a through hole 9 on both surfaces of the substrate 1 (FIG. 6).
(B)).

(2) The substrate on which the through hole 9 and the lower conductor circuit 4 are formed is washed with water and dried,
(10 g / l), NaClO ₂ (40 g / l), Na ₃
A blackening treatment using an aqueous solution containing PO ₄ (6 g / l) as a blackening bath (oxidizing bath), NaOH (10 g / l), Na
A reduction treatment was performed using an aqueous solution containing BH ₄ (6 g / l) as a reduction bath, and a roughened surface (not shown) was formed on the entire surface of the lower conductor circuit 4 including the through holes 9.

(3) Next, after preparing the resin filler described in the above B, within 24 hours after adjustment by the following method, the inside of the through hole 9 and the portion where the conductor circuit is not formed on the substrate 1 and the lower layer Layer 1 of resin filler on outer edge of conductive circuit 4
0 'was formed. That is, first, the resin filler is pushed into the through hole using a squeegee,
Dried under the conditions of minutes. Next, a mask having an opening corresponding to the portion where the conductor circuit is not formed is placed on the substrate, and a resin filler layer 10 'is formed on the recessed portion where the conductor circuit is not formed using a squeegee. It was dried at 20 ° C. for 20 minutes (see FIG. 6C).

(4) One surface of the substrate after the treatment of the above (3) is subjected to belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.) to form the surface of the lower conductor circuit 4 and the through holes 9. Polishing was performed so that the resin filler did not remain on the land surface, and then buffing was performed to remove scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate. Next, heat treatment was performed at 100 ° C. for 1 hour and at 150 ° C. for 1 hour to form the resin filler layer 10.

In this manner, the surface layer of the resin filler layer 10 formed in the through-hole 9 and the portion where the conductor circuit is not formed and the surface of the lower conductor circuit 4 are flattened.
And an insulating substrate in which the side surface 4a of the lower conductor circuit 4 is firmly adhered through the roughened surface, and the inner wall surface 9a of the through hole 9 and the resin filler layer 10 are firmly adhered through the roughened surface. Was obtained (see FIG. 6D). That is, by this step, the surface of the resin filler layer 10 and the surface of the lower conductive circuit 4 become flush with each other.

(5) After the above substrate was washed with water and acid degreased,
The surface of the lower conductor circuit 4 and the land surface of the through hole 9 are etched by spraying an etching solution onto both surfaces of the substrate by spraying, so that the entire surface of the lower conductor circuit 4 is roughened. (Not shown). In addition, as an etching solution, an etching solution (10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride (manufactured by MEC Corporation)
Mech etch bond) was used.

(6) Next, on both sides of the substrate, a resin film for an interlayer resin insulating layer slightly larger than the substrate prepared in the above A was placed on the substrate, and the pressure was 0.4 MPa, the temperature was 80 ° C.,
After temporary cutting under the condition of a pressing time of 10 seconds and cutting, the film was further pasted by using a vacuum laminator device by the following method, and then thermally cured to form an interlayer resin insulating layer 2 (FIG. 6 (e)). reference). That is, a resin film for an interlayer resin insulation layer was placed on a substrate, and the degree of vacuum was 67 Pa,
The film was completely pressure-bonded and adhered under the conditions of a pressure of 0.4 MPa, a temperature of 80 ° C, and a pressure-bonding time of 60 seconds.

(7) Next, through a mask having a through hole having a thickness of 1.2 mm formed on the interlayer resin insulating layer 2, a CO ₂ gas laser having a wavelength of 10.4 μm is used.
7 mm, a top hat mode, a pulse width of 8.0 μs, a diameter of a through hole of the mask of 1.0 mm, and a one-shot condition. a)).

(8) Further, the substrate in which the via hole opening 6 was formed was heated at 80 ° C. containing 60 g / l of permanganic acid.
Of the interlayer resin insulating layer 2 including the inner wall of the via hole opening 6 by dissolving and removing the epoxy resin particles present on the surface of the interlayer resin insulating layer 2 for 10 minutes. Z).

(9) Next, the substrate after the above treatment was immersed in a neutralizing solution (manufactured by Shipley) and washed with water. Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate subjected to the surface roughening treatment (roughening depth: 3 μm), the catalyst is formed on the surface of the interlayer resin insulating layer 2 and the inner wall surface of the via hole opening 6. Nuclei were attached.

(10) Next, the substrate was immersed in an electroless copper plating aqueous solution having the following composition, and the thickness of the substrate was reduced to 0.6 to
A 3.0 μm thin film conductor layer 12 was formed (see FIG. 7B). [Electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α'-bipyridyl 40 mg / l Polyethylene glycol (PEG) 0.10 g / l [Electroless plating conditions] 40 minutes at a liquid temperature of 35 ° C

(11) Next, a commercially available photosensitive dry film is affixed to the thin film conductor layer 12, and a mask is placed thereon.
The plating resist 3 was provided by exposing at 00 mJ / cm ² and developing with an aqueous 0.8% sodium carbonate solution. The shape of the plating resist non-forming portion for forming a via hole, is circular plan view shape, a diameter L ₁ is 150 [mu] m (see FIG. 7 (c)).

(12) Next, the substrate was washed with water at 50 ° C., degreased, washed with water at 25 ° C., further washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions. The layer 13 was formed (see FIG. 7D). [Electrolytic plating solution] _{CuSO 4 · 5H 2 O 210g /} l sulfuric acid 150g / ^l Cl - 40mg / ^l polyethylene glycol 300 mg / l bis disulphide 100 mg / l [electrolytic plating conditions] current density 1.0A / dm ² hours 60 minutes Temperature 25 ° C

(13) Subsequently, 40 g / l Na at 50 ° C.
The plating resist 3 was peeled off in an OH aqueous solution. Thereafter, the substrate is subjected to a heat treatment at 150 ° C. for one hour,
Using an etching solution containing an aqueous solution of hydrogen peroxide, the thin film conductor layer existing under the plating resist was removed to form an independent conductor circuit and a via hole in the shape of a filled via (see FIG. 8A). Here, the land diameter of the formed via hole is 35 μm.

(14) By repeating the above steps (5) to (11), an upper interlayer resin insulation layer 2 and a thin film conductor layer 12 are further formed, and thereafter, a plating resist 3 is formed on the thin film conductor layer 12. Was provided. The shape of the portion where the plating resist is not formed for forming the via hole has a circular shape in plan view and a diameter L ₂ of 250 μm (FIG. 8).
(B)).

(15) Next, (12) and (1)
In the same manner as in step 3), electrolytic copper plating treatment, peeling and removal of the plating resist, and etching of the thin film conductor layer were performed to form an independent conductor circuit and a via hole having a filled via shape (FIG. 8). (C)-(FIG. 9
(A)). The land diameter of the via hole formed here is 85 μm.

(16) By repeating the above steps (5) to (11), an upper interlayer resin insulating layer 2 and a thin film conductor layer 12 are further formed. A resist 3 was provided. The shape of the portion where the plating resist is not formed for forming the via hole has a circular shape in plan view and a diameter of 150 μm. Subsequently, the substrate was washed with water at 50 ° C. and degreased.
After washing with water at ℃, and further washing with sulfuric acid, electrolytic plating is performed under the following conditions, and the plating resist 3 non-formed portion is
An electrolytic copper plating film 13 was formed (see FIGS. 9B to 9C). [Electroplating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive 19.5 ml / l (Atotech Japan, Capparaside GL) [Electroplating conditions] Current density 1 A / dm ² hours 65 minutes Temperature 22 ± 2 ℃

(17) Next, in the same manner as in the step (13), the plating resist 3 was peeled off and the thin film conductor layer was etched to form independent conductor circuits and via holes. The via hole formed in this step has a land diameter of 35 μm and a concave upper surface. The distance between the via hole formed in this step and the adjacent conductor circuit is 50 μm (FIG. 10).
(A)).

(18) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight was used. Oligomer for imparting properties (molecular weight: 4000) 46.6
7 parts by weight, 80% by weight dissolved in methyl ethyl ketone
Of bisphenol A type epoxy resin (manufactured by Yuka Shell Co., Ltd.
Trade name: Epicoat 1001) 15.0 parts by weight, imidazole hardener (manufactured by Shikoku Chemicals, trade name: 2E4MZ-C)
N) 1.6 parts by weight, 3.0 parts by weight of a polyacrylic monomer (trade name: R604, manufactured by Nippon Kayaku Co., Ltd.), which is a photosensitive monomer, and polyvalent acrylic monomer (trade name: DPE6A, manufactured by Kyoei Chemical Co., Ltd.) ) 1.5 parts by weight, 0.71 part by weight of a dispersion defoaming agent (manufactured by San Nopco, S-65) in a container,
A mixed composition was prepared by stirring and mixing, and 2.0 parts by weight of benzophenone (manufactured by Kanto Kagaku) as a photopolymerization initiator and Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to the mixed composition. By adding 0.2 parts by weight, a solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C. was obtained. The viscosity was measured using a B-type viscometer (manufactured by Tokyo Keiki Co., Ltd., D
VL-B type, 60 min ^-1 (rpm), the rotor No. Rotor N for 4, 6 min ^-1 (rpm)
o. According to 3.

(19) Next, the above-mentioned solder resist composition is applied to both sides of the multilayer wiring board in a thickness of 20 μm.
After performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the thickness 5 on which the pattern of the solder pad is drawn is 5
The mm photomask is brought into close contact to the solder resist layer was exposed to ultraviolet rays of 1000 mJ / cm ^2, and developed with DMTG solution to form openings with a diameter of 80 [mu] m. Then, at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, 12
Heat treatment was performed at 0 ° C. for 1 hour and at 150 ° C. for 3 hours to cure the solder resist layer, thereby forming a solder resist layer 14 having an opening for forming a solder bump and having a thickness of 20 μm.

(20) Next, sodium persulfate is used as a main component.
Resist layer 14 is formed in the etching solution
Immersed substrate for 1 minute, and average roughness on conductor circuit surface
(Ra) forms a roughened surface (not shown) of 1 μm or less
Was. Further, this substrate was coated with nickel chloride (2.3 × 10
^-1mol / l), sodium hypophosphite (2.8 × 10
^-1mol / l), sodium citrate (1.6 × 10 ^-1
mol / l) and pH = 4.5
Immersion for 20 minutes in the cleaning solution, and a 5 μm thick nickel
A plating layer 15 was formed. In addition, the substrate is
Potassium gold iodide (7.6 × 10^-3mol / l), ammonium chloride
Monium (1.9 × 10^-1mol / l), sodium citrate
Li (1.2 × 10^-1mol / l), sodium hypophosphite
Li (1.7 × 10^-1mol / l)
Immerse in a plating solution at 80 ° C for 7.5 minutes,
A gold plating layer 16 having a thickness of 0.03 μm is formed on the plating layer 15.
Was formed to form a solder pad.

(21) Thereafter, the solder resist layer 14
A mask was placed on the top, and solder paste was printed on the openings for forming the solder bumps using a piston press-fit printing machine.
Thereafter, the solder paste was reflowed at 250 ° C., and further, flux cleaning was performed to obtain a multilayer printed wiring board provided with solder bumps (see FIG. 10B).

(Example 2) After the steps of Examples (1) to (4), a cover plating layer was formed on the through-holes (including the resin filler layer) by the following method. )), A multilayer printed wiring board was manufactured in the same manner as in Example 1 except that an opening for a via hole was formed on the cover plating layer.

[Formation of Cover Plating Layer] A resin filler layer is formed in the through hole and in the portion where the conductor circuit is not formed, and the surface of the conductor circuit (including the land portion of the through hole) and the surface of the resin filler layer are the same. After flattening, first, a catalyst nucleus was attached to the surface of the conductor circuit and the surface of the resin filler layer by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate.

Next, the substrate was immersed in an electroless copper plating aqueous solution having the same composition as the electroless plating solution used in the step (10) of Example 1, and a thickness of 0.6 to 3 was applied to the entire surface. 0.0 μm
Was formed.

Next, using a commercially available photosensitive dry film, a plating resist was formed on portions other than those on the through holes. Further, the substrate is washed with water at 50 ° C. and degreased.
After washing with water at 5 ° C. and further washing with sulfuric acid, electrolytic copper plating was performed under the following conditions to form an electrolytic copper plating layer on the through holes. [Electroplating solution] sulfuric acid 2.24 mol / l copper sulfate 0.26 mol / l additive 19.5 ml / l (manufactured by Atotech Japan, Capparaside GL) [electroplating conditions] current density 1 A / dm ² hours 65 minutes Temperature 22 + 2 ° C

Further, the plating resist was peeled off in a 40 g / l NaOH aqueous solution at 50 ° C., and then the thin film conductor layer existing under the plating resist was removed using an etching solution containing a sulfuric acid-hydrogen peroxide aqueous solution. A cover plating layer was formed.

(Example 3) In steps (6) and (7) of Example 1, except that an interlayer resin insulating layer having a via hole opening was formed using the following method.
A multilayer printed wiring board was manufactured in the same manner as in Example 1.
That is, after passing through the steps (1) to (5) of Example 1, the photosensitive resin composition B (viscosity: 1.5 Pa · s) was prepared, and then 24
Apply using a roll coater within 2 hours
After leaving for 0 minutes, drying (prebaking) was performed at 60 ° C. for 30 minutes. Next, the photosensitive resin composition A (viscosity:
7Pa · s) is applied using a roll coater within 24 hours after preparation, and left in a horizontal state for 20 minutes in the same manner.
Drying (prebaking) was performed at 60 ° C. for 30 minutes to form a two-layer semi-cured resin layer.

Next, a substrate having a resin layer in a semi-cured state is formed.
Photomask with black circle of 80μm diameter printed on both sides of
500mJ with an ultra-high pressure mercury lamp
/ Cm ^Two And then spray with DMDG solution
Developed. After that, the substrate was further converted to an ultra-high pressure mercury lamp.
3000mJ / cm^Two Exposure at 100 ° C
Heat treatment for 1 hour, 120 ° C for 1 hour, 150 for 3 hours
With excellent dimensional accuracy equivalent to a photomask film
Interlaminar tree having a via hole opening with a diameter of 80 μm
A fat insulating layer was formed.

The photosensitive resin compositions A and B were prepared by the following method. [Preparation of Photosensitive Resin Composition A] (i) A 25% acrylate of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight: 2500) was dissolved in diethylene glycol dimethyl ether (DMDG) at a concentration of 80% by weight. 35 parts by weight of resin liquid, photosensitive monomer (Aronix M315, manufactured by Toagosei Co., Ltd.) 3.1
5 parts by weight, antifoaming agent (S-65, manufactured by San Nopco) 0.5
Parts by weight and 3.6 parts by weight of N-methylpyrrolidone (NMP) were placed in a container and mixed by stirring to prepare a mixed composition.

(Ii) Polyether sulfone (PES) 1
2 parts by weight, 7.2 parts by weight of an epoxy resin particle (manufactured by Sanyo Kasei Co., polymer pole) having an average particle diameter of 1.0 μm and 3.09 parts by weight of an epoxy resin particle having an average particle diameter of 0.5 μm were placed in another container, After stirring and mixing, 30 parts by weight of NMP was further added and stirred and mixed with a bead mill to prepare another mixed composition.

(Iii) 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), a photopolymerization initiator (Irgacure, manufactured by Ciba Specialty Chemicals)
I-907) 2 parts by weight, photosensitizer (manufactured by Nippon Kayaku Co., Ltd., DE
TX-S) 0.2 part by weight and 1.5 parts by weight of NMP were further placed in another container, and mixed by stirring to prepare a mixed composition. Then, a photosensitive resin composition was obtained by mixing the mixed compositions prepared in (i), (ii) and (iii).

[Preparation of Photosensitive Resin Composition B] (i) A 25% acrylate of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight: 2500) was added to diethylene glycol dimethyl ether (DMDG) at a concentration of 80% by weight. 35 parts by weight of the dissolved resin solution, 4 parts by weight of a photosensitive monomer (manufactured by Toagosei Co., Aronix M315), 0.5 parts by weight of an antifoaming agent (S-65 manufactured by Sannopco) and N-methylpyrrolidone (NMP) 3 A mixed composition was prepared by placing 0.6 parts by weight in a container and mixing with stirring.

(Ii) Polyether sulfone (PES) 1
2 parts by weight and epoxy resin particles (manufactured by Sanyo Chemical Industries,
14.4 having an average particle size of 0.5 μm
9 parts by weight were placed in another container and mixed with stirring.
30 parts by weight of MP was added and mixed by stirring with a bead mill to prepare another mixed composition.

(Iii) 2 parts by weight of an imidazole curing agent (2E4MZ-CN manufactured by Shikoku Chemicals), a photopolymerization initiator (Irgacure manufactured by Ciba Specialty Chemicals)
I-907) 2 parts by weight, photosensitizer (manufactured by Nippon Kayaku Co., Ltd., DE
TX-S) 0.2 part by weight and 1.5 parts by weight of NMP were further placed in another container, and mixed by stirring to prepare a mixed composition. Then, a photosensitive resin composition was obtained by mixing the mixed compositions prepared in (i), (ii) and (iii).

(Example 4) In the same manner as in Example 1, production of a resin film for an interlayer resin insulating layer and preparation of a resin filler were performed.

B. Production of multilayer printed wiring board (1) Glass epoxy resin or BT with a thickness of 0.8 mm
18 μm copper foil 2 on both sides of insulating substrate 21 made of resin
A copper-clad laminate on which No. 8 was laminated was used as a starting material (see FIG. 11A). First, the copper-clad laminate was etched into a lower-layer conductor circuit pattern to form lower-layer conductor circuits 24 on both surfaces of the substrate (see FIG. 11B).

(2) The substrate 2 on which the lower conductor circuit 24 is formed
1 was washed with water and dried, then NaOH (10 g / l),
NaClO ₂ (40 g / l), Na ₃ PO ₄ (6 g / l)
a blackening treatment using an aqueous solution containing l) as a blackening bath (oxidizing bath);
And NaOH (10 g / l), NaBH ₄ (6 g / l
A reduction treatment using an aqueous solution containing 1) as a reduction bath was performed to form a roughened surface (not shown) on the surface of the lower conductor circuit 24.

(3) Next, the resin film for an interlayer resin insulating layer prepared in the above A was laminated by vacuum compression bonding at 0.5 MPa while heating to a temperature of 50 to 150 ° C. 22 was formed (see FIG. 11C). Further, the substrate 21 on which the interlayer resin insulation layer 22 is formed
Then, a through hole 39 having a diameter of 300 μm was formed by drilling.

(4) Next, a mask having a through hole having a thickness of 1.2 mm is placed on the interlayer resin insulating layer 22, and the beam diameter is adjusted to 4.0 using a CO ₂ gas laser having a wavelength of 10.4 μm.
mm, top hat mode, pulse width 8.0 μs, mask through-hole diameter 1.0 mm, via hole opening 2 with 80 μm diameter in interlayer resin insulation layer 22 under the condition of one shot.
No. 6 was formed (see FIG. 11D).

(5) Next, the substrate in which the via hole opening 26 was formed was heated at 80 ° C. containing 60 g / l of permanganate.
Of the via hole opening 26 by subjecting the wall surface of the through hole 39 to desmear treatment and dissolving and removing the epoxy resin particles present on the surface of the interlayer resin insulating layer 22 for 10 minutes. A roughened surface (not shown) was formed on the surface.

(6) Next, the substrate after the above treatment was immersed in a neutralizing solution (manufactured by Shipley) and washed with water. Further, by applying a palladium catalyst to the surface of the substrate that has been subjected to the surface roughening treatment (roughening depth: 3 μm), the surface of the interlayer resin insulating layer 22 (including the inner wall surface of the via hole opening 26), and A catalyst nucleus was attached to the wall surface of the through hole 39 (not shown). That is, palladium chloride (Pb)
The catalyst was applied by immersion in a catalyst solution containing Cl ₂ ) and stannous chloride (SnCl ₂ ) to precipitate palladium metal.

(7) Next, the substrate is immersed in an electroless copper plating aqueous solution at 34 ° C. for 40 minutes, and the surface of the interlayer resin insulating layer 22 (including the inner wall surface of the via hole opening 26) and the through hole A thin film conductor layer 32 having a thickness of 0.6 to 3.0 μm was formed on the wall surface of the substrate 39 (see FIG. 11E). In addition, as the electroless copper plating aqueous solution, the same aqueous solution as the electroless copper plating aqueous solution used in the step (10) of Example 1 was used.

(8) Next, a commercially available photosensitive dry film is adhered to the substrate on which the thin film conductor layer 32 is formed, a mask is placed, and exposure is performed at 100 mJ / cm ² , and a 0.8% aqueous solution of sodium carbonate is applied. Then, a plating resist 23 was provided (see FIG. 12A).

(9) Next, the substrate was washed with water at 50 ° C., degreased, washed with water at 25 ° C., further washed with sulfuric acid, and then subjected to the same conditions as in the step (12) of Example 1. Then, an electrolytic copper plating film 33 was formed in a portion where the plating resist 23 was not formed (see FIG. 12B).

(10) Further, the plating resist 23 is
After stripping and removal with% KOH, the electroless plating film under the plating resist 23 is etched using an etching solution containing sulfuric acid and hydrogen peroxide to form a through hole 29 and a conductor circuit 25 (including a via hole 27). ).

(11) Next, the substrate 30 on which the through holes 29 and the like are formed is immersed in an etching solution,
9 and conductor circuit 25 (including via hole 27)
A roughened surface (not shown) was formed on the surface of. As an etching solution, Mech etch bond manufactured by Mec Co. was used.

(12) Next, after preparing the resin filler described in the above A, within 24 hours after the preparation by the following method, the inside of the through hole 29 and the interlayer resin insulation layer 22 are prepared.
A resin filler layer was formed on the upper part of the conductor circuit non-formed portion and the outer edge of the conductor circuit 25. That is, first, the resin filler is pushed into the through hole using a squeegee,
It was dried at 20 ° C. for 20 minutes. Next, using a mask and a squeegee having an opening in a portion corresponding to the conductor circuit non-forming portion, a resin filler layer is formed in the conductor circuit non-forming portion having a concave portion, and the conditions are set at 100 ° C. for 20 minutes. Let dry.

Subsequently, in the same manner as in the step (4) of the first embodiment, the surface of the through-hole 29 and the resin filler layer 30 formed in the non-conductor-circuit-forming portion and the surface of the conductor circuit 25 are flattened. The surface of the resin filler layer 30 and the surface of the conductive circuit 25 were made the same plane (see FIG. 12C).

(13) Next, on the surface of the interlayer resin insulating layer 22 and the exposed surface of the resin filler layer 30,
A palladium catalyst (not shown) was applied by performing the same treatment as described above. Next, electroless plating was performed under the same conditions as in (7) above to form a thin film conductor layer 32 on the exposed surface of the resin filler layer 30 and on the upper surface of the conductor circuit 25.

(14) Next, a plating resist 23 was provided on the thin-film conductor layer 32 by using the same method as in (8) (see FIG. 12D). Subsequently, the substrate was washed with water at 50 ° C., degreased, washed with water at 25 ° C., further washed with sulfuric acid, and then subjected to electrolytic plating under the following conditions. A copper plating film 33 was formed (see FIG. 13A). [Electroplating solution] sulfuric acid 2.24 mol / l copper sulfate 0.26 mol / l additive 19.5 ml / l (manufactured by Atotech Japan, Capparaside GL) [electroplating conditions] current density 1 A / dm ² hours 65 minutes Temperature 22 + 2 ° C

(15) Next, 5% of plating resist 33
After stripping off with KOH, the electroless plating film under the plating resist 33 was dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to form a cover plating layer 31 (FIG. 1).
3 (b)). (16) Next, a roughened surface (not shown) was formed on the surface of the lid plating layer 31 using an etching solution (MEC etch bond).

(17) Next, the above steps (3) to (11) are repeated twice to further form the upper interlayer resin insulation layer 22 and the conductor circuit 25 (including the via hole 27) ( 13 (c) to 16 (a)). In this step, no through hole was formed. In the plating resist formed here, the portion of the plating resist non-formed portion for forming the via hole has a circular shape in plan view and a diameter of 250 μm. The formed via hole has a land diameter of 8
5 μm, which is a field via shape.

(18) The steps (3) to (11) are repeated again, except that the electrolytic plating is performed under the following conditions, whereby the upper interlayer resin insulation layer 22 and the conductor circuit 25 ( (Including via holes 27) to obtain a multilayer wiring board (see FIG. 16B). In addition,
In this step, no through hole was formed.

[Electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive 19.5 ml / l (Capparaside GL, manufactured by Atotech Japan) [Electroplating conditions] Current density 1 A / dm ² hours 65 minutes Temperature 22 ± 2 ℃

In the plating resist formed here, the portion of the plating resist non-formed portion for forming a via hole has a circular shape in plan view and a diameter of 1 mm.
50 μm. The formed via hole has a land diameter of 35 μm and has a shape having a depression on the upper surface. The distance between the via hole formed here and the adjacent conductor circuit is 50 μm.

(19) Next, (18) to (2) of the first embodiment
A multilayer printed wiring board provided with solder bumps was obtained in the same manner as in the step 1) (see FIG. 17).

(Embodiment 5) In the step (17) of the embodiment 4, the steps (3) to (11) are repeated twice.
In the fourth repetition step, multilayer printing was performed in the same manner as in Example 4 except that the shape of the portion where the plating resist was not formed for forming the via hole was circular in plan view and the diameter was 150 μm. A wiring board was manufactured. As a result, the land diameter of the lowermost via hole of the via holes formed in the stacked via structure is 85 μm.
m, the land diameter of the via hole between the inner layer and the outermost layer is 35
A μm multilayer printed wiring board (see FIG. 18A) was obtained.

(Embodiment 6) In the first repetition step when the steps (3) to (11) of the step (17) of the embodiment 4 are repeated twice, a plating resist for forming a via hole is not used. The formed part has a 200 μm diameter in plan view.
m, the via hole has a maximum land diameter of 85 μm, and in the second repetition step, the plating resist non-formed portion for forming the via hole has a planar shape of 200 μm in diameter. Except that it is circular and the via hole has a maximum land diameter of 85 μm, and the direction having the maximum land diameter is opposite to the direction having the maximum land diameter formed in the first repetition step. Manufactured a multilayer printed wiring board in the same manner as in Example 4.

As a result, the via hole land diameter between the lowermost layer and the inner layer of the via holes formed in the stacked via structure has a maximum land diameter of 85 μm and a minimum land diameter of 35 μm.
A multilayer printed wiring board (see FIG. 18 (b)) in which the direction having the maximum land diameter of μm is opposite to the direction of the via hole of the lowermost layer and that of the inner layer is opposite to each other.

(Comparative Example 1) A multilayer printed wiring board was manufactured in the same manner as in Example 2 except that all land diameters of via holes having a stacked via structure were 35 μm.

(Comparative Example 2) A multilayer printed wiring board was manufactured in the same manner as in Example 4 except that all land diameters of via holes having a stacked via structure were 35 μm.

With respect to the multilayer printed wiring boards obtained in Examples 1 to 6 and Comparative Examples 1 and 2, the cross-sectional shape of a via hole having a stack via structure before and after the heat cycle test was observed, and a conduction test was performed.

[0163]Evaluation method  (1) Heat cycle test A cycle of leaving at -65 ° C for 3 minutes and 130 ° C for 3 minutes
The cycle was repeated 1000 cycles. (2) Continuity test After manufacturing a multilayer printed wiring board, the heat cycle
Conduct a continuity test using a checker before and after the test and monitor
The conduction state was evaluated from the results indicated in the above.

(3) Observation of Shape After the multilayer printed wiring board was manufactured, before and after the heat cycle test, the multilayer printed wiring board was cut through a via hole having a stack via structure, and the cross section was magnified by 100 to 400. Observed using an optical microscope at a magnification of x.

As a result, in the multilayer printed wiring boards of Examples 1 to 6, no short circuit or disconnection occurred before and after the heat cycle test, and the conduction state was good. In the observation of the cross-sectional shape, no crack was generated in the interlayer resin insulating layer, and no peeling was generated between the interlayer resin insulating layer and the via hole.

On the other hand, in the multilayer printed wiring boards of Comparative Examples 1 and 2, after the heat cycle test, a conduction failure due to a short circuit or disconnection occurred. In the cross-sectional shape observation, after the heat cycle test, cracks occurred in the region below the conductor circuit non-forming region between the outermost via hole and the conductor circuit adjacent thereto, and the interlayer resin insulating layer And the via hole was peeled off.

[0167]

As described above, in the first to third multilayer printed wiring boards of the present invention, the via holes of different levels are formed so as to have a stacked via structure, so that the wiring of the conductor circuit is formed. The distance can be shortened, the signal transmission time can be shortened, and the degree of freedom in designing the conductor circuit is improved. Also,
In the multilayer printed wiring board, at least one of the via holes having different levels has a land diameter different from the land diameters of the other via holes, so that the via hole having a large land diameter is a reinforcing material for the interlayer resin insulating layer. As a result, the mechanical strength of the interlayer resin insulating layer is improved, and the occurrence of cracks in the interlayer resin insulating layer near the via hole can be avoided. Also, in the second and third multilayer printed wiring boards, via holes having a stacked via structure are formed on the through holes, so that the signal transmission time can be further reduced, and
It is easy to cope with high-density wiring.

[Brief description of the drawings]

FIG. 1A is a partial cross-sectional view schematically illustrating a part of an embodiment of a multilayer printed wiring board according to the first aspect of the present invention;
(B) is a perspective view schematically showing via holes of the multilayer printed wiring board shown in (a).

FIG. 2A is a partial cross-sectional view schematically showing a part of an embodiment of the first multilayer printed wiring board of the present invention;
(B) is a perspective view schematically showing via holes of the multilayer printed wiring board shown in (a).

FIG. 3A is a partial cross-sectional view schematically illustrating a part of an embodiment of the multilayer printed wiring board according to the first aspect of the present invention;
(B) is a perspective view schematically showing via holes of the multilayer printed wiring board shown in (a).

FIG. 4 is a partial sectional view schematically showing a part of an embodiment of the multilayer printed wiring board of the second invention.

FIG. 5 is a partial cross-sectional view schematically showing a part of an embodiment of the third multilayer printed wiring board of the present invention.

FIGS. 6A to 6E are cross-sectional views schematically showing a part of a process for manufacturing a multilayer printed wiring board according to the present invention.

FIGS. 7A to 7D are cross-sectional views schematically showing a part of a process of manufacturing the multilayer printed wiring board of the present invention.

FIGS. 8A to 8C are cross-sectional views schematically showing a part of a process for manufacturing a multilayer printed wiring board according to the present invention.

FIGS. 9A to 9C are cross-sectional views schematically showing a part of a process of manufacturing the multilayer printed wiring board of the present invention.

FIGS. 10A and 10B are cross-sectional views schematically showing a part of a process for manufacturing a multilayer printed wiring board according to the present invention.

FIGS. 11A to 11E are cross-sectional views schematically showing a part of a process of manufacturing the multilayer printed wiring board of the present invention.

FIGS. 12A to 12D are cross-sectional views schematically showing a part of a process of manufacturing a multilayer printed wiring board according to the present invention.

FIGS. 13A to 13D are cross-sectional views schematically showing a part of a process of manufacturing the multilayer printed wiring board of the present invention.

FIGS. 14A to 14C are cross-sectional views schematically showing a part of a process for manufacturing a multilayer printed wiring board according to the present invention.

FIGS. 15A to 15C are cross-sectional views schematically showing a part of a process of manufacturing a multilayer printed wiring board according to the present invention.

FIGS. 16A and 16B are cross-sectional views schematically showing a part of a process of manufacturing a multilayer printed wiring board according to the present invention.

FIG. 17 (a) is a cross-sectional view schematically showing a part of a step of manufacturing the multilayer printed wiring board of the present invention.

FIGS. 18 (a) and (b) are cross-sectional views schematically showing one example of the multilayer printed wiring board of the present invention.

19A is a cross-sectional view schematically illustrating an example of a conventional multilayer printed wiring board, and FIG. 19B is a schematic view illustrating a via hole of the multilayer printed wiring board illustrated in FIG. It is a perspective view.

[Explanation of symbols]

 1, 21 Substrate 8, 28 Copper foil 4, 24 Lower conductor circuit 9, 29 Through hole 6, 26 Via hole opening 12, 32 Thin film conductor layer 3, 23 Plating resist 13, 33 Electroplating film 2, 22 Interlayer resin insulation Layer 10, 30 Resin filler 31 Lid plating layer 14, 30 Solder resist layer 17, 37 Solder bump

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Daisuke Ikeda 1-1, Ibikawa-cho, Ibi-gun, Gifu Prefecture F-term in Ogaki-Kita Plant (reference) 5E346 AA02 AA06 AA12 AA15 AA43 CC02 CC08 CC09 CC10 CC12 CC13 CC14 CC32 CC37 CC52 CC57 DD02 DD03 DD16 DD17 DD25 DD32 DD44 EE33 EE35 EE38 FF03 FF04 FF07 FF10 FF15 GG15 GG17 GG18 GG22 GG23 GG27 HH05 HH11 HH25

Claims (4)

[Claims] 1. A multilayer printed wiring board in which a conductor circuit and an interlayer resin insulation layer are sequentially laminated on a substrate, and the conductor circuits sandwiching the interlayer resin insulation layer are connected via via holes. Among the via holes, via holes of different levels are formed so as to have a stacked via structure, and at least one of the via holes of different levels has a land diameter of a land of another via hole. A multilayer printed wiring board characterized by having a different diameter. 2. A conductive circuit and an interlayer resin insulating layer are sequentially laminated on a substrate, the conductive circuits sandwiching the interlayer resin insulating layer are connected via via holes, and the conductive circuits sandwiching the substrate are sandwiched. Is a multilayer printed wiring board connected via a through hole, wherein a via hole having a stacked via structure is formed immediately above the through hole, and at least one of the via holes having the stacked via structure is formed. One is a multilayer printed wiring board characterized in that the land diameter is different from the land diameters of other via holes. 3. A conductive circuit and an interlayer resin insulation layer are sequentially laminated on a substrate, and the conductor circuits sandwiching the interlayer resin insulation layer are connected via via holes. A multilayer printed wiring board in which conductor circuits sandwiched therebetween are connected via through holes, wherein via holes having a stacked via structure are formed immediately above the through holes, and via holes having the stacked via structure are provided. At least one of the multi-layer printed wiring boards has a land diameter different from that of another via hole. 4. At least one of said via holes
First, the shape is a field via shape.
3. The multilayer printed wiring board according to any one of 3.