JP2002204075A - Method of manufacturing multilayer printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer printed wiring board having coaxial-structured through-holes having a high reliability. SOLUTION: Using a drill, inner layer through-holes 62 and outer layer through-holes 36 are formed. Use of the drill prevents the through-hole from tapering and makes uniform the thickness of an outer layer resin filler 42 forming an insulation layer between the outer and inner layer through-holes 62, 63. Thus, the short circuit between the outer and inner layer through-holes can be prevented to improve the reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board whose front and back surfaces are electrically connected via through holes, and more particularly, to a multilayer printed circuit formed by alternately building up a resin insulating layer and a conductive circuit layer. The present invention relates to a method for manufacturing a multilayer printed wiring board which is composed of a wiring board and can be suitably used for a package substrate on which electronic components such as IC chips are mounted.

[0002]

2. Description of the Related Art A demand for higher density of a multilayer wiring board has attracted attention of a so-called build-up multilayer printed wiring board. This build-up multilayer printed wiring board is manufactured by a method disclosed in, for example, Japanese Patent Publication No. 55555/1992. That is, an adhesive for electroless plating made of a photosensitive resin is applied on the core substrate on which the lower conductor circuit is formed, and after drying, the exposed and developed treatment is performed to form an interlayer having an opening for a via hole. A resin insulating layer is formed. Next, after the surface of the interlayer resin insulating layer is roughened by a treatment with an oxidizing agent or the like, the interlayer resin insulating layer is exposed and developed to provide a plating resist, and then an electroless portion is formed on a portion where the plating resist is not formed. A conductive circuit pattern including via holes is formed by plating or the like. Subsequently, by repeating this step a plurality of times, a build-up multilayer wiring board is manufactured.

On the other hand, in order to enhance the performance of the through hole, a technique of forming the through hole into a coaxial structure including an inner layer through hole and an outer layer through hole is disclosed in JP-A-2000-6.
No. 8648.

[0004]

SUMMARY OF THE INVENTION However, Japanese Patent Application Laid-Open
In 000-68648, since the inner layer through-hole and the outer layer through-hole are formed by laser, the opening diameter on the laser incident side is large and the opening diameter on the opposite side is small,
The outer through hole and the inner through hole are tapered. For this reason, if the center between the outer layer through-hole and the inner layer through-hole is slightly deviated, the gap between the outer layer through-hole and the inner layer through-hole tends to be uneven, and the gap between the outer layer through-hole and the inner layer through-hole is likely to be uneven. Is concerned about the insulation reliability. In order to cope with such a problem, it was considered that laser irradiation was performed from both sides. However, it was difficult for the irradiated laser to reach the lower surface, and the distance for forming the through hole (the thickness of the core substrate and the distance between the core substrate and both sides thereof). (The thickness of the interlayer resin insulating layer) was long, so that the alignment accuracy was difficult.

[0005] In particular, the package substrate is mounted on an IC.
Since the heat generated by the chip is large, the core substrate made of resin, the interlayer resin insulating layer, and the filler in the through hole make the thermal expansion coefficient as close as possible to reduce the stress generated by the difference in thermal expansion coefficient. It is necessary to reduce the size and prevent the occurrence of cracks inside. Therefore, it is necessary that the insulating layer (resin filler) between the above-described inner layer through-hole and the outer layer through-hole contains particles that increase the coefficient of thermal expansion. On the other hand,
When particles are included in the resin, the particles easily propagate through the particles, and as described above, when the gap between the outer-layer through-hole and the inner-layer through-hole becomes non-uniform, a small gap portion is formed. In this case, a short circuit easily occurs, and the reliability of the through hole having the coaxial structure is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to propose a method of manufacturing a multilayer printed wiring board having a highly reliable coaxial through hole. It is in.

[0007]

According to a first aspect of the present invention, there is provided a method for manufacturing a multilayer printed wiring board, comprising at least steps (a) to (g). ) A step of forming a through hole for an outer layer through hole using a drill in the core substrate; (b) a step of applying a metal film to the through hole for the outer layer through hole to form an outer layer through hole; (c) a step of forming the outer layer through hole Filling the inside with a resin filler to form an outer resin insulating layer; (d) forming an interlayer resin insulating layer on one or both surfaces of the core substrate; (e) drilling a drill into the outer layer through hole. Forming a through-hole for an inner layer through-hole using the same; (f) applying a metal film to the through-hole for the inner-layer through-hole to form an inner-layer through-hole; and (g) resin filler in the inner-layer through-hole. To form an inner resin insulation layer.

According to the first aspect of the present invention, a through hole is formed using a drill. In other words, by using a drill,
The through hole is prevented from being tapered, and the thickness of the outer layer resin filler forming the insulating layer between the outer layer through hole and the inner layer through hole can be made uniform. For this reason, a short circuit between the through hole of the outer layer and the through hole of the inner layer can be prevented, and the reliability is improved.

A technical feature of the method for manufacturing a multilayer printed wiring board according to the second aspect is that the method includes at least steps (a) to (h): (a) outer layer through using a drill on a core substrate; Forming a through hole for a hole; (b) applying a metal film to the through hole for an outer layer through hole to form an outer layer through hole; (c) filling a resin filler in the outer layer through hole; Forming an outer resin insulating layer; (d) forming an interlayer resin insulating layer on one or both surfaces of the core substrate; (e) forming a through hole for the inner layer through hole using a drill in the outer layer through hole. (F) applying a metal film to the through hole for the inner layer through hole to form an inner layer through hole; and (g) filling the inner layer through hole with a resin filler to form an inner resin insulating layer. (H) forming a conductive lid on the inner layer through-hole.

According to the second aspect of the present invention, the through hole is formed using a drill. In other words, by using a drill,
The through hole is prevented from being tapered, and the thickness of the outer layer resin filler forming the insulating layer between the outer layer through hole and the inner layer through hole can be made uniform. For this reason, a short circuit between the through hole of the outer layer and the through hole of the inner layer can be prevented, and the reliability is improved. Further, since the through hole and the via hole are connected via the conductive lid, the connection reliability between the through hole and the via hole can be improved.

According to the third aspect of the present invention, a lid is formed on the inner through hole, and a via hole is formed on the lid.
That is, by providing a conductive lid on the inner layer through-hole, the via hole can be formed immediately above the through-hole, so that the wiring length can be reduced and the high-frequency performance can be improved.

According to the fourth aspect of the present invention, the lid is formed by plating on the inner layer through hole to a thickness of 5 to 20 μm. If the thickness of the lid is less than 5 μm, it will be difficult to establish electrical connection between the inner layer through hole and the lid by plating. Conversely, when the thickness of the lid by plating exceeds 20 μm,
Undercutting occurs during etching, making it impractical. Therefore, by setting the thickness of the lid to 5 to 20 μm, the lid can be suitably formed by plating.

According to the fifth aspect of the present invention, the surface of the conductor layer of the through hole is provided with a roughened layer. The roughened layer can prevent the resin filler from expanding and contracting, and can prevent the interlayer insulating layer formed on the through hole and the lid plating from being pushed up. Note that the roughened layer can be formed by oxidation-reduction treatment, blackening treatment, plating, and etching.

As the resin constituting the resin composition for filling through holes of the present invention, a thermosetting resin or a thermoplastic resin can be used. As the thermosetting resin, at least one resin selected from an epoxy resin, a polyimide resin, and a phenol resin is preferable. As the thermoplastic resin, polytetrafluoroethylene (PTFE), tetrafluoroethylene hexafluoropropylene copolymer (FEP),
Polytetrafluoroethylene perfluoroalkoxy copolymer (PF
A) and other fluororesins, polyethylene terephthalate (P
ET), polysulfone (PSF), polyphenylene sulfide (PPS), thermoplastic polyphenylene ether (PPE), polyether sulfone (PES), polyetherimide (PEI), polyphenylene sulfone (PPES), polyethylene naphthalate (PEN) ,
At least one selected from polyetheretherketone (PEEK) and polyolefin-based resins is preferred.

In particular, as the optimum resin used for filling the through holes, at least one selected from bisphenol type epoxy resin and novolak type epoxy resin is preferable. The reason is that the viscosity of the bisphenol type epoxy resin can be adjusted without using a diluting solvent by appropriately selecting a resin such as A type or F type,
Also, the novolak type epoxy resin is high in strength, excellent in heat resistance and chemical resistance, and does not decompose and does not thermally decompose even in a strongly basic solution such as an electroless plating solution. As the bisphenol type epoxy resin, bisphenol A
It is desirable to use at least one selected from a type epoxy resin and a bisphenol F type epoxy resin. Among them, bisphenol F type epoxy resin is advantageous because it can be used with low viscosity and without solvent.
As the novolak type epoxy resin, it is desirable to use at least one selected from a phenol novolak type epoxy resin and a cresol novolak type epoxy resin. When a novolak type epoxy resin and a bisphenol type epoxy resin are blended and used in such a resin, the blending ratio is 1/1 to 1/1 by weight.
100 is preferred. The reason for this is that a remarkable increase in viscosity can be suppressed. The amount of the inorganic particles contained is preferably 10 to 80 vol%. More desirable is 20 to 70 vol%. This is because even if the particles are agglomerated or dispersed, the above-mentioned problems are unlikely to occur.
It is preferable that at least one of an aluminum compound, a calcium compound, a potassium compound, a magnesium compound, and a silicon compound is blended in the contained inorganic particles. Examples of the aluminum compound include alumina and aluminum hydroxide. As calcium compounds, calcium carbonate, calcium hydroxide,
And the like. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate. Examples of the silicon compound include silica and zeolite.

The curing agent used in such a resin composition is preferably an imidazole curing agent, an acid anhydride curing agent, or an amine curing agent. This is because curing shrinkage is small. By suppressing the curing shrinkage, the filler can be integrated with the conductor layer covering the filler to improve the adhesion.

Further, such a resin composition can be diluted with a solvent, if necessary. As this solvent,
NMP (normal methylpyrrolidone), DMDG (diethylene glycol dimethyl ether), glycerin,
Water, 1- or 2- or 3-cyclohexanol, cyclohexanone, methylcellosolve, methylcellosolve acetate, methanol, ethanol, butanol, propanol, and the like. More preferably, a solvent is not contained in the filling resin composition.

In the present invention, it is preferable that a roughened layer is formed on the inner wall conductor surface of the through hole filled with the filler. The reason for this is that the filler and the through hole are in close contact with each other via the roughened layer, and no gap is generated. If there is a gap between the filler and the through-hole, the conductor layer formed by electrolytic plating directly above it will not be flat, or the air in the gap will thermally expand, causing cracks and peeling. Or cause water to accumulate in the voids, causing migration or cracks.
In this regard, the formation of the roughened layer can prevent such defects from occurring.

In the present invention, it is advantageous that a roughened layer similar to the roughened layer formed on the conductor surface on the inner wall of the through hole is formed on the surface of the conductor layer covering the filler. The reason for this is that the roughened layer can improve the adhesion to the interlayer resin insulating layer and via holes.
In particular, if the roughened layer is formed on the side surface of the conductor layer, cracks generated toward the interlayer resin insulation layer starting from the interface due to insufficient adhesion between the conductor layer side surface and the interlayer resin insulation layer can be suppressed. Can be.

The thickness of the roughened layer formed on the inner wall of the through hole and the surface of the conductor layer is preferably 0.1 to 10 μm.
The reason for this is that if it is too thick, it causes interlayer short-circuit, and if it is too thin, the adhesion to the adherend decreases. The roughened layer is formed by subjecting the conductor on the inner wall of the through hole or the surface of the conductor layer to an oxidation (blackening) -reduction treatment, or a treatment formed with a mixed aqueous solution of an organic acid and a cupric complex. Alternatively, a material formed by plating a copper-nickel-phosphorus needle-like alloy is preferable.

Among these treatments, in the method by oxidation (blackening) -reduction treatment, NaOH (20 g / l), NaClO ₂ (50 g
/ L), Na ₃ PO ₄ (15.0 g / l) in an oxidation bath (blackening bath), Na
OH (2.7 g / l) and NaBH ₄ (1.0 g / l) are used as the reducing bath.

In a treatment using an aqueous solution of an organic acid-cupric acid complex, a metal foil such as copper, which is a conductive circuit, is dissolved under the condition of coexistence of oxygen such as spraying or bubbling. Cu + [Cu (II) A] ⁿ → [2Cu (I) A] ^{n / 2} +
n / 4O ₂ + nAH (aeration) → [2Cu (I
I) A] ⁿ + n / 2H ₂ O A is a complexing agent (acting as a chelating agent), and n is a coordination number.

The cupric complex used in this treatment is preferably an azole cupric complex. The cupric complex of azoles acts as an oxidizing agent for oxidizing metallic copper and the like. As the azoles, diazole, triazole,
Tetrazole is preferred. Among them, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole and the like are preferable. The content of the cupric complex of azoles is preferably 1 to 15% by weight.
This is because, when it is in this range, solubility and stability are excellent.

The organic acid is added to dissolve copper oxide. Specific examples include formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, apple At least one selected from acids and sulfamic acids is preferred. The content of this organic acid is 0.1-30
% By weight is good. This is for maintaining the solubility of the oxidized copper and ensuring the solubility stability. The generated cuprous complex dissolves under the action of an acid and combines with oxygen to form a cupric complex, which again contributes to copper oxidation. Further, in addition to the organic acid, an inorganic acid such as borofluoric acid, hydrochloric acid, and sulfuric acid may be added.

In order to assist the dissolution of copper and the oxidizing action of azoles, a halogen ion, for example, a fluorine ion, a chlorine ion, a bromine ion or the like is added to the etching solution comprising the organic acid-cupric complex. Is also good. The halogen ions can be supplied by adding hydrochloric acid, sodium chloride, or the like. The amount of halogen ions is preferably 0.01 to 20% by weight. This is because if it is within this range, the adhesion between the formed roughened surface and the interlayer resin insulating layer will be excellent.

The etching solution comprising the organic acid-cupric complex is prepared by dissolving a cupric complex of an azole and an organic acid (halogen ion if necessary) in water.

In the plating of a needle-shaped alloy comprising copper-nickel-phosphorus, copper sulfate 1-40 g / l, nickel sulfate 0.1-6.0 g / l, citric acid 10-20 g / l, hypophosphite 10-100 g / l, boric acid 10-40 g / l, surfactant
It is desirable to use a plating bath having a liquid composition of 0.01 to 10 g / l.

In the present invention, it is preferable that the interlayer resin insulating layer is formed using a thermosetting resin sheet. The thermosetting resin sheet contains a sparingly soluble resin, soluble particles, a curing agent, and other components. Each is described below.

In the thermosetting resin sheet used in the production method of the present invention, particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble particles”) are resins that are hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a hardly soluble resin). ). The terms "sparingly soluble" and "soluble" used in the present invention are referred to as "soluble" for convenience when those immersed in a solution comprising the same acid or oxidizing agent for the same time have a relatively high dissolution rate. Those having a relatively low dissolution rate are referred to as "poorly soluble" for convenience.

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and an acid or an oxidizing agent. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

As the soluble resin particles, resin particles made of rubber can also be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

Examples of the above-mentioned soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

The soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin film can be ensured, and thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed on the interlayer resin insulating layer using an acid or an oxidizing agent. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, a via opening can be formed in the interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin,
Examples thereof include a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include a cresol novolak epoxy resin, a bisphenol A epoxy resin, a bisphenol F epoxy resin, a phenol novolak epoxy resin, an alkylphenol novolak epoxy resin, a biphenol F epoxy resin, and a naphthalene epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin film used in the present invention, the soluble particles are desirably substantially uniformly dispersed in the hardly-soluble resin. A roughened surface having unevenness with a uniform roughness can be formed, and even when a via or a through hole is formed in a resin film, the adhesion of a metal layer of a conductive circuit formed thereon can be secured. Because. Alternatively, a resin film containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby, since the portions other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin film, the amount of the soluble particles dispersed in the poorly soluble resin is desirably 3 to 40% by weight based on the resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities. If the amount exceeds 40% by weight, the soluble particles may be dissolved using an acid or an oxidizing agent. In addition, there is a case where the resin film is melted to a deep portion of the resin film and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.

The resin film desirably contains a curing agent and other components in addition to the soluble particles and the hardly soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and microcapsules of these curing agents, and organic materials such as triphenylphosphine, tetraphenylphosphonium, and tetraphenylborate. Phosphine compounds and the like can be mentioned.

The content of the above curing agent is preferably 0.05 to 10% by weight based on the resin film. 0.
If the amount is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidizing agent into the resin film is increased, and the insulating property of the resin film may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

The other components include, for example, fillers such as inorganic compounds or resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the printed wiring board can be improved by matching the thermal expansion coefficient, improving heat resistance and chemical resistance, and the like.

Further, the resin film may contain a solvent. As the solvent, for example, acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Ethyl acetate, butyl acetate, cellosolve acetate, and aromatic hydrocarbons such as toluene and xylene. These may be used alone or in combination of two or more.

[0048]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment First, the configuration of a multilayer printed wiring board used as a package substrate according to a first embodiment of the present invention will be described with reference to FIGS. FIG.
1 shows a sectional view of the package substrate 10 according to the first embodiment of the present invention. FIG. 8 is an explanatory diagram showing the coaxial through hole 66 in FIG. 7 in an enlarged manner.

The package substrate 10 has a build-up wiring layer 80A and a build-up wiring layer 80B formed on the front and back surfaces of the core substrate 30. Build-up wiring layer 8
0A, the build-up wiring layer 80B includes the interlayer resin insulation layer 44 in which the conductor circuit 58 and the via hole 60 are formed;
It comprises a conductor circuit 158 and an interlayer resin insulation layer 144 in which a via hole 160 is formed. The build-up wiring layer 80A on the front side and the build-up wiring layer 80B on the back side include a coaxial through-hole 66 used as a signal line formed on the core substrate 30 and a conductive through-hole mainly used as a ground line / power supply line. It is connected via a hole 34. A solder resist layer 70 is formed on the interlayer resin insulation layer 144, and the solder resist 70
The solder bumps 76U and 76D are formed in the conductor circuit 158 and the via hole 160 via the opening 71 of FIG. The solder bumps 76U on the front side are connected to the pads 92 of the IC chip 90. On the other hand, the solder bumps 76D on the back side or external terminal components (BGA / PG
A) is connected to the pad 96 of the daughter board 95.

As shown in FIG. 8, the coaxial through hole 66
Comprises an outer layer through hole 36 and an inner layer through hole 62. Outer layer through hole 36 and inner layer through hole 6
2 is the build-up wiring layer 80 on the front side as described above.
A is connected to the build-up wiring layer 80B on the back side. The outer layer through hole 36 is formed in the through hole 3 of the core substrate 30.
3 has a metal film 38 formed on the wall surface. An outer resin insulating layer (outer resin filler) 42 is formed inside the outer through hole 36. Outer resin insulation layer 42
, An inner layer through hole 62 is formed.

The inner layer through hole 62 is composed of three layers: a metal layer 50, an electroless plating film 52, and an electrolytic plating film 56.
In addition, it is also possible to form with each two layers. An inner resin insulating layer (inner resin filler) 64 is formed inside the inner through hole 62. By forming the through hole 66 used as a signal line to have the outer layer through hole 36 and the inner layer through hole 62 in a coaxial structure, it is possible to prevent standing waves and reflections from occurring in the through hole 66.

The outer resin insulating layer 42 inside the outer through hole 36 and the inner resin insulating layer 64 inside the inner through hole 62 are filled with a resin containing a thermosetting resin, a curing agent, and inorganic particles. It is formed by filling the agent 39. Since the resin filler 39 contains at least inorganic particles in the range of 10 to 80 vol%, the outer resin insulating layer 42, the inner resin insulating layer 64, and the core substrate 30
And the interlayer insulating layer 44 can be matched in thermal expansion coefficient to prevent stress concentration due to thermal contraction. Therefore, generation of cracks is prevented, and electrical connectivity and reliability can be improved.

As will be described later, in the package substrate 10 of the first embodiment, a through hole 33 having a vertical wall is formed in the core substrate 20 using a drill to form an outer layer through hole 36. Then, the inner layer through-hole 62 is formed by using a smaller diameter drill. That is, by using a drill instead of a laser, the outer layer through-hole 36 and the inner layer through-hole 62 are prevented from being tapered, and an outer layer that forms an insulating layer between the outer layer through-hole 36 and the inner layer through-hole 62 is formed. Resin insulation layer (resin filler)
The thickness of 42 is made uniform. This prevents a short circuit between the outer layer through-hole 36 and the inner layer through-hole 62, thereby improving electrical connectivity and reliability.

In particular, in the first embodiment, the outer resin insulating layer (resin filler) 42 between the outer layer through-hole 36 and the inner layer through-hole 62 in order to prevent the occurrence of cracks inside due to the difference in thermal expansion coefficient. Contains 10% or more of inorganic particles. For this reason, migration is likely to occur due to transmission of the inorganic particles, and a short circuit is likely to occur. However, by making the thickness of the outer resin insulation layer (resin filler) 42 uniform, the outer layer through-hole 36 and the inner layer through-hole 62 are formed. To prevent short circuit between them.

Next, a method of manufacturing the package substrate 10 according to the first embodiment will be described with reference to FIGS. Here, first, A.I used in the method of manufacturing the package substrate is described. The composition of the resin filler will be described.

A. Preparation of resin filler [Thermosetting resin] Bisphenol F type epoxy monomer (manufactured by Yuka Shell,
Molecular weight 310, YL983U) 100 parts by weight. [Curing agent] 6.5 parts by weight of imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals). [Inorganic particles] silica (Admatech, CRS 1101-C
E, where the silica used is SiO ₂ with an average particle size of 1.6 μm, the surface of which is coated with a silane coupling agent.
The size of the spherical particles and the maximum particles is not more than the thickness (15 μm) of the inner layer copper pattern described later) 170 parts by weight. In the first embodiment, the amount of the inorganic particles added to the resin filler is set to 10 to 80 vol%, here, 50 vol%, as described above. By mixing 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) with the bisphenol F type epoxy monomer, imidazole curing agent, and silica, the viscosity of the mixture is 5 to 30 Pa.s at 23 ± 1 ° C. Adjust to S. In the first embodiment, the viscosity is 5 Pa. S obtained by adjusting to S is used.

Manufacturing of package substrate (1) Glass epoxy resin or BT having a thickness of 0.8 mm
Substrate 30 made of (bismaleimide-triazine) resin
The starting material is a copper-clad laminate 30A in which copper foils 31 of 12 μm are laminated on both sides of the substrate (FIG. 1 (A)). Note that a base material impregnated with a reinforcing material such as FR4, FR5, or a glass epoxy resin can be used. A core substrate that has been multilayered in advance may be used.

(2) The copper-clad laminate 30A is drilled with a drill to form a through-hole 32 with a diameter of 300 μm for conduction.
Then, a through hole 33 for an outer layer through hole having a diameter of 350 μm is formed (FIG. 1B). Holes may be drilled using a laser, but it is preferable to use a drill to prevent tapering. In the present embodiment, since the coaxial through-hole and the normal through-hole are mixed, each is formed using a separate drill. Through hole 3 for outer layer through hole
The opening diameter of 3 is preferably 200 to 400 μm. Particularly desirable is 250 to 350 μm. Further, the opening diameter of the through hole 32 for the through hole for conduction is 50
It is preferable that the thickness be formed to 400 μm.

(3) Subsequently, the substrate 30 is subjected to an electroless copper plating process to form a through hole 34 for conduction and an outer layer through hole 36 (FIG. 1C). Furthermore, copper foil 31
Next, an inner layer copper pattern (metal film) 38 is formed on both surfaces of the substrate 30 by using a tenting method or a semi-additive method (FIG. 1D).

(4) The substrate 30 on which the inner layer copper pattern (metal film) 38, the conduction through hole 34, and the outer layer through hole 36 are formed is washed with water and dried. Then, NaOH (20 g / l), NaClO was used as an oxidation bath (blackening bath).
_Two (50 g / l), Na ₃ PO ₄ (15 g / l), NaOH (2.7 g / l), NaBH ₄ (1.0 g /
By the oxidation-reduction treatment using 1), the surfaces of the inner layer copper pattern (metal film) 38, the conduction through hole 34, and the outer layer through hole 36 are roughened layers 34α, 36α,
The roughened layer 38α is provided. (FIG. 1E) The roughened layer may be formed by plating, etching, or the like.

(5) The through hole 34 for conduction and the through hole 36 in the outer layer are filled with the resin filler 39 adjusted in the above A by printing (FIG. 2A). By filling the through hole 34 for conduction and the outer layer through hole 36 with the resin filler 39 adjusted in the above A, cracks are prevented from occurring, and electrical connectivity and reliability are improved. Here, based on a conventional filler (thermosetting resin, thermoplastic resin, or a resin composite thereof), an organic resin filler, an inorganic filler, a metal filler, etc. are blended to form a core substrate and an inner layer filler. Thermal expansion matching may be performed. At this time, the amount of the filler is preferably 10 to 80 vol%. The filler was semi-cured at 80 ° C. for 30 minutes. The semi-curing is performed to facilitate polishing.

(6) The substrate 30 after the processing of the above (5)
The surface of the lower conductor circuit (inner copper pattern) 38, the through hole 34 for conduction, the land 34a of the outer layer through hole 36, and the surface of the land 36a by belt sanding using a belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.) Polishing is performed so that the resin filler 39 does not remain. Next, buffing is performed to remove scratches caused by the belt sander polishing. This step is similarly performed on the other surface of the substrate. Then, the filled resin filler 39 is cured by heating to form the resin insulating layer 40 in the through hole 34 for conduction and the outer resin insulating layer 42 in the outer layer through hole 36 (FIG. 2B). The buffing may be performed only.

(7) Next, the surface of the lower conductive circuit 38 once flattened in the same manner as in (4), the through hole 34 for conduction and the outer layer The lower conductor circuit 38 is formed by etching the land 34a of the through hole 36 and the surface of the land 36a.
Rough surface 3 on the surface of the land 34a and the land 36a.
4β, a roughened surface 36β, and a roughened surface 38β are formed (FIG. 2).
(C)). The etching solution is composed of a cupric complex and an organic acid salt. The roughened surface can be formed by using electroless plating or oxidation-reduction treatment.

(8) A thermosetting resin sheet containing a soluble filler having a thickness of 50 μm is formed on both surfaces of the substrate 30 after the step (7) at a pressure of 5 kg / cm ² while the temperature is raised to a temperature of 50 to 150 ° C. Vacuum compression bonding is performed to provide an interlayer resin insulation layer 44 (FIG. 2D). The interlayer resin insulating layer may be a resin made of a thermosetting resin or a thermoplastic resin, or a resin obtained by substituting a photosensitive group for them. Specific examples include resins used for printed wiring boards, such as epoxy resins, polyphenol resins, and polyimide resins. Further, a resin having a low dielectric constant in a high frequency region may be used. The degree of vacuum during vacuum compression of resin is
10 mmHg. Although the interlayer insulating layer is formed by attaching a resin film here, the interlayer insulating layer may be formed by applying a resin using a printing machine.

(9) Next, an opening 46 to be a via hole is formed in the interlayer resin insulating layer 44 (FIG. 2E). Here, a carbon dioxide (CO ₂ ) gas laser is used, and the beam diameter is 5 m.
A via hole opening 46 having a diameter of 80 μm is provided in the interlayer resin insulating layer 44 under the conditions of m, pulse width 15 μs, mask hole diameter 0.8 mm, and one shot.

(10) Using a drill having a diameter of 60 to 200 μm, an outer layer through hole 36 formed in the core substrate 30 is formed.
A through hole 48 for an inner layer through hole is formed through the outer resin insulating layer 42 and the interlayer resin insulating layer 44 of FIG.
(A)). In the first embodiment, a 145 μm diameter drill with a diamond tip attached to the tip is rotated 16 times per minute, and the inner layer through-hole 48 having an inner diameter of 150 μm is formed.
Was drilled. If necessary, the smear in the through hole 48 for the inner layer through hole is removed by a wet process such as permanganic acid or a dry etching process such as a plasma or corona treatment. It is preferable that the diameter of the through hole 48 for the inner layer through hole is 75 to 200 μm. Particularly desirable is 100 to 150 μm. In the first embodiment, since the through hole 48 for a through hole having a vertical wall is formed using a drill, it is possible to prevent the shape of the inner layer through hole from being tapered unlike a laser. Therefore, it is possible to prevent a short circuit from occurring between the inner layer through-hole and the outer layer through-hole formed in a step described later.

(11) Next, a roughened surface 44α of the interlayer resin insulating layer 44 is provided by dipping in an oxidizing agent such as chromic acid or permanganate (see FIG. 3B).
The roughened surface 44α is preferably formed in a range of 0.1 to 5 μm. As an example, a roughened surface 44α of 2-3 μm is provided by immersing in a sodium permanganate solution 50 g / l at a temperature of 60 ° C. for 5 to 25 minutes.
In addition to the above, a plasma treatment is performed on the interlayer resin insulating layer 44 to roughen the surface layer of the interlayer resin insulating layer 44 so that the roughened layer 44α
To form At this time, argon gas was used as an inert gas, power was 200 W, gas pressure was 0.6 Pa, and temperature was 7
Under the condition of 0 ° C.
SV-4540) Perform plasma treatment for 2 minutes.

(12) Cu is sputtered into the surface layer of the interlayer resin insulation layer 44 and the through hole 48 for the inner layer through hole.
(Or Ni, P, Pd, Co, W) to form a metal layer 50 which targets an alloy (FIG. 3C). As the forming conditions, the pressure is 0.6 Pa, the temperature is 80 ° C., the electric power is 200 W, and the time is 5 minutes (the plasma apparatus SV-
4540). Thereby, the interlayer resin insulation layer 4
An alloy layer can be formed on the surface layer of No. 4 and the through-hole 48 for the inner layer through-hole. At this time, the thickness of the metal layer 50 is 0.2 μm. As the thickness of the metal layer 50,
0.1 to 2 μm is preferred. A plating layer may be formed without performing evaporation, sputtering, etc. other than sputtering.
Alternatively, these complexes may be used.

An example of plating will be described. The substrate 30 is conditioned, and the catalyst is applied in an alkaline catalyst solution for 5 minutes. The substrate 30 is activated, and the electroless plating film 5 having a thickness of 0.6 μm is formed in a Rochelle salt type chemical copper plating bath.
2 (FIG. 3D). Plating conditions for chemical copper plating: CuSO ₄ .5H ₂ O 10 g / l HCHO 8 g / l NaOH 5 g / l Rochelle salt 45 g / l Additive 30 ml / l Temperature 30 ° C. Plating time 18 minutes

(13) A photosensitive film (dry film) having a thickness of 25 μm is stuck on the metal film 52, a mask is placed thereon, exposed at 100 mJ / cm ² , and developed with 0.8% sodium carbonate. Then, a plating resist 54 is provided (FIG. 4A).

(14) Electroless plating is performed on the non-formed portion of the plating resist 54 on the electroless plated film 52 under the following conditions.
An electrolytic plating film 56 is formed (FIG. 4B). The thickness of the electrolytic plating film 56 is preferably 5 to 20 μm. Plating conditions of the electrolytic plating _{CuSO 4 · 5H 2 O 140g /} l H 2 SO 4 120g / l Cl - 50mg / l additive 300 mg / l acid amine 100 mg / l Temperature 25 ° C. Current density 0,8A / dm ² plating time 30 minutes thickness 18μm

(15) Then, 50 ° C., 40 g / l of N
The plating resist 54 is peeled off in an aOH aqueous solution.
Thereafter, the metal layer 50 and the electroless plating film 52 under the plating resist 54 are removed by etching using a sulfuric acid-hydrogen peroxide aqueous solution, and the conductor circuit 58 (including the via hole 60) is formed on the interlayer resin insulating layer 44. Is formed, and an inner layer through hole 62 is formed in the outer layer through hole 36. Thereafter, the surfaces of the conductor circuit 58, the via hole 60, and the inner layer through hole 62 are subjected to a roughening treatment (FIG. 4C).

(16) Next, similarly to the steps (4) to (6), the resin filler 39 adjusted in the above A is filled also in the inner through hole 62 (FIG. 4D). afterwards,
The resin filler 39 is polished. The polishing is performed using a nonwoven fabric containing an abrasive such as a buff on one side so that the resin filler 39 does not remain on the surface of the land 62a of the inner layer through hole 62. This step is similarly performed on the other surface of the substrate. Then, the filled resin filler 39 is cured by heating to form an inner resin insulating layer 64 in the inner through hole 62 (FIG. 5A). Thus, a coaxial through hole 66 including the outer layer through hole 36 and the inner layer through hole 62 is formed. In the first embodiment, the resin filler 39
Since the blending amount of the inorganic particles is 80 vol% or less, the polishing can be easily performed without performing mechanical polishing such as belt sander polishing, and without damaging the interlayer insulating layer 44, and Polishing can be performed without losing the roughened surface 44.

Here, the inner layer through-hole 62 is formed by filling the resin filler 39, but may be formed by printing. In addition, based on a conventional filler (thermosetting resin, thermoplastic resin, or a resin composite thereof), an organic resin filler, an inorganic filler, and the like are blended to form a thermal expansion between the interlayer insulating layer and the outer layer filler. Matching may be performed. At this time, the compounding amount was 10 to 80 vol%, and the viscosity was 5 to 50 Pa. S is desirable. Also,
By the resin filler 39 matched in the above A, the thermal expansion coefficients of the outer resin insulating layer 42, the inner resin insulating layer 64, the core substrate 30, and the interlayer insulating layer 44 are matched, so that stress concentration due to thermal contraction can be prevented. Therefore, generation of cracks is prevented, and electrical connectivity and reliability can be improved.

(17) Thereafter, the interlayer resin insulating layer 1
44, and through the steps (9) to (16), a conductor circuit 158 (including the through hole 160) is formed.
A package substrate consisting of six layers is obtained (FIG. 5B).

(18) On the other hand, 46.67 g of a photosensitizing oligomer (molecular weight 4000) obtained by acrylizing 50% of epoxy groups of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku) of 60% by weight dissolved in DMDG, 15.0 g of 80% by weight bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Chemicals, trade name: 2E4MZ-C)
N) 16 g, 3 g of a polyacrylic monomer (R604, manufactured by Nippon Kayaku), which is a photosensitive monomer, and 1.5 g of a polyvalent acrylic monomer (DPE6A, manufactured by Kyoeisha Chemical Co., Ltd.). -65) was mixed with 0.71 g, and 2 g of benzophenone (manufactured by Kanto Kagaku) as a photoinitiator and 0.2 g of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to the mixture to give a viscosity of 25. 2.0Pa at ℃
s is obtained. The viscosity was measured at 60 rpm using a B-type viscometer (Tokyo Keiki, DVL-B type).
For rotor No.4, for 6 rpm, rotor No.3.

(19) The solder resist composition is applied to both sides of the package substrate obtained in the above (18) by 20 μm.
Apply with a thickness of Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a 5 mm-thick photomask film on which a circular pattern (mask pattern) is drawn is placed in close contact with the substrate, and 1000 mJ / cm ^2. Exposure with UV light, DM
Perform TG development. And then at 80 ° C for 1 hour at 100 ° C
For 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours to form a solder resist layer 70 (20 μm thick) having an opening 71 in a solder pad portion (including a via hole and its land portion). It is formed (FIG. 5C). The solder pads for forming the solder bumps for connecting the IC chip are preferably opened with an opening diameter of 100 to 170 μm. Further, it is preferable that the solder pads for disposing BGA / PGA for connecting external terminals are opened with an opening diameter of 300 to 650 μm.

(20) Then, nickel chloride 2.3 × 10
^-1 mol / l, sodium hypophosphite 2.8 × 10 ^-1 m
ol / l, sodium citrate 1.6 × 10 ⁻¹ mol /
1 is immersed for 20 minutes in an electroless nickel plating solution having a pH of 4.5 to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. Then, on the surface layer, potassium cyanide 7.6 × 10 ⁻³ mol / l, ammonium chloride 1.9 × 10 ⁻¹ mol / l, sodium citrate 1.2 ×
10 ^-1 mol / l, sodium hypophosphite 1.7 × 10 ^-1
The nickel plating layer 72 was immersed in an electroless gold plating solution of 80 mol / l at 80 ° C. for 7.5 minutes to a thickness of 0.5
A gold plating layer 74 of 03 μm is formed (FIG. 5D).

(21) The solder resist layer 70
The solder bump (solder) 76U and the solder bump (solder) 76D are formed by printing a solder paste as a low melting point metal on the IC chip side in the opening 71 and reflowing at 230 ° C. 10 is completed (see FIG. 6).

The IC chip 90 is mounted on the solder bumps 76U of the completed package substrate 10 so that the pads 92 of the IC chip 90 correspond to the solder bumps 76U, and reflow is performed.
The package substrate 10 on which the IC chip 90 is mounted is
It is placed so as to correspond to the pad 96 on the daughter board 95 side, reflowed, and attached to the daughter board 95 (see FIG. 7). As a result, the package substrate 10 having the through holes 66 in which the BGA is provided and the outer layer through holes and the inner layer through holes have a coaxial structure can be obtained.

The resin filler 39 filling the through holes 66 of the package substrate 10 contains 10 to 80% of inorganic particles.
By blending, generation of stress due to heat shrinkage can be prevented. Therefore, the occurrence of cracks in the conductor portion can be prevented, so that electrical connectivity and reliability can be improved.

In the method of manufacturing the package substrate 10 according to the first embodiment of the present invention, the case where the BGA is provided is illustrated. However, the PGA may be provided as shown in FIG.
The steps (1) to (21) are the same when the PGA is provided. The subsequent steps will be described. First,
A solder paste is printed as a conductive adhesive 78 in the opening 71 on the lower surface side of the substrate (connection surface with the daughter board and the motherboard). Next, the conductive connection pin 97 is attached to and supported by an appropriate pin holding device, and the conductive connection pin 9
7 is brought into contact with the conductive adhesive 78 in the opening 71. Then, reflow is performed, and the conductive connection pins 9
7 is fixed to the conductive adhesive 78. In addition, as a method of attaching the conductive connecting pin 97, a conductive adhesive 78 formed in a ball shape or the like is put into the opening 71, or the conductive adhesive 78 is bonded to the fixing portion 97A to be conductive. The sexual connection pins 97 may be attached and then reflowed. In addition, the solder bumps 76 are provided in the openings 71 on the upper surface.
Is provided. As a result, the package substrate 10 having the through holes 66 in which the PGA is provided and the outer layer through holes and the inner layer through holes have a coaxial structure can be obtained.

[Second Embodiment] The package substrate of the second embodiment is almost the same as the first embodiment. However, in the second embodiment, the resin filler to be filled in the outer layer through-hole contains 40% of inorganic particles, and the resin filler to be filled in the inner layer through-hole contains 65% of inorganic particles. Is used to form the coaxial through hole 66.
In the second embodiment, the occurrence of cracks is prevented by blending inorganic particles with the resin filler.

[Third Embodiment] FIG. 11 shows a configuration of a package substrate according to a third embodiment, and FIG. 12 shows an enlarged view of the coaxial through hole 66 in FIG. The package substrate 10 of the third embodiment is almost the same as the first embodiment. However, in the third embodiment, the lid plated portion 94 is formed directly above the inner layer through hole 62, and the inner layer through hole 62 and the upper via hole 160 are connected via the lid plated portion 94. By interposing the cover plating portion 94, the inner through hole 62 and the upper via hole 160 are formed.
The connectivity with is improved. Then, via-holes 160 are formed immediately above the inner-layer through holes 62 by the lid plating portion 94.
Can be disposed, so that the wiring length can be reduced. The outer resin insulating layer 42 and the inner resin insulating layer 64 of the third embodiment contain 10 to 80 vol% of inorganic particles as in the first embodiment.
It is contained.

Here, the manufacturing process of the package substrate of the third embodiment will be described. Note that the manufacturing steps (1) to (16) are the same as those in the first embodiment when the cover plating section 94 is provided. The subsequent manufacturing steps will be described with reference to FIG.

(17) After a catalyst for electroless plating is applied to the substrate, electroless plating is performed to form an electroless plating film 68 (FIG. 10A). In the third embodiment, the inorganic particles of the resin filler 39 filled in the inner layer through-hole 62 are set to 80 vol% or less, so that a decrease in the amount of the applied catalyst and a stop of the reaction of the electroless plating film are prevented. The electroless plating film 68 can be appropriately deposited.

(18) Next, after a plating resist 67 having a predetermined pattern is formed on the substrate, electrolytic plating is performed.
An electrolytic plating film 69 is formed (FIG. 10B). Then, after the plating resist 67 is removed, the plating resist 67 is removed.
By removing the lower electroless plating film 68 by light etching, the electroless plating film 68
Then, a lid plating portion 94 made of the electrolytic plating film 69 is formed (FIG. 10C).

(19) Thereafter, the interlayer resin insulation layer 1
44, and (9) to (1) described in the first embodiment.
6), the conductor circuit 158 (through hole 16
0 is formed, and a package substrate composed of six layers is obtained (FIG. 10D). Note that the subsequent manufacturing steps are the same as (18) to (21) of the first embodiment, and a description thereof will be omitted. In the third embodiment, by reducing the amount of the inorganic particles of the inner resin filler 64 to 80 vol% or less, it is possible to prevent a decrease in the amount of the catalyst applied when forming the cover plating and stop the reaction of the electroless plating film. By properly forming the cover plating, it is possible to improve electrical connectivity and reliability.

[Fourth Embodiment] The package substrate of the fourth embodiment is almost the same as the third embodiment. However, in the fourth embodiment, the resin filler to be filled in the outer layer through-hole contains 40% of inorganic particles, and the resin filler to be filled in the inner layer through-hole contains 65% of inorganic particles. Is used to form the coaxial through hole 66.

In the fourth embodiment, by reducing the inorganic particles of the inner resin filler 64 to 65 vol%, it is possible to prevent a decrease in the amount of the catalyst applied during the formation of the cover plating and a stop of the reaction of the electroless plating film. By properly forming the cover plating 94, it is possible to improve electrical connectivity and reliability.

[First Comparative Example] The first comparative example is the same as the package substrate of the first embodiment. However, the outer layer through-holes and the inner layer through-holes were formed by piercing through holes with a laser.

[Second Comparative Example] The second comparative example is the same as the package substrate of the third embodiment. However, the outer layer through-holes and the inner layer through-holes were formed by piercing through holes with a laser.

The package substrates of the first to fourth embodiments,
The chart of FIG. 13 shows the results of the insulation test of the coaxial through-holes with the package substrates of the first and second comparative examples. First to fourth
In the package substrate of the embodiment, no short circuit occurred in the coaxial through-hole even after 1000 heat cycles. In contrast, in the package substrates of the first and second comparative examples, a short circuit occurred in the coaxial through hole.

In the first to fourth embodiments described above,
Although the through hole 66 is coaxial, the outer through hole 36 and the inner through hole 66 of the through hole 66 may be used as separate signal lines. In this case, the wiring density of the core substrate can be increased. Also,
In the first to fourth embodiments described above, the outer layer through-hole 3
Although a coaxial structure is formed by the inner layer 6 and the inner layer through hole 66, it is also possible to use as a capacitor by disposing a resin having a high dielectric constant as an outer layer resin filler between the outer layer through hole 36 and the inner layer through hole 66. is there.

[0095]

As described above, in the present invention, a through hole for a through hole having a vertical wall is formed by using a drill to prevent the through hole from being tapered.
The thickness of the outer resin filler forming the insulating layer between the outer through hole and the inner through hole can be made uniform. For this reason, a short circuit between the through hole of the outer layer and the through hole of the inner layer can be prevented, and the reliability is improved.

[Brief description of the drawings]

FIG. 1 (A), (B), (C), (D), (E)
It is a manufacturing process figure of the package board concerning a 1st embodiment of the present invention.

FIG. 2 (A), (B), (C), (D), (E)
It is a manufacturing process figure of the package board concerning a 1st embodiment of the present invention.

FIGS. 3A, 3B, 3C, and 3D are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIGS. 4A, 4B, 4C, and 4D are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIGS. 5A, 5B, 5C, and 5D are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIG. 6 is a sectional view of the package substrate according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a state in which an IC chip is mounted on a package substrate according to the first embodiment of the present invention and attached to a daughter board.

FIG. 8 is an explanatory diagram showing an enlarged configuration of a coaxial through hole in FIG. 7;

FIG. 9 is a sectional view of a package substrate according to a modification of the first embodiment of the present invention.

FIGS. 10A, 10B, 10C, and 10D are manufacturing process diagrams of a package substrate according to a third embodiment of the present invention.

FIG. 11 is a sectional view of a package substrate according to a third embodiment of the present invention.

FIG. 12 is an explanatory view showing an enlarged configuration of a coaxial through hole in FIG. 11;

FIG. 13 is a table showing the results of a comparative test of the package substrates of the first to fourth embodiments and the package substrates of the first and second comparative examples.

[Explanation of symbols]

 Reference Signs List 30 core substrate 34 conduction through hole 36 outer layer through hole 38 inner layer copper pattern 39 resin filler 40 resin insulation layer 42 outer layer resin insulation layer 44 interlayer resin insulation layer 48 inner layer through hole for through hole 50 metal layer 52 electroless plating film 56 Electrolytic plating film 58 Conductor circuit 60 Via hole 62 Inner layer through hole 64 Inner layer resin insulation layer 66 Coaxial through hole 70 Solder resist layer 71 Opening 72 Nickel plating layer 74 Gold plating layer 76U, 76D Solder bump 78 Conductive adhesive 80A, 80B Build-up wiring layer 90 IC chip 92 Fixing part 94 Lid plating part (lid) 97 Conductive connection pin 144 Interlayer resin insulation layer 158 Conductor circuit 160 Via hole

Claims (5)

[Claims] 1. A method for manufacturing a multilayer printed wiring board, comprising at least steps (a) to (g): (a) forming a through hole for an outer layer through hole using a drill in a core substrate; (B) applying a metal film to the through hole for the outer layer through hole to form an outer layer through hole; and (c) filling a resin filler in the outer layer through hole to form an outer resin insulating layer. (D) a step of forming an interlayer resin insulating layer on one or both surfaces of the core substrate; (e) a step of forming a through hole for an inner layer through hole using a drill in the outer layer through hole; (f) the inner layer A step of applying a metal film to the through hole for the through hole to form an inner layer through hole; and (g) a step of filling the inner layer through hole with a resin filler to form an inner resin insulating layer. 2. A method for manufacturing a multilayer printed wiring board, comprising at least steps (a) to (h): (a) forming a through hole for an outer layer through hole using a drill in a core substrate; (B) applying a metal film to the through hole for the outer layer through hole to form an outer layer through hole; and (c) filling a resin filler in the outer layer through hole to form an outer resin insulating layer. (D) a step of forming an interlayer resin insulating layer on one or both surfaces of the core substrate; (e) a step of forming a through hole for an inner layer through hole using a drill in the outer layer through hole; (f) the inner layer A step of forming an inner layer through hole by applying a metal film to the through hole for a through hole; (g) a step of filling the inner layer through hole with a resin filler to form an inner resin insulating layer; (h) the inner layer Step of applying a conductive cover on Ruhoru. 3. The multi-layer print according to claim 2, wherein after the lid is provided on the inner layer through hole, an interlayer resin insulating layer is formed, and a via hole is formed immediately above the lid. Manufacturing method of wiring board. 4. The method according to claim 2, wherein the lid is a plating layer having a thickness of 5 to 20 μm. 5. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein a roughened layer is formed on a surface of said inner layer through hole.