JP2001217544A - Multilayer circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer circuit board advantageous for increasing the wiring density and mounting semiconductor chips such as LSIs at higher densities. SOLUTION: The multilayer circuit board has layer resin insulation layers and conductor layers alternately laminated on one surface of a multilayer- structured board having conductor circuits in inner layers, and buildup wiring layers having conductor layers interconnected through vias. The multilayer- structured board is formed by laminating through adhesive layers and heating and pressing en bloc a plurality of circuit boards each having vias having conductor circuits, on one or both surfaces of an insulative hard base and a conductive paste layer or plating layer provided in holes piercing the insulative hard base to reach the conductor circuits. Solder bumps are formed on the surfaces of the outermost conductor layers of the buildup wiring layers, and conductive pins or conductive balls are formed on the surface of the multilayer-structured board where no buildup wiring layer is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer circuit board having a build-up wiring layer formed on one side of a multi-layer board as a base. This is performed by laminating a plurality of single-sided or double-sided circuit boards, and performing batch heating and pressing via an adhesive, and electrically connecting a conductive circuit in the multilayered board to a build-up wiring layer formed on one side of the multilayered board. The present invention proposes a multilayer circuit board which is advantageous for high-density wiring, in which connection can be ensured via a filled via hole formed in a multilayered board and a via hole in a build-up wiring layer formed immediately above the filled via hole.

[0002]

2. Description of the Related Art In recent years, package substrates on which electronic components including semiconductor chips such as LSIs are mounted have been adapted to miniaturization or high-speed of electronic devices accompanying the progress of the electronics industry. Is required. As such a package substrate, 19
In the January 1997 issue of "Surface Mount Technology", there is disclosed a technology in which build-up multilayer wiring layers are formed on both surfaces of a multilayer substrate.

However, in the above-mentioned conventional package substrate, the connection between the conductor layer in the multilayer substrate and the build-up wiring layer is performed by providing inner layer pads wired from through holes on the surface of the multilayer substrate. A via hole is connected to the inner layer pad. For this reason, the land shape of the through-hole becomes a Dharma shape or an iron array shape, and the area of the inner layer pad hinders an improvement in the arrangement density of the through-holes, and there is a certain limit to the number of through-holes formed. Therefore, when the core substrate is multilayered in order to increase the wiring density, there is a problem that the outer build-up wiring layer cannot secure sufficient electrical connection with the conductor layers in the multilayered substrate. Was.

[0004] Regarding such a problem, the present inventors have previously described Japanese Patent Application No. 10-15346 (Japanese Patent Application Laid-Open No.
No. 1-214846), and proposed an improvement method.
The multilayer circuit board according to such an improvement proposal has a build-up wiring in which an interlayer resin insulating layer and a conductor layer are alternately laminated on a multilayer substrate having a conductor layer in an inner layer, and each conductor layer is connected by a via hole. In a multilayer circuit board having layers formed therein, a through hole is formed in the multilayered board,
The through hole is filled with a filler and a conductor layer is formed so as to cover an exposed surface of the filler from the through hole, and a via hole is connected to the conductor layer. The arrangement density is improved, and the connection with the conductor circuit in the multi-layered core substrate can be secured through the through hole having the increased density.

[0005]

However, a through hole in a multilayer circuit board having such a structure is formed by drilling a through hole in a multilayered core board with a drill or the like, and electroless plating is applied to the wall surface of the through hole and the board surface. In consideration of the opening properties and economical efficiency, the lower limit of the through hole opening diameter that can be formed is about 300 μm, realizing ultra-high-density wiring that satisfies the current requirements of the electronics industry. In order to achieve this, it is desired to develop a technology for obtaining a smaller opening diameter of about 50 to 250 μm and a narrower through-hole land pitch.

Therefore, the present inventors have provided a conductor circuit on one or both sides of a core material made of a hard material, and filled a conductive material into an opening penetrating the core material from one surface and reaching the conductor circuit. By forming a multi-layer board by laminating a plurality of circuit boards each having a via hole and heating and pressing them together via an adhesive, a multilayer board can be formed without providing through holes in the multi-layer board. The electrical connection between the conductor circuits in the substrate and between the conductor circuit in the multilayer substrate and the build-up wiring layer formed on the multilayer substrate is based on the filled via hole formed on the multilayer substrate and the build formed directly above the via hole. That it can be sufficiently secured via the via holes in the up-wiring layer, and furthermore, a part of the outermost conductive circuit of the build-up wiring layer is formed on the solder pad, and the soldering is performed. A conductive bump that can be connected to an electronic component including a semiconductor chip such as an LSI is provided for the pad, and a conductive circuit that is directly above a via hole that is exposed outside the multilayer substrate or that is exposed from the via hole. High-density wiring and high-density mounting of electronic components can be achieved by forming a part of conductive material on solder pads and arranging conductive pins or conductive balls that can be directly connected to the motherboard for the solder pads. I learned that it would be possible. An object of the present invention is to provide a multilayer circuit board which is advantageous for such high-density wiring and high-density mounting.

[0007]

Means for Solving the Problems The inventors of the present invention have intensively studied for realizing the above-mentioned object, and as a result, have arrived at an invention having the following content as a gist configuration. That is, (1) In the multilayer circuit board of the present invention, an interlayer resin insulating layer and a conductor layer are alternately laminated on one surface of a multilayer substrate having a conductor circuit in an inner layer, and each conductor layer is connected by a via hole. A multilayer circuit board having a build-up wiring layer formed thereon, wherein the multilayered board has a conductor circuit on one or both sides of an insulating hard base material, and penetrates the insulating hard base material to form the conductive circuit. A plurality of circuit boards each having a via hole filled with a conductive substance in a hole reaching the substrate are formed by laminating via an adhesive layer, and hot-pressing collectively, and On the outermost conductor layer surface of the wiring layer, the LS
A solder bump connected to an electronic component including a semiconductor chip such as I is provided, and on the surface of the conductor circuit exposed on the other surface of the multilayer substrate, located just above the filling via hole, the mother board is disposed. A conductive pin or a conductive ball to be connected is provided. The conductive substance to be filled in the via hole forming opening of each circuit board constituting the multilayer substrate is formed by a conductive paste composed of metal particles and a thermosetting resin or a thermoplastic resin, or formed by electrolytic plating. It is desirable that the electrolytic copper plating be performed.

It is preferable that each circuit board constituting the multilayer substrate has a projecting conductor electrically connected to the via hole corresponding to the position of the via hole. It is desirable to be formed from a conductive paste.

Further, it is preferable that a part of the via hole of the build-up wiring layer is located immediately above the via hole formed in the multilayer substrate and is directly connected to the via hole.

The insulating substrate of each of the circuit boards constituting the multilayer substrate is a glass cloth epoxy resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, an aramid nonwoven-epoxy resin base material. It is desirable to be formed from any hard substrate selected from a resin substrate and an aramid nonwoven fabric-polyimide resin substrate, and more desirably formed from a glass cloth epoxy resin substrate having a thickness of 20 to 100 μm. .

The diameter of the filled via hole formed in the insulating substrate formed of such a glass cloth epoxy resin substrate is desirably 50 to 250 μm.

The via hole is formed on the surface of the glass cloth epoxy resin base material under the conditions that the pulse energy is 0.5 to 100 mJ, the pulse width is 1 to 100 μs, the pulse interval is 0.5 ms or more, and the number of shots is 3 to 50. It is desirable to form the opening formed by the carbon dioxide laser to be irradiated.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention has a conductor circuit on one or both sides of an insulative hard base material, and fills a through hole reaching the conductor circuit through the insulative hard base material with a conductive substance. An insulating layer and a conductor layer are alternately laminated on one surface of a multilayer substrate formed by laminating a plurality of circuit boards formed on each other via an adhesive layer and heat-pressing them collectively. In a multilayer circuit board on which a build-up wiring layer is formed such that electrical connection between the conductive layers is performed via the via hole, the outermost conductive layer surface of the build-up wiring layer is located immediately above the via hole. LSI
Solder bumps connected to electronic components including semiconductor chips such as are provided, and on the conductor circuit exposed on the other surface of the multilayered substrate on which the build-up wiring layer is not formed,
It is characterized in that a conductive pin or a conductive ball connected to the motherboard is disposed immediately above the filled via hole.

According to the configuration of the present invention, it is not necessary to provide a through hole in the core substrate, so that the degree of freedom in arranging pads such as lands is improved as compared with the prior art. As a result, the filled via holes can be provided at a high density, so that the wiring density in the multi-layer substrate can be increased, and the outer build-up wiring layer can be multilayered through the via holes thus densified. Sufficient connection with the conductor circuit in the substrate can be ensured, and high-density wiring can be realized.

Further, of the via holes formed at high density in the build-up wiring layer, conductive bumps are formed on conductive circuits (conductive pads) exposed in openings formed in the outermost solder resist layer. And a conductive pin or a conductive ball is disposed on the conductive pad immediately above the via hole exposed on the surface of the multilayer substrate on which the build-up wiring layer is not formed. Through the use of such conductive bumps, conductive pins or conductive balls, it is connected to electronic components including semiconductor chips such as LSIs and motherboards with the shortest wiring length, thereby achieving high-density wiring and high-density mounting of electronic components. Becomes possible.

In the present invention, each circuit board constituting the multilayer board is not formed of a semi-cured prepreg as in the prior art, but is formed of an insulating resin base material formed of a completely cured hard resin material. Is desirable.

Such insulating base materials include glass cloth epoxy resin base material, glass cloth bismaleimide triazine resin base material, glass cloth polyphenylene ether resin base material,
Aramid non-woven fabric-epoxy resin substrate, aramid non-woven fabric-
A rigid (hard) laminated substrate selected from polyimide resin substrates is used, and a glass cloth epoxy resin substrate is most desirable.

In the case where a conductor circuit is formed on the insulating base material, in the step of pressing the copper foil on the insulating base material by a hot press, the final thickness variation of the insulating base material due to the pressing pressure may vary. Therefore, the displacement of the via hole is suppressed to the minimum, the diameter of the via land can be reduced, and as a result, the wiring pitch can be reduced and the wiring density can be improved.

Further, since the cured resin substrate is used as an insulating substrate, the thickness of the substrate can be kept substantially constant, and the setting of laser processing conditions when forming an opening for forming a via hole can be achieved. Becomes easier.

The thickness of the insulating substrate is 20 to 600 μm.
m is desirable. The reason is to ensure insulation. If the thickness is less than 20 μm, the strength is reduced and handling becomes difficult, and the reliability with respect to electrical insulation is reduced. If the thickness is more than 600 μm, a fine via hole forming opening becomes difficult, and the substrate itself becomes thick. It is because it becomes.

The via hole forming opening formed on the glass epoxy substrate having a thickness in the above range has a pulse energy of 0.5 to 100 mJ and a pulse width of 1 to 1 m.
00μs, pulse interval 0.5ms or more, shot number 3
It is preferably formed by a carbon dioxide laser irradiated under the conditions of 50 to 50, and the opening diameter is 50 to 250 μm.
m is desirable. The reason is 50 μm
If it is less than 250 μm, it is difficult to fill the opening with a conductive substance, and the connection reliability is low. If it exceeds 250 μm, it is difficult to increase the density.

Before the opening is formed by the carbon dioxide laser, a resin film is adhered to the surface of the insulating substrate opposite to the surface on which the conductive circuit is formed, or if necessary, a resin adhesive layer in a semi-cured state. Stick the resin film through
It is desirable to perform laser irradiation from above the resin film. In the former method, a non-through hole is provided by irradiating a laser from the opposite side of the copper foil to an insulative base material on which copper foil is pasted on one side in advance, and the copper foil is used as a plating lead in the non-through hole. When manufacturing a single-sided circuit board by etching after filling the electrolytic plating layer, or by etching a single-sided copper clad laminate to form a non-through hole by laser irradiation on an insulative base material with a conductor circuit formed in advance It is adopted when manufacturing a single-sided circuit board by filling an electrolytic plating layer with a copper foil as a plating lead in the non-through hole, the latter providing a through hole by laser irradiation in advance on an insulating base material, After the through-holes are filled with a conductive paste, copper foil is attached to both surfaces of the insulating base material and etched to produce a double-sided circuit board. This resin adhesive is for bonding a copper foil to the surface of an insulating substrate, and is formed of, for example, a bisphenol A type epoxy resin and has a thickness of 1%.
The range of 0 to 50 μm is preferred.

The resin film stuck on the insulating base material or on the resin adhesive layer formed on the insulating base material forms a via hole by filling electrolytic plating in a via hole forming opening. As a protective film when doing
Alternatively, a conductive paste is filled in the opening to form a via hole and a projecting conductor, or a conductive paste is filled on the electrolytic plating layer to form a projecting conductor (bump) immediately above the electrolytic plating layer. It has a pressure-sensitive adhesive layer that functions as a printing mask when performing the process, and that is separated from the insulating base material or the adhesive layer after filling with the conductive substance. This resin film has, for example, a pressure-sensitive adhesive layer having a thickness of 1 to 20 μm.
m and the thickness of the film itself is preferably from 10 to 50 μm.

The reason is that the height of the projecting conductor described later depends on the thickness of the PET film.
If the thickness is less than this, the protruding conductor is too low, and connection failure tends to occur. Conversely, if the thickness exceeds 50 μm, the protruding conductor spreads too much at the connection interface, so that a fine pattern cannot be formed.

As the conductive substance filled in the opening formed in the insulating base material, metal plating or conductive paste formed by electrolytic plating is preferable. The conductive paste is preferable in terms of simplifying the process, reducing the manufacturing cost, and improving the yield, but metal plating is more preferable in terms of connection reliability.

As the conductive paste, silver, copper,
A conductive paste composed of at least one or more metal particles selected from gold, nickel and solder can be used. As the above-mentioned metal particles, those obtained by coating the surface of a metal particle with a dissimilar metal can also be used. Specifically, metal particles in which the surface of copper particles is coated with a noble metal selected from gold and silver can be used. As such a conductive paste,
An organic conductive paste in which a thermosetting resin such as an epoxy resin or a phenol resin and a thermoplastic resin such as polyphenylene sulfide (PPS) are added to metal particles is desirable.

The conductor circuit formed on one or both surfaces of the insulating base material is obtained by hot pressing a copper foil having a thickness of 5 to 18 μm via a resin adhesive layer held in a semi-cured state,
It is preferably formed by performing an appropriate etching process. Such hot pressing is performed under appropriate temperature and pressure. More preferably, it is performed under reduced pressure, and by curing only the resin adhesive layer in a semi-cured state, the copper foil can be firmly adhered to the insulating base material. The manufacturing time is shortened as compared with the case of FIG.

A circuit board in which such a conductor circuit is formed on both sides of an insulating substrate is suitable as a core of a multilayer core board. It is preferable that the via land (pad) as a part is formed in a range of 50 to 250 μm in diameter.

In a circuit board in which a conductor circuit is formed on one side of an insulating base material, not only can a plurality of these boards be sequentially laminated to form a multilayer board, but also a double-sided circuit board is used as a core. It is suitable as a circuit board for lamination to be laminated on both sides thereof, and it is preferable that a projecting conductor is formed just above the position of the conductive material filled in the via hole.

The projecting conductor is preferably formed of a conductive paste or a low-melting-point metal. In the step of laminating circuit boards and heat-pressing them collectively, the conductive paste or the low-melting-point metal is heated. Due to the deformation, the variation in height of the conductive material filled in the via hole can be absorbed, and therefore, a connection failure can be prevented and a multilayer core substrate excellent in connection reliability can be obtained. Such a projecting conductor can be formed of the same material as the conductive paste filled in the via hole, and can also be formed by the same filling step.

Further, when the build-up wiring layer formed on the multilayer core substrate is formed by applying and curing a resin as described later, the surface of the conductor circuit provided on the surface of the multilayer core substrate is roughened. Advantageously, a layer is formed. The reason is that it is possible to improve the adhesion to the interlayer resin insulating layer and the via hole in the build-up wiring layer laminated on the multilayer core substrate. In particular, when a roughened layer is formed on the side surface of the conductor circuit, cracks generated toward the interlayer resin insulation layer from these interfaces due to insufficient adhesion between the side surface of the conductor circuit and the interlayer resin insulation layer are suppressed. be able to.

On the other hand, when the build-up wiring layer is formed by laminating a resin film as described later and curing by heating and pressing, formation of a roughened layer is not always necessary.

The thickness of the roughened layer formed on the surface of such a conductor circuit is preferably 0.1 to 10 μm. The reason for this is that if it is too thick, it causes interlayer short-circuit, and if it is too thin, the adhesion to the adherend decreases. The roughened layer may be formed by treating with a mixed aqueous solution of an organic acid and a cupric complex, or may be formed by plating a copper-nickel-phosphorus needle-like alloy.

Among these roughening treatments, the treatment using a mixed aqueous solution of an organic acid-cupric complex works as follows under the condition of coexistence of oxygen such as spraying and bubbling, and the conductor circuit such as copper Dissolve the metal foil. _{Cu + Cu (II) A n} → 2Cu (I) A n / 2 2Cu (I) A n / 2 + n / 4O 2 + nAH ( _{aeration) → 2Cu (II) A n} + n / 2H 2 O A complexing agent (chelate N) is the coordination number.

The cupric complex used in this treatment is preferably an azole cupric complex. The cupric complex of azoles acts as an oxidizing agent for oxidizing metallic copper and the like. As the azoles, diazole, triazole,
Tetrazole is preferred. Among them, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole and the like are preferable. The content of the cupric complex of azoles is preferably 1 to 15% by weight. This is because, when it is in this range, solubility and stability are excellent.

The organic acid is added to dissolve copper oxide. Specific examples include formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, apple At least one selected from acids and sulfamic acids is preferred. The content of this organic acid is 0.1 to
30% by weight is good. This is for maintaining the solubility of the oxidized copper and ensuring the solubility stability. The generated cuprous complex dissolves under the action of an acid and combines with oxygen to form a cupric complex, which again contributes to copper oxidation. Further, in addition to the organic acid, an inorganic acid such as borofluoric acid, hydrochloric acid, and sulfuric acid may be added.

In order to assist the dissolution of copper and the oxidizing action of azoles, a halogen ion, for example, a fluorine ion, a chlorine ion, a bromine ion or the like is added to the etching solution comprising the organic acid-cupric complex. Is also good. The halogen ions can be supplied by adding hydrochloric acid, sodium chloride, or the like.

The amount of halogen ions is preferably 0.01 to 20% by weight. This is because if it is within this range, the formed roughened layer has excellent adhesion to the interlayer resin insulating layer. The etching solution comprising the organic acid-cupric complex is prepared by dissolving a cupric complex of azoles and an organic acid (halogen ion as required) in water.

In the plating of a needle-shaped alloy composed of copper-nickel-phosphorus, copper sulfate 1-40 g / l, nickel sulfate 0.1-6.0 g / l, citric acid 10-20 g / l,
Hypophosphite 10 to 100 g / l, boric acid 10 to 40
It is desirable to use a plating bath having a liquid composition of g / l and a surfactant of 001 to 10 g / l.

In the present invention, the multilayer core substrate is formed by laminating a plurality of the single-sided circuit boards and heating and pressurizing them all together. As the interlayer resin insulating layer constituting the up wiring layer, a thermosetting resin, a thermoplastic resin, or a composite of a thermosetting resin and a thermoplastic resin can be used.

As the thermosetting resin, epoxy resin, polyimide resin, phenol resin, thermosetting polyphenylene ether (PPE) and the like can be used. Examples of the thermoplastic resin include a phenoxy resin, a fluororesin such as polytetrafluoroethylene (PTFE), polyethylene terephthalate (PET), polysulfone (PSF), polyphenylene sulfide (PPS), thermoplastic polyphenylene ether (PPE), and polyether. Sulfone (PE
S), polyetherimide (PEI), polyphenylene sulfone (PPES), tetrafluoroethylene hexafluoropropylene copolymer (FEP), tetrafluoroethylene perfluoroalkoxy copolymer (PFA), polyethylene naphthalate (PEN) ), Polyetheretherketone (P
EEK), polyolefin-based resins and the like can be used. As a composite of a thermosetting resin and a thermoplastic resin, epoxy resin-PES, epoxy resin-PSF, epoxy resin-
PPS, epoxy resin-PPES, epoxy resin-phenoxy resin, phenol resin-phenoxy resin and the like can be used.

In the present invention, the interlayer resin insulation layer constituting the build-up wiring layer is formed by laminating a desired number of resin films such as polyolefin resin, heating and pressing, and then thermosetting to integrate. be able to.
The thickness of the polyolefin-based resin layer is desirably in the range of 5 to 200 μm. The reason is that if it is less than 5 μm, it is difficult to secure interlayer insulation, and if it exceeds 200 μm, it becomes difficult to form an opening by laser processing.

In the present invention, an adhesive for electroless plating can be used as the interlayer resin insulating layer constituting the build-up wiring layer. As the adhesive for electroless plating, heat-resistant resin particles that are soluble in a cured acid or oxidizing agent are dispersed in an uncured heat-resistant resin that becomes hardly soluble in an acid or an oxidizing agent by the curing treatment. Is best. The reason for this is that by treating with an acid or an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus pot-shaped anchor can be formed on the surface. The depth of the roughened surface is preferably 0.1 to 20 μm. This is to ensure adhesion. In the semi-additive process, the thickness is preferably 0.1 to 5 μm. This is because the electroless plating film can be removed while ensuring adhesion.

In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles which have been particularly hardened include a heat-resistant resin powder having an average particle diameter of 10 μm or less, and an average particle diameter of 2 μm.
agglomerated particles obtained by aggregating a heat-resistant resin powder having a particle diameter of 2 m or less, and a heat-resistant resin powder having an average particle diameter of 2 to 10 μm and an average particle diameter of 2 μm
m and a mixture with a heat-resistant resin powder having a mean particle size of 2 or less.
Pseudo particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 μm or less to the surface of a 10 μm heat-resistant resin powder, and an average particle diameter of 0.1 μm.
~ 0.8μm heat resistant resin powder and average particle size 0.8μ
It is desirable to use at least one selected from a mixture with a heat-resistant resin powder having a particle size exceeding m and less than 2 μm and a heat-resistant resin powder having an average particle diameter of 0.1 to 10 μm. Further, metal particles or inorganic particles may be used in place of the above resin particles, and a plurality of types thereof may be appropriately mixed and used. This is because a more complicated anchor can be formed. As the heat-resistant resin used in the adhesive for electroless plating, the aforementioned thermosetting resin, thermoplastic resin, or a composite of the thermosetting resin and the thermoplastic resin can be used.

In the present invention, the electrical connection between the conductor circuit formed on the multilayer core substrate and the conductor circuit in the build-up wiring layer can be made by a via hole formed in the interlayer resin insulation layer. In this case, the via hole may be filled with a plating film or a filler.

Hereinafter, an example of manufacturing a multilayer circuit board according to the present invention will be specifically described with reference to the accompanying drawings.
In the method described below, the build-up wiring layer is formed on the multilayer substrate by a semi-additive method, but a full-additive method, a multi-lamination method, or a pin lamination method can also be employed.

(A) Formation of Multilayer Board (1) First, a double-sided circuit board constituting a multilayer board is formed. As the core material, a completely cured insulating substrate is used. The insulating base material is selected from, for example, a glass cloth epoxy resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, an aramid nonwoven fabric-epoxy resin base material, and an aramid nonwoven fabric-polyimide resin base material. A rigid (hard) laminated substrate is used, and a glass cloth epoxy resin substrate is most preferred. The thickness of the insulating substrate 10 is 20 to 600 μm
Is desirable. The reason is to ensure insulation. If the thickness is less than 20 μm, the strength is reduced and handling becomes difficult. If the thickness is more than 600 μm, formation of fine via holes and filling of a conductive material becomes difficult.

An adhesive in a semi-cured state, that is, a B-stage adhesive layer 12 is provided on both surfaces of the insulating base material 10 (see FIG. 1A). A protective film 14 is attached (see FIG. 1 (b)). The adhesive 12 is for adhering a copper foil forming a conductive circuit, for example, an epoxy resin varnish is used, and its layer thickness is preferably in a range of 10 to 50 μm. The protective film 14 is used as a mask for printing a conductive paste described later, and for example, a polyethylene terephthalate (PET) film having a surface provided with an adhesive layer may be used. The PET film 14 has a thickness of the adhesive layer of 1 to 20 μm and a thickness of the film itself of 10 to 50 μm.
Is used.

(2) Next, laser irradiation is performed from above the PET film 14 stuck on the insulating base material 10,
An opening 16 for forming a via hole penetrating the insulating base material is formed (see FIG. 1C). This laser processing is performed by a pulse oscillation type carbon dioxide laser processing apparatus. The processing conditions are preferably such that the pulse energy is 0.5 to 100 mJ, the pulse width is 1 to 100 μs, the pulse interval is 0.5 ms or more, and the number of shots is 3 to 50. The diameter of the opening 16 that can be formed under such processing conditions is desirably 50 to 250 μm. Thereafter, desmear treatment such as oxygen plasma discharge treatment or corona discharge treatment is desirably performed to remove the resin remaining on the inner wall surface of the opening 16 from the viewpoint of ensuring connection reliability.

(3) Next, the conductive paste 18 is filled into the via hole forming opening 16 by printing from the opening formed in the PET film 14 in the step (2),
Alternatively, an electrolytic plating process is performed using the metal foil on the substrate as a plating lead, and the opening 16 is filled with an electrolytic plating layer to form a via hole 20 (see FIG. 1D). On this occasion,
The PET film 14 functions as a printing mask or a plating protection film.

In the method of filling the conductive substance, almost all of the gaps in the opening except for a small portion of the opening 16 formed through the insulating base material are filled with metal plating by plating. After that, a method of filling the opening formed through the PET film 14 and all the gaps in the opening formed through the adhesive layer 12 with the conductive paste, and a method of forming the opening through the insulating base material Opening 16
And an opening formed through the PET film 14,
There is a method of filling all the gaps in the openings formed through the adhesive layer 12 with the conductive paste. In this embodiment, the method described in the following is adopted. As the plating treatment, electrolytic plating treatment is preferable, and particularly, electrolytic copper plating formed by electrolytic copper plating treatment is preferable.
Further, as the conductive paste, a conductive paste composed of at least one kind of metal particles selected from silver, copper, gold, nickel and solder can be used. As the above metal particles,
What coated the different metal on the surface of the metal particle can also be used. Specifically, metal particles in which the surface of copper particles is coated with a noble metal selected from gold and silver can be used.
As such a conductive paste, an organic conductive paste obtained by adding a thermosetting resin such as an epoxy resin or a phenol resin or a thermoplastic resin such as polyphenylene sulfide (PPS) to metal particles is desirable.

In place of the above-mentioned conductive paste, a method of printing using a solder paste that is a low melting point metal, a method of performing a solder plating, or a method of immersing the conductive material in a solder melt is used to fill the opening with the conductive material. The low melting point metal may be a Pb-Sn solder, an Ag-Sn solder, an indium solder, or the like.

(4) After the PET film 14 is peeled off from the surface of the adhesive layer 12 (see FIG. 1E), the copper foil 22 is separated from the insulating base material 10 via the resin adhesive layer 12. The resin adhesive 12 is cured by press-bonding both sides by a hot press (see FIG. 1 (f)). At this time, the copper foil 22 is adhered to the insulating base material 10 via the cured resin adhesive 12, and the conductive paste 18 and the copper foil 22 are electrically connected.
The thickness of the copper foil 22 is preferably 5 to 18 μm. The reason is that when forming an opening for forming a via hole in an insulating base material by laser processing, if the opening is too thin, it will penetrate,
On the other hand, if the thickness is too large, an undercut is formed in the circuit pattern by etching, so that it is difficult to form a fine pattern.

(5) Next, an etching protection film is stuck on the copper foil 22 and a mask having a predetermined pattern is covered, and then an etching process is performed to form a conductor circuit 24 (including a via land) (FIG. 1). (g)). In this processing step, first, a photosensitive dry film resist is attached to the surface of the copper foil 22, or a liquid photosensitive resist is applied, and then exposed and developed along a predetermined circuit pattern to form an etching resist. After that, the metal layer in the portion where the etching resist is not formed is etched to form the conductor pattern 24 including the via land. As the etching solution, at least one aqueous solution selected from aqueous solutions of sulfuric acid hydrogen peroxide, persulfate, cupric chloride, and ferric chloride is desirable. As a pretreatment for etching the copper foil 22 to form the conductor circuit 24, in order to easily form a fine pattern, the entire surface of the copper foil 22 is previously etched to a thickness of 1 to 10 μm, more preferably 2 to 10 μm. ~ 8μ
m. The inner diameter of the via land as a part of the conductor circuit is substantially the same as the diameter of the via hole, but the outer diameter is preferably formed in the range of 50 to 250 μm.

(6) After the etching process, the surface of the conductor circuit 24 formed in the process (5) is roughened (roughened layer is not shown) to form the core circuit board 30.
This roughening treatment is for improving adhesion to the adhesive layer and preventing peeling (delamination) when forming a multilayer. Roughening methods include, for example, soft etching, blackening (oxidation) and one-reduction treatment, formation of a copper-nickel-phosphorus needle-like alloy plating (manufactured by Ebara Uzilite; trade name: Interplate), manufactured by MEC Corporation. Surface roughening by an etching solution called "Mech etch bond".

In this embodiment, the roughened layer is preferably formed by using an etching solution.
For example, it can be formed by etching the surface of a conductor circuit from a mixed aqueous solution of a cupric complex and an organic acid using an etchant. Such an etchant can dissolve the copper conductor circuit under the condition of coexistence of oxygen such as spraying or bubbling, and the reaction is presumed to proceed as follows. Cu + Cu (II) A _n → 2Cu (I) _{An / 2} 2Cu (I) _{An / 2} + n / 4O ₂ + nAH (aeration) → 2Cu (II) A _n + n / 2H ₂ O In the formula, A is a complex. Agent (acting as a chelating agent), n represents the coordination number.

As shown in this formula, the generated cuprous complex dissolves under the action of an acid and combines with oxygen to form a cupric complex, which again contributes to copper oxidation. The cupric complex used in the present invention is preferably a cupric complex of azoles. The etching solution comprising the organic acid-cupric complex can be prepared by dissolving a cupric complex of an azole and an organic acid (halogen ion as required) in water. The etching solution is, for example, an imidazole copper (II) complex
10 parts by weight, 7 parts by weight of glycolic acid, potassium chloride
It is formed from an aqueous solution mixed with 5 parts by weight.

(7) Next, a single-sided circuit board to be laminated on the core circuit board formed in the step (6) is manufactured. In manufacturing this single-sided circuit board for lamination, a metal layer 4
The insulating base material 40 formed with No. 2 is used as a starting material. The insulating base material 40 to be used is formed of a completely cured resin material similarly to the circuit board for the core, for example, a glass cloth epoxy resin base material, an aramid nonwoven fabric-epoxy resin base material, an aramid nonwoven fabric-polyimide base material. A rigid (hard) laminated base material selected from a material and a bismaleimide-triazine resin base material is used. Particularly, a glass cloth epoxy resin base material is preferable. The metal layer 42 formed on one surface of the insulating substrate 40 can use a copper foil. The copper foil may be matted to improve adhesion, and a copper layer formed by subjecting a surface of the insulating substrate 40 to a metal deposition and then performing an electrolytic plating process is used as the metal layer 42. You can also.

The thickness of the insulating substrate 40 is 20 to 60.
0 μm is desirable. The reason is to ensure insulation. If the thickness is less than 20 μm, the strength is reduced and handling becomes difficult, and the reliability for electrical insulation is reduced. If the thickness is more than 600 μm, it becomes difficult to form fine via holes and fill with a conductive material. . On the other hand, the thickness of the metal layer 42 is preferably 5 to 18 μm. The reason is that when forming an opening for forming a via hole in an insulating base material by laser processing, if it is too thin, it penetrates, and if it is too thick, it is difficult to form a fine pattern by etching. . As the insulating base material 40 and the metal layer 42, in particular, a single-sided copper-clad laminate obtained by laminating a prepreg obtained by impregnating an epoxy resin into a glass cloth into a B stage, and laminating a copper foil and pressing the laminate with heat. It is preferable to use a plate. The reason is that the positions of the wiring patterns and the via holes do not shift during handling after the metal layer 42 is etched, and the position accuracy is excellent.

(8) Next, a protective film 44 is attached to the surface of the insulating base material 40 opposite to the surface on which the metal layer 42 is formed (see FIG. 2A). As the protective film 44, a polyethylene terephthalate (PET) film having a surface provided with an adhesive layer may be used.

(9) Then, laser irradiation is performed from above the protective film 44 of the insulating base material 40 to form a via hole forming opening 46 that reaches the metal layer 42 through the protective film 44 and the insulating base material 40. (See FIG. 2B). The opening 46 is formed by a pulse oscillation type carbon dioxide laser processing apparatus. The processing conditions for such a via hole forming opening 46 are such that the pulse energy is 0.5 to 10
0 mJ, a pulse width of 1 to 100 μs, and a pulse interval of 0.
It is desirable that the number of shots be 5 ms or more and the number of shots be in the range of 3 to 50, and the opening diameter of the opening 46 formed under such processing conditions be 50 to 250 μm. Thereafter, desmear treatment such as oxygen plasma discharge treatment or corona discharge treatment is desirably performed to remove the resin remaining on the inner wall surface of the opening 46 from the viewpoint of ensuring connection reliability.

(10) Next, a conductive material 48 is filled in the via hole forming opening 46 formed by laser processing to form a via hole 49. Such a conductive substance 48 is
Similar to the above step (3), it is preferable to form by filling with conductive paste or filling with metal plating by electrolytic plating.

(11) After that, an etching protection film 50 is further applied on the protection film 44 applied on the insulating base material 40 (see FIG. 2C), while the metal layer 42 has a predetermined pattern. After being covered with the mask, etching is performed in accordance with the step (5) to form the conductor circuit 52 (see FIG. 2D). In this processing step, first, a photosensitive dry film resist is attached to the surface of the metal layer 42 or a liquid photosensitive resist is applied, and then exposed and developed along a predetermined circuit pattern to form an etching resist. After that, the metal layer 42 in the portion where the etching resist is not formed is etched to form the conductor pattern 52.

(12) After the etching treatment, the protective film 4
4 and 50 are peeled off (see FIG. 2E), and the surface of the conductor circuit 52 is subjected to a roughening treatment as necessary. This roughening treatment is for improving the adhesion to the adhesive layer and preventing peeling (delamination) when forming a multilayer, and the roughening treatment method is performed according to the above-mentioned step (6). Do.

When the protective film 50 is peeled off from the insulating substrate 40, the conductive material 48 filled in the opening 46 removes the protective film 44 from the surface of the insulating substrate 40.
Projecting portion 53 (hereinafter referred to as a protruding portion 53).
The height of the “projecting conductor” is preferably in the range of 10 to 40 μm. The reason is that if it is less than 10 μm, poor connection is likely to occur, and if it exceeds 40 μm, the resistance value increases, and when the protruding conductor is thermally deformed in the heating press step, it spreads too much along the surface of the insulating substrate. ,
This is because a fine pattern cannot be formed. Further, the protruding conductor formed from the conductive paste is preferably in a pre-cured state. The reason is that the protruding conductor is hard even in a semi-cured state, so it can penetrate the organic adhesive layer softened in the laminating press step described later and make electrical contact with the via holes of other circuit boards to be laminated This is because In addition, the contact area increases due to deformation at the time of hot pressing, so that not only the conduction resistance can be reduced, but also the variation in the height of the projecting conductor can be corrected.

(13) Next, a resin adhesive 54 is applied to the surface of the insulating base material 40 on the side of the protruding conductor 53 (see FIG. 2F). The circuit board for lamination is formed by laminating and bonding a plurality of the circuit boards to each other, or by laminating and bonding to a pre-manufactured circuit board for a core, and the adhesive is used in such a lamination step. . For example, the adhesive layer 54 is formed on the entire surface of the insulating substrate 40 on the side of the protruding conductor 53 and / or the entire surface of the insulating substrate 40 on the side of the conductor circuit 52 and is formed of an uncured resin in a dried state. This adhesive layer
Precuring is preferred for ease of handling, and its thickness is preferably in the range of 5 to 50 μm.

The adhesive layer 54 is preferably made of an organic adhesive. Examples of the organic adhesive include an epoxy resin, a polyimide resin, a phenol resin, a thermosetting polyphenolene ether (PPE), and an epoxy resin. It is desirable that the resin be at least one resin selected from a composite resin with a plastic resin, a composite resin with an epoxy resin and a silicone oil, and BT resin. As a method of applying the uncured resin which is an organic adhesive, a curtain coater, a spin coater, a roll coater, a spray coat, a screen printing, or the like can be used. Further, the formation of the adhesive layer can also be performed by laminating an adhesive sheet.

Immediately after the formation of the conductor circuit, the conductor circuit 52 and the via hole 49 can be inspected, and the presence or absence of a defective portion can be inspected before lamination. In the step of laminating the single-sided circuit board for the core, only a single-sided circuit board having no defect can be used, so that a multi-layered board and a multi-layered circuit board can be manufactured with a high yield.

(B) A plurality of double-sided and single-sided circuit boards, for example, four circuit boards, manufactured by the above-mentioned steps (1) to (13) are stacked on each other to manufacture a multilayer board. (1) First, the core double-sided circuit board 30 and the single-sided circuit boards for lamination 32, 34 and 36 are laminated so as to face each other (see FIG. 3). This superposition is performed by arranging the protruding conductors 53 and the conductor circuits 52 of the adjacent single-sided circuit boards at positions facing each other, that is, the guide holes are formed in guide holes provided around each circuit board. It is performed while positioning by inserting a pin (not shown). The alignment may be performed by image processing.

(2) The laminated four-layer substrate is heated at 150 to 200 ° C. by using a hot press,
a, desirably by hot pressing at 2 to 5 MPa, the circuit boards 30 to 36 are integrated by a single press molding to obtain a multilayer board 60 (see FIG. 4). Here, first, the single-sided circuit board 32 for lamination is pressed by being pressed.
The protrusion-shaped conductor 53 pushes out the uncured adhesive 54 to the surroundings, and the protrusion-shaped conductor 53 comes into contact with the conductor circuit 52 of the double-sided circuit board 30 for a core, thereby making an electrical connection therebetween.
Similarly, the protruding conductor 53 of the single-sided circuit board for lamination abuts on the conductor circuit 52 of the single-sided circuit board for lamination to make an electrical connection therebetween. The two-sided circuit board 30 is electrically connected to the conductor circuit 52 of the core double-sided circuit board 30.

Further, by heating simultaneously with pressing, the adhesive layer 54 of each of the circuit boards 30 to 36 is hardened, and strong bonding is performed between the adjacent single-sided circuit boards. It is preferable to use a vacuum hot press as the hot press. In this way, the projecting conductors of each circuit board are fitted and penetrated into the adhesive layer while heating and pressurizing the laminated four-layer circuit boards at a time, and the conductor circuits facing the projecting conductors are inserted into the adhesive circuit. By connecting and integrating, the multilayer substrate 60 is manufactured. In the above-described embodiment, the multi-layer board is formed by using the four-layer circuit board.

(C) Formation of Build-up Wiring Layer A build-up wiring layer is formed on one surface of the multilayered substrate 60 formed by the steps (A) and (B). FIG.
In FIG. 5, all of the double-sided and single-sided circuit boards constituting the multilayered board 60 are omitted for the purpose of simplification (see FIG. 5A). (1) A roughened layer 62 made of copper-nickel-phosphorus is formed on the surface of the conductor circuit 52 on one side of the multilayer substrate 60 (see FIG. 5B). This roughened layer 62 is formed by electroless plating. The solution composition of the electroless plating aqueous solution has a copper ion concentration, a nickel ion concentration, and a hypophosphite ion concentration of 2.2 × 10 ^{−2 to} 4.1 × 10 ⁻² , respectively.
mol / l, 2.2 × 10 ^{−3 to} 4.1 × 10 ⁻³ m
ol / l, preferably 0.20 to 0.25 mol / l. This is because the crystalline structure of the film deposited in this range has a needle-like structure, and thus has an excellent anchor effect. A complexing agent or an additive may be added to the electroless plating aqueous solution in addition to the above compounds. As a method of forming the roughened layer, as described above, a roughened surface is formed by a treatment using copper-nickel-phosphorus needle-like alloy plating, an oxidation-reduction treatment, and a treatment for etching the copper surface along grain boundaries. There are methods.

(2) Next, an interlayer resin insulating layer 64 is formed on the multilayered substrate 60 having the roughened layer prepared in the above (1) (FIG. 5C). In particular, in the present invention, it is desirable to use an adhesive for electroless plating using a composite of a thermosetting resin and a thermoplastic resin as a resin matrix as an interlayer resin insulating material for forming a via hole 70 described later. Further, a resin film in a semi-cured state may be laminated and used.

(3) After the adhesive layer for electroless plating formed in (2) is dried, an opening 65 for forming a via hole is provided (FIG. 5D). In the case of a photosensitive resin, exposure and development are performed followed by thermosetting, and in the case of a thermosetting resin, thermosetting and then laser processing are performed to form an opening for forming a via hole in the adhesive layer 64. Part 65
Is provided.

(4) Next, the cured epoxy resin particles present on the surface of the adhesive layer 64 are decomposed or dissolved by an acid or an oxidizing agent to remove them, and the surface of the adhesive layer is subjected to a roughening treatment to obtain a rough surface. The surface 66 is shown in FIG. 1 (e). Here, examples of the acid include phosphoric acid, hydrochloric acid, sulfuric acid, and organic acids such as formic acid and acetic acid, and it is particularly preferable to use an organic acid. This is because it is difficult to corrode the metal conductor layer exposed from the via hole when the roughening treatment is performed. On the other hand, it is desirable to use chromic acid and permanganate (such as potassium permanganate) as the oxidizing agent.

(5) Next, the roughened surface 66 on the surface of the adhesive layer 64
To a catalyst core. It is desirable to use a noble metal ion or a noble metal colloid for providing the catalyst nucleus, and generally, palladium chloride or a palladium colloid is used. Note that it is desirable to perform a heat treatment to fix the catalyst core. Palladium is preferred as such a catalyst core.

(6) Further, the surface of the adhesive layer 64 (for electroless plating) is subjected to electroless plating, and an electroless plating film 67 is formed so as to follow the entire roughened surface (FIG. 5).
(F)). At this time, the thickness of the electroless plating film 67 is
The range is preferably from 0.1 to 5 μm, more preferably
0.5 to 3 μm. Next, a plating resist 68 is formed on the electroless plating film 67 (FIG. 6A). As the plating resist composition, it is particularly desirable to use a composition comprising an acrylate of a cresol novolak type epoxy resin or an acrylate of a phenol novolak type epoxy resin and an imidazole curing agent. Alternatively, a commercially available dry film may be used.

(7) Further, a portion where the plating resist is not formed on the electroless plating film 67 is subjected to electrolytic plating to provide a conductor layer on which the upper conductor circuit 72 is to be formed, and to fill the inside of the opening 65 with the electrolytic plating film 69. Then, a via hole 70 is formed (FIG. 6B). At this time, the thickness of the electrolytic plating film 9 exposed outside the opening 5 is preferably 5 to 30 μm. Here, it is desirable to use copper plating as the electrolytic plating.

(8) Further, after removing the plating resist 68, a mixed solution of sulfuric acid and hydrogen peroxide, sodium persulfate,
The electroless plating film under the plating resist is dissolved and removed with an etching solution such as ammonium persulfate to form an independent upper conductor circuit 72 and a filled via hole 70.

(9) Next, the surface of the upper conductor circuit 72 is roughened.
A layer 74 is formed. As a method for forming the roughened layer 74,
Etching, polishing, oxidation-reduction and plating
is there. Of these treatments, the oxidation-reduction treatment is NaOH
(20 g / l), NaClO _Two(50 g / l), NaP
O₄(15.0 g / l) as an oxidation bath (blackening bath)
OH (2.7 g / l), NaBH₄(1.0 g / l)
Use as a reducing bath. In addition, the copper-nickel-phosphorus alloy layer
Roughened layer is formed by deposition by electroless plating.
It is.

The electroless plating solution for this alloy is as follows: copper sulfate 1 to 40 g / l, nickel sulfate 0.1 to 6.0 g / l
l, citric acid 10-20 g / l, hypophosphite 10-1
00g / l, boric acid 10-40g / l, surfactant 0.
It is desirable to use a plating bath having a liquid composition of from 01 to 10 g / l. Further, the surface of the roughened layer 74 is covered with a layer of a metal or a noble metal whose ionization tendency is greater than copper and equal to or less than titanium. In the case of tin, tin borofluoride-thiourea or tin chloride-thiourea liquid is used. At this time, an Sn layer having a thickness of about 0.1 to 2 μm is formed by the substitution reaction of Cu—Sn. In the case of a noble metal, a method such as sputtering or vapor deposition can be adopted.

(10) Next, an adhesive layer 76 for electroless plating is formed as an interlayer resin insulating layer on the substrate. (11) Further, by repeating the above steps (3) to (9), another via hole 80 is provided directly above the via hole 70 and the upper conductor circuit 8 is further disposed outside the upper conductor circuit 72.
2 and a roughened layer 84 are provided (see FIG. 6C). The surface of the via hole 80 is formed as a conductor pad functioning as a solder pad.

(12) Next, a solder resist composition 90 is applied to the outer surface of the wiring substrate thus obtained, and the coating film is dried. Then, a photomask film in which an opening is drawn is applied to the coating film. An opening 91 exposing a solder pad (including a conductor pad and a via hole) in the conductor layer is formed by mounting, exposing, and developing (see FIG. 7A). Here, the opening diameter of the exposed opening can be larger than the diameter of the solder pad, and the solder pad may be completely exposed. Conversely, the opening diameter of the opening can be made smaller than the diameter of the solder pad.
0 can be coated. In this case, the solder pads can be suppressed by the solder resist layer 90, and peeling of the solder pads can be prevented.

(13) Further, the solder resist layer 9
A metal layer made of “nickel-gold” is formed on the solder pad exposed from the opening 91 of the “0”. The thickness of the nickel layer 92 is preferably 1 to 7 μm, and the thickness of the gold layer is 0.01 to 0.1 μm.
06 μm is preferred. The reason for this is that if the nickel layer 92 is too thick, it causes an increase in the resistance value, and if it is too thin, it is easy to peel off. On the other hand, if the gold layer 94 is too thick, the cost increases, and if it is too thin, the effect of adhering to the solder body is reduced.

(14) Further, the conductor circuit exposed from the opening 91 (opening located above) in one of the solder resist layers located on the outermost side of the build-up wiring layer formed on one side of the multilayer substrate. (Solder pad)
The solder body is supplied to form the solder bumps 96, and the solder body is supplied to the conductor circuit 52 (solder pad) exposed on the surface of the multi-layer substrate on the side where the build-up wiring layer is not formed. 96 or solder ball 1
By forming 00, a multilayer circuit board is manufactured (see FIG. 7B).

As a method for supplying the solder body, a solder transfer method or a printing method can be used. Here, in the solder transfer method, a solder foil is bonded to a prepreg, and the solder foil is etched leaving only a portion corresponding to an opening, thereby forming a solder pattern to form a solder carrier film. This is a method of applying a flux to a solder resist opening portion of a substrate, laminating a film so that a solder pattern is in contact with a pad, and heating and transferring the film. On the other hand, the printing method is a method in which a printing mask (metal mask) having a through-hole provided in a portion corresponding to a pad is placed on a substrate, and a solder paste is printed and heat-treated. As the solder, tin-silver, tin-indium, tin-zinc, tin-bismuth and the like can be used.

As the solder body for forming the conductive bumps 96, tin / lead solder (melting point: 183 ° C.) or tin / silver solder (melting point: 220 ° C.) having a relatively low melting point is used.
As a solder body for connecting the conductive pins 98 and the conductive balls 100, tin / antimony solder, tin / silver solder, tin / silver solder having a relatively high melting point of 230 ° C. to 270 ° C.
Preferably, a silver / copper solder is used.

[0088]

EXAMPLES (Example 1) (1) A single-sided copper-clad laminate obtained by laminating a prepreg in which epoxy resin is impregnated in a glass cloth into a B stage and a copper foil and pressing the laminate with heat is used as a substrate. To manufacture a double-sided circuit board. The thickness of the insulating base material 10 was 75 μm, and the thickness of the copper foil 12 was 12 μm. On the surface of the laminate opposite to the surface on which the copper foil is formed, a pressure-sensitive adhesive layer having a thickness of 10 μm is provided.
A μm PET film 14 is laminated.

(2) Then, a non-through hole 16 for forming a via hole reaching the copper foil 12 is formed by irradiating a pulse oscillation type carbon dioxide laser from above the PET film 14, and further, electrolytic copper plating is performed using the copper foil 12 as a plating lead. By performing the treatment, the interior of the non-through hole is filled with electrolytic copper plating 18 leaving a slight gap above the non-through hole 16 to form a filled via hole 20.

In this embodiment, a non-through hole for forming a via hole is formed by using a high peak short pulse oscillation type carbon dioxide laser processing machine made by Mitsubishi Electric Co., Ltd. Laminated to
A glass film epoxy resin substrate having a thickness of 75 μm was irradiated with a laser beam from the PET film side by a mask image method, and an opening for forming a 150 μmφ via hole was formed at a speed of 100 holes / sec.

(3) Using the PET film 14 as a printing mask, the conductive paste 22 is inserted from the opening formed by the laser irradiation into the gap remaining above the filled via hole 20.
Was charged.

(4) Insulating the PET film 14 with the insulating substrate 1
0, on the surface of the insulating substrate 10 on the side of the via hole 20, the projecting conductor 2 just above the via hole 20.
4 are formed. Further, an epoxy resin adhesive is applied to the entire surface on the protruding conductor side, and dried at 100 ° C. for 30 minutes to form an adhesive layer 26 having a thickness of 20 μm.
A 2 μm copper foil 28 is heated at 180 ° C. for a heating time of 70
Then, under the conditions of a pressure of 2 MPa and a degree of vacuum of 2.5 × 10 ³ Pa, hot pressing is performed on the adhesive layer 26.

(5) Thereafter, the copper foils 12 and 28 on both sides of the substrate were subjected to an appropriate etching treatment to form conductor circuits 30 and 32 (including via lands), thereby producing a double-sided circuit board 34 for a core.

(6) Next, a single-sided circuit board for lamination is manufactured. This circuit board uses a single-sided copper-clad laminate as a substrate, like the double-sided circuit board. The thickness of the insulating substrate 10 is 7
5 μm, and the thickness of the copper foil 12 is 12 μm. On the surface of the laminate opposite to the surface on which the copper foil is formed, a PET film having a 10 μm-thick pressure-sensitive adhesive layer and a 12 μm-thick film itself is used.
The film 14 is laminated.

(7) Next, the conductive paste 22 is filled in the small gaps between the filled via holes 20 by performing the processing according to the steps (2) and (3) to form the projecting conductors 44. .

(8) Covering the PET film 14,
22μm thick PET as etching protection film
After attaching the film 25, the copper foil 12 attached to the surface of the insulating substrate 10 opposite to the filling via hole 20 is subjected to an appropriate etching treatment to form the conductor circuit 40.

(9) Thereafter, when the PET films 14 and 25 are all peeled off from the insulating base material 10, a projecting conductor 44 is formed on the surface of the insulating base material 10 on the via hole 20 side directly above the via hole 20. You. Further, an epoxy resin adhesive is applied to the entire surface of the projecting conductor side and precured to form an adhesive layer 46 for multilayering. Three such single-sided circuit boards for lamination are manufactured.

(10) Using the single-layer double-sided circuit board 34 formed by the processes (1) to (9) as a core,
Three-layered single-sided circuit boards 50, 52 and 54 are stacked on predetermined positions on both sides thereof (see FIG. 3), and laminated and pressed at a temperature of 180 ° C. using a vacuum hot press so that all the layers are I-shaped.
A multilayer core substrate 60 having a VH structure was created (see FIG. 4). In the multilayer core substrate 60 manufactured as described above, L / S = 75 μm / 75 μm, and the land diameter is 250 μm.
m, via hole diameter is 150 μm, and conductor layer thickness is 12
μm, and the thickness of the insulating layer was 75 μm. Since the multilayer circuit board of the present invention is manufactured by forming a build-up wiring layer on one surface of the multilayer core board 60, the multilayer core board 60 is formed before the build-up wiring layer is formed.
A protective film (not shown) is stuck on one side of.

(11) Next, a multilayer core substrate 60 having a protective film adhered to one side thereof was coated with copper sulfate 8 g / l, nickel sulfate 0.6 g, citric acid 15 g / l, sodium hypophosphite 29 g / l, Boric acid 31 g / l, surfactant 0.
It was immersed in a 1 g / l electroless plating solution having a pH of 9 to form a 3 μm-thick roughened layer 62 made of copper-nickel-phosphorus on the surface of the conductor circuit 40 on one side of the multilayer core substrate 60. Next, the substrate was washed with water, and 0.1 mol /
A tin layer of 0.3 μm was provided on the surface of the roughened layer 63 by immersing it in an electroless tin displacement plating bath composed of l-boron fluoride-1.0 mol / l thiourea solution at 50 ° C. for 1 hour (FIG. 5 (b), but the tin layer is not shown).

(12) The composition obtained below was mixed and stirred to prepare an adhesive for electroless plating. Cresol novolak epoxy resin (Nippon Kayaku,
35 parts by weight (solid content: 80%) of a 25% acrylate having a molecular weight of 2500), 4 parts by weight of a photosensitive monomer (Aronix M315, manufactured by Toa Gosei), an antifoaming agent (S-65, manufactured by San Nopco)
0.5 parts by weight and 3.6 parts by weight of NMP were mixed with stirring. After mixing 8 parts by weight of polyether sulfone (PES) and 7.245 parts by weight of an epoxy resin particle (manufactured by Sanyo Kasei Co., Ltd., polymer pole) having an average particle size of 0.5 μm, 20 parts by weight of NMP were further added and stirred. Mixed. 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), a photoinitiator (Irgacure I-90, manufactured by Ciba-Geigy)
7) 2 parts by weight, photosensitizer (Nippon Kayaku, DETX-S) 0.2
Parts by weight and 1.5 parts by weight of NMP were mixed with stirring.

(13) The adhesive for electroless plating prepared in the above (12) is applied to the substrate 60 which has been treated in the above (11) (see FIG. 5 (c)), and dried to form an adhesive layer. A photomask film on which a black circle of 85 μmφ was printed was brought into close contact with both surfaces of the formed substrate 60, and was exposed at 500 mJ / cm ² by an ultra-high pressure mercury lamp. This is DMDG
By performing spray development with a (diethylene glycol dimethyl ether) solution, an opening 65 serving as a 85 μmφ via hole was formed in the adhesive layer. Further, the substrate was exposed to 3000 mJ / cm ² by an ultra-high pressure mercury lamp,
By performing a heat treatment at 00 ° C. for 1 hour and then at 150 ° C. for 5 hours, a 35 μm-thick interlayer insulating material layer 64 (adhesive layer) having openings with excellent dimensional accuracy corresponding to a photomask film is formed. (See FIG. 5D). The tin plating layer was partially exposed in the opening 65 serving as a via hole.

(14) The substrate on which the via-hole forming openings 65 are formed is immersed in chromic acid for 20 minutes to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer, and the surface of the adhesive layer 64 is subjected to Rmax. The surface was roughened to a depth of about 1 to 5 μm to form a roughened surface 66, which was then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water.

(15) By applying a palladium catalyst (manufactured by Atotech) to the roughened layer 66 (roughened depth 3.5 μm) on the surface of the adhesive layer, the adhesive layer 64 and the opening 65 for forming a via hole are formed. Catalyst nuclei were provided on the surface.

(16) The substrate was immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 67 having a thickness of 0.6 μm on the entire roughened surface (FIG. 5F). reference). At this time, since the electroless plating film 67 was thin, irregularities following the roughened surface 66 of the adhesive layer 64 were observed on the film surface. [Electroless plating solution] NiSO _4: 0.003 mol / l tartaric acid: 0.20 mol / l copper sulfate: 0.03mol / l HCHO: 0.05mol / l NaOH: 0.10mol / l α, α'- bipyridyl: 40 mg / l polyethylene glycol (PEG): 0.1 g / l [Electroless plating conditions] Liquid temperature of 33 ° C

(17) A commercially available photosensitive dry film is stuck on the electroless copper plating film 67 formed in the above (16), a mask is placed, and exposure is performed at 100 mJ / cm ² .
It was developed with 0.8% sodium carbonate to provide a plating resist 68 having a thickness of 15 μm (see FIG. 6A).

(18) Next, plating is performed under the following conditions.
Electroless plating is applied to the non-resist area, and the thickness is 20μm
To form an upper conductor circuit 72
At the same time that the conductor layer to be provided is provided, the plating film 69 is formed in the opening.
To form a via hole 70 (see FIG. 6B).
See). [Aqueous electrolytic plating solution] Copper sulfate pentahydrate: 60 g / l Leveling agent (manufactured by Atotech, HL): 40 ml / l Sulfuric acid: 190 g / l Brightening agent (manufactured by Atotech, UV): 0.5 ml / l chloride ion : 40 ppm [Electroplating conditions] Bubbling: 3.0 l / min Current density: 0.5 A / dm²  Set current value: 0.18 A Plating time: 130 minutes

(19) After the plating resist 68 is peeled off and removed, the electroless plating film 67 under the plating resist is dissolved and removed with a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate and ammonium persulfate. And a thickness of about 2 composed of the electroless plating film 67 and the electrolytic copper plating film 69.
0 μm, L / S = 25 μm / 25 μm Upper layer conductor circuit 7
2 was formed. At this time, the surface of the via hole 70 was flat, and the level of the conductor circuit surface was the same as that of the via hole surface.

(20) The substrate is subjected to the same treatment as in (11) to form a roughened layer 84.
(19) are repeated to further laminate the upper interlayer resin insulating layer 76 and the conductor circuit 82 (including the via hole 80) to obtain a three-layered build-up wiring layer on one side (FIG. 7A )reference). Here, a roughened layer 84 made of copper-nickel-phosphorus is provided on the surface of the conductor circuit 82,
No tin substitution plating layer is formed on the surface of the roughened layer 84.

(21) On the other hand, 60 dissolved in DMDG
46.67 parts by weight of a sensitizing oligomer (molecular weight 4000) obtained by acrylated 50% of an epoxy group of a cresol nopolak type epoxy resin (manufactured by Nippon Kayaku Co.)
80% by weight bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, Epicoat 1)
001) 14.121 parts by weight, imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals) 1.6 parts by weight, polyvalent acrylic monomer which is a photosensitive monomer (Nippon Kayaku, R6
04) 1.5 parts by weight, 30 parts by weight of a polyvalent acrylic monomer (manufactured by Kyoeisha Chemical, DPE6A) and 0.36 parts by weight of a leveling agent made of an acrylate ester polymer (manufactured by Kyoeisha, Polyflow No. 75) were also mixed. Penzophenone (Kanto Chemical) as a photoinitiator for this mixture
20 parts by weight, 0.2 parts by weight of EAB (manufactured by Hodogaya Chemical) as a photosensitizer, 10 parts by weight of DMDG (diethylene glycol dimethyl ether) were added, and the viscosity was 1.4 ± 0.3 pa · s was obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type) at 60 rpm.
In the case of No. 4, rotor No. 4 was used, and in the case of 6 rpm, rotor No. 3 was used.

(22) The solder resist composition obtained in the above (21) was applied to a thickness of 20 μm on the surface of the build-up wiring layer obtained in the above (20). Then
After drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a 5 mm thick soda lime glass substrate on which a circular pattern (mask pattern) of a solder resist opening is drawn by a chromium layer is placed on a chrome layer. The side on which was formed was brought into close contact with the solder resist layer, exposed to ultraviolet light of 1000 mJ / cm ² , and subjected to DMTG development treatment. In addition, 80
1 hour at 100 ° C, 1 hour at 100 ° C, 1 hour at 120 ° C,
Heat treatment was performed at 50 ° C. for 3 hours to form a solder resist layer 90 (thickness: 20 μm) with an opening in the pad portion (opening diameter: 200 μm).

(23) Next, the substrate on which the solder resist layer 90 was formed was replaced with nickel chloride 30 g / 1, sodium hypophosphite 10 g / 1, sodium citrate 10 g / 1.
Immersed in an electroless nickel plating solution having a pH of 5 for 20 minutes to form a nickel plating layer 92 having a thickness of 5 μm on the opening.
Was formed. Further, the substrate was placed on an electroless gold plating solution composed of gold cyanide 2 g / 1, ammonium chloride 75 g / 1, sodium citrate 50 g / 1, and sodium hypophosphite 10 g / 1 at 93 ° C. for 23 hours. By immersion for 2 seconds, a gold plating layer 94 having a thickness of 0.03 μm was formed on the nickel plating layer 92.

(24) Then, after the protective film adhered to one surface of the multilayer substrate 60 is peeled off in the step (11), the conductor circuit 40 (solder pad) formed on one surface of the multilayer substrate 60 is removed. ), A solder paste made of tin / antimony solder having a melting point of 230 ° C. is printed, and reflow is performed at an ambient temperature near the melting point, so that the T pin 96 or the solder ball 100 is fixed on the solder pad, and build-up wiring Layer of solder resist layer 90
A solder paste made of tin / lead solder having a melting point of 183 ° C. is printed on the gold plating layer 94 (solder pad) exposed from the opening of the solder pad, and the solder paste is reflowed at an ambient temperature near the melting point. The multilayer circuit board was manufactured by forming the bumps 96 (see FIG. 7B).

In the multilayer circuit board manufactured in this manner, the land shape of the via hole of the multilayer core substrate can be made a perfect circle, and the land pitch can be set to about 600 μm. Densification can be easily achieved. In addition, since the number of via holes in the multilayer core substrate can be increased, electrical connection between the conductor circuits in the multilayer core substrate and the conductor circuits in the build-up wiring layer can be sufficiently ensured. Also, it is connected to an electronic component including a semiconductor chip such as an LSI via a solder bump 96 formed on a gold plating layer 94 (solder pad) exposed from an opening of a solder resist layer 90 provided outside the build-up wiring layer, Conductive pins 98 formed on conductor circuits 40 (solder pads) on one side of a multilayer core substrate
Alternatively, since it is connected to a connection terminal or the like on the motherboard via the conductive ball 100, high-density mounting of electronic components becomes possible.

(Example 2) A non-through hole for forming a via hole of a double-sided circuit board and a single-sided circuit board constituting a multilayer core board is filled with a conductive paste to form a via hole, and the same process as that for forming the via hole is performed. A multilayer circuit board was manufactured in the same manner as in Example 1 except that a conductive paste was filled on the via hole to form a projecting conductor.

Example 3 An interlayer resin insulating layer having a thickness of 20
An epoxy resin film having a diameter of 60 μm is formed by thermocompression bonding of an epoxy resin film having a diameter of 60 μm, and an opening for forming a via hole having a diameter of 60 μm is provided. A multilayer circuit board was manufactured in the same manner as in Example 1 except that the roughening treatment was performed. The epoxy resin film is preferably a resin composite with a phenoxy resin, and contains particles for forming a roughened layer.

Example 4 A non-through hole for forming a via hole of a double-sided circuit board and a single-sided circuit board constituting a multilayer core board is filled with a conductive paste to form a via hole, and the same process as that for forming the via hole is performed. A multilayer circuit board was manufactured in the same manner as in Example 3, except that a conductive paste was filled on the via hole to form a projecting conductor.

Example 5 An interlayer resin insulating layer was formed to a thickness of 20 μm.
m is formed by thermocompression bonding of a polyolefin resin film, and an opening for forming a via hole having a diameter of 60 μm is provided by irradiating a carbon dioxide laser, and then, instead of forming an electroless plating film, without performing a roughening treatment. A 0.1 μm thick Cu sputtered film or Cu—N film on the surface of the interlayer resin insulating layer including the inner wall surface of the opening by sputtering.
A multilayer circuit board was manufactured in the same manner as in Example 1 except that an i-sputtered film was formed.

(Example 6) A non-through hole for forming a via hole of a double-sided circuit board and a single-sided circuit board constituting a multilayer core board is filled with a conductive paste to form a via hole, and the same process as that for forming the via hole is performed. A multilayer circuit board was manufactured in the same manner as in Example 5, except that a conductive paste was filled in the via hole to form a projecting conductor.

Comparative Example (1) An insulating substrate formed of a 0.8 μm-thick double-sided copper-clad laminate was used as a core substrate, and a through hole having a diameter of 300 μm was drilled in the core substrate using a drill. Conducting plating and electrolytic plating to form a conductor layer including through-holes, further providing a roughened layer on the entire surface of the conductor layer including through-holes, and filling the through-holes with a non-conductive filling material for filling holes. And dried and cured. (2) Next, the filler protruding from the through-hole is removed and flattened, and the surface thereof is subjected to electroless plating and electrolytic plating to be thickened to cover the conductor circuit and the conductor covering the filler filled in the through-hole. A layer portion was formed. (3) An etching resist is formed on the surface of the substrate on which a portion serving as a conductive layer covering the conductive circuit and the filler filled in the through holes is formed, and the plating film in a portion where the etching resist is not formed is removed by etching. The etching resist was peeled off to form a conductor layer covering the independent conductor circuit and the filler. Further, a multilayer circuit board was manufactured according to the same steps as (11) to (23) of Example 1.

For the above Examples 1 to 6 and Comparative Example,
The wiring length from the IC chip to the solder bumps, BGA (ball grid array) or PGA (pin grid array) and the number of core lands formed were checked.
It was possible to reduce the number of core lands per unit area (cm ² ) by 10 to 30% by reducing the number of core lands by 0 to 25%.

[0121]

As described above, according to the multilayer circuit board of the present invention, a large number of circuit boards having fine filled via holes and conductive circuits formed by laser processing are laminated and hot-pressed at once. Since the build-up wiring layer is formed on one side of the multi-layer board, the wiring in the multi-layer board can be made denser, and the electrical connection with the build-up wiring layer can be made without providing through holes as in the past. It can be sufficiently ensured through the filled via hole.

Further, since the number of build-up wiring layers can be reduced, the thickness of the entire wiring board including electronic components including semiconductor chips such as LSIs mounted on the wiring board can be reduced. The effect can be obtained.

Further, conductive bumps are provided on the conductor pads exposed in the openings provided in the solder resist layer of the build-up wiring layer, ie, on the solder pads immediately above the via holes, so that the build-up wiring layer of the multi-layer substrate is formed. A conductive pin or a conductive ball is disposed on a conductive circuit (solder pad) exposed on the surface on which the is not formed, so that the wiring layer in the build-up wiring layer is formed by a conductive bump directly above the via hole. And the wiring layer in the multi-layer substrate is connected to the motherboard with the shortest wiring length via conductive pins or conductive balls directly above the filled via holes. Thus, high-density wiring and high-density mounting of electronic components can be realized.

Further, since the multilayered substrate has a structure in which a single-sided or double-sided circuit board is formed of the same material and is laminated, cracks and peeling at the interface originating from thermal expansion hardly occur. Test reliability is also improved. In addition, when a multi-layer substrate is formed using only a single-sided circuit board, an effect that warpage hardly occurs irrespective of whether or not wiring is formed is also obtained.

[Brief description of the drawings]

FIGS. 1 (a) to 1 (f) are views showing a part of a manufacturing process of a multilayer substrate as a base of a multilayer circuit board according to the present invention.

2 (a) to 2 (e) are views showing a part of a manufacturing process of a multilayer substrate as a base of the multilayer circuit board according to the present invention.

FIG. 3 is a diagram illustrating a part of a manufacturing process of a multilayered substrate serving as a base of the multilayered circuit board according to the present invention.

FIG. 4 is a view showing a multilayered board in a multilayer circuit board according to the present invention.

FIGS. 5A to 5F are views showing a part of a manufacturing process of a multilayer circuit board according to the present invention.

FIGS. 6A to 6C are diagrams illustrating a part of a manufacturing process of the multilayer circuit board according to the present invention.

FIGS. 7A and 7B are diagrams illustrating a part of the manufacturing process of the multilayer circuit board according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Insulating base material 12 Adhesive 14 Protective film 16 Via hole forming opening 18 Conductive paste 20 Via hole 22 Copper foil 24 Conductive circuit 30 Double-sided circuit board 32, 34, 36 Single-sided circuit board 40 Insulating base material 42 Copper foil 44 PET Film 46 Via hole forming opening 48 Conductive paste 49 Via hole 50 Etching protection film 52 Conductive circuit 53 Projecting conductor 54 Adhesive layer 60 Multi-layer substrate 62 Roughening layer 64 Electroless plating adhesive layer 65 Via hole forming opening 66 Rough Layer 67 Electroless plating film 68 Plating resist 69 Electroplating film 70 Via hole 72 Conductor circuit 74 Roughening layer 76 Adhesive layer for electroless plating 80 Via hole 82 Conductor circuit 84 Roughening layer 90 Solder resist layer 92 Nickel plating layer 94 Gold Plating layer 96 It bumps 98 T pin 100 solder ball

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H05K 3/46 H05K 3/46 X H01L 23/12 1/03 610L H05K 1/03 610 610N 1/11 N 1/11 3/00 N 3/00 H01L 23/12 NF term (reference) 5E317 AA24 BB01 BB02 BB03 BB12 CC25 CC33 CC53 CD32 GG14 5E346 AA04 AA05 AA06 AA12 AA22 AA32 AA43 AA51 BB15 BB16 CC02 CC04 CC09 CC32 DD02 DD12 DD25 DD25 DD25 EE09 EE13 EE15 EE19 EE33 EE38 FF06 FF07 FF09 FF10 FF12 FF18 FF24 FF35 FF45 GG15 GG17 GG18 GG19 GG22 GG25 GG27 GG28 HH11 HH22 HH25

Claims (9)

[Claims] 1. A build-up wiring layer in which interlayer resin insulation layers and conductor layers are alternately laminated on one surface of a multilayer substrate having a conductor circuit in an inner layer, and each conductor layer is connected by a via hole. In the multilayer circuit board formed by the above, the multilayered substrate has a conductor circuit on one or both surfaces of an insulating hard base material, and in a hole that penetrates the insulating hard base material and reaches the conductor circuit A plurality of circuit boards having via holes filled with a conductive substance are formed by laminating via an adhesive layer and hot-pressing collectively, and further, the outermost of the build-up wiring layer The surface of the conductor layer of
A solder bump connected to an electronic component including a semiconductor chip such as an LSI is provided immediately above the via hole, and a conductive circuit exposed on the other surface of the multilayer substrate is provided immediately above the filled via hole. Wherein a conductive pin or a conductive ball connected to the motherboard is provided. 2. The multilayer circuit board according to claim 1, wherein the conductive material is a conductive paste made of metal particles and a thermosetting resin or a thermoplastic resin. 3. The multilayer circuit board according to claim 1, wherein the conductive material layer is electrolytic copper plating formed by an electrolytic plating process. 4. A circuit board according to claim 1, wherein each of the circuit boards constituting the multilayer board has a projecting conductor electrically connected to the via hole corresponding to the via hole position. 4. The multilayer circuit board according to any one of 3. 5. The multilayer circuit board according to claim 4, wherein the projecting conductor is formed from a conductive paste. 6. The via hole of the build-up wiring layer, wherein a part of the via hole is located immediately above the via hole formed in the multilayer substrate and is directly connected to the via hole. 6. The multilayer circuit board according to any one of 5. 7. The insulating substrate of each of the circuit boards constituting the multi-layer substrate is a glass cloth epoxy resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, an aramid non-woven epoxy resin. The multilayer circuit board according to any one of claims 1 to 6, wherein the multilayer circuit board is formed from any one of a hard base material selected from a resin base material and an aramid nonwoven fabric-polyimide resin base material. 8. The insulating substrate of each circuit board constituting the multilayer substrate is formed of a glass cloth epoxy resin substrate having a thickness of 20 to 100 μm, and the filled via hole diameter is 5 μm.
The multilayer circuit board according to claim 7, wherein the thickness is from 0 to 250 m. 9. The via hole of each circuit board constituting the multilayer substrate has a pulse energy of 0.5 to 100 m.
J, pulse width 1 ~ 100μs, pulse interval 0.5ms
9. The multilayer circuit according to claim 8, wherein the number of shots is 3 to 50, and the opening is formed with respect to the opening formed by the carbon dioxide laser irradiated onto the surface of the glass cloth epoxy resin base material. substrate.