JP2007042706A - Component built-in wiring board - Google Patents

Component built-in wiring board Download PDF

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JP2007042706A
JP2007042706A JP2005222518A JP2005222518A JP2007042706A JP 2007042706 A JP2007042706 A JP 2007042706A JP 2005222518 A JP2005222518 A JP 2005222518A JP 2005222518 A JP2005222518 A JP 2005222518A JP 2007042706 A JP2007042706 A JP 2007042706A
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insulating layer
wiring pattern
wiring
wiring board
component
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JP5100989B2 (en
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Kenji Sasaoka
賢司 笹岡
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a component built-in wiring board which hardly loses reliability as a wiring board even if components are incorporated therein. <P>SOLUTION: The component built-in wiring board comprises a first insulation film, a second insulation film stacked on the first insulation layer; an electric or electronic component embedded in the second insulation film; a wiring pattern which is formed between the first and second insulation films and includes patterns which are smaller in size in projection view in a board thickness direction than those of terminals of the electric or electronic component, and serve as lands for mounting the electric or electronic components and a soldering portion for connecting the terminals of the electric or electronic component and the mounting lands. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、絶縁板中に電気/電子部品を埋設して有する部品内蔵配線板に係り、特に、部品内蔵によって配線板としての信頼性が低下することを防止するのに好適な部品内蔵配線板に関する。   The present invention relates to a component built-in wiring board having an electric / electronic component embedded in an insulating plate, and in particular, a component built-in wiring board suitable for preventing deterioration of reliability as a wiring board due to the built-in component. About.

部品内蔵配線板の従来技術として下記特許文献1に開示されたものがある。同文献図1に示されるその構造によると、電気部品の配線層への電気的接続には半田(または導電性組成物)が用いられている。その製造方法は、あらかじめ、コアとなる配線板に半田(または導電性組成物)を用いて電気部品を電気的・機械的に接続する。またこれとは別の絶縁樹脂層に穴あけを行いこの穴に導電性組成物を充填し、先に部品実装したコア板と位置合わせ配置して積層・一体化する。   As a prior art of a component built-in wiring board, there is one disclosed in Patent Document 1 below. According to the structure shown in FIG. 1 of the same document, solder (or a conductive composition) is used for electrical connection of the electrical component to the wiring layer. In the manufacturing method, electrical components are electrically and mechanically connected to a wiring board serving as a core in advance using solder (or a conductive composition). In addition, a hole is formed in another insulating resin layer, and the hole is filled with a conductive composition, aligned and arranged with the core plate on which the component has been previously mounted, and laminated and integrated.

コアとなる配線板への電気部品の半田による接続では、その接続ランドが電気部品の外側にも広がりこれにより電気部品の側面にはフィレットが形成されている。同文献には、接続ランドと部品とのサイズの関係や、実装材料(半田)の量および配置についてはこれ以上の開示はない。
特開2003−197849号公報
In the connection of the electrical component to the core wiring board by solder, the connection land extends to the outside of the electrical component, thereby forming a fillet on the side surface of the electrical component. This document does not disclose any more about the size relationship between the connection land and the component, and the amount and arrangement of the mounting material (solder).
JP 2003-197849 A

実装材料として半田を使用して内層に部品を実装した構造の部品内蔵配線板では、2次実装時に内部の半田が再溶融することがあり、これにより半田が体積膨張する。このような体積膨張は、周囲の樹脂にクラックやデラミネーションなどの欠陥を発生させる元凶となり得る。   In a component built-in wiring board having a structure in which a component is mounted on an inner layer using solder as a mounting material, the internal solder may be remelted during secondary mounting, which causes volume expansion of the solder. Such volume expansion can be a cause of defects such as cracks and delamination in the surrounding resin.

本発明は、絶縁板中に電気/電子部品を埋設して有する部品内蔵配線板において、部品内蔵によっても配線板としての信頼性が低下しにくい部品内蔵配線板を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a component built-in wiring board in which an electrical / electronic component is embedded in an insulating plate, and the reliability as a wiring board is not easily lowered even if the component is embedded.

上記の課題を解決するため、本発明に係る部品内蔵配線板は、第1の絶縁層と、前記第1の絶縁層に対して積層状に位置する第2の絶縁層と、前記第2の絶縁層に埋め込まれた電気/電子部品と、前記第1の絶縁層と前記第2の絶縁層とに挟まれて設けられ、かつ、前記電気/電子部品の端子の板厚み方向投影図形に内包される大きさのパターンを該電気/電子部品の実装用ランドとして有する配線パターンと、前記電気/電子部品の前記端子と前記実装用ランドとを接続する半田部とを具備することを特徴とする。   In order to solve the above-described problem, a component built-in wiring board according to the present invention includes a first insulating layer, a second insulating layer positioned in a stacked manner with respect to the first insulating layer, and the second insulating layer. An electric / electronic component embedded in an insulating layer, provided between the first insulating layer and the second insulating layer, and included in a projected thickness direction figure of a terminal of the electric / electronic component And a solder pattern for connecting the terminals of the electrical / electronic components and the mounting lands. .

すなわち、第2の絶縁層に埋め込まれた電気/電子部品は、その実装用ランドが第1および第2の絶縁層に挟まれて位置する配線パターンによって提供され、ここで、この実装用ランドが、電気/電子部品の端子の板厚み方向投影図形に内包される大きさとなっている。これにより、電気/電子部品と実装用ランドとを接続する半田の量を極めて少なくでき、かつ接続後の半田部は電気/電子部品の端子の板厚み方向投影図形より外には広がらない。つまり、半田部の再溶融が生じた場合であってもその体積膨張は小さく抑えられ、周囲の樹脂(絶縁層)にクラックやデラミネーションなどの欠陥を発生させることを効果的に防止する。よって配線板としての信頼性が低下しにくい。   That is, the electrical / electronic component embedded in the second insulating layer is provided by a wiring pattern in which the mounting land is located between the first and second insulating layers, where the mounting land is The size is included in the projected figure in the thickness direction of the terminals of the electrical / electronic components. As a result, the amount of solder connecting the electric / electronic component and the mounting land can be extremely reduced, and the solder portion after the connection does not spread outside the projected figure in the plate thickness direction of the terminal of the electric / electronic component. That is, even when the remelting of the solder portion occurs, the volume expansion is suppressed small, and it is possible to effectively prevent the surrounding resin (insulating layer) from generating defects such as cracks and delamination. Therefore, the reliability as a wiring board is not easily lowered.

本発明によれば、絶縁板中に電気/電子部品を埋設して有する部品内蔵配線板において、部品内蔵によっても配線板としての信頼性が低下しにくい部品内蔵配線板を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, in the component built-in wiring board which embeds the electrical / electronic component in the insulating board, the component built-in wiring board which cannot easily reduce the reliability as a wiring board even if the component is embedded can be provided.

本発明の実施態様として、前記第2の絶縁層が、少なくとも2つの絶縁層の積層であり、前記少なくとも2つの絶縁層の間に挟まれて設けられた第2の配線パターンと、前記第2の絶縁層の積層方向一部を貫通して前記配線パターンの面と前記第2の配線パターンの面との間に挟設され、かつ導電性組成物からなり、かつ積層方向に一致する軸を有し該軸の方向に径が変化している形状である層間接続体とをさらに具備する、としてもよい。この層間接続体は、電気/電子部品を埋め込んでいる第2の絶縁層の積層方向一部を貫通する層間接続体の一例であり、例えば導電性組成物のスクリーン印刷により形成された導電性バンプを由来とする層間接続体である。   As an embodiment of the present invention, the second insulating layer is a laminate of at least two insulating layers, and a second wiring pattern provided between the at least two insulating layers, and the second An axis that penetrates part of the insulating layer in the stacking direction and is sandwiched between the surface of the wiring pattern and the surface of the second wiring pattern, and is made of a conductive composition and coincides with the stacking direction. And an interlayer connection body having a shape whose diameter changes in the direction of the axis. This interlayer connection body is an example of an interlayer connection body that penetrates a part in the stacking direction of the second insulating layer in which the electric / electronic component is embedded. For example, conductive bumps formed by screen printing of a conductive composition Is an interlayer connection body derived from

また、実施態様として、前記第2の絶縁層が、少なくとも2つの絶縁層の積層であり、前記少なくとも2つの絶縁層の間に挟まれて設けられた第2の配線パターンと、前記第2の絶縁層の積層方向一部を貫通して前記配線パターンの面と前記第2の配線パターンの面との間に挟設され、かつ金属からなり、かつ積層方向の一致する軸を有し該軸の方向に径が変化している形状である層間接続体とをさらに具備する、としてもよい。この層間接続体は、電気/電子部品を埋め込んでいる第2の絶縁層の積層方向一部を貫通する層間接続体の別の例であり、例えば金属板をエッチングすることにより形成された導体バンプを由来とする層間接続体である。   As an embodiment, the second insulating layer is a laminate of at least two insulating layers, and a second wiring pattern provided between the at least two insulating layers, and the second wiring layer An insulating layer that has a shaft that penetrates part of the insulating layer in the stacking direction and is sandwiched between the surface of the wiring pattern and the surface of the second wiring pattern and that is made of metal and coincides with the stacking direction. And an interlayer connection body having a shape whose diameter changes in the direction of. This interlayer connection body is another example of an interlayer connection body that penetrates a part in the stacking direction of the second insulating layer in which the electric / electronic component is embedded. For example, a conductor bump formed by etching a metal plate Is an interlayer connection body derived from

また、実施態様として、前記第1の絶縁層の前記配線パターンが位置する側とは反対側に設けられた第2の配線パターンと、前記第1の絶縁層を貫通して前記配線パターンの面と前記第2の配線パターンの面との間に挟設され、かつ導電性組成物からなり、かつ積層方向に一致する軸を有し該軸の方向に径が変化している形状である層間接続体とをさらに具備する、としてもよい。この層間接続体は、電気/電子部品を埋め込んでいる第2の絶縁層とは別の第1の絶縁層を貫通する層間接続体の一例であり、例えば導電性組成物のスクリーン印刷により形成された導電性バンプを由来とする層間接続体である。   As an embodiment, a surface of the wiring pattern penetrating through the first insulating layer, a second wiring pattern provided on the opposite side of the first insulating layer from the side on which the wiring pattern is located, and Between the first wiring pattern and the surface of the second wiring pattern, and is made of a conductive composition and has an axis that coincides with the laminating direction and has a shape whose diameter changes in the direction of the axis It may be further provided with a connection body. This interlayer connection body is an example of an interlayer connection body that penetrates a first insulating layer different from the second insulating layer in which the electric / electronic component is embedded, and is formed by, for example, screen printing of a conductive composition. It is an interlayer connection body derived from the conductive bump.

また、実施態様として、前記第1の絶縁層の前記配線パターンが位置する側とは反対側に設けられた第2の配線パターンと、前記第1の絶縁層を貫通して前記配線パターンの面と前記第2の配線パターンの面との間に挟設され、かつ金属からなり、かつ積層方向に一致する軸を有し該軸の方向に径が変化している形状である層間接続体とをさらに具備する、としてもよい。この層間接続体は、電気/電子部品を埋め込んでいる第2の絶縁層とは別の第1の絶縁層を貫通する層間接続体の別の例であり、例えば金属板をエッチングすることにより形成された導体バンプを由来とする層間接続体である。   As an embodiment, a surface of the wiring pattern penetrating through the first insulating layer, a second wiring pattern provided on the opposite side of the first insulating layer from the side on which the wiring pattern is located, and And an interlayer connection body that is sandwiched between the surface of the second wiring pattern and is made of metal and has an axis that coincides with the lamination direction and has a diameter that changes in the direction of the axis; It is good also as comprising. This interlayer connection body is another example of the interlayer connection body that penetrates the first insulating layer different from the second insulating layer in which the electric / electronic component is embedded, and is formed, for example, by etching a metal plate It is an interlayer connection body derived from the conductive bump.

また、実施態様として、前記第1の絶縁層の前記配線パターンが位置する側とは反対側に設けられた第2の配線パターンと、前記第1の絶縁層を貫通して前記配線パターンの面と前記第2の配線パターンの面との間に挟設され、かつ導電性組成物からなり、かつ積層方向に一致する軸を有し該軸の方向に径が変化していない形状である層間接続体とをさらに具備する、としてもよい。この層間接続体は、電気/電子部品を埋め込んでいる第2の絶縁層とは別の第1の絶縁層を貫通する層間接続体のさらに別の例であり、例えば第1の絶縁層を貫通する穴に導電性組成物を充填して形成される層間接続体である。   As an embodiment, a surface of the wiring pattern penetrating through the first insulating layer, a second wiring pattern provided on the opposite side of the first insulating layer from the side on which the wiring pattern is located, and Between the first wiring pattern and the surface of the second wiring pattern, and is made of a conductive composition and has an axis that coincides with the lamination direction and has a shape in which the diameter does not change in the direction of the axis It may be further provided with a connection body. This inter-layer connection body is still another example of the inter-layer connection body that penetrates the first insulating layer different from the second insulating layer in which the electric / electronic component is embedded. For example, the inter-layer connection body penetrates the first insulating layer. It is an interlayer connection body formed by filling a hole to be filled with a conductive composition.

また、実施態様として、前記第1の絶縁層の前記配線パターンが位置する側とは反対側に設けられた第2の配線パターンと、前記第1の絶縁層を貫通して前記配線パターンの面と前記第2の配線パターンの面との間に挟設され、かつ金属からなり、かつ積層方向に一致する軸を有し該軸の方向に径が変化していない形状である層間接続体とをさらに具備する、としてもよい。この層間接続体は、電気/電子部品を埋め込んでいる第2の絶縁層とは別の第1の絶縁層を貫通する層間接続体のさらに別の例であり、例えば金属めっきにより形成された導体バンプを由来とする層間接続体である。   As an embodiment, a surface of the wiring pattern penetrating through the first insulating layer, a second wiring pattern provided on the opposite side of the first insulating layer from the side on which the wiring pattern is located, and An interlayer connection body that is sandwiched between the surface of the second wiring pattern and is made of metal and has an axis that coincides with the stacking direction and has a diameter that does not change in the direction of the axis; It is good also as comprising. This interlayer connection body is still another example of the interlayer connection body that penetrates the first insulating layer different from the second insulating layer in which the electric / electronic component is embedded, and is, for example, a conductor formed by metal plating. This is an interlayer connection body derived from a bump.

また、実施態様として、前記半田部により前記電気/電子部品が前記配線パターンに接続される該電気/電子部品の側とは反対の側の該電気/電子部品の表面が、表出している、とすることができる。部品内蔵配線板として厚みをできるだけ抑えた構成である。   As an embodiment, the surface of the electrical / electronic component on the side opposite to the electrical / electronic component connected to the wiring pattern by the solder portion is exposed. It can be. As a component built-in wiring board, the thickness is suppressed as much as possible.

また、実施態様として、前記半田部により前記電気/電子部品が前記配線パターンに接続される該電気/電子部品の側とは反対の側の該電気/電子部品の表面が、前記第2の絶縁層により隠されている、とすることもできる。部品内蔵配線板として内蔵部品を内部に完全に閉じ込めた構成である。   As an embodiment, the surface of the electrical / electronic component on the side opposite to the electrical / electronic component connected to the wiring pattern by the solder portion is the second insulation. It can also be hidden by layers. As a component built-in wiring board, the built-in components are completely enclosed inside.

以上を踏まえ、以下では本発明の実施形態を図面を参照しながら説明する。図1は、本発明の一実施形態に係る部品内蔵配線板の構成を模式的に示す断面図である。図1に示すように、この部品内蔵配線板は、絶縁層11(第1の絶縁層)、同12、同13、同14(12、13、14で第2の絶縁層)、同15、配線層21(第2の配線パターン)、同22(配線パターン)、同23(もうひとつの第2の配線パターン)、同24、同25、同26(=合計6層)、層間接続体31、同32、同34、同35、スルーホール導電体33、チップ部品41(電気/電子部品)、半田部51を有する。   Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to an embodiment of the present invention. As shown in FIG. 1, this component built-in wiring board includes insulating layers 11 (first insulating layers), 12, 12, 13 (second insulating layers at 12, 13, 14), 15, Wiring layer 21 (second wiring pattern), 22 (wiring pattern), 23 (another second wiring pattern), 24, 25, 26 (= 6 layers in total), interlayer connector 31 , 32, 34, 35, through-hole conductor 33, chip component 41 (electric / electronic component), and solder part 51.

チップ部品41は、ここでは例えばチップコンデンサであり、その平面的な大きさは例えば0.6mm×0.3mmである。両端に端子(電極)41aを有し、その下側が配線層22による内蔵部品実装用ランド22aに対向位置している。チップ部品41の端子41aと実装用ランド22aとは半田部51により電気的・機械的に接続されている。   Here, the chip component 41 is, for example, a chip capacitor, and its planar size is, for example, 0.6 mm × 0.3 mm. Terminals (electrodes) 41 a are provided at both ends, and the lower side thereof is opposed to the built-in component mounting land 22 a by the wiring layer 22. The terminal 41 a of the chip component 41 and the mounting land 22 a are electrically and mechanically connected by a solder portion 51.

ここで、チップ部品41の端子41aと実装用ランド22aとの配置および大きさの関係は、図2に示すようになっている。図2は、図1に示した部品内蔵配線板におけるチップ部品41付近の構造を示す平面図である。すなわち、チップ部品41の端子41aそれぞれの板厚み方向投影図形に内包される大きさに実装用ランド22aが形成されている。このようなチップ部品41の端子41aと実装用ランド22aとの関係によれば、それら間の接続を行う半田部51は、少ない量で形成できる。   Here, the relationship between the arrangement and the size of the terminal 41a of the chip component 41 and the mounting land 22a is as shown in FIG. FIG. 2 is a plan view showing a structure in the vicinity of the chip component 41 in the component built-in wiring board shown in FIG. That is, the mounting land 22a is formed in a size that is included in the projected thickness direction figure of each terminal 41a of the chip component 41. According to the relationship between the terminal 41a of the chip component 41 and the mounting land 22a, the solder portion 51 for connecting between them can be formed in a small amount.

したがって、2次実装時(この部品内蔵配線板の外側の配線層21、26に部品実装されるとき)に半田部51が再溶融することがあっても、その体積膨張はわずかなものに抑制され、絶縁層11、12、配線層22などにクラックやデラミネーションが発生することを効果的に防止できる。なお、半田部51は、実装用ランド22aに連なる配線層22にも広がっている可能性があるが、その連なるパターンの幅は、この実施形態では例えば0.15mm程度であり、非常に少ないはみ出し量にしかなり得ず問題となる影響を発生しない。   Therefore, even if the solder portion 51 may be remelted during secondary mounting (when components are mounted on the wiring layers 21 and 26 outside the component built-in wiring board), the volume expansion is suppressed to a slight level. Thus, cracks and delamination can be effectively prevented from occurring in the insulating layers 11 and 12, the wiring layer 22, and the like. The solder portion 51 may also extend to the wiring layer 22 connected to the mounting land 22a, but the width of the continuous pattern is, for example, about 0.15 mm in this embodiment, and the protrusion is very small. There is no significant effect on the amount, and no problem effects occur.

部品内蔵配線板としてのほかの構造について述べると、上記言及した外側の配線層21、26とは別の配線層22、23、24、25はそれぞれ内層の配線層であり、順に、配線層21と配線層22の間に絶縁層11が、配線層22と配線層23の間に絶縁層12が、配線層23と配線層24との間に絶縁層13が、配線層24と配線層25との間に絶縁層14が、配線層25と配線層26との間に絶縁層15が、それぞれ位置しこれらの配線層21〜26を隔てている。各配線層21〜26は、例えばそれぞれ厚さ18μmの金属(銅)箔からなっている。   The other structure as the component built-in wiring board will be described. The wiring layers 22, 23, 24, and 25, which are different from the outer wiring layers 21 and 26 mentioned above, are the inner wiring layers, respectively. Insulating layer 11 between wiring layer 22, insulating layer 12 between wiring layer 22 and wiring layer 23, insulating layer 13 between wiring layer 23 and wiring layer 24, and wiring layer 24 and wiring layer 25. The insulating layer 14 is located between the wiring layer 25 and the wiring layer 26, and the insulating layer 15 is located between the wiring layer 25 and the wiring layer 26. Each of the wiring layers 21 to 26 is made of, for example, a metal (copper) foil having a thickness of 18 μm.

なお、内層の配線層22〜25は、絶縁層12または絶縁層14の側に沈み込んで位置し、絶縁層11、13、15の側に配線層の沈み込みはない。これは製造工程に依拠してこのようになっており、配線層22、25については製造工程の違いでまた別の沈み込みの位置となる場合がある(後述する)。   The inner wiring layers 22 to 25 are positioned so as to sink into the insulating layer 12 or the insulating layer 14 side, and there is no sinking of the wiring layer into the insulating layers 11, 13, and 15. This is based on the manufacturing process, and the wiring layers 22 and 25 may be in different subsidence positions due to differences in the manufacturing process (described later).

各絶縁層11〜15は、絶縁層13を除き例えばそれぞれ厚さ100μm、絶縁層13のみ例えば厚さ300μmで、それぞれ例えばガラスエポキシ樹脂からなるリジッドな素材である。特に絶縁板13は、内蔵されたチップ部品41に相当する位置部分が開口部となっており、チップ部品41を内蔵するための空間を提供する。絶縁層12、14は、内蔵されたチップ部品41のための絶縁層13の上記開口部および絶縁層13のスルーホール導電体33内部の空間を埋めるように変形進入しており内部に空隙となる空間は存在しない。   Each of the insulating layers 11 to 15 is a rigid material made of, for example, a glass epoxy resin, for example, having a thickness of 100 μm, and the insulating layer 13 only having a thickness of, for example, 300 μm. In particular, the insulating plate 13 has an opening at a position corresponding to the built-in chip component 41, and provides a space for incorporating the chip component 41. The insulating layers 12 and 14 are deformed so as to fill the opening of the insulating layer 13 for the built-in chip component 41 and the space inside the through-hole conductor 33 of the insulating layer 13 and become voids inside. There is no space.

配線層21と配線層22とは、それらのパターンの面の間に挟設されかつ絶縁層11を貫通する層間接続体31により導通し得る。同様に、配線層22と配線層23とは、それらのパターンの面の間に挟設されかつ絶縁層12を貫通する層間接続体32により導通し得る。配線層23と配線層24とは、絶縁層13を貫通して設けられたスルーホール導電体33により導通し得る。配線層24と配線層25とは、それらのパターンの面の間に挟設されかつ絶縁層14を貫通する層間絶縁体34により導通し得る。配線層25と配線層26とは、それらのパターンの面の間に挟設されかつ絶縁層15を貫通する層間接続体25により導通し得る。   The wiring layer 21 and the wiring layer 22 can be conducted by an interlayer connector 31 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 11. Similarly, the wiring layer 22 and the wiring layer 23 can be conducted by an interlayer connector 32 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 12. The wiring layer 23 and the wiring layer 24 can be conducted by a through-hole conductor 33 provided through the insulating layer 13. The wiring layer 24 and the wiring layer 25 can be conducted by an interlayer insulator 34 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 14. The wiring layer 25 and the wiring layer 26 can be conducted by an interlayer connector 25 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 15.

層間接続体31、32、34、35は、それぞれ、導電性組成物のスクリーン印刷により形成される導電性バンプを由来とするものであり、その製造工程に依拠して軸方向(図1の図示で上下の積層方向)に径が変化している。その直径は、太い側で例えば200μmである。   The interlayer connectors 31, 32, 34, and 35 are derived from conductive bumps formed by screen printing of a conductive composition, respectively, and depend on the manufacturing process in the axial direction (shown in FIG. 1). The diameter changes in the upper and lower stacking directions). The diameter is, for example, 200 μm on the thick side.

この実施形態に係る部品内蔵配線板は、2次実装時に半田部51が再溶融することがあっても、その体積膨張はわずかなものに抑制され、絶縁層11、12、配線層22などにクラックやデラミネーションが発生することを効果的に防止できる。クラックやデラミネーションは過度の場合、配線パターン同士をショートさせることもあり、信頼性のほか製品歩留まりにも影響がある。したがって、本実施形態により信頼性向上および歩留まり向上が見込める。また、実装用ランド22aそれぞれの大きさを従来のものより小さく形成しているので、絶縁板11上の領域の利用効率が向上し実装密度の高い部品内蔵配線板を提供できる。さらに、部品内蔵に使用する半田の量を減少させるのでコスト減の意味でも利点がある。   In the component built-in wiring board according to this embodiment, even if the solder portion 51 may be remelted during the secondary mounting, the volume expansion is suppressed to a slight level, and the insulating layers 11, 12, the wiring layer 22, etc. Cracks and delamination can be effectively prevented from occurring. If cracks and delamination are excessive, the wiring patterns may be short-circuited, affecting the product yield as well as reliability. Therefore, this embodiment can improve reliability and yield. In addition, since the size of each mounting land 22a is smaller than that of the conventional one, the utilization efficiency of the region on the insulating plate 11 is improved, and a component built-in wiring board having a high mounting density can be provided. Furthermore, since the amount of solder used for incorporating components is reduced, there is an advantage in terms of cost reduction.

次に、図1に示した部品内蔵配線板の製造工程を図3ないし図5を参照して説明する。図3ないし図5は、それぞれ、図1に示した部品内蔵配線板の製造過程の一部を模式的断面で示す工程図である。これらの図において図1中に示した構成要素と同一または同一相当のものには同一符号を付してある。   Next, the manufacturing process of the component built-in wiring board shown in FIG. 1 will be described with reference to FIGS. 3 to 5 are process diagrams schematically showing a part of the manufacturing process of the component built-in wiring board shown in FIG. In these figures, the same or equivalent components as those shown in FIG.

図3から説明する。図3は、図1中に示した各構成のうち絶縁板11を中心とした部分の製造工程を示している。まず、図3(a)に示すように、厚さ例えば18μmの金属箔(電解銅箔)22A上に例えばスクリーン印刷により、層間接続体31となるペースト状の導電性組成物をほぼ円錐形のバンプ状(底面径例えば200μm、高さ例えば160μm)に形成する。この導電性組成物は、ペースト状の樹脂中に銀、金、銅などの金属微細粒または炭素微細粒を分散させたものである。説明の都合で金属箔22Aの下面に印刷しているが上面でもよい(以下の各図も同じである)。層間接続体31の印刷後これを乾燥させて硬化させる。   It demonstrates from FIG. FIG. 3 shows a manufacturing process of a portion centering on the insulating plate 11 in each configuration shown in FIG. First, as shown in FIG. 3 (a), a paste-like conductive composition to be an interlayer connection 31 is formed on a metal foil (electrolytic copper foil) 22A having a thickness of, for example, 18 μm by, for example, screen printing. It is formed in a bump shape (bottom diameter, for example, 200 μm, height, for example, 160 μm). This conductive composition is obtained by dispersing fine metal particles such as silver, gold and copper or fine carbon particles in a paste-like resin. For convenience of explanation, printing is performed on the lower surface of the metal foil 22A, but it may be printed on the upper surface (the following drawings are also the same). After the interlayer connector 31 is printed, it is dried and cured.

次に、図3(b)に示すように、金属箔22A上に厚さ例えば公称100μmのFR−4のプリプレグ11Aを積層して層間接続体31を貫通させ、その頭部が露出するようにする。露出に際してあるいはその後その先端を塑性変形でつぶしてもよい(いずれにしても層間接続体31の形状は、積層方向に一致する軸を有しその軸方向に径が変化する形状である。)。続いて、図3(c)に示すように、プリプレグ31A上に金属箔(電解銅箔)21Aを積層配置して加圧・加熱し全体を一体化する。このとき、金属箔21Aは層間接続体31と電気的導通状態となり、プリプレグ11Aは完全に硬化して絶縁層11になる。   Next, as shown in FIG. 3B, an FR-4 prepreg 11A having a thickness of, for example, 100 μm is laminated on the metal foil 22A to penetrate the interlayer connector 31 so that the head is exposed. To do. At the time of exposure or afterwards, the tip thereof may be crushed by plastic deformation (in any case, the shape of the interlayer connection body 31 is a shape having an axis coinciding with the stacking direction and the diameter changing in the axial direction). Subsequently, as shown in FIG. 3C, a metal foil (electrolytic copper foil) 21A is laminated on the prepreg 31A, and the whole is integrated by pressing and heating. At this time, the metal foil 21A is in electrical continuity with the interlayer connector 31, and the prepreg 11A is completely cured to become the insulating layer 11.

次に、図3(d)に示すように、片側の金属箔22Aに例えば周知のフォトリソグラフィによるパターニングを施し、これを、実装用ランド22aを含む配線パターン22に加工する。そして、加工により得られた実装用ランド22a上に、図3(e)に示すように、例えばスクリーン印刷によりクリーム半田51Aを印刷する。クリーム半田51Aは、フラックス中に微細な半田粒を分散させたものでありスクリーン印刷を用いれば容易に所定パターンに印刷できる。スクリーン印刷に代えてディスペンサを使用することもできる。   Next, as shown in FIG. 3D, the metal foil 22A on one side is patterned by, for example, well-known photolithography, and processed into a wiring pattern 22 including a mounting land 22a. Then, as shown in FIG. 3E, cream solder 51A is printed on the mounting land 22a obtained by processing, for example, by screen printing. The cream solder 51A is obtained by dispersing fine solder particles in a flux, and can be easily printed in a predetermined pattern by using screen printing. A dispenser can be used instead of screen printing.

次に、チップ部品41をクリーム半田51Aを介して実装用ランド22a上に例えばマウンタで載置し、さらにその後クリーム半田51Aを例えばリフロー炉でリフローさせる。これにより、図3(f)に示すように、半田部51を介してチップ部品41が実装用ランド22a上に接続された状態の配線板素材1が得られる。この配線板素材1を用いる後の工程については図5で後述する。   Next, the chip component 41 is placed on the mounting land 22a via the cream solder 51A, for example, with a mounter, and then the cream solder 51A is reflowed in a reflow furnace, for example. As a result, as shown in FIG. 3F, the wiring board material 1 in a state where the chip component 41 is connected to the mounting land 22a via the solder portion 51 is obtained. The subsequent steps using this wiring board material 1 will be described later with reference to FIG.

次に、図4を参照して説明する。図4は、図1中に示した各構成のうち絶縁板13および同12を中心とした部分の製造工程を示している。まず、図4(a)に示すように、両面に例えば厚さ18μmの金属箔(電解銅箔)23A、24Aが積層された例えば厚さ300μmのFR−4の絶縁層13を用意し、その所定位置にスルーホール導電体を形成するための貫通孔62をあけ、かつ内蔵するチップ部品41に相当する部分に開口部61を形成する。   Next, a description will be given with reference to FIG. FIG. 4 shows a manufacturing process of a part centering on the insulating plates 13 and 12 in each configuration shown in FIG. First, as shown in FIG. 4A, for example, an FR-4 insulating layer 13 having a thickness of, for example, 300 μm in which metal foils (electrolytic copper foils) 23A and 24A having a thickness of 18 μm are laminated on both surfaces is prepared. A through-hole 62 for forming a through-hole conductor is formed at a predetermined position, and an opening 61 is formed in a portion corresponding to the chip component 41 to be incorporated.

次に、無電解めっきおよび電解めっきを行い、図4(b)に示すように、貫通孔62の内壁にスルーホール導電体33を形成する。このとき開口部61の内壁にも導電体が形成される。さらに、図4(c)に示すように、金属箔23A、24Aを周知のフォトリソグラフィを利用して所定にパターニングして配線層23、24を形成する。配線層23、24のパターニング形成により、開口部61の内壁に形成された導電体も除去される。   Next, electroless plating and electrolytic plating are performed to form a through-hole conductor 33 on the inner wall of the through-hole 62 as shown in FIG. At this time, a conductor is also formed on the inner wall of the opening 61. Further, as shown in FIG. 4C, the metal foils 23A and 24A are patterned in a predetermined manner using well-known photolithography to form wiring layers 23 and 24. By patterning the wiring layers 23 and 24, the conductor formed on the inner wall of the opening 61 is also removed.

次に、図4(d)に示すように、配線層23上の所定の位置に層間接続体32となる導電性バンプ(底面径例えば200μm、高さ例えば160μm)をペースト状導電性組成物のスクリーン印刷により形成する。続いて、図4(e)に示すように、絶縁層12とすべきFR−4のプリプレグ12A(公称厚さ例えば100μm)を配線層23側にプレス機を用い積層する。プリプレグ12Aには、絶縁層13と同様の、内蔵するチップ部品41に相当する部分の開口部をあらかじめ設けておく。   Next, as shown in FIG. 4 (d), conductive bumps (bottom diameter: 200 μm, height: 160 μm, for example) that will become the interlayer connector 32 are formed at predetermined positions on the wiring layer 23 of the paste-like conductive composition. It is formed by screen printing. Subsequently, as shown in FIG. 4E, an FR-4 prepreg 12A (nominal thickness, for example, 100 μm) to be the insulating layer 12 is laminated on the wiring layer 23 side using a press. The prepreg 12 </ b> A is previously provided with an opening corresponding to the built-in chip component 41, similar to the insulating layer 13.

この積層工程では、層間接続体32の頭部をプリプレグ12Aに貫通させる。なお、図10(e)における層間接続体32の頭部の破線は、この段階でその頭部を塑性変形させてつぶしておく場合と塑性変形させない場合の両者あり得ることを示す。この工程により、配線層23はプリプレグ12A側に沈み込んで位置することになる。以上により得られた配線板素材を配線板素材2とする。   In this lamination process, the head of the interlayer connector 32 is passed through the prepreg 12A. In addition, the broken line of the head part of the interlayer connection body 32 in FIG. 10 (e) indicates that there are both cases where the head part is plastically deformed and crushed at this stage, and when it is not plastically deformed. By this step, the wiring layer 23 is located by sinking to the prepreg 12A side. The wiring board material obtained as described above is referred to as a wiring board material 2.

なお、以上の図4に示した工程は、以下のような手順とすることも可能である。図4(a)の段階では、貫通孔62のみ形成し内蔵部品用の開口部61を形成せずに続く図4(b)から図4(d)までの工程を行う。次に、図4(e)に相当する工程として、プリプレグ12A(開口のないもの)の積層を行う。そして、絶縁層13およびプリプレグ12Aに部品内蔵用の開口部を同時に形成する、という工程である。   Note that the steps shown in FIG. 4 may be performed as follows. In the stage of FIG. 4A, only the through hole 62 is formed and the subsequent steps from FIG. 4B to FIG. 4D are performed without forming the opening 61 for the built-in component. Next, as a process corresponding to FIG. 4E, prepreg 12A (without opening) is stacked. And it is the process of forming simultaneously the opening part for components incorporation in the insulating layer 13 and the prepreg 12A.

次に、図5を参照して説明する。図5は、上記で得られた配線板素材1、2などを積層する配置関係を示す図である。ここで、図示上側の配線板素材3は、下側の配線板素材1と同様な工程を適用し、かつそのあと層間接続体34およびプリプレグ14Aを図示中間の配線板素材2における層間接続体32およびプリプレグ12Aと同様にして形成し得られたものである。ただし、部品(チップ部品41)およびこれを接続するための部位(実装用ランド22a)のない構成であり、さらにプリプレグ14Aにはチップ部品41用の開口部も設けない。そのほかは、金属箔(電解銅箔)26A、絶縁層15、層間接続体35、配線層25、プリプレグ14A、層間接続体34とも、それぞれ配線板素材1の金属箔21A、絶縁層11、層間接続体31、配線層22、配線板素材2のプリプレグ12A、層間接続体32と同じである。   Next, a description will be given with reference to FIG. FIG. 5 is a diagram showing an arrangement relationship in which the wiring board materials 1 and 2 obtained as described above are stacked. Here, the upper wiring board material 3 applies the same process as that of the lower wiring board material 1, and thereafter, the interlayer connector 34 and the prepreg 14A are connected to the interlayer connector 32 in the intermediate wiring board material 2 shown in the figure. And it was obtained in the same manner as the prepreg 12A. However, there is no component (chip component 41) and no part (mounting land 22a) for connecting it, and the prepreg 14A is not provided with an opening for the chip component 41. Other than that, the metal foil (electrolytic copper foil) 26A, the insulating layer 15, the interlayer connection body 35, the wiring layer 25, the prepreg 14A, and the interlayer connection body 34 are the metal foil 21A of the wiring board material 1, the insulating layer 11, and the interlayer connection, respectively. The same as the body 31, the wiring layer 22, the prepreg 12 </ b> A of the wiring board material 2, and the interlayer connection body 32.

図5に示すような配置で各配線板素材1、2、3を積層配置してプレス機で加圧・加熱する。これにより、プリプレグ12A、14Aが完全に硬化し全体が積層・一体化する。このとき、加熱により得られるプリプレグ12A、14Aの流動性により、チップ部品41の周りの空間およびスルーホール導電体33内部の空間にはプリプレグ12A、14Aが変形進入し空隙は発生しない。また、配線層22、24は、層間接続体32、34にそれぞれ電気的に接続される。この積層工程の後、上下両面の金属箔26A、21Aを周知のフォトリソグラフィを利用して所定にパターニングし、図1に示したような部品内蔵配線板を得ることができる。   The respective wiring board materials 1, 2, and 3 are laminated and arranged in the arrangement as shown in FIG. Thereby, the prepregs 12A and 14A are completely cured, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 12 </ b> A and 14 </ b> A obtained by heating, the prepregs 12 </ b> A and 14 </ b> A are deformed into the space around the chip component 41 and the space inside the through-hole conductor 33, and no gap is generated. The wiring layers 22 and 24 are electrically connected to the interlayer connectors 32 and 34, respectively. After this laminating step, the metal foils 26A and 21A on the upper and lower surfaces can be patterned in a predetermined manner using well-known photolithography to obtain a component built-in wiring board as shown in FIG.

変形例として、中間の絶縁層13に設けられたスルーホール導電体33については、層間接続体31や同32と同様なものとする構成も当然ながらあり得る。また、外側の配線層21、26は、最後の積層工程のあとにパターニングして得る以外に、各配線板素材1、3の段階で(例えば図3(d)の段階で)形成するようにしてもよい。   As a modification, the through-hole conductor 33 provided in the intermediate insulating layer 13 can naturally have a configuration similar to the interlayer connector 31 or 32. In addition, the outer wiring layers 21 and 26 are formed at the stage of each wiring board material 1 and 3 (for example, at the stage of FIG. 3D) other than patterning after the last lamination step. May be.

また、図5に示した積層工程において、配線板素材1、2については、プリプレグ12Aおよび層間接続体32の部分を配線板素材2の側ではなく配線板素材1の側に設けておくようにしてもよい。すなわち、層間接続体32の形成およびプリプレグ12Aの積層を、配線板素材1の配線層22上(絶縁板11上)であらかじめ行うようにする。この場合、実装されたチップ部品41が、一見、層間接続体32をスクリーン印刷で形成するときに干渉要因となるように見えるが、チップ部品41として十分薄い部品の場合は実際上干渉要因とはならない。プリプレグ12Aの積層工程のときには、チップ部品41の厚さを吸収できるクッション材を介在させて加圧・加熱すれば面内方向均一にプリプレグ12Aを積層できる。   Further, in the laminating process shown in FIG. 5, for the wiring board materials 1 and 2, the prepreg 12 </ b> A and the interlayer connector 32 are provided not on the wiring board material 2 side but on the wiring board material 1 side. May be. That is, the formation of the interlayer connector 32 and the lamination of the prepreg 12A are performed in advance on the wiring layer 22 (on the insulating plate 11) of the wiring board material 1. In this case, the mounted chip component 41 seems to be an interference factor when the interlayer connection body 32 is formed by screen printing at first glance. However, when the chip component 41 is a sufficiently thin component, what is actually an interference factor? Don't be. In the step of laminating the prepreg 12A, the prepreg 12A can be laminated uniformly in the in-plane direction by pressing and heating with a cushioning material capable of absorbing the thickness of the chip component 41 interposed therebetween.

次に、本発明の別の実施形態に係る部品内蔵配線板について図6を参照して説明する。図6は、本発明の別の実施形態に係る部品内蔵配線板の構成を模式的に示す断面図であり、すでに説明した図中に示した構成要素と同一または同一相当のものには同一符号を付してある。その部位については加える事項がない限り説明を省略する。   Next, a component built-in wiring board according to another embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to another embodiment of the present invention. Components identical or equivalent to those shown in the already described drawings are denoted by the same reference numerals. Is attached. The description of the part is omitted unless there is an additional matter.

この実施形態では、導電性組成物の印刷による層間接続体32、34に代わり、金属板エッチングにより形成された層間接続体72、74を有している。これらの層間接続体72、74の配線層22側または配線層25側には、図示するように、エッチングストッパ層が残存している。また、絶縁層11(15)の絶縁層12(14)との境界は、図1に示した実施形態と比較して配線層22(25)の厚さ分だけ深い方に移動している。以下、このような構成になっている理由を含めて製造工程を説明する。   In this embodiment, it has the interlayer connection bodies 72 and 74 formed by metal plate etching instead of the interlayer connection bodies 32 and 34 by printing of the conductive composition. As shown in the drawing, an etching stopper layer remains on the wiring layer 22 side or the wiring layer 25 side of these interlayer connectors 72 and 74. Further, the boundary between the insulating layer 11 (15) and the insulating layer 12 (14) is moved deeper by the thickness of the wiring layer 22 (25) as compared with the embodiment shown in FIG. Hereinafter, the manufacturing process will be described including the reason for such a configuration.

図7は、図6に示した部品内蔵配線板の製造過程の一部を模式的断面で示す工程図であり、図6における絶縁層11、配線層21、22(実装用ランド22aを含む)、層間接続体31、72の部分の製造工程を示したものである。図6における絶縁層15、配線層25、26、層間接続体35、74の部分の製造工程もほぼ同様である。なお、図6中に示した構成要素と同一または同一相当のものには同一符号を付してある。   FIG. 7 is a process diagram schematically showing a part of the manufacturing process of the component built-in wiring board shown in FIG. 6 in an insulating layer 11, wiring layers 21 and 22 (including mounting lands 22a) in FIG. The manufacturing process of the part of the interlayer connection bodies 31 and 72 is shown. The manufacturing process of the insulating layer 15, wiring layers 25 and 26, and interlayer connectors 35 and 74 in FIG. 6 is substantially the same. In addition, the same code | symbol is attached | subjected to the same or equivalent thing as the component shown in FIG.

まず、例えば厚さ18μmの金属箔(電解銅箔)22Aにごく薄い厚さ例えば2μmの例えばニッケル合金からなる層(エッチングストッパ層ES)が積層された積層膜を用意し、このエッチングストッパ層ES側に厚さ例えば120μmの金属板(銅板)72Aを積層一体化して、図7(a)に示すように3層構造のクラッド材を得る。   First, for example, a laminated film in which a layer (etching stopper layer ES) made of, for example, a nickel alloy having a very thin thickness, for example, 2 μm, is prepared on a metal foil (electrolytic copper foil) 22A having a thickness of 18 μm is prepared, and this etching stopper layer ES is prepared. A metal plate (copper plate) 72A having a thickness of, for example, 120 μm is laminated and integrated on the side to obtain a clad material having a three-layer structure as shown in FIG.

次に、図7(b)に示すように、金属箔22Aを周知のフォトリソグラフィを利用し銅のみエッチング可能なエッチング液で所定にパターニングする。これにより配線層22を形成する。さらに、図7(c)に示すように、配線層22上の所定の位置に層間接続体31をペースト状の導電性組成物のスクリーン印刷により形成する。続いて、図7(d)に示すように、絶縁層11とすべきプリプレグ11Aを配線層22側にプレス機を用い積層する。このとき層間接続体31の頭部をプリプレグ11Aに貫通させる。この積層工程により、配線層22はプリプレグ11A側に沈み込んで位置することになる。なお、図7(d)における層間接続体31の頭部の破線は、この段階で層間接続体31の頭部を塑性変形させてつぶしておく場合と塑性変形させない場合の両者あり得ることを示す。   Next, as shown in FIG. 7B, the metal foil 22A is patterned in a predetermined pattern with an etchant that can etch only copper using well-known photolithography. Thereby, the wiring layer 22 is formed. Further, as shown in FIG. 7C, an interlayer connection 31 is formed at a predetermined position on the wiring layer 22 by screen printing of a paste-like conductive composition. Subsequently, as shown in FIG. 7D, the prepreg 11A to be the insulating layer 11 is laminated on the wiring layer 22 side using a press machine. At this time, the head of the interlayer connector 31 is made to penetrate the prepreg 11A. By this lamination process, the wiring layer 22 sinks to the prepreg 11A side and is positioned. Note that the broken line at the head of the interlayer connector 31 in FIG. 7D indicates that there are both cases where the head of the interlayer connector 31 is plastically deformed and crushed at this stage and when it is not plastically deformed. .

次に、積層されたプリプレグ11A上に、配線層21とすべき厚さ例えば18μmの金属箔(電解銅箔)21Aを配置してプレス機で積層方向に加圧・加熱する。これにより、図7(e)に示すように、プリプレグ11Aが完全に硬化して絶縁層11となり積層・一体化がされる。このとき金属箔21Aは層間接続体31に電気的に接続される。   Next, a metal foil (electrolytic copper foil) 21A having a thickness of 18 μm, for example, is arranged on the laminated prepreg 11A, and is pressed and heated in the laminating direction by a press. Thereby, as shown in FIG.7 (e), the prepreg 11A is hardened | cured completely and becomes the insulating layer 11, and is laminated | stacked and integrated. At this time, the metal foil 21A is electrically connected to the interlayer connector 31.

次に、金属板72A上に所定位置のエッチングレジストを形成する。このエッチングレジストは、エッチングによる層間接続体72を形成すべきところに残存させる。そして銅のみをエッチング可能なエッチング液を用いてエッチング加工し、図7(f)に示すように、金属板のエッチング加工による層間接続体72を形成する。その形状は、エッチングレジストの形状や大きさ、エッチング加工時間によって変わり、一般には積層方向に一致する軸を有しこの軸の方向に径が変化する形状になる。   Next, an etching resist at a predetermined position is formed on the metal plate 72A. This etching resist is left where the interlayer connector 72 is to be formed by etching. Then, etching is performed using an etchant that can etch only copper, and an interlayer connector 72 is formed by etching a metal plate, as shown in FIG. The shape varies depending on the shape and size of the etching resist and the etching processing time. Generally, the shape has an axis that coincides with the stacking direction, and the diameter changes in the direction of the axis.

そして、形成された層間接続体72をマスクにエッチングストッパ層ESをエッチング除去することにより、図7(g)に示すような形態の配線板素材を得ることできる。以下の工程としては、図3(e)以下に示したチップ部品の実装、および図4(e)に示したプリプレグ12Aの積層(ただし、プリプレグ12Aは図7(g)における配線層22の側に積層する)を行う。得られた配線板素材は、図5に示した積層工程における下側の配線板素材1に代えて用いることができる。中間の配線板素材2に相当するものには、層間接続体32の形成およびプリプレグ12Aの積層のないものを使用する。以上により図6に示した部品内蔵配線板を得ることができる。   Then, the wiring board material having a form as shown in FIG. 7G can be obtained by etching away the etching stopper layer ES using the formed interlayer connector 72 as a mask. The following steps include mounting of the chip components shown in FIG. 3E and subsequent steps, and stacking of the prepreg 12A shown in FIG. 4E (however, the prepreg 12A is on the wiring layer 22 side in FIG. 7G). To be laminated). The obtained wiring board material can be used in place of the lower wiring board material 1 in the laminating process shown in FIG. As the intermediate wiring board material 2, the one without the formation of the interlayer connector 32 and the lamination of the prepreg 12 </ b> A is used. Thus, the component built-in wiring board shown in FIG. 6 can be obtained.

次に、本発明のさらに別の実施形態について図8を参照して説明する。図8は、本発明のさらに別の実施形態に係る部品内蔵配線板の構成を模式的に示す断面図である。すでに説明した図中に示した構成要素と同一または同一相当のものには同一符号を付してある。その部位については加える事項がない限り説明を省略する。この実施形態は、図1に示した部品内蔵配線板の層間接続体31、35に代えて、金属からなり、積層方向に一致する軸を有しその軸方向に径が変化する形状の層間接続体81、85を用いたものである。   Next, still another embodiment of the present invention will be described with reference to FIG. FIG. 8 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to still another embodiment of the present invention. Components that are the same as or equivalent to the components shown in the drawings already described are denoted by the same reference numerals. The description of the part is omitted unless there is an additional matter. In this embodiment, instead of the interlayer connection bodies 31 and 35 of the component built-in wiring board shown in FIG. 1, the interlayer connection is made of metal and has an axis that coincides with the stacking direction and has a shape whose diameter changes in the axial direction. The bodies 81 and 85 are used.

以下、図8に示した部品内蔵配線板の製造工程について図9を参照して説明する。図9は、図8に示した部品内蔵配線板の一部製造過程を模式的断面で示す工程図であり、配線層22(より厳密には配線層22に加工される金属箔22A)と層間接続体81とからなる部分の製造工程を示すものである。   Hereinafter, the manufacturing process of the component built-in wiring board shown in FIG. 8 will be described with reference to FIG. FIG. 9 is a process diagram schematically showing a partial manufacturing process of the component built-in wiring board shown in FIG. 8, in which the wiring layer 22 (more precisely, the metal foil 22A processed into the wiring layer 22) and the interlayer The manufacturing process of the part which consists of the connection body 81 is shown.

まず、例えば厚さ18μmの金属箔(電解銅箔)22Aにごく薄い厚さ例えば2μmの例えばニッケル合金からなる層(エッチングストッパ層ES)が積層された積層膜を用意し、このエッチングストッパ層ES側に金属板(銅板)81Aを積層一体化して、図9(a)に示すような3層構造のクラッド材を得る。そして、金属板81A上の所定位置にエッチングマスク89を形成する。   First, for example, a laminated film in which a layer (etching stopper layer ES) made of, for example, a nickel alloy having a very thin thickness, for example, 2 μm, is prepared on a metal foil (electrolytic copper foil) 22A having a thickness of 18 μm is prepared, and this etching stopper layer ES is prepared. A metal plate (copper plate) 81A is laminated and integrated on the side to obtain a clad material having a three-layer structure as shown in FIG. Then, an etching mask 89 is formed at a predetermined position on the metal plate 81A.

次に、エッチングマスク89が形成された3層クラッド材の金属板81Aを、銅のみエッチング可能なエッチング液でエッチングする。これにより図9(b)に示すように、層間接続体81を得ることができる。そして形成された層間接続体81をマスクにエッチングストッパ層ESをエッチング除去する。これにより図9(c)に示す素材が得られる。以下の工程は、この図9(c)に示した素材を図3(a)に示す素材に代えて、図3(b)以下の工程を行えばよい。以上の説明は、配線層25と層間接続体85とからなる部分について同様である。   Next, the three-layer clad metal plate 81A on which the etching mask 89 is formed is etched with an etchant that can etch only copper. As a result, as shown in FIG. 9B, an interlayer connector 81 can be obtained. Then, the etching stopper layer ES is removed by etching using the formed interlayer connector 81 as a mask. As a result, the material shown in FIG. 9C is obtained. In the following steps, the material shown in FIG. 9C may be replaced with the material shown in FIG. 3A, and the steps shown in FIG. The above description is the same for the portion composed of the wiring layer 25 and the interlayer connector 85.

次に、本発明のさらに別の実施形態について図10を参照して説明する。図10は、本発明のさらに別の実施形態に係る部品内蔵配線板の構成を模式的に示す断面図である。図10において、すでに説明した構成部分と同一または同一相当の部分には同一符号を付し、その説明は省略する。この実施形態は、図1に示した部品内蔵配線板の層間接続体31、35に代えて、導電性組成物からなり、積層方向に一致する軸を有しその軸方向に径が変化しない形状の層間接続体91、95を用いたものである。   Next, still another embodiment of the present invention will be described with reference to FIG. FIG. 10 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to still another embodiment of the present invention. In FIG. 10, the same or equivalent parts as those already described are denoted by the same reference numerals, and the description thereof is omitted. In this embodiment, instead of the interlayer connection bodies 31 and 35 of the component built-in wiring board shown in FIG. 1, a shape made of a conductive composition and having an axis that coincides with the laminating direction and whose diameter does not change in the axial direction. The interlayer connection bodies 91 and 95 are used.

以下、図10に示した部品内蔵配線板の製造工程について図11を参照して説明する。図11は、図10に示した部品内蔵配線板の一部製造過程を模式的断面で示す工程図であり、絶縁層11とその両面の配線層21、22、および絶縁層11を貫通する層間接続体91の部分の製造工程を示すものである。   Hereinafter, the manufacturing process of the component built-in wiring board shown in FIG. 10 will be described with reference to FIG. FIG. 11 is a process diagram schematically showing a partial manufacturing process of the component built-in wiring board shown in FIG. 10. The insulating layer 11, the wiring layers 21 and 22 on both sides thereof, and the layers penetrating the insulating layer 11 are shown in FIG. The manufacturing process of the part of the connection body 91 is shown.

まず、図11(a)示すように、例えば厚さ公称100μmのプリプレグ11Aの所定位置に穴あけを行い、その穴内部を導電性組成物で充填し層間接続体91とする。次に、図11(b)に示すように、プリプレグ11Aの両面に厚さ例えば18μmの金属箔(電解銅箔)21A、22Aを積層し加圧・加熱して一体化する。この積層・一体化で各金属箔21A、22Aは層間接続体91との電気的導通状態を確立し、プリプレグ11Aは完全に硬化して絶縁層11となる。   First, as shown in FIG. 11A, for example, a predetermined position of a prepreg 11 </ b> A having a nominal thickness of 100 μm is formed, and the inside of the hole is filled with a conductive composition to form an interlayer connector 91. Next, as shown in FIG. 11B, metal foils (electrolytic copper foils) 21A, 22A having a thickness of, for example, 18 μm are laminated on both surfaces of the prepreg 11A, and are integrated by pressing and heating. By this lamination and integration, the respective metal foils 21A and 22A establish electrical continuity with the interlayer connector 91, and the prepreg 11A is completely cured to become the insulating layer 11.

次に、図11(c)に示すように、片側の金属箔22Aに例えば周知のフォトリソグラフィによるパターニングを施し、これを配線層22(実装用ランド22aを含む)に加工する。そして、この図11(c)に示す素材を図3(d)に示す素材の代わりに用い、その後の工程は図3(e)以下における説明と同様である。以上の説明は、絶縁層15とその両面の配線層25、26、および絶縁層15を貫通する層間接続体95の部分について同様である。   Next, as shown in FIG. 11C, patterning by, for example, well-known photolithography is performed on the metal foil 22A on one side, and this is processed into the wiring layer 22 (including the mounting land 22a). The material shown in FIG. 11C is used instead of the material shown in FIG. 3D, and the subsequent steps are the same as those described in FIG. The above description is the same for the insulating layer 15, the wiring layers 25 and 26 on both sides thereof, and the portion of the interlayer connector 95 that penetrates the insulating layer 15.

次に、本発明のさらに別の実施形態について図12を参照して説明する。図12は、本発明のさらに別の実施形態に係る部品内蔵配線板の構成を模式的に示す断面図である。図12において、すでに説明した構成部分と同一または同一相当の部分には同一符号を付し、その説明は省略する。この実施形態は、図1に示した部品内蔵配線板の層間接続体31、35に代えて、金属からなり、積層方向に一致する軸を有しその軸方向に径が変化しない形状の層間接続体101、105を用いたものである。   Next, still another embodiment of the present invention will be described with reference to FIG. FIG. 12 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to still another embodiment of the present invention. In FIG. 12, parts that are the same as or equivalent to those already described are given the same reference numerals, and descriptions thereof are omitted. In this embodiment, instead of the interlayer connection bodies 31 and 35 of the component built-in wiring board shown in FIG. 1, the interlayer connection is made of metal and has a shape that has an axis that coincides with the stacking direction and does not change its diameter in the axial direction. The bodies 101 and 105 are used.

以下、図12に示した部品内蔵配線板の製造工程について図13を参照して説明する。図13は、図12に示した部品内蔵配線板の一部製造過程を模式的断面で示す工程図であり、上記説明のうち、配線層22(より厳密には配線層22に加工される金属箔22A)と層間接続体101とからなる部分の製造工程を示すものである。   Hereinafter, the manufacturing process of the component built-in wiring board shown in FIG. 12 will be described with reference to FIG. FIG. 13 is a process diagram schematically showing a partial manufacturing process of the component built-in wiring board shown in FIG. 12. In the above description, the wiring layer 22 (more precisely, the metal processed into the wiring layer 22) is shown. The manufacturing process of the part which consists of foil 22A) and the interlayer connection body 101 is shown.

まず、図13(a)に示すように、例えば厚さ18μmの金属箔(電解銅箔)22A上に、所定位置にマスク除去部109Aを有するめっき阻止マスク109を形成する。マスク除去部109Aの形状は例えばほぼ円筒状である。次に、金属箔22Aを電気供給路としてそのめっき阻止マスク109側に電解めっき工程を施し、図13(b)に示すように、マスク除去部109A内に例えば銅のめっき層を成長させる。この成長させためっき層が層間接続体101になる。めっき層成長後、めっき阻止マスク109を除去すると図13(c)に示すような素材が得られる。以下の工程は、この図13(c)に示した素材を図3(a)に示す素材に代えて、図3(b)以下の工程を行えばよい。以上の説明は、配線層25と層間接続体104とからなる部分について同様である。   First, as shown in FIG. 13A, a plating prevention mask 109 having a mask removal portion 109A at a predetermined position is formed on a metal foil (electrolytic copper foil) 22A having a thickness of 18 μm, for example. The shape of the mask removal unit 109A is, for example, a substantially cylindrical shape. Next, an electrolytic plating process is performed on the plating prevention mask 109 side using the metal foil 22A as an electric supply path, and as shown in FIG. 13B, for example, a copper plating layer is grown in the mask removal portion 109A. This grown plating layer becomes the interlayer connection body 101. After the plating layer is grown, the plating block mask 109 is removed to obtain a material as shown in FIG. In the following steps, the material shown in FIG. 13C may be replaced with the material shown in FIG. 3A, and the steps shown in FIG. The above description is the same for the portion composed of the wiring layer 25 and the interlayer connector 104.

以上、図8ないし図13では、絶縁層11およびその両面の配線層21、22からなる両面配線板の部分と、絶縁層15およびその両面の配線層25、26からなる両面配線板の部分とについての諸例を、その層間接続体の構成という観点から示した。これらの説明以外の層間接続体を有する両面配線板を用いてもよいことは無論である。例えば、層間接続体として、周知の、穴あけおよびめっき工程によるスルーホール内壁導電体としてもよい。さらにその他様々な構成の層間接続体を有する両面配線板を用いることができる。   8 to 13, the double-sided wiring board portion including the insulating layer 11 and the wiring layers 21 and 22 on both sides thereof, and the double-sided wiring board portion including the insulating layer 15 and the wiring layers 25 and 26 on both sides thereof. The examples are shown from the viewpoint of the structure of the interlayer connector. Of course, a double-sided wiring board having an interlayer connection other than those described above may be used. For example, the interlayer connection body may be a well-known through-hole inner wall conductor formed by a drilling and plating process. Furthermore, a double-sided wiring board having various other configurations of the interlayer connector can be used.

次に、本発明のさらに別の実施形態について図14を参照して説明する。図14は、本発明のさらに別の実施形態に係る部品内蔵配線板の構成を模式的に示す断面図である。図14において、すでに説明した構成部分と同一または同一相当の部分には同一符号を付し、その説明は省略する。この実施形態は、図1に示した部品内蔵配線板において絶縁層14から上の部分(層間接続体34、配線層25、絶縁層15、層間接続体35、配線層26)がない構成のものであり、これによりチップ部品41の実装側と反対側が表出している。部品内蔵配線板として厚みをできるだけ抑えた構成である。   Next, still another embodiment of the present invention will be described with reference to FIG. FIG. 14 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to still another embodiment of the present invention. In FIG. 14, parts that are the same as or equivalent to those already described are given the same reference numerals, and descriptions thereof are omitted. In this embodiment, the component built-in wiring board shown in FIG. 1 has a configuration in which there is no portion above the insulating layer 14 (interlayer connector 34, wiring layer 25, insulating layer 15, interlayer connector 35, wiring layer 26). Thus, the side opposite to the mounting side of the chip component 41 is exposed. As a component built-in wiring board, the thickness is suppressed as much as possible.

図15は、図14に示した部品内蔵配線板の製造過程の一部を模式的断面で示す工程図である。すでに示した図中に示した構成要素と同一または同一相当のものには同一符号を付してある。図15は、図5に相当する積層工程を示し、図示するように、配線板素材1、2については図1ないし5により説明した実施形態と同じものを使用できる。   FIG. 15 is a process diagram schematically showing a part of the manufacturing process of the component built-in wiring board shown in FIG. Components that are the same as or equivalent to the components shown in the drawings already shown are denoted by the same reference numerals. FIG. 15 shows a lamination process corresponding to FIG. 5, and as shown, the same wiring board materials 1 and 2 as those described with reference to FIGS. 1 to 5 can be used.

この積層工程において積層上側には離型シート141を用いる。これにより、上側面には、配線層24のようなわずかな突起を吸収して離型シート141が密着する。そして、積層時の加熱によりプリプレグ12Aが流動性を得て、チップ部品41の周りの空間およびスルーホール導電体33内部の空間にプリプレグ12Aが変形進入する。積層工程の後、離型シートは除去される。チップ部品41の高さは絶縁層13の上側に合わせされており、これによりチップ部品41の表面が表出することになる。   In this lamination step, a release sheet 141 is used on the upper side of the lamination. As a result, a slight protrusion such as the wiring layer 24 is absorbed on the upper side surface so that the release sheet 141 adheres. The prepreg 12 </ b> A obtains fluidity by heating at the time of lamination, and the prepreg 12 </ b> A deforms and enters the space around the chip component 41 and the space inside the through-hole conductor 33. After the lamination process, the release sheet is removed. The height of the chip component 41 is adjusted to the upper side of the insulating layer 13, and thereby the surface of the chip component 41 is exposed.

本発明の一実施形態に係る部品内蔵配線板の構成を模式的に示す断面図。Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on one Embodiment of this invention. 図1に示した部品内蔵配線板におけるチップ部品41付近の構造を示す平面図。The top view which shows the structure of the chip component 41 vicinity in the component built-in wiring board shown in FIG. 図1に示した部品内蔵配線板の製造過程の一部を模式的断面で示す工程図。Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. 図1に示した部品内蔵配線板の製造過程の別の一部を模式的断面で示す工程図。Process drawing which shows another part of manufacturing process of the component built-in wiring board shown in FIG. 図1に示した部品内蔵配線板の製造過程のさらに別の一部を模式的断面で示す工程図。FIG. 9 is a process diagram schematically showing still another part of the manufacturing process of the component built-in wiring board shown in FIG. 1. 本発明の別の実施形態に係る部品内蔵配線板の構成を模式的に示す断面図。Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on another embodiment of this invention. 図6に示した部品内蔵配線板の製造過程の一部を模式的断面で示す工程図。Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. 本発明のさらに別の実施形態に係る部品内蔵配線板の構成を模式的に示す断面図。Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on another embodiment of this invention. 図8に示した部品内蔵配線板の製造過程の一部を模式的断面で示す工程図。Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. 本発明のさらに別の実施形態に係る部品内蔵配線板の構成を模式的に示す断面図。Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on another embodiment of this invention. 図10に示した部品内蔵配線板の製造過程の一部を模式的断面で示す工程図。Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. 本発明のさらに別の実施形態に係る部品内蔵配線板の構成を模式的に示す断面図。Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on another embodiment of this invention. 図12に示した部品内蔵配線板の製造過程の一部を模式的断面で示す工程図。Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. 本発明のさらに別の実施形態に係る部品内蔵配線板の構成を模式的に示す断面図。Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on another embodiment of this invention. 図14に示した部品内蔵配線板の製造過程の一部を模式的断面で示す工程図。Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. 14 with a typical cross section.

符号の説明Explanation of symbols

1…配線板素材、2…配線板素材、3…配線板素材、11…絶縁層、11A…プリプレグ、12…絶縁層、12A…プリプレグ、13…絶縁層、14…絶縁層、14A…プリプレグ、15…絶縁層、21…配線層(金属配線パターン)、21A…金属箔(銅箔)、22…配線層(金属配線パターン)、22a…内蔵部品実装用ランド、22A…金属箔(銅箔)、23…配線層(金属配線パターン)、23A…金属箔(銅箔)、24…配線層(金属配線パターン)、24A…金属箔(銅箔)、25…配線層(金属配線パターン)、26…配線層(金属配線パターン)、31…層間接続体(導電性組成物印刷による導電性バンプ)、32…層間接続体(導電性組成物印刷による導電性バンプ)、33…スルーホール導電体、34…層間接続体(導電性組成物印刷による導電性バンプ)、35…層間接続体(導電性組成物印刷による導電性バンプ)、41…チップ部品(電気/電子部品)、41a…端子(電極)、51…半田、51a…クリーム半田、61…開口部、62…貫通孔、72,74…層間接続体(金属板エッチングにより形成された金属バンプ)、72A…金属板(銅板)、81,85…層間接続体(金属板エッチングにより形成された金属バンプ)、81A…金属板(銅板)、89…エッチングマスク、91,95…層間接続体(導電性組成物充填)、101,105…層間接続体(めっきにより形成された導体バンプ)、109…めっき阻止マスク、109A…マスク除去部、141…離型シート、ES…エッチングストッパ。   DESCRIPTION OF SYMBOLS 1 ... Wiring board material, 2 ... Wiring board material, 3 ... Wiring board material, 11 ... Insulating layer, 11A ... Prepreg, 12 ... Insulating layer, 12A ... Prepreg, 13 ... Insulating layer, 14 ... Insulating layer, 14A ... Prepreg, DESCRIPTION OF SYMBOLS 15 ... Insulating layer, 21 ... Wiring layer (metal wiring pattern), 21A ... Metal foil (copper foil), 22 ... Wiring layer (metal wiring pattern), 22a ... Land for mounting a built-in component, 22A ... Metal foil (copper foil) , 23 ... wiring layer (metal wiring pattern), 23A ... metal foil (copper foil), 24 ... wiring layer (metal wiring pattern), 24A ... metal foil (copper foil), 25 ... wiring layer (metal wiring pattern), 26 ... wiring layer (metal wiring pattern), 31 ... interlayer connection (conductive bump by conductive composition printing), 32 ... interlayer connection (conductive bump by conductive composition printing), 33 ... through-hole conductor, 34 ... Interlayer connector (lead Conductive bump by conductive composition printing), 35 ... interlayer connection (conductive bump by conductive composition printing), 41 ... chip component (electric / electronic component), 41a ... terminal (electrode), 51 ... solder, 51a ... Cream solder, 61 ... Opening, 62 ... Through hole, 72,74 ... Interlayer connection (metal bump formed by metal plate etching), 72A ... Metal plate (copper plate), 81,85 ... Interlayer connection (metal) Metal bumps formed by plate etching), 81A ... Metal plate (copper plate), 89 ... Etching mask, 91, 95 ... Interlayer connection (filled with conductive composition), 101, 105 ... Interlayer connection (formed by plating) 109: plating prevention mask, 109A: mask removing portion, 141: release sheet, ES: etching stopper.

Claims (9)

第1の絶縁層と、
前記第1の絶縁層に対して積層状に位置する第2の絶縁層と、
前記第2の絶縁層に埋め込まれた電気/電子部品と、
前記第1の絶縁層と前記第2の絶縁層とに挟まれて設けられ、かつ、前記電気/電子部品の端子の板厚み方向投影図形に内包される大きさのパターンを該電気/電子部品の実装用ランドとして有する配線パターンと、
前記電気/電子部品の前記端子と前記実装用ランドとを接続する半田部と
を具備することを特徴とする部品内蔵配線板。
A first insulating layer;
A second insulating layer positioned in a stack with respect to the first insulating layer;
An electrical / electronic component embedded in the second insulating layer;
A pattern having a size that is sandwiched between the first insulating layer and the second insulating layer and is included in a projected thickness direction figure of the terminal of the electric / electronic component is the electric / electronic component. A wiring pattern as a mounting land of
A component built-in wiring board comprising: a solder portion that connects the terminal of the electrical / electronic component and the mounting land.
前記第2の絶縁層が、少なくとも2つの絶縁層の積層であり、
前記少なくとも2つの絶縁層の間に挟まれて設けられた第2の配線パターンと、
前記第2の絶縁層の積層方向一部を貫通して前記配線パターンの面と前記第2の配線パターンの面との間に挟設され、かつ導電性組成物からなり、かつ積層方向に一致する軸を有し該軸の方向に径が変化している形状である層間接続体と
をさらに具備することを特徴とする請求項1記載の部品内蔵配線板。
The second insulating layer is a stack of at least two insulating layers;
A second wiring pattern provided between the at least two insulating layers;
The second insulating layer penetrates a part in the stacking direction and is sandwiched between the surface of the wiring pattern and the surface of the second wiring pattern, and is made of a conductive composition and coincides with the stacking direction. 2. The component built-in wiring board according to claim 1, further comprising: an interlayer connection body having a shaft that has a shape that changes in diameter in a direction of the shaft.
前記第2の絶縁層が、少なくとも2つの絶縁層の積層であり、
前記少なくとも2つの絶縁層の間に挟まれて設けられた第2の配線パターンと、
前記第2の絶縁層の積層方向一部を貫通して前記配線パターンの面と前記第2の配線パターンの面との間に挟設され、かつ金属からなり、かつ積層方向に一致する軸を有し該軸の方向に径が変化している形状である層間接続体と
をさらに具備することを特徴とする請求項1記載の部品内蔵配線板。
The second insulating layer is a stack of at least two insulating layers;
A second wiring pattern provided between the at least two insulating layers;
An axis that penetrates a part of the second insulating layer in the stacking direction and is sandwiched between the surface of the wiring pattern and the surface of the second wiring pattern, is made of metal, and coincides with the stacking direction. The component built-in wiring board according to claim 1, further comprising: an interlayer connection body having a shape that has a diameter that changes in a direction of the axis.
前記第1の絶縁層の前記配線パターンが位置する側とは反対側に設けられた第2の配線パターンと、
前記第1の絶縁層を貫通して前記配線パターンの面と前記第2の配線パターンの面との間に挟設され、かつ導電性組成物からなり、かつ積層方向に一致する軸を有し該軸の方向に径が変化している形状である層間接続体と
をさらに具備することを特徴とする請求項1記載の部品内蔵配線板。
A second wiring pattern provided on the side of the first insulating layer opposite to the side on which the wiring pattern is located;
An axis that penetrates the first insulating layer and is sandwiched between the surface of the wiring pattern and the surface of the second wiring pattern, is made of a conductive composition, and coincides with the stacking direction. 2. The component built-in wiring board according to claim 1, further comprising an interlayer connection body having a shape whose diameter changes in a direction of the axis.
前記第1の絶縁層の前記配線パターンが位置する側とは反対側に設けられた第2の配線パターンと、
前記第1の絶縁層を貫通して前記配線パターンの面と前記第2の配線パターンの面との間に挟設され、かつ金属からなり、かつ積層方向に一致する軸を有し該軸の方向に径が変化している形状である層間接続体と
をさらに具備することを特徴とする請求項1記載の部品内蔵配線板。
A second wiring pattern provided on the side of the first insulating layer opposite to the side on which the wiring pattern is located;
An axis that penetrates the first insulating layer and is sandwiched between the surface of the wiring pattern and the surface of the second wiring pattern, is made of metal, and has an axis that coincides with the stacking direction. The component built-in wiring board according to claim 1, further comprising an interlayer connection body having a shape whose diameter changes in the direction.
前記第1の絶縁層の前記配線パターンが位置する側とは反対側に設けられた第2の配線パターンと、
前記第1の絶縁層を貫通して前記配線パターンの面と前記第2の配線パターンの面との間に挟設され、かつ導電性組成物からなり、かつ積層方向に一致する軸を有し該軸の方向に径が変化していない形状である層間接続体と
をさらに具備することを特徴とする請求項1記載の部品内蔵配線板。
A second wiring pattern provided on the side of the first insulating layer opposite to the side on which the wiring pattern is located;
An axis that penetrates the first insulating layer and is sandwiched between the surface of the wiring pattern and the surface of the second wiring pattern, is made of a conductive composition, and coincides with the stacking direction. 2. The component built-in wiring board according to claim 1, further comprising an interlayer connection body having a shape whose diameter does not change in the direction of the axis.
前記第1の絶縁層の前記配線パターンが位置する側とは反対側に設けられた第2の配線パターンと、
前記第1の絶縁層を貫通して前記配線パターンの面と前記第2の配線パターンの面との間に挟設され、かつ金属からなり、かつ積層方向に一致する軸を有し該軸の方向に径が変化していない形状である層間接続体と
をさらに具備することを特徴とする請求項1記載の部品内蔵配線板。
A second wiring pattern provided on the side of the first insulating layer opposite to the side on which the wiring pattern is located;
An axis that penetrates the first insulating layer and is sandwiched between the surface of the wiring pattern and the surface of the second wiring pattern, is made of metal, and has an axis that coincides with the stacking direction. The component built-in wiring board according to claim 1, further comprising an interlayer connection body having a shape whose diameter does not change in the direction.
前記半田部により前記電気/電子部品が前記配線パターンに接続される該電気/電子部品の側とは反対の側の該電気/電子部品の表面が、表出していることを特徴とする請求項1記載の部品内蔵配線板。   The surface of the electrical / electronic component on the side opposite to the electrical / electronic component connected to the wiring pattern by the solder portion is exposed. The component built-in wiring board according to 1. 前記半田部により前記電気/電子部品が前記配線パターンに接続される該電気/電子部品の側とは反対の側の該電気/電子部品の表面が、前記第2の絶縁層により隠されていることを特徴とする請求項1記載の部品内蔵配線板。   The surface of the electrical / electronic component opposite to the electrical / electronic component connected to the wiring pattern by the solder portion is hidden by the second insulating layer. The component built-in wiring board according to claim 1.
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JP2009283689A (en) * 2008-05-22 2009-12-03 Dainippon Printing Co Ltd Method for manufacturing of component-incorporating wiring board, and component-incorporating wiring board
JP2010267845A (en) * 2009-05-15 2010-11-25 Dainippon Printing Co Ltd Component built-in wiring board and method of manufacturing the component built-in wiring board
JP2010272563A (en) * 2009-05-19 2010-12-02 Dainippon Printing Co Ltd Wiring board with built-in component and method of manufacturing the same
JP2012248897A (en) * 2012-09-18 2012-12-13 Dainippon Printing Co Ltd Manufacturing method of component built-in wiring board, and component built-in wiring board
WO2013061500A1 (en) * 2011-10-24 2013-05-02 山一電機株式会社 Flexible wiring board and method for manufacturing same
JP2013225711A (en) * 2013-08-07 2013-10-31 Dainippon Printing Co Ltd Wiring board with component incorporated therein
JP2014053642A (en) * 2013-12-03 2014-03-20 Dainippon Printing Co Ltd Wiring board incorporating component, manufacturing method of wiring board incorporating component
CN103904048A (en) * 2012-12-27 2014-07-02 欣兴电子股份有限公司 Built-in chip packaging structure
JP2015015489A (en) * 2014-09-05 2015-01-22 大日本印刷株式会社 Component built-in wiring board

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63169793A (en) * 1987-01-07 1988-07-13 株式会社村田製作所 Structure of fitting chip parts onto printed board
JP2003037205A (en) * 2001-07-23 2003-02-07 Sony Corp Multilayer substrate with built-in ic-chip, and method of manufacturing the same
JP2004039723A (en) * 2002-07-01 2004-02-05 Matsushita Electric Ind Co Ltd Module with built-in circuit component and its manufacturing method
JP2004265930A (en) * 2003-02-13 2004-09-24 Daiwa Kogyo:Kk Multilayer wiring board and its manufacturing method
JP2005039094A (en) * 2003-07-16 2005-02-10 Dt Circuit Technology Co Ltd Semiconductor chip built-in wiring board and method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63169793A (en) * 1987-01-07 1988-07-13 株式会社村田製作所 Structure of fitting chip parts onto printed board
JP2003037205A (en) * 2001-07-23 2003-02-07 Sony Corp Multilayer substrate with built-in ic-chip, and method of manufacturing the same
JP2004039723A (en) * 2002-07-01 2004-02-05 Matsushita Electric Ind Co Ltd Module with built-in circuit component and its manufacturing method
JP2004265930A (en) * 2003-02-13 2004-09-24 Daiwa Kogyo:Kk Multilayer wiring board and its manufacturing method
JP2005039094A (en) * 2003-07-16 2005-02-10 Dt Circuit Technology Co Ltd Semiconductor chip built-in wiring board and method for manufacturing the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008270479A (en) * 2007-04-19 2008-11-06 Dainippon Printing Co Ltd Electronic component-mounted wiring board and method of preventing exfoliation of electronic component in electronic component-mounted wiring board
JP2009260084A (en) * 2008-04-17 2009-11-05 Dainippon Printing Co Ltd Wiring board with built-in component
JP2009283689A (en) * 2008-05-22 2009-12-03 Dainippon Printing Co Ltd Method for manufacturing of component-incorporating wiring board, and component-incorporating wiring board
JP2010267845A (en) * 2009-05-15 2010-11-25 Dainippon Printing Co Ltd Component built-in wiring board and method of manufacturing the component built-in wiring board
JP2010272563A (en) * 2009-05-19 2010-12-02 Dainippon Printing Co Ltd Wiring board with built-in component and method of manufacturing the same
WO2013061500A1 (en) * 2011-10-24 2013-05-02 山一電機株式会社 Flexible wiring board and method for manufacturing same
JP2012248897A (en) * 2012-09-18 2012-12-13 Dainippon Printing Co Ltd Manufacturing method of component built-in wiring board, and component built-in wiring board
CN103904048A (en) * 2012-12-27 2014-07-02 欣兴电子股份有限公司 Built-in chip packaging structure
JP2013225711A (en) * 2013-08-07 2013-10-31 Dainippon Printing Co Ltd Wiring board with component incorporated therein
JP2014053642A (en) * 2013-12-03 2014-03-20 Dainippon Printing Co Ltd Wiring board incorporating component, manufacturing method of wiring board incorporating component
JP2015015489A (en) * 2014-09-05 2015-01-22 大日本印刷株式会社 Component built-in wiring board

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