JP2004343030A - Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board - Google Patents

Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board Download PDF

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JP2004343030A
JP2004343030A JP2003307897A JP2003307897A JP2004343030A JP 2004343030 A JP2004343030 A JP 2004343030A JP 2003307897 A JP2003307897 A JP 2003307897A JP 2003307897 A JP2003307897 A JP 2003307897A JP 2004343030 A JP2004343030 A JP 2004343030A
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circuit board
formed
bump
surface
wiring
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Kimiyoshi Endo
Asao Iijima
Kazuo Ikenaga
Hiroshi Ohira
洋 大平
和夫 池永
仁誉 遠藤
朝雄 飯島
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North:Kk
株式会社ノース
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    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/3025Electromagnetic shielding

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of steps required for forming solder balls 12 for connecting bumps 6 of a wiring circuit board 2 using the bumps 6 as an interlayer connecting means to another board, e.g. a wiring layer 16 of a printed circuit board 14 to achieve low-cost manufacturing of the wiring circuit board 2. <P>SOLUTION: A plurality of bumps 6 are formed directly or via an etching barrier layer 8 on the surface portion of a wiring layer 10, and an interlayer insulating film 4 is formed on a portion where the bumps 6 are not formed on the bump forming surface of the wiring layer 10, and a solder ball 12 is directly formed on the top of each of the solder balls 6. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、例えばIC、LSI等の電子デバイス実装用の配線回路基板、特に高密度実装を実現できる配線回路基板と、その製造方法と、その配線回路基板を備えた回路モジュールに関する。 The present invention is, for example IC, a printed circuit board for an electronic device mounting the LSI such as a printed circuit board in particular can realize high-density mounting, and its manufacturing method, a circuit module including the wiring circuit board.

本願出願人会社は、多層配線回路基板製造技術として、バンプ形成用の銅層(厚さ例えば100μm)の一方の主面に例えばニッケルからなるエッチングバリア層(厚さ例えば1μm)を例えばメッキにより形成し、更に、該エッチングバリア層の主表面に導体回路形成用の銅箔(厚さ例えば18μm)を形成した配線回路基板形成用部材をベースとして用い、それを適宜加工することにより多層配線回路基板を得る技術を開発し、その開発した技術について例えば特願2002−230142(:特開2002−43506号公報)、特願2002−66410等の出願により提案した。 Applicant company, formed as a multilayer wiring circuit board manufacturing techniques, the one main surface, for example etching barrier layer made of nickel (thickness e.g. 1 [mu] m), for example, copper plating layer for forming bumps (having a thickness of, for example 100 [mu] m) and, further, multi-layer wiring circuit board by using copper foil (having a thickness of, for example, 18 [mu] m) wiring circuit board forming member formed with a conductor circuit formed on the main surface of the etching barrier layer as a base, to process it appropriately We developed a get techniques, for example, Japanese Patent application for technology that developed 2002-230142 (: JP 2002-43506 JP), proposed by the applicant such as Japanese Patent application No. 2002-66410.

このようなバンプを活かした配線回路基板のバンプと、他のプリント回路基板の配線層との半田ボールを介しての接続は、従来においては、図14に示すように行われていた。 Connection of such a bump of the wiring circuit board utilizing bumps, through the solder balls and the wiring layer of another printed circuit board, conventionally, has been performed as shown in FIG. 14.
同図において、aは配線回路基板の層間絶縁膜で、例えばポリイミドからなる。 In the figure, a is an interlayer insulating film of a printed circuit board, for example made of polyimide. bは銅からなるバンプ、cはニッケルからなるエッチングバリア層、dは銅からなる配線層、eは上記層間絶縁膜aの各バンプb毎にその頂面を開口させるようにその上部に形成された開口孔、fは該各開口孔に形成された半田ボール下地膜で、銅下地上にニッケル、金等により形成された多層構造を有し、メッキ等により形成される。 b bumps made of copper, c is etching barrier layer made of nickel, d wiring layer made of copper, e is formed thereon so as to open the top face each bump b of the interlayer insulating film a opening holes, f is the solder ball base film formed respective openings, nickel on the copper underlayer, having a multilayer structure formed by gold or the like, is formed by plating or the like.

このような配線回路基板は、例えば次のようにしてつくられる。 Such a wired circuit board, for example made in the following manner. 上記バンプbとなる厚い銅層と、エッチングバリア層cとなるニッケル層と、配線層dとなる薄い銅層を積層した三層構造の金属層を用意し、その銅層bを選択的にエッチングする(その際にエッチングバリア層cがエッチングストッパとなって配線層dとなる薄い銅層が侵蝕されるのを阻む)ことによりバンプbを形成し、その後、上記層間絶縁膜aのバンプb部の上面から選択的にポリイミド樹脂を化学的にエッチングすることにより或いはレーザ光照射をすることにより上記開口孔eを形成する。 A thick copper layer serving as the bump b, and prepared a nickel layer as an etching barrier layer c, and a metal layer of a three-layer structure of a thin copper layer as a wiring layer d, selectively etching the copper layer b to (the time the etching barrier layer c is thwart the thin copper layer as a wiring layer d becomes an etching stopper is attack on) to form a bump b by, then the bump b of the interlayer insulating film a by or by laser light irradiation etching from the upper surface selectively polyimide resin chemically to form the openings e.

その後、メッキにより上記半田ボール下地膜fを形成し、該半田ボール下地膜fを選択的にエッチングすることにより配線回路を形成し、更に、銅層dの選択的エッチングにより配線層dを形成する。 Then, by plating to form the solder balls underlayer f, to form a wiring circuit by selectively etching the solder ball base film f, further forming a wiring layer d by selective etching of the copper layer d . その後、上記選択的にエッチングされた各半田ボール下地膜f上に半田ボールgを形成する。 Thereafter, a solder ball g of the above selectively each solder ball base film f etched.
そして、上記各配線層dには図示しないLSI等の半導体チップの各電極が接続される等して配線回路基板に半導体チップがフェースダウンあるいはフェースアップで搭載される。 Then, the above-described wiring layers d semiconductor chip is mounted face down or face-up and the like each electrode of the semiconductor chip such as an LSI (not shown) is connected to the wiring circuit board.

更に、その配線回路基板には、図14に示すようにプリント回路基板hに搭載される。 Furthermore, its printed circuit board, are mounted on a printed circuit board h, as shown in FIG. 14. 具体的には、プリント回路基板hの各配線層iを、配線回路基板の、該各配線層iに対応する半田ボールgに接続することにより、配線回路基板がプリント回路基板hに搭載される。 Specifically, the respective wiring layers i of the printed circuit board h, the printed circuit board, by connecting the solder balls g corresponding to respective wiring layers i, the wiring circuit board is mounted on the printed circuit board h .
特開2002−43506号公報 JP 2002-43506 JP 特願2002−66410 Japanese Patent Application No. 2002-66410

ところで、上述した従来の技術には、配線回路基板に層間絶縁膜aを形成した後、半田ボールgを形成するまでに要する工程数が多く、製造コストが高くなるという問題があった。 Incidentally, the conventional technology described above, after forming an interlayer insulating film a wiring circuit board, the number of steps required until forming solder balls g lot, there is a problem that manufacturing cost becomes high.
即ち、上記従来の技術によれば、層間絶縁膜aの形成後、その選択的エッチングにより開口孔eを形成し、メッキにより複数層の半田ボール下地膜fを形成し、その選択的エッチングを行って各バンプb毎にそれと接続された半田ボール下地膜fが独立するようにパターニングし、その後、半田ボールgを形成するというかなり多くの工程が必要であった。 That is, according to the prior art described above, after formation of the interlayer insulating film a, to form an opening hole e by its selective etching, to form the solder balls base film f of the plurality of layers by plating, performed the selective etching patterned so connected solder balls base film f it independently for each bump b Te, then quite a lot of steps of forming a solder ball g was required.

本発明はこのような問題を解決すべく為されたもので、バンプを層間接続手段とする配線回路基板の該バンプと他の基板、例えばプリント回路基板の配線層等との間を接続するのに要する工程を少なくすることのできるようにし、延いては、配線回路基板の低価格化を図ることを目的とする。 The present invention has been made to solve the above problems, to connect the printed circuit said bumps and other substrates of the substrate bumps and interlayer connecting member, between the example wiring layer of a printed circuit board or the like as capable of reducing the steps required for, by extension, it aims to reduce the cost of the printed circuit board.

請求項1の配線回路基板は、配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、該配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成したことを特徴とする。 Printed circuit board according to claim 1, directly or through an etching barrier layer to form a plurality of bumps, the interlayer insulation is not formed part of the bumps of the bump formation surface of the wiring layer on the surface portion of the interconnect layer film is formed, the top surface of the bump, directly or via a wiring layer formed so as to connect with the bumps on the surface of the interlayer insulating film, characterized in that the formation of the solder balls.
尚、配線層と、バンプとの間に、エッチングバリア層を設けることは必ずしも不可欠ではない。 Incidentally, the wiring layers, between the bumps, the provision of the etch barrier layer is not necessarily essential. というのは、金属層を一方の表面側から選択的にハーフエッチング(金属層の厚さよりも適宜浅いエッチング)することによりバンプを形成するということが可能であり、その場合にはエッチングバリア層が必要ではないからである。 Because, it is possible that they form a bump by a metal layer selectively half-etched from one surface side (than the thickness appropriately shallow etching of the metal layer), the etching barrier layer in that case is This is because not required. このことは、他の請求項の配線回路基板にも当てはまる。 This also applies to the wiring circuit board of the other claims.

請求項2の配線回路基板は、請求項1記載の配線回路基板において、前記配線層及びバンプが銅からなることを特徴とする。 Printed circuit board according to claim 2, in the printed circuit board according to claim 1, wherein the wiring layer and the bump are made of copper.
請求項3の配線回路基板は、請求項1又は2記載の配線回路基板において、前記層間絶縁膜に、バンプが多数形成されたバンプ形成領域と、バンプが形成されないフレキシブルなバンプ非形成領域とを有し、該バンプ非形成領域が曲折可能にしてなる或いは少なくとも一部にて曲折してなることを特徴とする。 Printed circuit board according to claim 3, in the printed circuit board according to claim 1 or 2 wherein, in the interlayer insulating film, and a bump formation region on which the bumps are formed a large number, and a flexible bump formed area where the bumps are not formed a, the bump-formed region is characterized by being bent at to become or at least in part on the bendable.

請求項4の配線回路基板は、請求項1、2又は3記載の配線回路基板において、前記各バンプの頂面が凹球面に形成され、上記バンプの凹球面に形成された上記頂面に直接に半田ボールが形成されてなることを特徴とする。 Printed circuit board according to claim 4, in the printed circuit board according to claim 1, 2 or 3, wherein said top surface of each bump is formed on the concave spherical surface, directly on the top surface formed on the concave spherical surface of the bump wherein the solder balls is formed on.

請求項5の回路モジュールは、配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成したフレキシブルな配線回路基板と、リジットな絶縁基板の少なくとも一方の表面に上記配線膜と接続される配線膜が形成されたリジットな配線回路基板と、からなり、上記フレキシブルな配線回路基板の配線膜の少なくとも一部と、上記リジットな配線回路基板の配線膜の少なくとも一部とが、上記半田ボールを介して接続されてなることを特徴とする。 The circuit module of claim 5, directly or via etching barrier layer on the surface portion of the wiring layer to form a plurality of bumps, the interlayer insulating film in the portion which is not formed in the bump of the bump formation surface of the wiring layer forming a, the top surface of the bump, directly, or in the interlayer insulating film surface via a wiring layer formed so as to connect with the bumps, a flexible wiring circuit board forming the solder balls, rigid and a rigid printed circuit board on which a wiring layer to be connected to the wiring layer is formed on at least one surface of the Do insulating substrate made of, at least a portion of the wiring layer of the flexible wiring circuit board, which said rigid at least part of the wiring layer of the wiring circuit board, characterized by comprising connected via the solder balls.

請求項6の回路モジュールは、配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成したフレキシブルな配線回路基板と、フレキシブルな絶縁基板の少なくとも一方の表面に上記配線膜と接続される配線膜が形成された上記配線回路基板とは別のフレキシブルな配線回路基板と、からなり、上記フレキシブルな配線回路基板の配線膜の少なくとも一部と、上記別のフレキシブルな配線回路基板の配線膜の少なくとも一部とが、上記半田ボールを介して接続されてなることを特徴とする。 The circuit module of claim 6, directly or via etching barrier layer on the surface portion of the wiring layer to form a plurality of bumps, the interlayer insulating film in the portion which is not formed in the bump of the bump formation surface of the wiring layer forming a, the top surface of the bump, directly, or in the interlayer insulating film surface via a wiring layer formed so as to connect with the bumps, a flexible wiring circuit board forming the solder balls, flexible and another flexible printed circuit board and the wiring circuit board on which a wiring layer is formed to be connected to the wiring layer on at least one surface of the Do insulating substrate made, the wiring film of the flexible printed circuit board at least a portion, and at least a part of the wiring layer of the another flexible printed circuit board, characterized by comprising connected via the solder balls.

請求項7の回路モデュールは、請求項5又は6記載の回路モデュールにおいて、前記各バンプの頂面が凹球面に形成され、上記バンプの凹球面に形成された上記頂面に直接に半田ボールが形成されてなることを特徴とする。 Circuit module of claim 7, in the circuit module according to claim 5 or 6, wherein said top surface of each bump is formed on the concave spherical surface, directly to the solder ball on the top surface formed on the concave spherical surface of the bumps It is formed, characterized by comprising.
請求項8の配線回路基板の製造方法は、金属層の表面に直接に又はエッチングバリア層を介してバンプを形成した基板を用意し、該基板の金属層のバンプ形成側の面のバンプが形成されていない部分にバンプより厚く層間絶縁膜を形成し、上記基板の層間絶縁膜を上記各バンプの頂面が露出するまで研磨し、該基板の上記各バンプの露出する頂面上に半田ボールを形成することを特徴とする。 Method of manufacturing a printed circuit board according to claim 8, directly or prepared substrate formed with bumps through the etching barrier layer, the bumps of the surface of the bump formation side of the metal layer of the substrate is formed on the surface of the metal layer is thicker to form an interlayer insulating film than bump portions not, an interlayer insulating film of the substrate was polished until the top surface of each bump is exposed, the solder balls on the top surface to expose the respective bumps of the substrate and forming a.

請求項9の配線回路基板の製造方法は、金属層の表面に直接に又はエッチングバリア層を介してバンプを形成した基板を用意し、該基板の金属層のバンプ形成側の面のバンプが形成されていない部分にバンプより厚く層間絶縁膜を形成し、上記基板の層間絶縁膜を上記各バンプの頂面が露出するまで研磨し、該基板の上記層間絶縁膜の表面に金属層を形成し、該層間絶縁膜表面の金属層を選択的にエッチングすることにより配線層を形成し、各バンプの露出する頂面上に又は該バンプと接続された上記配線層上に半田ボールを形成することを特徴とする。 Method of manufacturing a printed circuit board according to claim 9, directly or prepared substrate formed with bumps through the etching barrier layer, the bumps of the surface of the bump formation side of the metal layer of the substrate is formed on the surface of the metal layer is thicker to form an interlayer insulating film than bump portions not, an interlayer insulating film of the substrate was polished until the top surface of each bump is exposed, the metal layer is formed on the surface of the interlayer insulating film of the substrate , forming a solder ball on a wiring layer is formed, the wiring layer connected to or the bumps on the top surface to expose the respective bumps by selectively etching the metal layer of the interlayer insulating film surface the features.

請求項10の配線回路基板の製造方法は、請求項8又は9記載の配線回路基板の製造方法において、前記層間絶縁膜を形成するよりも前に、各バンプを上から加圧して押し潰すことによりその頂面の径を大きくする工程を有することを特徴とする。 Method of manufacturing a printed circuit board according to claim 10 is a method of manufacturing a printed circuit board according to claim 8 or 9, wherein before forming the interlayer insulating film, the crushed under pressure from the top of each bump It characterized by having a step of increasing the diameter of its top surface by.
請求項11の配線回路基板の製造方法は、請求項8、9又は10記載の配線回路基板の製造方法において、前記基板の前記層間絶縁膜を前記各バンプの頂面が露出するまで研磨した後、該バンプの露出した頂面上に前記半田ボールを形成する前に、該バンプの頂面をエッチングすることにより凹球面にする工程を有することを特徴とする。 Method of manufacturing a printed circuit board according to claim 11 is a method of manufacturing a printed circuit board according to claim 8, 9 or 10 wherein, after polishing the interlayer insulating film of the substrate to the top surface of each bump is exposed , before forming the solder balls on the exposed top surface of the bump, characterized by having a step of the concave spherical surface by etching the top surface of the bump.

請求項12の回路モジュールは、配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成した一つの配線回路基板と、液晶素子の基板を成し、透明配線膜を有する液晶装置用透明基板と、からなり、上記一つの配線回路基板の各バンプと、上記別の液晶装置用透明基板の透明配線膜の上記各バンプと対応する部分とが、直接に或いは上記バンプの頂面に形成した配線膜及び半田ボールを介して接続されて液晶装置を成すことを特徴とする。 The circuit module of claim 12, directly or via etching barrier layer on the surface portion of the wiring layer to form a plurality of bumps, the interlayer insulating film in the portion which is not formed in the bump of the bump formation surface of the wiring layer and one of the wiring circuit substrate formed with, form a substrate of a liquid crystal device, a transparent substrate for a liquid crystal device having a transparent wiring film made of, and the bumps of the one printed circuit board, for the further liquid crystal device and each bump transparent wiring film of the transparent substrate and corresponding parts, are directly or connected through a wiring layer and solder balls were formed on the top surface of the bump, wherein the forming the liquid crystal device.

請求項13の回路モジュールは、請求項12記載の回路モジュールにおいて、前記一つの配線回路基板の各バンプの頂面が凹球面に形成され、その凹球面に形成された上記頂面に直接に半田ボールが形成されてなることを特徴とする。 The circuit module of claim 13, in the circuit module according to claim 12, wherein the top surface of each bump of the one printed circuit board is formed on the concave spherical surface, directly solder the top surface formed on the concave spherical surface ball, characterized in that is formed.

請求項1の配線回路基板によれば、バンプの頂面に直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して半田ボールを形成してなるので、半田ボールの下地となる半田ボール下地膜をわざわざ形成する必要がなくなり、配線回路基板を製造するに必要となる製造工数の低減を図ることができる。 According to the wired circuit board according to claim 1, directly to the top surface of the bump, or because by forming a solder ball through a wiring layer formed to be connected with the bumps on the surface of the interlayer insulating film, it is not necessary to specially form the solder balls underlying film underlying the solder balls, it is possible to reduce the manufacturing steps required for manufacturing a wiring circuit board.
従って、配線回路基板の低価格化を図ることができる。 Therefore, it is possible to reduce the cost of the printed circuit board.

請求項2の配線回路基板によれば、前記配線層及びバンプが比抵抗が小さな銅からなるので、寄生抵抗を低減することができる。 According to the wired circuit board according to claim 2, wherein the wiring layer and the bump because specific resistance of small copper, it is possible to reduce the parasitic resistance.
請求項3の配線回路基板によれば、前記層間絶縁膜に、バンプが多数形成されたバンプ形成領域と、バンプが形成されないバンプ非形成領域とを設け、その一部を曲折して使用するので、LSI等の半導体チップを立体的に配置して使用することができ、限られた空間内に多数のチップを高密度配置することができる。 According to the wired circuit board according to claim 3, wherein the interlayer insulating film, and a bump formation region on which the bumps are formed a large number, and a bump-free region where the bump is not formed is provided, because it uses by bending a part of , semiconductor chips such as LSI and arranged three-dimensionally can be used, it is possible to densely arrange a plurality of chips in a limited space.

請求項4の配線回路基板によれば、請求項1、2又は3の配線回路基板において、バンプの凹球面に形成された頂面に半田ボールを直接に形成するので、接続面積をより広くし、接続強度をより強めることができるので、より信頼度を高め、寿命を長くすることができる。 According to the wired circuit board according to claim 4, in the printed circuit board according to claim 1, 2 or 3, so to form a solder ball directly to the top surface formed on the concave spherical surface of the bump, a connection area with wider , it is possible to enhance more the connection strength, more enhanced reliability, it is possible to increase the life.
請求項5の回路モジュールによれば、請求項1に係るフレキシブルな配線回路基板と、リジットな配線回路基板とを接続してなるので、フレキシブルな配線回の電極をフレキシブルな配線回路基板によって引き出すというようなことが為し得る。 According to the circuit module according to claim 5, the flexible printed circuit board according to claim 1, since by connecting the rigid wiring circuit board, that elicit electrodes of the flexible wiring times by a flexible printed circuit board it may be made, such as.

請求項6の回路モジュールによれば、請求項1に係るフレキシブルな配線回路基板と、フレキシブルな配線回路基板とを接続してなるので、フレキシブルな配線回路基板同士を一体化した回路モジュールを提供することができる。 According to the circuit module according to claim 6, a flexible printed circuit board according to claim 1, since by connecting the flexible printed circuit board, to provide a circuit module that integrates a flexible wiring circuit boards be able to.
請求項7の回路モジュールによれば、請求項5又は6記載の回路モジュールにおいて、バンプの凹球面に形成された頂面に半田ボールを直接に形成するので、接続面積をより広くし、接続強度をより強めることができるので、より信頼度を高め、寿命を長くすることができる。 According to the circuit module according to claim 7, in the circuit module according to claim 5 or 6, wherein, because it forms a solder ball directly to the top surface formed on the concave spherical surface of the bumps, and wider connection area, the connection strength it is possible to enhance more the more enhanced reliability, it is possible to increase the life.

請求項8の配線回路基板の製造方法によれば、金属層の表面にバンプを形成した基板を用意し、該基板の金属層のバンプ形成側の面にバンプより厚く層間絶縁膜を形成し、該層間絶縁膜を上記各バンプの頂面が露出するまで研磨し、該基板の上記各バンプの露出する頂面上に半田ボールを形成するので、請求項1の配線回路基板を製造することができる。 According to the manufacturing method of the printed circuit board according to claim 8, providing a substrate formed with bumps on the surface of the metal layer thicker to form an interlayer insulating film than the bumps on the surface of the bump formation side of the metal layer of the substrate, the interlayer insulating film is polished until the top surface of each bump is exposed, since the solder balls are formed on the top surface to expose the respective bumps of the substrate, it is possible to manufacture a printed circuit board according to claim 1 it can.

請求項9の配線回路基板の製造方法によれば、金属層の表面にバンプを形成した基板を用意し、該基板の金属層のバンプ形成側の面にバンプより厚く層間絶縁膜を形成し、該層間絶縁膜を上記各バンプの頂面が露出するまで研磨し、該基板の上記各バンプの露出する頂面上に半田ボールを形成し、該基板の上記層間絶縁膜の表面に金属層を形成し、該層間絶縁膜表面の金属層を選択的にエッチングすることにより配線層を形成し、上記各バンプの露出する頂面上に又は該バンプと接続された上記配線層上に半田ボールを形成したので、層間絶縁膜の両面に配線膜を有する配線回路基板を製造することができる。 According to the manufacturing method of the printed circuit board according to claim 9, providing a substrate formed with bumps on the surface of the metal layer thicker to form an interlayer insulating film than the bumps on the surface of the bump formation side of the metal layer of the substrate, the interlayer insulating film is polished until the top surface of each bump is exposed, the solder balls are formed on the top surface to expose the respective bumps of the substrate, the metal layer on the surface of the interlayer insulating film of the substrate formed, a wiring layer is formed by selectively etching the metal layer of the interlayer insulating film surface, the solder balls on the top surface on or the bump and connected the wiring layer exposed in the respective bump since the formed, it is possible to manufacture a printed circuit board having a wiring film on both surfaces of the interlayer insulating film.

請求項10の配線回路基板の製造方法によれば、前記層間絶縁膜を形成する前に、各バンプを上から加圧して押し潰すことによりその頂面の径を大きくするので、半田ボールの各バンプへの接着強度を充分に強めることが容易に為し得る。 According to the manufacturing method of the printed circuit board according to claim 10, before forming the interlayer insulating film, since increasing the diameter of its top surface by the respective bumps crushed under pressure from above, the solder balls each to enhance the bonding strength of the bumps sufficiently can easily None.
請求項11の配線回路基板の製造方法は、請求項8、9又は10記載の配線回路基板の製造方法において、前記層間絶縁膜を前記各バンプの頂面が露出するまで研磨した後、該バンプの露出した頂面上に前記半田ボールを形成する前に、該バンプの頂面をエッチングすることにより凹球面にするので、その後、その頂面に形成する半田ボールのその頂面との接続面積をより広くし、接続強度をより強めることができる。 Method of manufacturing a printed circuit board according to claim 11 is a method of manufacturing a printed circuit board according to claim 8, 9 or 10 wherein, after the interlayer insulating film is a top surface of each bump was polished to expose, said bump before forming the solder balls on the exposed top surface on, since the concave spherical surface by etching the top surface of the bump, then, the connection area between the top surface of the solder balls formed on the top surface it can be more widely, enhance more the connection strength. 従って、配線回路基板の信頼度をより高め、寿命を長くすることができる。 Therefore, increase more the reliability of the wiring circuit board, it is possible to increase the life.

請求項12の回路モジュールによれば、液晶装置の透明配線膜を、請求項1の配線回路基板を通じて引き出すようにすることができる。 According to the circuit module of claim 12, the transparent wiring film of the liquid crystal device, it is possible to draw through the wiring circuit board according to claim 1.
請求項13の回路モジュールによれば、請求項12の回路モジュールにおいて、バンプの凹球面に形成された頂面に半田ボールを直接に形成するので、接続面積をより広くし、接続強度をより強めることができるので、より信頼度を高め、寿命を長くすることができる。 According to the circuit module according to claim 13, in the circuit module according to claim 12, because it forms a solder ball directly to the top surface formed on the concave spherical surface of the bump, the connection area is wider, enhance more the connection strength it is possible, further enhanced reliability, it is possible to increase the life.

本発明は、基本的には、回路モジュール等に用いられる配線回路基板として、配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、該配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成したものを提供するというものであり、上記のバンプは銅により形成することが好ましい。 The present invention is basically as a wiring circuit board for use in circuit modules or the like, directly or via etching barrier layer on the surface portion of the wiring layer to form a plurality of bumps, the bump formation faces of the wiring layer forming an interlayer insulating film in the portion which is not formed of the bumps, the top surface of the bump, directly or via a wiring layer formed so as to connect with the bumps on the surface of the interlayer insulating film, solder is intended that provides one formed a ball, it is preferable that the bumps are made of copper. というのは、導電性、機械的強度が優れ、また、バンプを銅により形成して層間接続手段として用いる技術は既に本願出願人会社において確立した技術となっているからである。 Because the electrical conductivity, excellent mechanical strength, Further, a technique of using as the interlayer connecting means a bump formed by copper because has a technique already established in the present applicant company.

本発明配線回路基板の一つの良好な実施の形態は、バンプを設けたバンプ形成領域と、バンプを設けないバンプ非形成領域を設け、該バンプ非形成領域を以てフレキシブルな領域とし、バンプ形成領域を以てリジットな領域とするというものである。 One good embodiment of the present invention the wiring circuit board, a bump formation region having a bump, the bump-free region provided with no bumps provided, and a flexible region with a said bump-free region, with a bump formation region it is that the rigid region.
また、別の良好な実施形態として、バンプはその形成後、層間絶縁膜形成前に、上から押し潰してその頂面の面積を広くすることが挙げられる。 As another favorable embodiment, the bumps after their formation, before forming an interlayer insulating film, and is possible to widen the area of ​​the top surface crushed from above. その面積を広くすることはバンプと半田ボールとの接続面積の増大に繋がり、延いては、接続強度の増大、信頼性の向上に繋がるからである。 Possible to increase the area leads to an increase in contact area between the bump and the solder balls, by extension, increased connection strength, because leads to improvement of reliability.

また、バンプの半田ボールとの接続面となる頂面を例えばエッチングにより凹球面に形成し、その凹球面に形成された頂面に半田ボールを直接に形成することとすることも良好な実施の形態例として挙げられる。 Further, for example, by etching a connecting surface to become the top surface of the solder ball bumps formed on the concave spherical surface, also good practice be to form a solder ball directly to the top surface formed on the concave spherical surface It cited as example forms. というのは、接続面積をより広くし、また半田ボールが基板に食い込んだ形になるので、接続強度をより強めることができるので、より信頼度を高め、寿命を長くすることができるからである。 Is a connection area and more widely, and because solder balls become shape bites into the substrate, it is possible to enhance more the connection strength, because more enhanced reliability, it is possible to increase the life because .
尚、バンプの半田ボールとの接続面となる頂面を例えばエッチングにより凹球面に形成することとする実施の形態は、本発明における、バンプの頂面に直接半田ボールを形成することとするすべての形態に対して適用することができる。 Note that embodiments to be formed on the concave spherical surface a top surface, for example, by etching a connecting surface with the solder ball bumps are all to be in the present invention, to form a direct solder balls on the top surface of the bump it can be applied to the form.

以下、本発明を図示実施例に従って詳細に説明する。 Hereinafter will be described in detail with the illustrated embodiment of the present invention.
図1は本発明配線回路基板の第1の実施例を示す断面図である。 Figure 1 is a sectional view showing a first embodiment of the present invention the printed circuit board.
図において、2は配線回路基板、4はポリイミド樹脂からなる層間絶縁膜、6は該層間絶縁膜4を略貫通するように形成された略コニーデ状のバンプで、銅からなる。 In FIG, 2 is a wiring circuit board, 4 denotes an interlayer insulating film made of a polyimide resin, 6 stands volcano-shaped bumps formed so as to substantially penetrate the interlayer insulating film 4, made of copper. そして、各バンプ6の頂面は、層間絶縁膜4から露出し、該層間絶縁膜4表面と同一平面上に位置するようにされている。 Then, the top surface of each bump 6 is exposed from the interlayer insulating film 4, which is to be located on the interlayer insulating film 4 flush with the surface.

8は該バンプ6の底面に形成されたニッケルからなるエッチングバリア層、10は銅からなる配線層で、上記各バンプ6は上記エッチングバリア層8を介して該配線層10に形成されている。 8 etch barrier layer made of nickel is formed on the bottom surface of the bump 6, 10 is a wiring layer made of copper, each of the bumps 6 are formed on the wiring layer 10 through the etching barrier layer 8. 尚、該配線層10は銅膜表面に金、銀、ロジウム、錫、半田、アルミニウム等を被覆したものであっても良い。 Incidentally, gold wiring layer 10 is the surface of the copper film, silver, rhodium, tin, solder, or may be coated with aluminum or the like. 該配線層10には図1、2では図示を省略した半導体チップの電極が、或いはハンダボール付きのIC(フリップチップ)が直接に或いはボンディングワイヤを介して接続される。 The wiring layer 10 is a semiconductor chip of electrodes not shown in FIGS. 1 and 2, or IC with a solder ball (flip chip) is connected directly or via a bonding wire. 尚、この接続態様の各別の例を図4(A)、(B)に示し、また、その説明を後で行う。 Incidentally, FIG. 4 each another example of the connection mode (A), shown (B), the addition is performed the description later.

12は各バンプ6の頂面に形成された半田ボール、14は配線回路基板2にマウントされる例えばリジットなプリント回路基板(2点鎖線で示した。)、16は該プリント回路基板14の表面に形成された配線層(2点鎖線で示した。)である。 12 each solder ball formed on the top surface of the bump 6, 14 is the example rigid printed circuit board mounted on the printed circuit board 2 (shown in two-dot chain line.), 16 the surface of the printed circuit board 14 (indicated by a two-dot chain line.) formed wiring layer is.
尚、該各配線層16に、それと対応するところの配線回路基板2のバンプ6を半田ボール12を介して接続することにより、配線回路基板2のプリント回路基板14への配線回路基板2の搭載が行われる。 Incidentally, the respective wiring layers 16, therewith corresponding bumps 6 of the printed circuit board 2 where the by connecting via the solder balls 12, mounted in the wiring circuit board 2 to a printed circuit board 14 of the wiring circuit board 2 It is carried out. すると、配線回路基板2とプリント回路基板14からなる回路モジュールができる。 Then, it is the circuit module comprising a printed circuit board 2 and the printed circuit board 14. 配線回路基板2は薄くフレキシブルであるのに対して、プリント回路基板14は上述したようにリジットであるので、その回路モジュールは、リジットなプリント回路基板14とフレキシブルな配線回路基板2を組み付けたものとなる。 Whereas the printed circuit board 2 is thin and flexible, since the printed circuit board 14 is a rigid, as described above, the circuit module, which assembled the rigid printed circuit board 14 and the flexible wiring circuit board 2 to become. 従って、例えばリジットなプリント回路基板14の電極乃至端子等をフレキシブルな配線回路基板2により電気的に導出するというような回路モジュールを得ることができる。 Therefore, it is possible to obtain a circuit module such that electrically led for example electrodes or terminals, etc. of the rigid printed circuit board 14 by a flexible printed circuit board 2.

このような配線回路基板2によれば、層間絶縁膜4の表面に露出する各バンプ6の頂面に直接半田ボール12を形成するので、半田ボールの下地となる半田ボール下地膜をわざわざ形成する必要がなくなり、配線回路基板2を製造するに必要となる製造工数の低減を図ることができる。 According to this wired circuit board 2, because it forms a direct solder balls 12 on the top surface of each bump 6 exposed on the surface of the interlayer insulating film 4, specially forming solder balls underlying film underlying the solder balls it is not necessary, it is possible to reduce the manufacturing steps required for manufacturing the wiring circuit board 2.

以下に、断面図である図2(A)〜(D)及び図3(E)〜(H)に従って図1に示した配線回路基板(第1の実施例)2の製造方法を工程順(A)〜(H)に説明する。 Hereinafter, a cross-sectional view FIG. 2 (A) ~ (D) and FIG. 3 (E) ~ (H) according to the wiring circuit board (first embodiment) shown in FIG. 1 second manufacturing method process steps ( A) will be explained ~ (H).
(A)図2(A)に示すように、中間層としてエッチングバリア層を含む三層構造の金属板20を用意する。 (A) As shown in FIG. 2 (A), it is prepared a metal plate 20 of a three-layer structure including an etch barrier layer as an intermediate layer. 20aは該金属板20の銅からなる厚い金属層で、選択的エッチングにより上記バンプ6となる。 20a is a thick metal layer of copper of the metal plate 20, and the bumps 6 by selective etching. 20bは該金属板20の中間層を成すエッチングバリア層(8)で、上記厚い金属層20aの選択的エッチングのときに次に述べる銅からなる薄い金属層(20c)が侵蝕(エッチング)されることを阻む役割を果たす。 20b is etched barrier layer forming the intermediate layer of the metal plate 20 (8), the thick thin metal layer made of copper described below when the selective etching of the metal layer 20a (20c) is attack (etching) It serves to prevent that. 20cは選択的エッチングにより配線層10となる薄い銅からなる金属層である。 20c is a metal layer made of thin copper serving as the wiring layer 10 by selective etching.

(B)次に、例えばフォトレジスト膜の塗布形成、露光、現像等によりエッチングマスク膜を形成し、該エッチングマスク膜をマスクとして上記厚い金属層20aを選択的にエッチングすることにより、バンプ6を形成する。 (B) Next, for example, coating the formation of a photoresist film, exposed by development or the like to form an etching mask film, by selectively etching the thick metal layer 20a of the etching mask film as a mask, the bumps 6 Form. その後、エッチングマスク膜を除去する。 Thereafter, the etching mask film is removed. 図2(A)はそのエッチングマスク膜の除去後の状態を示す。 FIG. 2 (A) shows a state after removal of the etching mask film.
(C)次に、上記エッチングバリア層20b(8)を、上記バンプ6をマスクとしてエッチングすることにより除去する。 (C) Next, the etching barrier layer 20b (8), is removed by etching the bump 6 as a mask. 図2(C)はその除去後の状態を示す。 FIG. 2 (C) shows the state after its removal.

(D)次に、前駆体の状態にある液状の例えばポリイミド樹脂をコータ等により塗布し、べーク処理することによりイミド化を行い、丈夫なポリイミド樹脂にする。 (D) Next, a polyimide resin, for example a liquid in the state of the precursor is applied by coater performs imidization by treating baking, to durable polyimide resin. 該樹脂はバンプ6の高さより若干厚く、従って各バンプ6を覆う層間絶縁膜4を形成する。 The resin slightly thicker than the height of the bumps 6, thus forming an interlayer insulating film 4 covering each bump 6. 図2(D)は該層間絶縁膜4形成後の状態を示す。 Figure 2 (D) shows the state after the interlayer insulating film 4 formed.
(E)次に、上記層間絶縁膜4の表面部を、上記各バンプ6の頂面が完全に露出するまで研磨し、絶縁樹脂層とバンプ頂面を面一にする。 (E) Next, the surface portion of the interlayer insulating film 4, the top surface of each bump 6 is polished to completely exposed, the insulating resin layer and the bump top surface flush. 図3(E)はその研磨後の状態を示す。 Figure 3 (E) shows the state after polishing.

(F)次に、上記金属層20cを選択的にエッチングすることにより配線層10を形成する。 (F) Next, a wiring layer 10 by selectively etching the metal layer 20c. 尚、該配線層10の形成前又は形成後に2点鎖線で示すように、例えば半田レジストからなるダム18を形成して半田接合面の均一化とダレによるショート防止を図るようにしても良い。 As it is shown by two-dot chain line before or after the formation of the wiring layer 10, may be achieved preventing short circuit caused by uniform and sagging of the solder joint surface to form a dam 18, for example made of solder resist.
(G)次に、半田ボールとなる球状半田を各バンプ6の上記層間絶縁膜4から露出する頂面上に配置し、配線回路基板2を加熱炉に通してリフロー処理することにより各バンプ6頂面に該バンプ6接続固定された半田ボール12を形成する。 (G) Next, the spherical solder comprising the solder ball disposed on the top surface exposed from the interlayer insulating film 4 of the bumps 6, each of the bumps 6 by reflow processing through the printed circuit board 2 in a heating furnace forming the bump 6 connected fixed solder ball 12 to the top surface. 図3(G)はそのリフロー処理後の状態を示す。 Figure 3 (G) shows the state after the reflow treatment.

尚、球状半田の配置は、具体的には、各バンプ6の頂面と対応する位置関係で球状半田を位置させ、真空吸引でその球状半田をその位置に保持できる治具を用い、その治具を、各球状半田が対応するバンプ6上に位置するように位置させ、真空吸引を停止することにより各球状半田の自重により対応するバンプ6頂面上に落させて位置させるという方法で行うこともできる。 The arrangement of the spherical solder, specifically, a spherical solder is positioned in a positional relationship corresponding to the top surface of each bump 6, using a jig capable of holding the spherical solder in position by vacuum suction, the Osamu the ingredients, each spherical solder is positioned to be located on a corresponding bump 6, carried out in a way that by dropping to a corresponding bump 6 top plane is positioned by the weight of the spherical solder by stopping the vacuum suction it is also possible. また、半田クリームをバンプ面に選択的に印刷し、加熱リフローすることにより、半田ボールを形成するようにしても良い。 Further, a solder cream is selectively printed on the bump surface, by heating reflow, it may be formed of solder balls.

(H)図3(H)は、プリント回路基板14に該配線回路基板2を搭載した状態を示す。 (H) Fig. 3 (H) shows a state in which mounting the wiring circuit board 2 to a printed circuit board 14. 尚、一般に、該配線回路基板2にはプリント回路基板等への搭載前に、例えば半導体チップ等が搭載されるが、図3ではその半導体チップの図示を省略した。 In general, prior to mounting on a printed circuit board or the like on the wiring circuit board 2, for example, a semiconductor chip or the like is mounted, is not shown in the semiconductor chip in FIG. 尚、半導体チップの搭載例は後で図4(A)、(B)を参照して説明する。 Note that example of mounting the semiconductor chip Later FIG. 4 (A), described with reference to (B).
このような配線回路基板2の製造方法によれば、図3(G)に示すように、層間絶縁膜4の表面に露出する各バンプ6の頂面に直接半田ボール12を形成するので、前述のように、半田ボールの下地となる半田ボール下地膜をわざわざ形成する必要がなくなり、配線回路基板2を製造するに必要となる製造工数を低減することができる。 According to this wired circuit substrate manufacturing method 2, as shown in FIG. 3 (G), because it forms a direct solder balls 12 on the top surface of each bump 6 exposed on the surface of the interlayer insulating film 4, above as in, it is not necessary to specially form the solder balls underlying film underlying the solder balls, it is possible to reduce manufacturing man-hours required for manufacturing the wiring circuit board 2.

図4(A)、(B)は配線回路基板2への半導体チップの各別の搭載例を示す断面図である。 Figure 4 (A), (B) is a sectional view showing each another example of mounting the semiconductor chip on the wiring circuit board 2. 図1では、配線回路基板2の2点鎖線で示したリジットなプリント回路基板14への搭載例を示したが、図4(A)、(B)に示すように、本配線回路基板2には半導体チップを直接的に搭載することができるのである。 In Figure 1, there is shown an example of mounting a rigid printed circuit board 14 shown by a two-dot chain line in the wiring circuit board 2, as shown in FIG. 4 (A), (B), to the printed circuit board 2 it is it is possible to directly mount the semiconductor chips.
図4(A)は半導体チップの電極と配線回路基板2の配線層10との接続をワイヤボンディングにより行う搭載例を示し、図4(B)は半導体チップ24の電極10aと配線回路基板2の配線層10とを直接接続することにより配線回路基板2に半導体チップ24を搭載する搭載例を示す。 4 (A) shows a mounting example in which the connection between the electrode of the semiconductor chip and the wiring layer 10 of the printed circuit board 2 by wire bonding, Fig. 4 (B) and the electrode 10a of the semiconductor chip 24 of the printed circuit board 2 It shows a mounting example of mounting the semiconductor chip 24 on the printed circuit board 2 by connecting the wiring layer 10 directly.

図4(A)を参照してワイヤボンディングを用いた搭載例を説明する。 Referring to FIG. 4 (A) illustrating a mounting example using wire bonding. 図4(A)において、24はLSI等の半導体チップ、26は該半導体チップ24を配線回路基板2に固定するダイボンド接着層、28は配線回路基板2の配線層10と、半導体チップ24の電極との間を接続するボンディングワイヤで、例えば金線からなる。 In FIG. 4 (A), is such as LSI semiconductor chip 24, the die bonding layer for fixing the semiconductor chip 24 on the wiring circuit board 2 is 26, 28 and the wiring layer 10 of the printed circuit board 2, the electrode of the semiconductor chip 24 a bonding wire for connecting between, for example, a gold wire. 各電極は該ボンディングワイヤ28及び配線層10を通じていずれかのバンプ6に、更には半田ボール12に接続され、電気的に導出される。 The bump 6 one through each electrode the bonding wires 28 and the wiring layer 10, and further connected to the solder balls 12 are electrically led. 30は半導体チップ24を封止する樹脂で、通常エポキシ樹脂からなるポッテング樹脂である。 30 is a resin for sealing the semiconductor chip 24, a potting resin made of usual epoxy resin.

図4(B)を参照してフリップチップタイプのICの搭載例を説明する。 Referring to FIG. 4 (B) illustrating the example of mounting the flip chip type of the IC. IC、LSI等の半導体チップ24にはハンダからなるバンプ乃至金メッキバンプ10aが形成されており、配線基板2に搭載後、必要に応じ封止樹脂26を注入硬化させてなる。 IC, the semiconductor chip 24 such as an LSI have bumps or gold plating bumps 10a made of solder is formed, after mounting on the wiring board 2, made by injection cure the sealing resin 26 necessary. また、半導体チップ24にAuのスタッドバンプを形成し、異方性導電接着剤(図面略)を介して回路基板に接合してもよい。 Further, the stud bumps of Au is formed on the semiconductor chip 24 may be bonded to the circuit board through anisotropic conductive adhesive (drawing omitted). そのボンディング後、半導体チップ24・配線回路基板2間が樹脂26で固定され、封止される。 After the bonding, between the semiconductor chip 24 and wiring circuit board 2 is fixed with resin 26 and sealed.

図5は本発明配線回路基板の第2の実施例を示す断面図である。 Figure 5 is a sectional view showing a second embodiment of the present invention the printed circuit board.
本実施例2'は、図1に示した実施例2とは、各バンプ6の頂面6aを凹球面に形成し、その凹球面に形成された頂面6aに半田ボール12を形成した点でのみ相違し、それ以外の点では、共通する。 Points embodiment 2 'is the second embodiment shown in FIG. 1, the top surface 6a of each of the bumps 6 formed on the concave spherical surface, to form the solder balls 12 on the top surface 6a formed on the concave spherical surface only different in, in terms of otherwise, are common.
このように、本実施例2'によれば、各バンプ6の頂面6aを凹球面に形成するので、頂面6aと半田ボール12との接続面積が増加し、接続強度を強めて、配線回路基板としての信頼度を高め、長寿命化を図ることができる。 Thus, according to the second embodiment ', since the top surface 6a of each of the bumps 6 formed on the concave spherical surface, an increased contact area between the top surface 6a and the solder balls 12, strengthening the connection strength, wire enhance the reliability of the circuit board, it is possible to increase the life of.

このように、各バンプ6の頂面6aを凹球面に形成することは、図1に示した実施例1の配線回路基板を製造する方法における、図3(F)に示す工程と、図3(G)に示す工程との間に、銅をクイックエッチングする工程を設けることにより、容易に為し得る。 Thus, by forming the top surface 6a of each of the bumps 6 on the concave spherical surface, in a method of manufacturing a wiring circuit board of the first embodiment shown in FIG. 1, the process shown in FIG. 3 (F), FIG. 3 between the step shown in (G), by providing a step of quick etching of copper, may readily without.
図6(A)〜(C)はその凹球面形成工程とその前後の工程を工程順に示す断面図である。 FIG 6 (A) ~ (C) are sectional views showing the before and after step and its concave spherical surface forming step in process order.
(A)金属層20c〔図3(E)参照〕を選択的にエッチングすることにより配線層10を形成する。 (A) forming a wiring layer 10 by selectively etching the metal layer 20c [see FIG 3 (E)]. 尚、該配線層10の形成前又は形成後に2点鎖線で示すように、例えば半田レジストからなるダム18を形成して半田接合面の均一化とダレによるショート防止を図るようにしても良い。 As it is shown by two-dot chain line before or after the formation of the wiring layer 10, may be achieved preventing short circuit caused by uniform and sagging of the solder joint surface to form a dam 18, for example made of solder resist. 図6(A)はその配線層10を形成した後の状態を示す。 FIG 6 (A) shows the state after forming the wiring layer 10.

(B)次に、図6(B)に示すように、上記各バンプ6の頂面6aをウェットエッチングすることにより凹球面状にする。 (B) Next, as shown in FIG. 6 (B), to concave spherical by wet-etching the top surface 6a of each bump 6.
(C.)次に、半田ボールとなる球状半田を各バンプ6の上記層間絶縁膜4から露出する頂面6a上に配置し、配線回路基板2を加熱炉に通してリフロー処理することにより各バンプ6頂面6a上に該バンプ6と直接に接続固定された半田ボール12を形成する。 (C.) Then, a spherical solder comprising the solder ball disposed on the top surface 6a exposed from the interlayer insulating film 4 of the bumps 6, each by a reflow process through the printed circuit board 2 in a heating furnace directly forming a connection fixed solder ball 12 and the bump 6 on the bump 6 top surface 6a. 図6(C)はそのリフロー処理後の状態を示す。 FIG 6 (C) shows the state after the reflow treatment.
このように、図6(B)に示すウェットエッチング工程を付加することにより図5に示す第2の実施例2'の配線回路基板2が得られる。 Thus, the wiring circuit board 2 of the second embodiment 2 'shown in FIG. 5 is obtained by adding the wet etching step shown in FIG. 6 (B). 尚、この実施例2の各バンプ6の頂面6aを凹球面状にすることは、図4(A)、(B)に示す各搭載例にも適用することができるし、また、バンプ6に直接に半田ボール12を形成する態様のすべてに適用し得る。 Incidentally, it is to the top surface 6a of each of the bumps 6 of Example 2 to concave spherical, FIG. 4 (A), the to be applied to respective mounting example (B), the addition, the bumps 6 It may be applied to all aspects of forming the solder balls 12 directly to.
尚、ここでは回路パターン10とバンプ頂面のエツチングを別々の工程で行うように記載したが、両面同時のウェットエッチングでもよく、その方が効率がよい。 Here, has been described as do etching of the circuit patterns 10 and the bumps top surface in a separate step may be a wet etching of a double-sided simultaneous, that it is more efficient.

図7(A)〜(E)は図2(A)〜(D)及び図3(E)〜(H)に示した配線回路基板の製造方法の一部を変形させた実施例3の要部を工程順に示す断面図である。 Figure 7 (A) ~ (E) are essential in FIG 2 (A) ~ (D) and FIG. 3 (E) ~ Example was partially modified method of manufacturing the printed circuit board shown in (H) 3 parts is a sectional view showing the order of steps.
(A)図2(A)〜(C)で示した工程と同じ工程を行う。 (A) performs the same steps as shown in FIG. 2 (A) ~ (C). 図7(A)はその工程を終えた状態、換言すれば、図2(C)に示した状態を示す。 Figure 7 (A) is a state in which after the step, in other words, showing the state shown in FIG. 2 (C).
ここで、図2(C)に示した状態になるまでを簡単に説明する。 Here, brief description will be until the state shown in FIG. 2 (C). 中間層としてエッチングバリア層を有する含む三層構造の金属板20を用意し、該金属板20の厚い金属層20aを選択的にエッチングすることにより、バンプ6を形成し、その後、上記エッチングバリア層20b(8)を、上記バンプ6をマスクとしてエッチングすることにより選択的に除去する。 A metal plate 20 of a three-layer structure including having etching barrier layer is prepared as an intermediate layer, by selectively etching the thick metal layer 20a of the metal plate 20, to form a bump 6, then, the etching barrier layer 20b (8), it is selectively removed by etching the bump 6 as a mask. その状態が図7(A)に示される。 Its state is shown in FIG. 7 (A).

(B)次に、上記各バンプ6を一斉に加圧して押し潰すことにより図7(B)に示すように、該各バンプ6の頂面の径を大きくする。 (B) Next, as shown in FIG. 7 (B) by crushing the pressed simultaneously pressure to each bump 6, increasing the diameter of the top surface of each of the bumps 6. このように押し潰して各バンプ6の頂面の径を大きくするのは、後でその頂面に形成する半田ボールのバンプとの強度を強くし、バンプを取れにくくするためである。 Thus crushing and to increase the diameter of the top surface of each bump 6 is to later to increase the intensity of the bump of solder balls formed in its top surface, hard to remove the bump.
即ち、配線回路基板の配線膜の狭ピッチ化、IC、LSI等の電極数の増加等の傾向から、バンプの配置密度を高めることが要求され、その結果、バンプの大きさを大きくすることが制約されている。 In other words, narrow pitch wiring films of the printed circuit board, IC, from the tendency of increase in the number electrodes such as an LSI, it is required to increase the arrangement density of the bumps, so that is possible to increase the size of the bump It is constrained. 従って、バンプとしてその頂面の径が70μm程度のものを形成しなければならないケースが生じている。 Accordingly, the diameter of the top surface is occurring cases must form a of about 70μm as a bump.

しかし、実際上、バンプの頂面の径は、少なくとも100μm程度ないと半田ボールのバンプへの接着強度を充分な程度に高めることが難しく、半田ボールのバンプへの接着の信頼度を充分な高さに確保することが容易ではなかった。 However, in practice, the diameter of the top surface of the bump is at least 100μm approximately and without difficulty to increase the adhesion strength to the bumps of solder balls to a sufficient extent, a reliability of the adhesion to the solder ball bumps sufficiently high it is not easy to secure to be.
そこで、半田ボールのバンプへの接着強度を高めるためにバンプの頂面の面積を増やすべく、各バンプ6を一斉に加圧して押し潰すのである。 Therefore, to increase the area of ​​the top surface of the bump in order to increase the adhesion strength to the bumps of solder balls is of each bump 6 crushed simultaneously pressurized. このようにすると、実際に各バンプ6の頂面の径を、例えば70μm程度から例えば100μm以上に大きくすることができる。 In this way, actually the diameter of the top surface of each bump 6, for example, can be increased from 70μm approximately, for example more than 100 [mu] m.

(C)次に、図7(C)に示すように、各バンプ6を覆う層間絶縁膜4を形成する〔図2(D)に示す工程と同じ〕。 (C) Next, as shown in FIG. 7 (C), an interlayer insulating film 4 covering each bump 6 [identical to steps shown in FIG. 2 (D)]. は該層間絶縁膜4形成後の状態を示す。 Shows the state after the interlayer insulating film 4 formed.
(D)次に、図7(D)に示すように、上記層間絶縁膜4の表面部を、上記各バンプ6の頂面が完全に露出するまで研磨し、絶縁樹脂層とバンプ頂面を面一(ツライチ)にする[図3(E)に示す工程と同じ。 (D) Next, as shown in FIG. 7 (D), the surface portion of the interlayer insulating film 4, the top surface of each bump 6 is polished to completely exposed, the insulating resin layer and the bump top surface to flush (Tsuraichi) same as the step shown in FIG. 3 (E). ]。 ].

(E)その後、上記金属層20cを選択的にエッチングすることにより配線層10を形成し[図3(F)に示す工程と同じ。 (E) Then, a wiring layer 10 is formed by selectively etching the metal layer 20c [same as the step shown in FIG. 3 (F). ]、しかる後、半田ボール12を形成する[図3(G)に示す工程と同じ。 ], And thereafter, to form the solder balls 12 Same as the step shown in FIG. 3 (G). 〕。 ]. 尚、該配線層10の形成前又は形成後に2点鎖線で示すように、例えば半田レジストからなるダム18を形成して半田接合面の均一化とダレによるショート防止を図るようにしても良いこと、図2及び図3に示す配線回路基板の製造方法と同じである。 Incidentally, it as shown by the two-dot chain line before or after the formation of the wiring layer 10, may be achieved preventing short circuit caused by uniform and sagging of the solder joint surface to form a dam 18, for example made of solder resist is the same as the method of manufacturing a printed circuit board shown in FIGS.

このような図7に示す配線回路基板の製造方法によれば、前記層間絶縁膜の形成前に、各バンプを上から加圧して押し潰すことによりその頂面の径を大きくする工程を有するので、各バンプ6の頂面の径を、例えば70μm程度から100μm以上に大きくすることができる。 According to the production method of the wired circuit board shown in this Figure 7, prior to formation of the interlayer insulating film, by squeezing under pressure from the top of each bump because it has a step of increasing the diameter of the top surface the diameter of the top surface of each bump 6, for example, can be increased more than 100μm from 70μm approximately.
従って、各半田ボール12の各バンプ6への接着強度を充分に強めることが容易に為し得る。 Therefore, it sufficiently strengthened can easily without the adhesive strength to the bumps 6 of each solder ball 12.

尚、各バンプ6を一斉に加圧するのは本実施例においては、エッチングバリア層8のバンプ6をマスクとしての選択的エッチング後であったが、選択的エッチング前に加圧を行うようにしても良い。 In the present embodiment pressurize each bump 6 simultaneously, although the bumps 6 of the etching barrier layer 8 was after the selective etching as a mask, so as to perform the pressure before selective etching it may be.
また、図7(D)に示す工程の終了後、図7(E)に示す工程の終了前に、各バンプ6の頂面6aをウェットエッチングにより凹球面状にする工程を設けても良い(実施例2参照)。 Further, after completion of the step shown in FIG. 7 (D), before the end of the process shown in FIG. 7 (E), may be the top surface 6a of each of the bumps 6 provided a process for the concave spherical shape by wet etching ( see example 2). これにより、バンプ6と半田ボール12との接続面積をより広め、接続強度をより強めてより信頼度の向上、長寿命化を図ることができるからである。 Thus, it spreads more the contact area between the bump 6 and solder balls 12, increased more reliability increasingly more connection strength, because it is possible to increase the life of.

図8は本発明配線回路基板の第4の実施例2aを示す断面図である。 Figure 8 is a sectional view showing a fourth embodiment 2a of the present invention the printed circuit board. 本実施例2aは、本発明を、両面に配線層を有する配線回路基板に適用したものである。 This Example 2a, the present invention is applied to a printed circuit board having wiring layers on both sides.
即ち、図1に示した第1の実施例2等は、層間絶縁膜4の半田ボール12が形成されたのと反対側にのみ配線層10があり、半田ボール12が形成された側には配線層がなかったが、本実施例2aには、層間絶縁膜4の半田ボール12が形成された側にも配線層11がある。 That is, the first embodiment 2 and the like shown in FIG. 1, there is only the wiring layer 10 on the opposite side as the solder balls 12 of the interlayer insulating film 4 is formed, the solder balls 12 are formed side is there was no wiring layer, the present example 2a is also the side where the solder balls 12 of the interlayer insulating film 4 is formed is a wiring layer 11.
そして、半田ボール12は、バンプ6の頂面に直接形成するようにしても良いし、バンプ6頂面と接する配線層11(図8において2点鎖線で示す配線層11)を形成し、その配線層11上に半田ボール12を形成するようにしても良い。 Then, the solder balls 12 may be directly formed on the top surface of the bump 6, and a wiring layer 11 in contact with the bump 6 top surface (the wiring layer 11 shown by the two-dot chain line in FIG. 8), the it may be formed of solder balls 12 on the wiring layer 11.

図9(A)〜(D)は図8に示す配線回路基板(本発明配線回路基板の第2の実施例)2aの製造方法を工程順に示す断面図であり、この図9を参照して配線回路基板2aの製造方法を説明する。 9 (A) ~ (D) are sectional views showing a manufacturing method (second embodiment of the present invention the printed circuit board) 2a wiring circuit board shown in FIG. 8 in the order of steps, with reference to FIG. 9 the method of manufacturing a printed circuit board 2a will be described.
(A)図2、図3に示した配線回路基板2の製造方法における工程(E)が終了した状態のもの(但し、ダム18は形成しない)と、半田ボール12側の配線層11となる、銅からなる金属層19を用意し、図9(A)に示すように、該金属層19を配線回路基板2の層間絶縁膜4表面に臨ませる。 (A) and FIG. 2, those states step (E) is completed in a manufacturing method of a wired circuit board 2 shown in FIG. 3 (however, the dam 18 is not formed), the wiring layer 11 of the solder balls 12 side , prepared metal layer 19 made of copper, as shown in FIG. 9 (a), to face the metal layer 19 on the interlayer insulating film 4 surface of the printed circuit board 2.
(B)次に、図9(B)に示すように、上記金属層19を配線回路基板に積層する。 (B) Next, as shown in FIG. 9 (B), laminating the metal layer 19 on the printed circuit board. 2aは積層後の配線回路基板を指す。 2a refers to the printed circuit board after lamination.

(C)次に、上記金属層19及び20cを同時又は所定の順で選択的にエッチングすることにより配線層10及び11を形成する。 (C) Next, a wiring layer 10 and 11 by selectively etching the metal layer 19 and 20c simultaneously or in a predetermined order. 図9(C)は該配線層10、11形成後の状態を示す。 Figure 9 (C) shows the state after the wiring layers 10 and 11 formed.
(D)次に、図9(D)に示すように、バンプ6と接続された配線層11上に半田ボール12を形成する。 (D) Next, as shown in FIG. 9 (D), to form the solder balls 12 on the wiring layer 11 connected to the bump 6.
尚、半田ボール12は、図9(D)に示すようにバンプ6と接続された配線層11上に形成するようにしても良いが、バンプ6上には配線膜11を形成しないように金属層19に対するパターニングを行うこととしてバンプ6頂面を露出させたままにし、その露出したバンプ6に頂面に直接半田ボール12を形成するようにしても良い。 The solder balls 12 may be formed on the wiring layer 11 connected to the bump 6 as shown in FIG. 9 (D), a metal as the upper bumps 6 not forming the wiring film 11 and leaving exposed the bumps 6 top surface as possible to perform patterning for the layer 19 may be directly formed solder balls 12 on the top surface to the bump 6 and the exposed.

図10はそのように製造して得た配線回路基板、即ち、本発明配線回路基板の第5の実施例2bを示すものである。 Figure 10 is a wiring circuit board obtained by so produced, i.e., it illustrates a fifth embodiment 2b of the present invention the printed circuit board.
図11(A)〜(C)は本発明配線回路基板2、2a或いは2bにバンプが形成されていない領域、即ちバンプ非形成領域40を設けてフレキシブルにし、そのフレキシブルにした部分にて曲折した回路モジュールの各別の例を示す断面図である。 Figure 11 (A) ~ (C) are regions not bump is formed in the present invention the printed circuit board 2,2a or 2b, i.e. the flexible provided a bump formed area 40, is bent at the portion in the flexible it is a sectional view showing each another example of a circuit module.
このように配線回路基板にバンプ非形成領域40を設けて曲折可能にし、任意に曲折して使用できるようにした回路モジュールを形成することにより、LSI等の半導体チップ24を立体的に配置して使用することができ、限られた領域内の多数のチップ24を高密度配置することができる。 Thus the bendable by a bump-free region 40 on the printed circuit board is provided, by forming a circuit module which is to be used by bending optionally, a semiconductor chip 24 such as an LSI and arranged three-dimensionally can be used, the number of chips 24 in a limited region can be densely arranged. 尚、42はバンプ形成領域である。 Incidentally, 42 is a bump formation region.
尚、本実施例においても、バンプ6の頂面6aをウェットエッチングにより凹球面状に形成するという実施例を適用できる。 Also in this embodiment, the top surface 6a of the bumps 6 can be applied to embodiments that form a concave spherical shape by wet etching.

図12は本発明配線回路基板に別のフレキシブルな配線回路基板を接続することによって構成された本発明回路モジュールの別の実施例を示す断面図である。 Figure 12 is a sectional view showing another embodiment of the present invention the circuit module configured by connecting another flexible wiring circuit board of the present invention the printed circuit board.
図12において、2の符号が付された配線回路基板は、図1に示した配線回路基板2と同じであり、既に説明済みなので、特に説明はしない。 12, a printed circuit board 2 are labeled the is the same as the wiring circuit board 2 shown in FIG. 1, already because already been described that, are not specifically described.
50は該配線回路基板2とは別のフレキシブルな配線回路基板であり、52はそのベースを成す層間絶縁膜、54は該層間絶縁膜52の裏面に形成された例えば銅からなる配線膜、56は該層間絶縁膜52を貫通するように形成されたバンプ、58はバンプ56の底面と上記配線膜54との間に介在するエッチングバリア層、60は上記層間絶縁膜52の表面に形成された配線膜で、少なくとも一部の配線膜60は上記バンプ56の頂面に接続された状態で形成されている。 50 is another flexible wiring circuit board and the wiring circuit board 2, 52 denotes an interlayer insulating film and forming a base, 54 wiring film made of the interlayer back surface formed, for example, copper of the insulating film 52, 56 bumps which are formed to penetrate the interlayer insulating film 52, 58 is etched barrier layer interposed between the bottom face and the wiring film 54 of the bump 56, 60 is formed on the surface of the interlayer insulating film 52 in the wiring film, at least a part of the wiring layer 60 is formed in a state of being connected to the top surface of the bump 56.

該配線回路基板50は、配線回路基板2と略同じ方法で形成される。 Wiring circuit board 50 is formed substantially in the same manner as the wiring circuit board 2. 該配線回路基板50の配線回路基板2との違いは、配線回路基板2においては層間絶縁膜の一方の面に配線膜が形成されていないが、配線回路基板50においては両方の面に配線膜54、60が形成されていることのみである。 The difference between the printed circuit board 2 of the wiring circuit board 50 is in the printed circuit board 2 is not wired film formed on one surface of the interlayer insulating film, wiring film on both surfaces in the printed circuit board 50 54 and 60 is only that is formed.
この配線回路基板2と配線回路基板50とは、配線回路基板2のバンプ6の頂面に配線回路基板50の配線膜54を、半田ボール12を介して接続することによって一体化されて、回路モジュールを構成している。 The wired circuit board 2 and the wiring circuit board 50, the wiring film 54 of the printed circuit board 50 to the top surface of the bump 6 of the wiring circuit board 2, are integrated by connecting via the solder balls 12, the circuit constitute a module. これにより、フレキシブルな配線回路基板同士を接続した回路モジュールを容易に構成し得る。 This may easily form a circuit module connected to the flexible printed circuit boards.

図13はガラス配線基板(リジット)に上記本発明配線回路基板の第1の実施例を接続して構成した液晶装置を成す回路モジュールを示す断面図である。 Figure 13 is a sectional view showing a circuit module constituting the liquid crystal device constructed by connecting the first embodiment of the present invention the printed circuit board to the glass wiring substrate (rigid).
70は液晶装置(回路モジュール)で、ガラス配線基板72上に平行にシール材78を介して対向ガラス板76を配設し、該ガラス配線基板72と対向ガラス板76との間に液晶80を封入したものに、本発明配線回路基板の第1の実施例2を半田ボール12を介して接続してなるものである。 70 in the liquid crystal device (circuit modules) in parallel on the glass wiring substrate 72 through the sealing member 78 is disposed to face the glass plate 76, the liquid crystal 80 between the glass wiring substrate 72 and the opposing glass plate 76 to that enclosed, are those formed by connecting the first embodiment 2 of the present invention the printed circuit board via the solder balls 12. 74は上記ガラス配線基板72の表面に形成された透明配線膜で、ITO(インジウムテンオキサイド)膜からなる。 74 is a transparent wiring film formed on the surface of the glass wiring substrate 72, made of ITO (indium Ten oxide) film. 或いは、ITO膜の表面に更に金属(例えば銅、アルミニウム、チタン、ニッケル、錫或いは銀)膜を形成してなる場合もある。 Alternatively, there further metal (e.g., copper, aluminum, titanium, nickel, tin or silver) on the surface of the ITO film may obtained by forming a film.

ガラス配線基板と配線回路基板2との接続は、具体的には、上記ガラス配線基板72の透明配線膜74の端部と本発明配線回路基板の第1の実施例2のバンプ6との間を半田ボール12を介して接続される。 Connection between the glass wiring substrate and the wiring circuit board 2 is specifically between the first bump 6 of Example 2 of the end and the present invention the printed circuit board of the transparent wiring film 74 of the glass wiring substrate 72 It is connected to through the solder balls 12.
このように、フレキシブルな配線回路基板2を電極引き出しに用いた液晶装置を提供することができる。 Thus, it is possible to provide a liquid crystal device using a flexible printed circuit board 2 to the electrode withdrawing. このような回路モジュールにも、図5に示すようにバンプの頂面を例えばウェットエッチングにより凹球面状に形成し、その凹球面状に形成した頂面に直接に半田ボールを形成するという実施例を適用できる。 Also such a circuit module, implemented as formed in concave spherical shape by for example wet etching a top surface of the bump as shown in FIG. 5, is formed directly on the solder balls on the top surface formed on the concave spherical Example It can be applied.
以上に述べた回路モジュールは、本発明配線回路基板2を用いた回路モジュールの一部であり、これらに本発明に係る回路モジュールが限定されてしまうものではない。 Circuit module described above is a part of a circuit module using the present invention the wiring circuit board 2, not intended circuit module according to the present invention these is limited.

本発明は、例えばIC、LSI等の電子デバイス実装用の配線回路基板、特に高密度実装を実現できる配線回路基板と、その製造方法と、その配線回路基板を備えた回路モジュールに適用することができ、回路モジュールの具体例としては液晶装置が挙げられるが、必ずしもそれに限定されず、種々のものに利用可能性がある。 The present invention is, for example IC, a printed circuit board for an electronic device mounting the LSI such as a printed circuit board in particular can realize high-density mounting, and a manufacturing method thereof, be applied to a circuit module including the wiring circuit board can, the liquid crystal device may be mentioned as specific examples of the circuit module, not necessarily limited thereto and may use a variety of things.

本発明配線回路基板の第1の実施例を示す断面図である。 It is a sectional view showing a first embodiment of the present invention the printed circuit board. (A)〜(D)は上記第1の実施例の製造方法の工程(A)〜(D)を順にs示す断面図である。 (A) ~ (D) are sectional views illustrating in sequence s the process of the manufacturing method of the first embodiment (A) ~ (D). (E)〜(H)は上記第1の実施例の製造方法の工程(E)〜(H)を順に示す断面図である。 (E) ~ (H) are sectional views showing the steps of the manufacturing method of the first embodiment (E) ~ a (H) in this order. (A)、(B)は配線回路基板への半導体チップの各別の搭載例を示す断面図である。 (A), (B) is a sectional view showing each another example of mounting the semiconductor chip on the wiring circuit board. 本発明配線回路基板の第2の実施例を示す断面図である。 It is a sectional view showing a second embodiment of the present invention the printed circuit board. (A)〜(C)は図5に示した上記第2の実施例の製造方法におけるその凹球面形成工程とその前後の工程を工程順に示す断面図である。 (A) ~ (C) is a sectional view showing the concave spherical surface forming step and the preceding and succeeding steps in the manufacturing method of the second embodiment shown in FIG. 5 in the order of steps. (A)〜(E)は図2(A)〜(D)及び図3(E)〜(H)に示した配線回路基板の製造方法の一部を変形させた第3の実施例の要部を工程順に示す断面図である。 (A) ~ (E) are essential in the third embodiment is partially modified method of manufacturing the printed circuit board shown in FIG. 2 (A) ~ (D) and FIG. 3 (E) ~ (H) parts is a sectional view showing the order of steps. 本発明配線回路基板の第4の実施例を示す断面図である。 It is a sectional view showing a fourth embodiment of the present invention the printed circuit board. (A)〜(D)は本発明配線回路基板の上記第4の実施例の製造方法を工程順に示す断面図である。 (A) ~ (D) are sectional views sequentially showing the steps of producing the fourth embodiment of the present invention the printed circuit board. 本発明配線回路基板の第5の実施例を示すものである。 It shows a fifth embodiment of the present invention the printed circuit board. (A)〜(C)は本発明配線回路基板にバンプ非形成領域を設けてフレキシブルにし、そのフレキシブルにした部分にて曲折して使用した各別の使用例を示す断面図である。 (A) ~ (C) is flexible by providing a bump-free region in the present invention the wiring circuit board is a sectional view showing each another use example using by bending at the portion to the flexible. 本発明配線回路基板に別のフレキシブルな配線回路基板を接続することによって構成された本発明回路モジュールの第6の実施例を示す断面図である。 It is a sectional view showing a sixth embodiment of the present invention the circuit module configured by connecting another flexible wiring circuit board of the present invention the printed circuit board. ガラス配線基板(リジット)に上記本発明配線回路基板を接続して構成した液晶装置を成す回路モジュールを示す断面図である。 It is a sectional view showing a circuit module constituting the liquid crystal device constructed in the glass wiring substrate (rigid) by connecting the present invention the printed circuit board. 従来例の配線回路基板を示す断面図である。 It is a cross-sectional view showing a printed circuit board in the conventional example.

符号の説明 DESCRIPTION OF SYMBOLS

2、2a、2b・・・配線回路基板、4・・・層間絶縁膜、6・・・バンプ、 2, 2a, 2b ... wiring circuit board, 4 ... interlayer insulation film, 6 ... bumps,
6a・・・バンプの頂面、8・・・エッチングバリア層、10、11・・・配線層、 The top surface of the 6a ... bumps, 8 ... etching barrier layer, 10, 11 ... wiring layer,
12・・・半田ボール、14・・・プリント回路基板、 12 ... solder balls, 14 ... printed circuit board,
16・・・プリント回路基板の配線層、20・・・三層金属板、24・・・半導体チップ、 16 ... printed circuit board wiring layer, 20 ... three-layer metal plate, 24 ... semiconductor chip,
40・・・バンプ非形成領域(曲折可能な領域)、42・・・バンプ形成領域、 40 ... bump-free region (bendable space) 42 ... bump formation region,
50・・・フレキシブルな配線回路基板、70・・・液晶装置、72・・・透明基板、 50 ... flexible wired circuit board, 70 ... liquid crystal device, 72 ... transparent substrate,
74・・・透明配線膜。 74 ... transparent wiring film.

Claims (13)

  1. 配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、 Directly or via etching barrier layer on the surface portion of the wiring layer to form a plurality of bumps,
    上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、 Forming an interlayer insulating film is not formed part of the bumps of the bump formation surface of the wiring layer,
    上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成した ことを特徴とする配線回路基板。 The top surface of the bump, directly or wiring circuit board in the interlayer insulating film surface via a wiring layer formed so as to connect with the bumps, characterized in that the formation of the solder balls.
  2. 前記配線層及び前記バンプが銅からなる ことを特徴とする請求項1記載の配線回路基板。 Printed circuit board according to claim 1, wherein said wiring layer and the bumps is characterized in that it consists of copper.
  3. 前記層間絶縁膜に、バンプが多数形成されたバンプ形成領域と、バンプが形成されないフレキシブルなバンプ非形成領域とを有し、 The interlayer insulating film has a bump formation region on which the bumps are formed a large number, and a flexible bump formed area where the bump is not formed,
    上記バンプ非形成領域が曲折可能である、又は、その少なくとも一部を曲折してなる ことを特徴とする請求項1又は2記載の配線回路基板。 Is bendable is the bump-free region, or printed circuit board according to claim 1 or 2, wherein the formed by bent and at least a part.
  4. 前記各バンプの頂面が凹球面に形成され、 It said top surface of each bump is formed on the concave spherical surface,
    上記各バンプの凹球面に形成された上記頂面に直接に半田ボールが形成されてなる ことを特徴とする請求項1、2又は3記載の配線回路基板。 Printed circuit board according to claim 1, 2 or 3, wherein the comprising directly to the solder ball is formed on the top surface formed on the concave spherical surface of each bump.
  5. 配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成したフレキシブルな配線回路基板と、 Directly or via etching barrier layer on the surface portion of the wiring layer to form a plurality of bumps, an interlayer insulating film is not formed part of the bumps of the bump formation surface of the wiring layer, the top of the bump the surface, directly, or in the interlayer insulating film surface via a wiring layer formed so as to connect with the bumps, a flexible wiring circuit board forming the solder balls,
    リジットな絶縁基板の少なくとも一方の表面に上記配線膜と接続される配線膜が形成されたリジットな配線回路基板と、 And a rigid printed circuit board on which a wiring layer to be connected to the wiring layer is formed on at least one surface of the rigid insulating substrate,
    からなり、 It consists of,
    上記フレキシブルな配線回路基板の配線膜の少なくとも一部と、上記リジットな配線回路基板の配線膜の少なくとも一部とが、上記半田ボールを介して接続されてなる ことを特徴とする回路モジュール。 Circuit module and at least a portion, and at least part of the wiring layer of the rigid wiring circuit board, characterized by comprising connected via the solder balls of the wiring layer of the flexible wiring circuit board.
  6. 配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成したフレキシブルな配線回路基板と、 Directly or via etching barrier layer on the surface portion of the wiring layer to form a plurality of bumps, an interlayer insulating film is not formed part of the bumps of the bump formation surface of the wiring layer, the top of the bump the surface, directly, or in the interlayer insulating film surface via a wiring layer formed so as to connect with the bumps, a flexible wiring circuit board forming the solder balls,
    フレキシブルな絶縁基板の少なくとも一方の表面に上記配線膜と接続される配線膜が形成された上記配線回路基板とは別のフレキシブルな配線回路基板と、 And another flexible printed circuit board is a flexible the wiring circuit board on which a wiring layer is formed to be connected to the wiring layer on at least one surface of the insulating substrate,
    からなり、 It consists of,
    上記フレキシブルな配線回路基板の配線膜の少なくとも一部と、上記別のフレキシブルな配線回路基板の配線膜の少なくとも一部とが、上記半田ボールを介して接続されてなる ことを特徴とする回路モジュール。 Circuit module, wherein at least a portion of the wiring layer of the flexible wiring circuit board, and at least a part of the wiring layer of the another flexible printed circuit board, to become connected via the solder balls .
  7. 前記各バンプの頂面が凹球面に形成され、 It said top surface of each bump is formed on the concave spherical surface,
    上記各バンプの凹球面に形成された上記頂面に直接に半田ボールが形成されてなる ことを特徴とする請求項5又は6記載の回路モデュール。 Circuit module according to claim 5 or 6, characterized in that formed by directly solder balls formed on the top surface formed on the concave spherical surface of each bump.
  8. 金属層の表面に直接に又はエッチングバリア層を介してバンプを形成した基板を用意し、 Directly or via etching barrier layer on the surface of the metal layer providing a substrate formed with the bumps,
    上記基板の金属層のバンプ形成側の面のバンプが形成されていない部分にバンプより厚く層間絶縁膜を形成し、 Thick to form an interlayer insulating film than bump portions where the bumps are not formed in the surface of the bump formation side of the metal layer of the substrate,
    上記基板の層間絶縁膜を上記各バンプの頂面が露出するまで研磨し、 An interlayer insulating film of the substrate was polished until the top surface of each bump is exposed,
    上記基板の上記各バンプの露出する頂面上に半田ボールを形成する ことを特徴とする配線回路基板の製造方法。 Method of manufacturing a printed circuit board and forming solder balls on the top surface to expose the respective bumps of the substrate.
  9. 金属層の表面に直接に又はエッチングバリア層を介してバンプを形成した基板を用意し、 Directly or via etching barrier layer on the surface of the metal layer providing a substrate formed with the bumps,
    上記基板の金属層のバンプ形成側の面のバンプが形成されていない部分にバンプより厚く層間絶縁膜を形成し、 Thick to form an interlayer insulating film than bump portions where the bumps are not formed in the surface of the bump formation side of the metal layer of the substrate,
    上記基板の層間絶縁膜を上記各バンプの頂面が露出するまで研磨し、 An interlayer insulating film of the substrate was polished until the top surface of each bump is exposed,
    上記基板の上記層間絶縁膜の表面に金属層を形成し、 The metal layer is formed on the surface of the interlayer insulating film of the substrate,
    上記層間絶縁膜表面の金属層を選択的にエッチングすることにより配線層を形成し、 The wiring layer is formed by selectively etching the metal layer of the interlayer insulating film surface,
    各バンプの露出する頂面上に又は該バンプと接続された上記配線層上に半田ボールを形成する ことを特徴とする配線回路基板の製造方法。 Method of manufacturing a printed circuit board and forming solder balls on the top surface on or the bump and connected the wiring layer exposed in the bumps.
  10. 前記層間絶縁膜を形成するよりも前に、各バンプを上から加圧して押し潰すことによりその頂面の径を大きくする工程を有する ことを特徴とする請求項8又は9記載の配線回路基板の製造方法。 Before forming the interlayer insulating film, a wiring circuit board according to claim 8 or 9, wherein by each bump crushed under pressure from above, characterized by comprising the step of increasing the diameter of the top surface the method of production.
  11. 前記基板の前記層間絶縁膜を前記各バンプの頂面が露出するまで研磨した後、該バンプの露出した頂面上に前記半田ボールを形成する前に、該バンプの頂面をエッチングすることにより凹球面にする工程を有する ことを特徴とする請求項8、9又は10記載の配線回路基板の製造方法。 After polishing the interlayer insulating film of the substrate to the top surface of each bump is exposed, before forming the solder balls on the exposed top surface of the bump, by etching the top surface of the bump the method of manufacturing the printed circuit board according to claim 8, 9 or 10, wherein further comprising a step of the concave spherical surface.
  12. 配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成した一つの配線回路基板と、 Directly or via etching barrier layer on the surface portion of the wiring layer to form a plurality of bumps, the wiring circuit of one forming an interlayer insulating film in the portion not forming the bumps of the bump formation surface of the wiring layer board When,
    液晶素子の基板を成し、透明配線膜を有する液晶装置用透明基板と、 Form a substrate of a liquid crystal device, a transparent substrate for a liquid crystal device having a transparent wiring film,
    からなり、 It consists of,
    上記一つの配線回路基板の各バンプと、上記別の液晶装置用透明基板の透明配線膜の上記各バンプと対応する部分とが、直接に或いは上記バンプの頂面に形成した配線膜及び半田ボールを介して接続されて液晶装置を成す ことを特徴とする回路モジュール。 And the bumps of the one printed circuit board, and the respective bumps and the corresponding portions of the transparent wiring film of the transparent substrate for the further liquid crystal device, directly or wiring film and the solder balls are formed on the top surface of the bump It is connected via a circuit module characterized by forming the liquid crystal device.
  13. 前記一つの配線回路基板の各バンプの頂面が凹球面に形成され、 The top surface of each bump of the one printed circuit board is formed on the concave spherical surface,
    その凹球面に形成された上記頂面に直接に半田ボールが形成されてなる ことを特徴とする請求項12記載の回路モジュール The circuit module of claim 12, wherein the directly to the solder ball on the top surface formed on the concave spherical surface is formed
JP2003307897A 2003-03-31 2003-08-29 Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board Pending JP2004343030A (en)

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TW93107787A TWI333687B (en) 2003-03-31 2004-03-23
KR20040021668A KR20040086783A (en) 2003-03-31 2004-03-30 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit module
US10812349 US20040201096A1 (en) 2003-03-31 2004-03-30 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit module
CN 200810169136 CN101408688B (en) 2003-03-31 2004-03-31 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit module
CN 200410031894 CN100542375C (en) 2003-03-31 2004-03-31 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit module
HK05106338A HK1073965A1 (en) 2003-03-31 2005-07-25 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit module
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