KR101617023B1 - Method of manufacturing PCB substrate having metal post - Google Patents

Abstract

The technical subject of the present invention is to provide a printed circuit board capable of forming an external connection unit of a narrow pitch size by replacing a traditional solder ball connection unit, and a manufacturing method thereof. In the manufacturing method of a printed circuit board including a metal post according to an embodiment, provided is a carrier substrate including an insulation core layer and a base copper layer formed on the insulation core layer. An insulation bonding layer including a first contact pattern to expose at least a part of the base copper layer is formed on the upper side of the base copper layer. One or more circuit pattern layers which fill the first contact pattern and are formed on the base copper layer are stacked. The lower side of the base copper layer is exposed by separating the insulation core layer and the base copper layer of the carrier substrate. A resist pattern layer including a second contact pattern to selectively expose the base copper layer is formed on the lower side of the base copper layer. A post plating pattern layer which fills the second contact pattern is formed on the exposed base copper layer by using the resist pattern layer. The insulation bonding layer is exposed by selectively etching a part of the base copper layer where the post plating pattern layer is not formed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a printed circuit board having a metal post,

The present invention relates to a printed circuit board having a metal post and a method of manufacturing the same.

Today, the semiconductor industry is moving towards manufacturing light-weighted, miniaturized, high-speed, multi-functional, high-performance, and highly reliable products at low cost. One of the important technologies to achieve this is semiconductor package technology. The semiconductor package technology is a technique for securing operation reliability of a semiconductor chip by protecting a semiconductor chip formed with a circuit part through a wafer assembling process from an external environment and easily mounting the semiconductor chip on a substrate. In recent years, demand for laminated package products such as POP (Package On Package) has been rapidly increasing due to the trend of high performance and high performance of packaged products.

1 is a view schematically showing an example of a POP stacking package according to the prior art. 1, the POP laminate package 10 includes a first printed circuit board 12 on which a first chip 160 is mounted and a second printed circuit board 12 on which a plurality of second chips 152, 154, and 156 are mounted. And the substrate 14 is laminated. The first printed circuit board 12 may include an insulating layer 120, a first connection pad 122, and a second connection pad 124. The first chip 160 can be connected to the first printed circuit board 12 by the bumps 162 and the bumps 164 can be arranged to be protected by the underfill 164. The second printed circuit board 154 may include an insulating layer 140, a third connection pad 142, and a fourth connection pad 144. A plurality of second chips 152, 154, 156 may be stacked on the second printed circuit board 154 by an adhesive layer. The chip pads 158 on the second chips 152 and 156 and the connection terminals 146 on the second printed circuit board 154 are connected to each other by the wires 151 to connect the second printed circuit board 154 and the second The chips 152, 154, and 156 may be electrically connected to each other. The plurality of second chips (152, 154, 156) can be protected by the molding member (170).

 The first printed circuit board 12 and the second printed circuit board 14 can be electrically connected by the first solder ball connecting means 16. [ The first solder ball connecting means 16 can electrically connect the second connection pad 124 of the first printed circuit board 12 and the first connection pad 142 of the second printed circuit board 14. In addition, second solder ball connecting means 18 for connection with an external medium may be disposed on the first connecting pad 122 of the first printed circuit board 12. As described above, the conventional POP structure laminated package can be manufactured by connecting different printed circuit boards on which at least one chip is mounted by solder ball connecting means.

2A and 2B are views schematically showing a conventional method of forming solder ball connecting means. 2A is a plan view of an insulating layer 210, a via layer 224 in the insulating layer 210, first circuit patterns 222 and 223 and second circuit patterns 223 and 223 located on the upper and lower surfaces of the insulating layer 210, respectively. 226). ≪ / RTI >

The solder resist pattern 230 exposes at least a part of the first circuit patterns 222 and 223 and the exposed first circuit pattern 222 can constitute the first connection pad 222. [ In addition, the solder resist pattern 230 may expose at least a portion of the second circuit pattern 226 and the exposed second circuit pattern 226 may constitute the second connection pad 226.

Referring to FIG. 2A, a metal mask pattern layer 240 is disposed between first connection pads 222 to manufacture solder ball connection means. Subsequently, a solder ball 250 is disposed on the first connection pad 222. The metal mask pattern layer 240 can position the solder ball 250 and help the solder ball 250 be positioned at a designated location above the first contact pad 222.

2B, the solder ball connecting unit 255 is formed by eutectic bonding the solder ball 250 with the first connection pad 222 by applying heat after removing the metal mask pattern layer 240 . At this time, the solder ball 250 may be deformed to adhere to the first connection pad 222 and the solder resist pattern 230.

Referring to FIGS. 2A and 2B, a conventional solder ball connecting means is formed by flowing a solder ball 250. Generally, the solder ball connecting means is formed to have a generally spherical or hemispherical shape, and therefore, it is difficult to manufacture only the height of the solder ball connecting means while fixing the width of the solder ball connecting means.

In recent years, due to the tendency of high-performance and high performance of packaged products, the number of connection pads of the printed circuit board is increased and the pitch size between the connection pads is decreasing. The solder ball connecting means described above is applied as means for connecting such high- There are difficulties in doing so.

SUMMARY OF THE INVENTION The present invention is directed to a printed circuit board and a method of manufacturing the printed circuit board, which realize an external connection means with a narrower pitch size in place of the conventional solder ball connecting means.

According to an aspect of the present invention, there is provided a method of manufacturing a printed circuit board having a metal post. In the above manufacturing method, there is provided a carrier substrate including an insulating core layer and a base copper layer formed on the insulating core layer. And an insulating adhesive layer having a first contact pattern exposing at least a portion of the base copper layer is formed on the upper surface of the base copper layer. At least one or more circuit pattern layers formed on the base copper layer to fill the first contact pattern are laminated. The insulating core layer of the carrier substrate and the base copper layer are separated from each other to expose the bottom surface of the base copper layer. A resist pattern layer having a second contact pattern selectively exposing the base copper layer is formed on the lower surface of the base copper layer. The resist pattern layer is used to form a post-plating pattern layer that fills the second contact pattern on the exposed base copper layer. The portion of the base copper layer on which the post-plating pattern layer is not formed is selectively etched to expose the insulating adhesive layer.

According to another aspect of the present invention, there is provided a printed circuit board having a metal post. The printed circuit board includes an insulating layer, at least one circuit pattern layer, an insulating adhesive layer, a base copper pattern layer, and a post-plating pattern layer. The insulating layer has a first surface and a second surface facing the first surface. At least a portion of the one or more circuit pattern layers is disposed inside the insulating layer. The insulating adhesive layer surrounds the first connection pad layer which is a part of the circuit pattern layer which is projected onto the first surface of the insulating layer. And the base copper pattern layer is disposed on the insulating adhesive layer in contact with the first connection pad layer. The post-plating pattern layer is laminated on the base copper pattern layer. The line width of the base copper pattern layer is larger than the line width of the first connection pad layer.

According to another aspect of the present invention, there is provided a method of manufacturing a printed circuit board having a metal post. The connection pad layer being connected to the at least one circuit pattern layer and disposed on one surface of the insulating layer, And a solder mask pattern layer selectively exposing the connection pad layer on one surface of the insulating layer. A plating seed layer is formed on the connection pad layer and the solder mask pattern layer. A first photosensitive resist film covering at least the plating seed layer is formed on the laminated circuit substrate. A first resist pattern layer having a lower contact pattern for selectively exposing and developing the first photosensitive resist film and exposing at least a part of the plating seed layer is formed. A lower bump layer filling the lower contact pattern is formed on the plating seed layer by applying a plating method using the first resist pattern layer, wherein an upper surface of the lower bump layer and an upper surface of the first resist pattern layer have the same height Respectively. A second photosensitive resist film is formed on the first resist pattern layer and the lower bump layer. A second resist pattern layer having an upper contact pattern selectively exposing the lower bump layer by selectively exposing and developing the second photosensitive resist film is formed. A plating method using the second resist pattern layer is applied to form an upper bump layer on the lower bump layer to fill the upper contact pattern. The first and second resist pattern layers are removed and portions of the plating seed layer on which the lower bump layer is not formed are selectively etched.

According to one embodiment of the present application, in place of the conventional solder ball connecting means, the patterned metal posts can be manufactured as connection means between printed circuit boards. It is possible to easily reduce the pitch size between connecting means as compared with the conventional method by manufacturing the metal posts by a plating method using a resist pattern formed by optical exposure and development. This makes it possible to easily manufacture connection means corresponding to connection pads of a narrow pitch size required in recent printed circuit boards.

According to one embodiment, the height of the metal post can be easily controlled by manufacturing the metal post by performing the plating method using the photosensitive resist layer pattern layer at least once. As a result, it is possible to manufacture a connecting means having a relatively reduced pitch size and a relatively increased height as compared with conventional solder ball connecting means.

According to one embodiment, the structural reliability of the metal post layer can be improved by disposing an insulating adhesive layer under at least a portion of the metal post layer.

1 is a view schematically showing an example of a POP stacking package according to the prior art.
2A and 2B are views schematically showing a conventional method of forming solder ball connecting means.
3 is a flowchart schematically showing a method of manufacturing a printed circuit board having a metal post according to an embodiment of the present application.
4A to 4M are cross-sectional views schematically showing a method of manufacturing a printed circuit board having a metal post according to the first embodiment of the present application.
5A to 5E are cross-sectional views schematically showing a method of manufacturing a printed circuit board having a metal post according to a second embodiment of the present application.
6A to 6G are cross-sectional views schematically showing a method of manufacturing a printed circuit board having a metal post according to a third embodiment of the present disclosure.

Embodiments of the present application will now be described in more detail with reference to the accompanying drawings. However, the techniques disclosed in this application are not limited to the embodiments described herein but may be embodied in other forms. It should be understood, however, that the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the width, thickness, and the like of the components are enlarged in order to clearly illustrate the components of each device. In addition, although only a part of the components is shown for convenience of explanation, those skilled in the art can easily grasp the rest of the components. It is to be understood that when an element is described as being located on another element, it is meant that the element is directly on top of the other element or that additional elements can be interposed between the elements . It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. In the drawings, the same reference numerals denote substantially the same elements.

Meanwhile, the meaning of the terms described in the present application should be understood as follows. The terms " first " or " second " and the like are intended to distinguish one element from another and should not be limited by these terms. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise, and the terms "comprise" Or combinations thereof, and does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Further, in carrying out the method or the manufacturing method, each of the steps constituting the above method may occur differently from the stated order unless clearly specified in the context. That is, each process may occur in the same order as described, may be performed substantially concurrently, or may be performed in the opposite order.

3 is a flowchart schematically showing a method of manufacturing a printed circuit board having a metal post according to an embodiment of the present application. Referring to FIG. 3, in step S310, a carrier substrate including an insulating core layer and a base copper layer formed on the insulating core layer is provided.

In step S320, an insulating adhesive layer having a first contact pattern exposing at least a portion of the base copper layer is formed on the upper surface of the base copper layer.

In step S330, at least one or more circuit pattern layers formed on the insulating adhesive layer are laminated so as to fill the first contact pattern. An interlayer insulating layer for electrical insulation may be formed between the at least one or more circuit pattern layers.

In step S340, the insulating core layer of the carrier substrate and the base copper layer are separated from each other to expose the bottom surface of the base copper layer. Thereby, a part of the carrier substrate is separated, and the above-mentioned at least one layer of the circuit pattern layer can be laminated on the base copper layer.

In step S350, a resist pattern layer having a second contact pattern selectively exposing the base copper layer is formed on the lower surface of the base copper layer.

In step S360, the resist pattern layer is used to form a post-plating pattern layer that fills the second contact pattern on the exposed base copper layer. The post-plating pattern layer can constitute a part of the metal posts for external connection.

In step S370, the portion of the base copper layer on which the post-plating pattern layer is not formed is selectively removed to expose the insulating adhesive layer. As a result, a metal post including the base copper layer and the post-plating pattern layer can be formed.

Hereinafter, one embodiment of the present application will be described in more detail with reference to cross-sectional views of the process steps.

4A to 4M are cross-sectional views schematically showing a method of manufacturing a printed circuit board having a metal post according to the first embodiment of the present application. Referring to FIG. 4A, a carrier substrate 400 is provided. The carrier substrate 400 includes a carrier copper layer 412 and a base copper layer 414 which are sequentially stacked on both sides of an insulating core layer 410.

Referring to FIG. 4B, an insulating resin layer 416 is formed on the upper surface of the base copper layer 414. The insulating resin layer 416 may include a material having excellent adhesion to a metal such as copper, tin, or the like. The insulating resin layer 416 may include, for example, a urethane-based or epoxy-based resin, but is not limited thereto and may include various known resins. The insulating resin layer 416 can improve the adhesion with the base copper layer 414 and improve the structural reliability of the post plating pattern layer 460 disposed on the base copper layer 414 as described later.

According to one embodiment, the step of forming the insulating resin layer 416 may be performed by applying a thermosetting ink composition on the upper surface of the base copper layer 414 and drying the ink composition to form a thin film layer. At this time, the thermosetting ink composition may include the above-mentioned resin composition.

Referring to FIG. 4C, a copper foil layer 418 is formed on the insulating resin layer 416. As an example, a method of forming the copper foil layer 418 may be a process of preparing a copper foil having a predetermined thickness and bonding the copper foil to the insulating resin layer 416.

4D, the copper thin film layer 418 and the insulating resin layer 416 are selectively processed to form the copper thin film pattern layer 418a and the insulating resin layer pattern 416a having the first contact pattern 419, . At this time, the first contact pattern 419 may have a contact inner bottom line width of the first width W1.

Referring to FIG. 4E, a first circuit pattern layer 420 is formed which fills the first contact pattern 419 and is disposed on the copper foil pattern layer 418a. The first circuit pattern layer 420 may be formed by a copper plating method. The copper plating method may, for example, be carried out by a chemical plating method, an electrolytic plating method, or a combination thereof. Specifically, the first circuit pattern layer 420 can be formed by performing a known tenting, a semi-additive process (SAP), or a modified semi-additive process (MSAP).

4F, a method of laminating the first insulating layer 422 and the interlayer copper layer 424 includes preparing a preliminary substrate in which a first insulating layer 422 and an interlayer copper layer 424 are sequentially stacked , The preliminary substrate is bonded to the first circuit pattern layer 420 by applying a predetermined heat and pressure. The first insulating layer 422 and the interlayer copper layer 424 covering the first circuit pattern layer 420 can be stacked on the copper thin film pattern layer 418a. The first insulating layer 422 may include, for example, an insulating resin such as a prepreg. Alternatively, the first insulating layer 422 may be a resin copper foil coating (RCC) resin or an ABF resin in which an epoxy resin and a thermoplastic resin are blended.

Referring to FIG. 4G, the first insulating layer 422 and the interlayer copper layer 424 are selectively processed to form a via hole exposing the first circuit pattern layer 420. Subsequently, a second circuit pattern layer 430 is formed on the interlayer copper layer 424 and the inside of the via hole by a copper plating method. Subsequently, the interlayer copper layer 424 between the second circuit pattern layers 430 is removed by a copper etching method, so that the second circuit pattern layers 430 can be electrically insulated from each other. After the copper etching process, the interlayer copper layer 424 may remain in the form of a copper pattern layer 424a only under the second circuit pattern layer 430.

The copper plating method may, for example, be carried out by a chemical plating method, an electrolytic plating method, or a combination thereof. Specifically, the second circuit pattern layer 430 may be formed by performing a known tenting, a semi-additive process (SAP), or a modified semi-additive process (MSAP).

Referring to FIG. 4H, a solder resist film covering the second circuit pattern layer 430 is formed on the first insulating layer 422, and the solder resist film is selectively exposed and developed to form the second circuit pattern layer 430 Thereby forming a solder mask pattern layer 440 that exposes a part of the solder mask pattern layer 440. [ A portion of the second circuit pattern layer 430 exposed by the solder mask pattern layer 440 may function as a connection pad layer for external connection, as described later.

Referring to FIG. 4I, the carrier copper layer 412 and the base copper layer 414 of the carrier substrate 400 are separated from each other to expose the bottom surface 414n of the base copper layer 414. The method of separating the carrier copper layer 412 and the base copper layer 414 may be a method of applying heat or pressure to the interface between the carrier copper layer 412 and the base copper layer 414. [

Referring to FIG. 4J, a photosensitive resist film covering the lower surface 414n of the exposed base copper layer 414, the solder mask pattern layer 440, and the second circuit pattern layer 430 is formed. Subsequently, the photosensitive resist film formed on the lower surface 414n of the base copper layer 414 is selectively exposed and developed to form a photosensitive resist pattern layer 450 having the second contact pattern 455. At this time, the second contact pattern 455 may selectively expose the base copper layer 414. The second contact pattern 455 may have a contact inner bottom line width of the second width W2. The second width W2 of the second contact pattern 455 may be greater than the first width W1 of the first contact pattern 419 shown in Fig.

Referring to FIG. 4K, a photoresist pattern layer 450 is used to form a post-plating pattern layer 460 that fills the second contact pattern 455 on the exposed base copper layer 414. The post-plating pattern layer 460 may include, for example, copper, tin or an alloy thereof. The post-plating pattern layer 460 may be formed by chemical plating, electroplating, or a combination thereof, as an example.

Referring to FIG. 4L, the photosensitive resist pattern layer 450 is removed. Referring to FIG. 4M, the portion of the base copper layer 414 on which the post-plating pattern layer 460 is not formed is selectively removed to expose the insulating resin layer pattern 416a. In a specific embodiment, a known wet etching method such as flash etch may be performed until the base copper layer 414 on the insulating resin layer pattern 416a is removed. Thereby, the base copper layer 414 can be converted into the base copper pattern layer 414a. By proceeding with the above-described steps, a printed circuit board having a metal post can be manufactured.

5A to 5E are cross-sectional views schematically showing a method of manufacturing a printed circuit board having a metal post according to a second embodiment of the present application. First, a part of the manufacturing steps of the first embodiment described above with reference to FIGS. 4A to 4I is performed to separate the carrier copper layer 412 and the base copper layer 414 of the carrier substrate 400 from each other, A first circuit pattern layer 420 and a second circuit pattern layer 430 are stacked on the layer 414.

5A, the carrier copper layer 412 and the base copper layer 414 are separated from each other so that the bottom surface 414n of the exposed base copper layer 414, the solder mask pattern layer 440, Thereby forming a photosensitive resist film that covers the photosensitive layer 430. Subsequently, the photosensitive resist film formed on the lower surface 414n of the base copper layer 414 is selectively exposed and developed to form a resist pattern layer 550 having the second contact pattern 555. At this time, the second contact pattern 555 may selectively expose the base copper layer 414. The second contact pattern 555 may have a bottom line width size of the second width W3. The second width W3 of the second contact pattern 555 may be greater than the first width W1 of the first contact pattern 419 shown in Fig.

Referring to FIG. 5B, a first post plating pattern layer 560 is formed using the resist pattern layer 550 to fill the second contact pattern 555 on the exposed base copper layer 414. The first post-plating pattern layer 560 may include, for example, copper, tin or an alloy thereof. The first post-plating pattern layer 560 may be formed by chemical plating, electrolytic plating, or a combination thereof, as an example. The first post-plating pattern layer 560 may be formed to have the same surface as the resist pattern layer 550.

5C, a third contact pattern 575 is formed on the first post plating pattern layer 560 and the resist pattern layer 550 to expose at least a portion of the first post plating pattern layer 560 A resist pattern layer 570 can be formed. The third contact pattern 575 may have a bottom line width size of the third width W4. As an example, the third width W4 of the third contact pattern 575 may be smaller than the second width W3 of the second contact pattern 555.

5D, a resist pattern layer 570 may be used to form the second post-plating pattern layer 580 filling the third contact pattern 575. [ The second post-plating pattern layer 580 may comprise, by way of example, copper, tin or an alloy thereof. The second post-plating pattern layer 580 may be formed, for example, by chemical plating, electroplating, or a combination thereof.

5E, the resist pattern layers 550 and 570 are removed, and the portions of the base copper layer 414 where the first post plating pattern layer 560 or the second post plating pattern layer 580 are not formed The insulating resin layer pattern 416a is exposed. In a specific embodiment, a known wet etching method such as flash etch may be performed until the base copper layer 414 on the insulating resin layer pattern 416a is removed. Thereby, the base copper layer 414 can be converted into the base copper pattern layer 414a. By proceeding with the above-described steps, a printed circuit board having a metal post including the first and second post-plating pattern layers 560 and 580 can be manufactured.

As described above, according to the embodiment of the present application, the patterned metal posts can be manufactured as connecting means between the printed circuit boards instead of the conventional solder ball connecting means. It is possible to easily reduce the pitch size between the connecting means as compared with the prior art by manufacturing the metal posts by a plating method using a resist pattern formed by optical exposure and development. As a result, the connection means can be easily manufactured corresponding to the connection pads of a narrow pitch size required in recent printed circuit boards.

According to one embodiment, the height of the metal post can be easily controlled by manufacturing the metal post by performing the plating method using the photosensitive resist layer pattern layer at least once. As a result, it is possible to manufacture a connecting means having a relatively reduced pitch size and a relatively increased height as compared with conventional solder ball connecting means. At this time, the line width of the second post plating pattern layer above the line width of the lower first post plating pattern layer may be made small in manufacturing the metal post. In this case, when physical bonding is performed between the second post-plating pattern layer and the external printed circuit board, the interval between adjacent second post-plating pattern layers can be increased, and the risk of electrical conduction due to contact between the metal posts Can be lowered.

According to one embodiment, the structure reliability of the metal post layer can be improved by forming an adhesive layer which is an insulating resin pattern layer between the metal post layer and the circuit pattern layer in the insulating layer.

Although the case where the first post-plating pattern layer 560 and the second post-plating pattern layer 580 have different linewidths is shown and described in the above-described embodiment, the present invention is not limited thereto. The second contact pattern 555 and the third contact pattern 575 are arranged such that the second contact pattern 555 and the third contact pattern 575 have the same line width and the alignment of the second contact pattern 555 and the third contact pattern 575 coincides with each other. The line widths of the first post-plating pattern layer 560 and the second post-plating pattern layer 580 can be made the same by forming the resist pattern layers 550 and 570.

Hereinafter, a printed circuit board having a metal post formed by the manufacturing method according to one embodiment of the present application will be described with reference to FIG. 5E.

The printed circuit board includes an insulating layer 422, at least one circuit pattern layer 418a, 420, 424a, 430, an insulating adhesive layer 416a, a base copper pattern layer 414a, and a post plating pattern layer 560, Respectively.

The insulating layer 422 may have a first surface 422a and a second surface 422b opposite the first surface 422a. At least a portion of the one or more circuit pattern layers 418a, 420, 424a, and 430 may be disposed inside the insulating layer 422. [ A portion of the one or more circuit pattern layers 418a, 420, 424a and 430 may protrude from the first surface 422a of the insulating layer 422 and the protruding portion may protrude from the first connection pad layer 420a. .

The insulating adhesive layer 416a may be disposed so as to surround the first connection pad layer 420a. The upper surface of the insulating adhesive layer 416a may be flush with the upper surface of the first connection pad layer 420a. The insulating adhesive layer 416a may be, for example, a thermosetting resin. The insulating adhesive layer 416a improves the adhesion with the base copper pattern layer 414a and can improve the structural reliability of the post plating pattern layers 560 and 580 disposed on the base copper pattern layer 414a.

The base copper pattern layer 414a contacts the first connection pad layer 420a and can be disposed on the insulating adhesive layer 416a. Post-plating pattern layers 560 and 580 may be deposited on base copper pattern layer 414a. The post plating pattern layer 560 includes a lower post pattern layer 560 having the same line width as the base copper pattern layer 414a and an upper post pattern layer 580 having a different line width from the lower post pattern layer 560 can do. The line width of the upper post pattern layer 580 may be less than the line width of the lower post pattern layer 560.

A second connection pad layer 430 extending from a portion of one or more circuit pattern layers 418a, 420, 424a, and 430 may be disposed on the second surface 422b of the insulating layer 422. [ In addition, a solder mask pattern layer 440 may be disposed on the second surface 422b to expose at least a portion of the second contact pad layer 430.

6A to 6G are cross-sectional views schematically showing a method of manufacturing a printed circuit board having a metal post according to a third embodiment of the present disclosure. Referring to FIG. 6A, first, a laminated circuit board is provided. The laminated circuit board includes an insulating layer 610, a circuit pattern layer 620 disposed inside the insulating layer 610, and a plurality of circuit patterns 620 connected to the circuit pattern layer 620 and each disposed on one surface of the insulating layer 610 First and second contact patterns 635 and 636 selectively exposing the first and second contact pad layers 622 and 624 on one surface of the first and second contact pad layers 622 and 624 and the insulating layer 610, 636 may be formed on the first and second solder mask pattern layers 632, 634.

Although the via layer 620 is shown as the circuit pattern layer 620 in Fig. 6A, the circuit pattern layer 620 is not necessarily limited to this, and at least one or more circuit pattern layers may be additionally disposed.

Referring again to FIG. 6A, a plating seed layer 640 is formed on the first connection pad layer 622 and the first solder mask pattern layer 634. The plating seed layer 640 may be formed by, for example, a sputtering method or a chemical plating method. The plating seed layer 640 may be formed along the inner wall of the first contact pattern 635.

Referring to FIG. 6B, a first photosensitive resist film covering at least the plating seed layer 640 is formed on the laminated circuit substrate. Then, the first photosensitive resist film is selectively exposed and developed to form a first resist pattern layer 650 having a lower contact pattern 655 exposing at least a portion of the plating seed layer 640. The lower contact pattern 655 may expose at least a portion of the plating seed layer 640 in a position covering the first connection pad layer 622. [ That is, the portion of the plating seed layer 640 formed in the first contact pattern 635 can be exposed. At this time, the lower contact pattern 655 may have a lower line width size of the first width W5.

Referring to FIG. 6C, a plating process using the first resist pattern layer 650 is applied to form a lower bump layer 660 on the plating seed layer 640 to fill the lower contact pattern 655. At this time, the upper surface of the lower bump layer 660 and the upper surface of the first resist pattern layer 650 may be formed to have the same height.

Referring to FIG. 6D, a second photosensitive resist film is formed on the first resist pattern layer 650 and the lower bump layer 660. Next, the second resist pattern layer 670 is formed by selectively exposing and developing the second photosensitive resist film to form an upper contact pattern 675 selectively exposing the lower bump layer 660. The upper contact pattern 675 may have a lower width W6 of the second width W6 and the second width W6 may be smaller than the first width W5 of the lower contact pattern 655. [

Referring to FIG. 6E, a plating method using the second resist pattern layer 670 is applied to form an upper bump layer 680 on the lower bump layer 660 to fill the upper contact pattern 675. When the second width W6 of the upper contact pattern 675 is less than the first width W5 of the lower contact pattern 655 the width of the upper bump layer 680 is greater than the width of the corresponding lower bump layer 660 .

Referring to FIG. 6F, the first and second resist pattern layers 650 and 670 are removed. 6G, a portion of the plating seed layer 640 on which the lower bump layer 660 is not formed is selectively etched to expose the first solder mask pattern layer 632. Next, as shown in FIG. Thus, the plating seed layer 640 can be converted into the plating seed pattern layer 640a.

Through the above-described process, a metal post including the lower bump layer 660 and the upper bump layer 680 can be formed on the printed circuit board. In the above-described embodiment, the widths of the lower bump layer 660 and the upper bump layer 680 are different from each other, but the present invention is not limited thereto. The first and second resist pattern layers 655 and 655 are formed so that the lower contact pattern 655 and the upper contact pattern 675 have the same line width and at the same time the alignment of the lower contact pattern 655 and the upper contact pattern 675 is aligned. 650, and 670, the widths of the lower bump layer 660 and the upper bump layer 680 may be the same.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It can be understood that

10: POP laminate package, 12: first printed circuit board, 14: second printed circuit board,
16: first solder ball connecting means, 18: second solder ball connecting means,
120: insulating layer, 122: first connection pad, 124: second connection pad,
140: insulating layer, 142: third connection pad, 144: fourth connection pad,
146: connection terminal, 151: wire,
152 154 156: second chip, 158: chip pad,
160: first chip, 162 164: bump, 170: molding member,
210: insulating layer, 222 223: first circuit pattern,
224: via layer, 226: second circuit pattern,
230: solder resist pattern, 240: metal mask pattern layer,
250: solder ball, 255: solder ball connecting means,
400: carrier substrate, 410: insulating core layer, 412: carrier copper layer,
414 base copper layer, 414a base copper pattern layer, 414n base copper layer,
416: insulating resin layer, 416a: insulating resin layer pattern,
418: copper thin film layer, 418a: copper thin film pattern layer,
419: first contact pattern, 420: first circuit pattern layer,
422: first insulating layer, 422a: first surface of the first insulating layer, 422b: second surface of the first insulating layer,
424: an interlayer copper layer, 424a: a copper pattern layer,
430: second circuit pattern layer, 440: solder mask pattern layer,
450: photosensitive resist pattern layer, 455: second contact pattern,
460: Post-plating pattern layer,
550: resist pattern layer, 555: second contact pattern,
560: first post-plating pattern layer, 570: resist pattern layer,
575: third contact pattern, 580: second post plating pattern layer,
610: insulating layer, 622: first connection pad layer, 624: second connection pad layer,
632: first solder mask pattern layer, 634: second solder mask pattern layer,
635: first contact pattern, 636: second contact pattern,
640: plating seed layer, 640a: plating seed pattern layer,
650: first resist pattern layer, 655: lower contact pattern,
660: lower bump layer, 670: second resist pattern layer,
675: upper contact pattern, 680: upper bump layer.

Claims (19)

(a) providing a carrier substrate comprising an insulating core layer and a base copper layer formed on the insulating core layer;
(b) forming, on an upper surface of the base copper layer, an insulating adhesive layer having a first contact pattern exposing at least a portion of the base copper layer;
(c) stacking at least one or more circuit pattern layers formed on the insulating adhesive layer to fill the first contact pattern;
(d) separating the insulating core layer and the base copper layer of the carrier substrate from each other to expose a bottom surface of the base copper layer;
(e) forming, on the lower surface of the base copper layer, a resist pattern layer having a second contact pattern selectively exposing the base copper layer;
(f) forming a post-plating pattern layer on the exposed base copper layer using the resist pattern layer to fill the second contact pattern; And
(g) removing the resist pattern layer and selectively removing portions of the base copper layer on which the post-plating pattern layer is not formed to expose the insulating adhesive layer,
(f)
(f1) forming a first post-plating pattern layer filling the second contact pattern using a resist pattern layer having the second contact pattern;
(f2) forming a resist pattern layer having a third contact pattern exposing at least a part of the first post-plating pattern layer on the first post-plating pattern layer and the resist pattern layer;
(f3) forming a second post-plating pattern layer filling the third contact pattern using the resist pattern layer having the third contact pattern; And
(f4) removing the resist pattern layer having the second and third contact patterns, respectively
A method of manufacturing a printed circuit board having a metal post.
The method according to claim 1,
(b)
(b1) forming an insulating resin layer on an upper surface of the base copper layer;
(b2) selectively processing the insulating resin layer to form the first contact pattern
A method of manufacturing a printed circuit board having a metal post.
3. The method of claim 2,
(b1)
Applying a thermosetting ink composition to an upper surface of the base copper layer; And
And drying the ink composition to form a thin film layer
A method of manufacturing a printed circuit board having a metal post.
3. The method of claim 2,
(c)
(c1) performing a copper plating process to fill the first contact pattern and form a first circuit pattern layer disposed on the insulating resin layer;
(c2) forming a first insulating layer on the insulating resin layer to cover the first circuit pattern layer;
(c3) selectively etching the first insulating layer to form a via hole exposing the first circuit pattern layer; And
(c4) forming a second circuit pattern layer in the via hole and on the first insulating layer by a copper plating method
A method of manufacturing a printed circuit board having a metal post.
The method according to claim 1,
(c)
(c1) forming a solder resist film on top of the base copper layer to cover the uppermost layer of the at least one circuit pattern layer; And
(c2) selectively exposing and developing the solder resist film to form a solder mask pattern layer that exposes a portion of the uppermost layer of the circuit pattern layer
A method of manufacturing a printed circuit board having a metal post.
The method according to claim 1,
(e)
(e1) forming a photosensitive resist film covering the lower surface of the exposed base copper layer and the upper surface of the at least one circuit pattern layer; And
(e2) selectively exposing and developing the photosensitive resist film formed on the lower surface of the base copper layer to form a photosensitive resist pattern layer having the second contact pattern
A method of manufacturing a printed circuit board having a metal post.

The method according to claim 6,
The contact inner line width of the second contact pattern is formed to be larger than the contact inner line width of the first contact pattern
A method of manufacturing a printed circuit board having a metal post.
The method according to claim 1,
The post-plating pattern layer in step (f)
At least one selected from the group consisting of copper and tin
A method of manufacturing a printed circuit board having a metal post.
The method according to claim 1,
The post-plating pattern layer
Electroplating, and chemical plating. ≪ RTI ID = 0.0 >
A method of manufacturing a printed circuit board having a metal post.
delete An insulating layer having a first surface and a second surface opposite to the first surface;
At least a portion of which is disposed inside the insulating layer;
An insulating adhesive layer surrounding the first connection pad layer which is a part of the circuit pattern layer protruding from the first surface of the insulating layer;
A base copper pattern layer in contact with the first connection pad layer and disposed on the insulating adhesive layer; And
And a post plating pattern layer laminated on the base copper pattern layer,
The line width of the base copper pattern layer is larger than the line width of the adjacent first connection pad layer,
Wherein the post-plating pattern layer comprises a lower post pattern layer having the same line width as the base copper pattern layer,
And an upper post pattern layer having a line width different from that of the lower post pattern layer on the lower post pattern layer
A printed circuit board comprising a metal post.
12. The method of claim 11,
The insulating adhesive layer is a thermosetting resin layer
A printed circuit board comprising a metal post.
delete 12. The method of claim 11,
The line width of the upper post pattern layer is smaller than the line width of the lower post pattern layer
A printed circuit board comprising a metal post.
12. The method of claim 11,
A second connection pad layer disposed on the second surface of the insulating layer and extending from a portion of the one or more circuit pattern layers; And
And a solder mask pattern layer that exposes at least a portion of the second contact pad layer on the second surface
A printed circuit board comprising a metal post.
delete delete delete delete

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