FI336936 九、發明說明： 钃 【發明所屬之技術領域】 本發明係關於一種積體電路基板，特別是關於一種無 焊球之積體電路基板。 ' 【先前技術】 在傳統之球狀閘陣列（Ball Grid Array, BGA )封裝與 _ 覆晶封裝（Flip-Chip )等晶片封裝技術中，會使用焊球2〇 將晶片封裝10與電路板30作電連接，如第1圖所示。一 般說來，封裝後焊球20使得晶片封裝1〇與電路板30間分 隔約350微米（μπι)左右’同時球墊40的間距也因此大約在 300μηι 左右。 由於球墊40的間距與封裝接點的密度十分相關，若球 墊40的間距越小’封裝接點的密度就可以越高，因此對於 ® 系統單晶片（System on a Chip，SoC)、多晶片模組 (Multi-Chip Module, MCM)、多晶片封裝(Muiti_Chip Package, MCP)、系統封裝（System in a package，sip)等各式 封裝技術而言，增加封裳接點密度與封裝層數的封裝技 術，以達成較低的封较厚度、良好的連接信賴度、低成本 的組裝以及小間距、高封裝接點密度，便是目前與未來的 . 一重要發展方向。 Ί336936 【發明内容】 本發明即提供一種新穎的積體電路基板與封裝技術， 其具有多層封裝結構、較低的封裝厚度、良好的連接信賴 度、低成本的組裝以及小間距、高封裝接點密度等等諸多 優點。 本發明之積體電路基板，包含具有表面與至少一第一 開口的絕緣層（insulation layer )、位於表面上之至少一介 電層，此介電層具有第一表面、第二表面及至少一第二開 口、曝露於第一開口中以電性連接至少一晶片之至少一接 墊（chip-side pad )、位於介電層之第一表面並覆蓋第二開 口之至少一金屬凸塊（metal bump )、位于介電層之第二表 面以電性連接金屬凸塊與接墊之至少一線路層、位於接墊 上之至少第一金屬覆層以及位於金屬凸塊上之至少一第二 金屬覆層。 本發明另外提供一種製造積體電路基板之方法。首 先，提供具有上表面與下表面之金屬片，並在下表面上形 成第一複合層，其包含第一介電層與第一金屬層。其次， 在第一複合層中形成至少一第一開口，使得第一開口曝露 出金屬片。之後，設置第一導電材料於第一開口中，使其 電性連接第一金屬片與第一金屬層。接著，選擇性移除部 分之第一導電材料與第一金屬層成為第一圖案化金屬層， 再選擇性形成覆蓋第一圖案化金屬層之絕緣層，其具有至 6 第一開口，以曝露出第一圖宰化 至小回系化金屬層之部分而形成 至J一接墊，同時第一圖案化全屬 ^ 路層。繼p 露之部分形成線 、’ j接墊场成第-似1丨轉層，並選擇性在 表面上形成第二蝕刻阻障層。 ^ .L , 便用第—蝕刻阻障 :及第二蝕刻阻障層作為遮罩，蝕刻金屬片而形成至少一 金屬凸塊’使得金屬凸塊與接塾及線路層電性連接。 【實施方式】 本發明提供-種新賴的積體電路基板，其中使用體積 乂】的金屬凸塊來取代傳統晶#封裝技術巾體積較大的焊 球作為晶片封裝與電路板間的電連接，並可以形成多層之 線路層，因此不但能夠減低封裝厚度、形成多層封裝結構、 縮小間距與增加封裝接點密度，還進一步具有良好的連接 信賴度與低成本的組裝等等諸多優點。 請參考第2圖’例示本發明積體電路基板之一較佳實 施例。本發明積體電路基板200，包含絕緣層210、介電層 220、接墊230、金屬凸塊240、線路層250、第一金屬覆 層260與第二金屬覆層270。絕緣層210具有一表面211 與至少一第一開口 212。其中，絕緣層210上的表面211 作為與介電層220連接之用。此外，絕緣層210，可以使 用不導電的材料，例如聚醯亞胺（polyimide)等。 位於表面211上的介電層220可以包含一樹脂材料 1336936 ψ 並且分別具有第一表面221、第二表面222及至少一第二 4 開口 223。其中，第二表面222與絕緣層210上的表面211 相接觸，而第二開口 223則位於第二表面222上。 r 用來電性連接至少一晶片（圖未示）的至少一接墊 * 230，則是曝露於絕緣層210上的第一開口 212中。在介電 層220的第一表面221上則設有至少一金屬凸塊240，其 φ 位置覆蓋了第二開口 223來作為積體電路基板200與電路 板（圖未示）間的電連接。金屬凸塊240 —般具有頂面241 與側壁242，使得金屬凸塊240的橫載面呈梯形。此外， 若要減低封裝厚度、縮小間距與增加封裝接點密度，金屬 凸塊240之高度可介於200-80"m間，並包含導電材料， 例如銅等。 至少一線路層250位于介電層220的第二表面222 胃上，用以將金屬凸塊240與接墊230電性連接在一起。線 路層250可以包含一導電材料，例如銅等。由於導電層250 的連接，使得封裝後的晶片（圖未示）與電路板（圖未示） 電連接。本發明積體電路基板200的一項優點在於，線路 層250可以是一種多層結構，也就是線路層250至少有一 層，較佳為多層，可以形成多層封裝結構以配合未來多變 、 的封裝線路設計。 接墊230與金屬凸塊240上還分別具有第一金屬覆層 丨1336936 ♦ 260與第二金屬覆層270，作為保護之用。例如，第一金屬 覆層260與第二金屬覆層270可以分別為一複合層。例如， 包含金層與錄層等。其中，黃金的化學鈍性可以保證接墊 230與金屬凸塊240不受外界環境的傷害。 P' • 第二金屬覆層270保護金屬凸塊240的方式可以有多 種變化。首先，如第2圖所示，第二金屬覆層270可以僅 丨覆蓋頂面241。或是，如第3圖所示，第二金屬覆層270 覆蓋頂面241與部分側壁242。較佳者，還可以如第4圖 所示，第二金屬覆層270完全覆蓋頂面241與側壁242使 得金屬凸塊240受到最佳的覆蓋保護。 請參考第5-19圖，例示製造本發明積體電路基板之多 個較佳實施例。如第5圖所示，製造本發明積體電路基板 500之方法，首先提供一金屬片510,具有一上表面511與 > 一下表面512。金屬片510較佳可為一銅片等之導電金屬 箔片，厚度可以介於60-80/zm間。 其次，如第6圖所示，在下表面512上形成一第一複 合層520，其可以包含一第一介電層521與一第一金屬層 522。而第一金屬層522亦可以為一複合金屬層，例如，包 含金層與鎳層等。其中，若第一複合層520為封裝技術常 用之背膠銅箔（RCC)時，即同時具有作為第一金屬層522 之銅箔與作為第一介電層521之樹脂層。此外，第一介電 9 1336936 4FI336936 IX. Description of the Invention: 技术 Technical Field of the Invention The present invention relates to an integrated circuit substrate, and more particularly to an integrated circuit substrate without solder balls. [Prior Art] In a conventional chip package technology such as a Ball Grid Array (BGA) package and a Flip-Chip, a solder ball 2 is used to package the chip package 10 and the circuit board 30. Make an electrical connection as shown in Figure 1. In general, the packaged solder balls 20 are such that the wafer package 1 is separated from the circuit board 30 by about 350 micrometers (μπι) and the pitch of the ball pads 40 is thus about 300 μm. Since the pitch of the ball pads 40 is very related to the density of the package contacts, if the pitch of the ball pads 40 is smaller, the density of the package contacts can be higher, so for the System on a Chip (SoC), Increased sealing contact density and number of package layers for various package technologies such as Multi-Chip Module (MCM), Multi-Chip Package (MCP), and System in a package (SIP) The packaging technology to achieve lower sealing thickness, good connection reliability, low cost assembly and small pitch, high package contact density, is the current and future. An important development direction. Ί336936 SUMMARY OF THE INVENTION The present invention provides a novel integrated circuit substrate and packaging technology, which has a multi-layer package structure, low package thickness, good connection reliability, low cost assembly, and small pitch, high package contacts. Density and many other advantages. The integrated circuit substrate of the present invention comprises an insulating layer having a surface and at least one first opening, at least one dielectric layer on the surface, the dielectric layer having a first surface, a second surface and at least one a second opening, at least one chip-side pad exposed to the first opening to electrically connect at least one of the wafers, at least one metal bump on the first surface of the dielectric layer and covering the second opening Bumps, at least one circuit layer electrically connecting the metal bumps and the pads on the second surface of the dielectric layer, at least a first metal coating on the pads, and at least a second metal coating on the metal bumps Floor. The present invention further provides a method of manufacturing an integrated circuit substrate. First, a metal piece having an upper surface and a lower surface is provided, and a first composite layer is formed on the lower surface, which includes a first dielectric layer and a first metal layer. Next, at least one first opening is formed in the first composite layer such that the first opening exposes the metal sheet. Thereafter, a first conductive material is disposed in the first opening to electrically connect the first metal piece and the first metal layer. Then, selectively removing a portion of the first conductive material and the first metal layer to form a first patterned metal layer, and then selectively forming an insulating layer covering the first patterned metal layer, having a first opening to 6 to expose The first pattern is slaughtered to a portion of the small metallization metal layer to form a J-pad, and the first pattern is all of the layer. A portion of the p-exposed line is formed, the 'j pad field is formed into a first-like turn layer, and a second etch barrier layer is selectively formed on the surface. ^.L, the first etch barrier is used: and the second etch barrier layer is used as a mask, and the metal sheet is etched to form at least one metal bump ′ such that the metal bump is electrically connected to the interface and the wiring layer. [Embodiment] The present invention provides a novel integrated circuit substrate in which a metal bump of a volume is used instead of a conventional solder ball of a large size as a chip package and an electrical connection between the circuit board. Moreover, a plurality of circuit layers can be formed, thereby not only reducing the package thickness, forming a multi-layer package structure, reducing the pitch and increasing the density of package contacts, but also further having many advantages such as good connection reliability and low-cost assembly. Referring to Fig. 2, a preferred embodiment of the integrated circuit substrate of the present invention is exemplified. The integrated circuit substrate 200 of the present invention comprises an insulating layer 210, a dielectric layer 220, pads 230, metal bumps 240, a wiring layer 250, a first metal cladding layer 260 and a second metal cladding layer 270. The insulating layer 210 has a surface 211 and at least a first opening 212. The surface 211 on the insulating layer 210 is used as a connection with the dielectric layer 220. Further, as the insulating layer 210, a non-conductive material such as polyimide or the like can be used. The dielectric layer 220 on the surface 211 may include a resin material 1336936 ψ and has a first surface 221, a second surface 222, and at least a second opening 223, respectively. The second surface 222 is in contact with the surface 211 on the insulating layer 210, and the second opening 223 is located on the second surface 222. r is electrically connected to at least one pad of the wafer (not shown) * 230, which is exposed in the first opening 212 on the insulating layer 210. At least one metal bump 240 is disposed on the first surface 221 of the dielectric layer 220, and the φ position covers the second opening 223 as an electrical connection between the integrated circuit substrate 200 and a circuit board (not shown). The metal bump 240 generally has a top surface 241 and a sidewall 242 such that the cross-sectional surface of the metal bump 240 is trapezoidal. In addition, to reduce package thickness, reduce pitch and increase package contact density, the metal bumps 240 can be between 200-80"m and contain conductive materials such as copper. At least one circuit layer 250 is located on the stomach of the second surface 222 of the dielectric layer 220 for electrically connecting the metal bumps 240 to the pads 230. The wiring layer 250 may comprise a conductive material such as copper or the like. Due to the connection of the conductive layer 250, the packaged wafer (not shown) is electrically connected to a circuit board (not shown). An advantage of the integrated circuit substrate 200 of the present invention is that the circuit layer 250 can be a multi-layer structure, that is, the circuit layer 250 has at least one layer, preferably a plurality of layers, and can form a multi-layer package structure to match the future variable package line. design. The pads 230 and the metal bumps 240 further have a first metal cladding layer 3361336936 ♦ 260 and a second metal cladding layer 270, respectively, for protection. For example, the first metal cladding 260 and the second metal cladding 270 may each be a composite layer. For example, it includes a gold layer and a recording layer. Among them, the chemical bluntness of gold can ensure that the pads 230 and the metal bumps 240 are not damaged by the external environment. P' • The manner in which the second metal cladding 270 protects the metal bumps 240 can vary. First, as shown in Fig. 2, the second metal cladding 270 may cover only the top surface 241. Alternatively, as shown in FIG. 3, the second metal cladding 270 covers the top surface 241 and a portion of the sidewall 242. Preferably, as shown in Fig. 4, the second metal cladding 270 completely covers the top surface 241 and the sidewall 242 so that the metal bumps 240 are optimally covered. Referring to Figures 5-19, a number of preferred embodiments for fabricating the integrated circuit substrate of the present invention are illustrated. As shown in Fig. 5, in the method of manufacturing the integrated circuit substrate 500 of the present invention, first, a metal piece 510 having an upper surface 511 and a lower surface 512 is provided. The metal piece 510 is preferably a conductive metal foil such as a copper sheet, and may have a thickness of between 60 and 80/zm. Next, as shown in FIG. 6, a first composite layer 520 is formed on the lower surface 512, which may include a first dielectric layer 521 and a first metal layer 522. The first metal layer 522 may also be a composite metal layer, for example, including a gold layer and a nickel layer. Wherein, if the first composite layer 520 is a backing copper foil (RCC) commonly used in packaging technology, it has both a copper foil as the first metal layer 522 and a resin layer as the first dielectric layer 521. In addition, the first dielectric 9 1336936 4
層521亦可為聚醯亞胺（polyimide)等。 然後，如第7圖所示，在第一複合層520中形成至少 一第一開口 523 ’並使得第—開σ 523曝露出金屬片別 之下表面512。於此，可以使用一般機械方式、雷射鑽孔、 蝕刻等技術來形成第一開口 523。 一接者’如第8圖所示，將一第一導電材料似填滿第 一開口 523，並使得金屬片51〇經由第一導電材料524電 性連接第:金屬層522。第一導電材料524可以為銅等金 形成方法可為電鑛等習知方式，在此不多加贅述。 再來，如第9圖所示，選擇性移除部分之第一導電材 料524與第—金屬層522,曝露相對應之第-介電層521， 並使剩下之第—導電材料524與第一金層層切成為第— =案化金屬層525。此時’可以使用習知的方式，例如微 〜”蝕刻，來定義第一圖案化金屬層525的圖案。 少由於本發明的一項優點在於，圖案化金屬層可以是一 種夕層結構’於是形成多層封裝結構以配合未來多變的封 ^線路叹计，因此可以視情況需要，反覆以下步驟至少一 -欠，來形成多層圖案化金屬層。 例如，如第1〇圖所示，在完成第一圖案化金屬層5乃 1336936 的製程之後，先形成一第二複合層520’以覆蓋第一圖案化 金屬層525,其亦具有第二介電層521’與第二金屬層522’， 並使得第二介電層521’接觸第一圖案化金屬層525與第一 介電層521。其次，在第二複合層520’中形成至少一第三 * 開口 523’，並使得第三開口 523’曝露出部分之第一圖案化 * 金屬層525。之後，以第二導電材料524’填滿第三開口 523’ 使得第二導電材料524’與第一圖案化金屬層525電性連 • 接。第二導電材料524’亦可為銅等金屬。繼續，選擇性移 除部分之第二導電材料524’與第二金屬層522’後，即完成 了位於外層的第二圖案化金屬層525’，並曝露相對應之第 二介電層521’。類似地，可以使用習知的方式，例如微影 與蝕刻，來定義第二圖案化金屬層525’的圖案。 在完成前述形成多層圖案化金屬層之步驟後，繼續要 形成一絕緣層，來選擇性覆蓋最外層的圖案化金屬層。為 了簡化方便，以下僅例示單層圖案化金屬層結構。如第11 圖所示，絕緣層530具有至少一第二開口 532，以曝露出 最外層的，即第一圖案化金屬層525之部分來形成至少一 接墊540，而第一圖案化金屬525層未曝露之部分則形成 一線路層550。 接下來，如第12圖所示，分別在接墊540上與選擇性 在上表面511上，例如使用電鑛或沉積、餘刻、印刷等的 方式，形成由導電或非導電材料所構成之第一蝕刻阻障層 1336936 , 541，以及第二蝕刻阻障層513。其中，第二蝕刻阻障層513 的位置代表與預定電路板（圖未示）之電連接的位置，而 第一蝕刻阻障層541係用來作為第一金屬覆層。 繼續，如第13圖所示，使用第一蝕刻阻障層541以及 第一蝕刻阻障層513作為遮罩，來蝕刻金屬片51〇而形成 至少一金屬凸塊514，於是完成了本發明積體電路基板 • 500。線路層550使得金屬凸塊514與接墊54〇電性連接， 藉此封裝後的晶片（圖未示）才能與電路板（圖未示）間 達成電連接。由於蝕刻特性的原因，金屬凸塊514通常呈 梯形’並具有頂面515與側壁516。 視情況需要，在形成至少一金屬凸塊514後還可以除 去第二蝕刻阻障層513，並於金屬凸塊514上再形成一第 瞻二金屬覆層56G，作為保護之用。而第—金屬覆層與第二 金屬覆層56G皆可以分別為單—金屬層或複合層，例如， 包含金層與鎳層等。其中，黃金的化學鈍性可以保證接塾 540與金屬凸塊514不受外界環境的傷害。 第二金屬覆層560保護金屬凸塊514的方式可以有多 種變化。首先，如第14圖所示，第二金屬覆層56〇僅覆蓋 ，頂f 24卜或疋’如第15圖所示，第二金屬覆層剔完全 復蓋金屬凸塊514之頂面515與側壁516。 12 1336936 ， 此外，第二金屬覆層560還可以覆蓋頂面515與部分 的丨J 516以下將έ兒明形成覆蓋頂面515與部分側壁$ π 的第-金屬覆層560的方法。首先，提供如第8圖所示之 .結構，接著利用圖案化光阻（圖未示）進行雙面餘刻，選擇 .[生移除金屬片510之上表面51卜形成至少一凸出⑴，並 同時選擇性移除第-導電材料524與第一金屬層Μ2，成 為第一圖案化金屬層仍，如第16圖所示。或視情況需要， 移除金屬片510之上表面511以形成至少一凸出川之步 驟’與選擇性移除第一導電材料524與第一金屬層522之 步驟亦可以分開進行，且不限其先後順序。其中，各層之 材料與形成方法皆如前所述，而且選擇性移除金屬片训 之上表面5U的方法係以半韻刻的方式來定義將要形成的 金屬凸塊的位置，故會留下部分的金屬片51〇。The layer 521 may also be a polyimide or the like. Then, as shown in Fig. 7, at least one first opening 523' is formed in the first composite layer 520 and the first opening σ 523 is exposed to the lower surface 512 of the metal sheet. Here, the first opening 523 can be formed using a general mechanical method, laser drilling, etching, or the like. As shown in Fig. 8, a first conductive material fills the first opening 523 as shown in Fig. 8, and the metal piece 51 is electrically connected to the metal layer 522 via the first conductive material 524. The first conductive material 524 may be a gold such as copper. The formation method may be a conventional method such as electric ore, and will not be further described herein. Then, as shown in FIG. 9, the first conductive material 524 and the first metal layer 522 are selectively removed, and the corresponding first dielectric layer 521 is exposed, and the remaining first conductive material 524 is The first gold layer is cut into a first-case metal layer 525. At this time, the pattern of the first patterned metal layer 525 can be defined by a conventional method such as micro-etching. Less than one advantage of the present invention is that the patterned metal layer can be a layer structure. The multi-layer package structure is formed to match the versatile sealing circuit stagnation in the future, so that the multi-layer patterned metal layer can be formed by at least one-under-reverse according to the following steps, as needed, for example, as shown in FIG. After the first patterned metal layer 5 is processed by 1336936, a second composite layer 520' is formed to cover the first patterned metal layer 525, which also has a second dielectric layer 521' and a second metal layer 522'. And the second dielectric layer 521' contacts the first patterned metal layer 525 and the first dielectric layer 521. Secondly, at least a third * opening 523' is formed in the second composite layer 520', and the third opening is made 523' exposes a portion of the first patterned * metal layer 525. Thereafter, the third opening 523' is filled with the second conductive material 524' such that the second conductive material 524' is electrically connected to the first patterned metal layer 525. Second. Second The electrical material 524' may also be a metal such as copper. Continuing, after selectively removing portions of the second conductive material 524' and the second metal layer 522', the second patterned metal layer 525' located on the outer layer is completed, and Exposing the corresponding second dielectric layer 521'. Similarly, the pattern of the second patterned metal layer 525' can be defined using conventional means such as lithography and etching. After the step, an insulating layer is further formed to selectively cover the outermost patterned metal layer. For the sake of simplicity, only a single layer patterned metal layer structure is exemplified below. As shown in FIG. 11, the insulating layer 530 has at least A second opening 532 is formed to expose the outermost portion, that is, a portion of the first patterned metal layer 525 to form at least one pad 540, and the unexposed portion of the first patterned metal 525 layer forms a wiring layer 550. Next, as shown in FIG. 12, the conductive pad or the non-conductive material is formed on the pad 540 and selectively on the upper surface 511, for example, by using electric ore deposit, deposition, printing, or the like. a first etch barrier layer 1336936, 541, and a second etch barrier layer 513. The location of the second etch barrier layer 513 represents a location electrically connected to a predetermined circuit board (not shown), and the first etch The barrier layer 541 is used as the first metal cladding. Continuing, as shown in FIG. 13, the first etch barrier layer 541 and the first etch barrier layer 513 are used as a mask to etch the metal sheet 51. Forming at least one metal bump 514, thus completing the integrated circuit substrate 500 of the present invention. The wiring layer 550 electrically connects the metal bump 514 and the pad 54, whereby the packaged wafer (not shown) can be combined with Electrical connections are made between the boards (not shown). Metal bumps 514 are generally trapezoidal' and have a top surface 515 and sidewalls 516 due to etch characteristics. Optionally, after forming at least one metal bump 514, the second etch barrier layer 513 may be removed, and a second metal cladding layer 56G may be formed on the metal bump 514 for protection. The first metal cladding layer and the second metal cladding layer 56G may each be a single metal layer or a composite layer, for example, a gold layer and a nickel layer. Among them, the chemical bluntness of gold can ensure that the joint 540 and the metal bump 514 are not damaged by the external environment. The manner in which the second metal cladding 560 protects the metal bumps 514 can vary widely. First, as shown in Fig. 14, the second metal cladding 56 is only covered, and the top f 24 or 疋' is as shown in Fig. 15, and the second metal cladding completely covers the top surface 515 of the metal bump 514. With side wall 516. 12 1336936, in addition, the second metal cladding 560 may also cover the top surface 515 and a portion of the 丨J 516 to form a first metal cladding layer 560 covering the top surface 515 and a portion of the sidewall π. First, a structure as shown in Fig. 8 is provided, and then a double-sided engraving is performed by using a patterned photoresist (not shown), and [the upper surface 51 of the metal piece 510 is removed to form at least one protrusion (1). And simultaneously removing the first conductive material 524 and the first metal layer Μ2 to form the first patterned metal layer, as shown in FIG. Or, as the case requires, the step of removing the upper surface 511 of the metal piece 510 to form at least one protrusion and the step of selectively removing the first conductive material 524 and the first metal layer 522 may be performed separately, and is not limited thereto. In order. Wherein, the materials and formation methods of the layers are as described above, and the method of selectively removing the surface 5U of the metal sheet is defined in a semi-rhymatic manner to define the position of the metal bump to be formed, thus leaving Part of the metal piece 51〇.
然後，如第17圖所示，在第一圖案化金屬層仍上選 擇性形成絕緣層53〇來覆蓋第一圖案化金屬層525，並使 得第-圖案化金屬層525上具有至少一第二開口奶，以 曝露部分的第一圖案化金屬層525形成至少一接墊爾。 另外’第-圖案化金制⑵未曝露之部分卿成線 550 〇 類似地 、θ 於本發明的—項優點在於圖案化金屬層可 以是-種多層結構’所以在介於騎性移除部分之第 電材料524與第一金屬層522以及形成絕緣層530的步驟 1 13 1336936 間，亦可以進行如前所述之形成多層圖案化金屬層之步驟 至少一次。 接著，如第18圖所示，分別在接墊540上與在凸出 611上，例如使用電鍍或沉積等的方式，形成一第一金屬 覆層570以及一第二金屬覆層560,使得第二金屬覆層560 完全覆蓋凸出611。類似地，第一金屬覆層570與第二金 屬覆層560還可以分別為一複合層，例如，包含金層與鎳 層等。 繼續，如第19圖所示，使用第一金屬覆層570以及第 二金屬覆層560作為遮罩，蝕刻金屬片510而形成至少一 金屬凸塊514，於是完成了本發明積體電路基板500。如前 所述，金屬凸塊514經由線路層550與接墊540電性連接。 經由上述步驟後，第二金屬覆層560即完全覆蓋頂面515 與部分的側壁516。類似地，由於蝕刻特性的原因，金屬 凸塊514通常呈梯形。 第20圖例示本發明積體電路基板之另一較佳實施 例，其中有幾項值得注意之處。首先，如前所述，本實施 例為多種較佳實施例中之一者。其次，複合層可以是一種 多層結構，例如有介電層521、第一圖案化金屬層525與 第二圖案化金屬層526之雙層複合層。再者，圖案化金屬 層間的導孔580不一定在金屬凸塊514的正下方。還有， 1336936 接墊540的位置也不一定要在金屬凸塊514的正下方。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍。 【圖式簡單說明】 第1圖例示傳統晶片封裝技術中使用焊球將晶片封裝 與電路板電連接。 第2-4與20圖例示本發明積體電路基板之一較佳實施 例。 第5-19圖，例示製造本發明積體電路基板之一較佳實 施例。 【主要元件符號說明】 200積體電路基板 210絕緣層 211表面 212第一開口 220介電層 221第一表面 222第二表面 223第二開口 230接墊 240金屬凸塊 241頂面 242側壁 250線路層 260第一金屬覆層 270第二金屬覆層 510金屬片 511上表面 1336936 512下表面 513第二蝕刻阻障層 514金屬凸塊 515頂面 516側壁 520第一複合層 521第一介電層 522第一金屬層 ‘ 523第一開口 524第一導電材料 ' 525第一圖案化金屬層 526第二圖案化金屬層 520’第二複合層 521’第二介電層 • 522’第二金屬層 523’第三開口 524’第二導電材料 525’第二圖案化金屬層 530絕緣層 532第二開口 540接墊 541第一蝕刻阻障層 550線路層 560第二金屬覆層 570第一金屬覆層 611凸出 • 580導孔 16Then, as shown in FIG. 17, the insulating layer 53 is selectively formed on the first patterned metal layer to cover the first patterned metal layer 525, and the first patterned metal layer 525 has at least a second The open milk is formed by exposing at least a portion of the first patterned metal layer 525 to form at least one pad. In addition, the 'first-patterned gold system (2) unexposed part of the line 550 〇 similarly, θ in the present invention - the advantage is that the patterned metal layer can be a multi-layer structure 'so in the ride removal part Between the first electrical material 524 and the first metal layer 522 and the step 1 13 1336936 for forming the insulating layer 530, the step of forming the multilayer patterned metal layer as described above may also be performed at least once. Next, as shown in FIG. 18, a first metal cladding layer 570 and a second metal cladding layer 560 are formed on the pads 540 and on the protrusions 611, for example, by electroplating or deposition. The two metal cladding 560 completely covers the projection 611. Similarly, the first metal cladding layer 570 and the second metal cladding layer 560 may also be a composite layer, for example, including a gold layer and a nickel layer. Continuing, as shown in FIG. 19, the first metal cladding layer 570 and the second metal cladding layer 560 are used as masks, and the metal sheets 510 are etched to form at least one metal bumps 514, thus completing the integrated circuit substrate 500 of the present invention. . As described above, the metal bumps 514 are electrically connected to the pads 540 via the wiring layer 550. After the above steps, the second metal coating 560 completely covers the top surface 515 and a portion of the sidewall 516. Similarly, metal bumps 514 are generally trapezoidal due to etch characteristics. Fig. 20 illustrates another preferred embodiment of the integrated circuit substrate of the present invention, in which there are several notable points. First, as described above, this embodiment is one of many preferred embodiments. Second, the composite layer can be a multilayer structure such as a dielectric layer 521, a two-layer composite layer of a first patterned metal layer 525 and a second patterned metal layer 526. Furthermore, the vias 580 between the patterned metal layers are not necessarily directly under the metal bumps 514. Also, the position of the 1336936 pad 540 does not have to be directly below the metal bump 514. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the invention are intended to be included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates the use of solder balls in a conventional chip package technology to electrically connect a chip package to a circuit board. Figs. 2-4 and 20 illustrate a preferred embodiment of the integrated circuit substrate of the present invention. Figs. 5-19 illustrate a preferred embodiment of manufacturing an integrated circuit substrate of the present invention. [Main component symbol description] 200 integrated circuit substrate 210 insulating layer 211 surface 212 first opening 220 dielectric layer 221 first surface 222 second surface 223 second opening 230 pad 240 metal bump 241 top surface 242 sidewall 250 line Layer 260 first metal cladding 270 second metal cladding 510 metal sheet 511 upper surface 1336936 512 lower surface 513 second etch barrier layer 514 metal bump 515 top surface 516 sidewall 520 first composite layer 521 first dielectric layer 522 first metal layer '523 first opening 524 first conductive material '525 first patterned metal layer 526 second patterned metal layer 520' second composite layer 521 'second dielectric layer · 522 'second metal layer 523 'third opening 524 ′ second conductive material 525 ′ second patterned metal layer 530 insulating layer 532 second opening 540 pad 541 first etch barrier layer 550 circuit layer 560 second metal coating 570 first metal cover Layer 611 protruding • 580 guide hole 16