TWI720735B - Package structure and manufacturing method thereof - Google Patents

Abstract

A package structure includes a redistribution structure, a chip, inner conductive reinforcing element, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed on the redistribution structure and electrically connected to the second circuit layer. The inner conductive reinforcing element is disposed on the redistribution structure. The inner conductive reinforcing element has a Young's modulus of 30 to 200GPa. The protective layer covers the chip and the sidewalls of the inner conductive reinforcing element.

Description

Packaging structure and manufacturing method thereof

The present invention relates to a packaging structure and a manufacturing method of the packaging structure.

Traditionally, the chip package structure includes a substrate, a chip on the substrate, and a packaging material layer covering the chip. Since the thermal expansion coefficients of the substrate, the chip, and the packaging material layer are greatly different, when the thermal process is performed to form the chip and the packaging material layer on the substrate, the chip packaging structure often warps severely. Therefore, the yield rate of the chip package structure mounted on the printed circuit board is reduced.

On the other hand, when it is desired to form a package-on-package (POP) structure in which one package structure is formed on another package structure, the warpage phenomenon also causes difficulties in the manufacturing process.

Some embodiments of the present invention provide a package structure including a circuit redistribution structure, a chip, at least one internal conductive strengthening element, and a first protective layer. The circuit redistribution structure includes a first circuit layer and a second circuit layer disposed on the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer. The chip is arranged on the circuit redistribution structure and is electrically connected to the second circuit layer. The inner conductive strengthening element is arranged on the line redistribution structure. The inner conductive strengthening element includes a strengthening layer and a conductive connecting piece. The strengthening layer has a Young's modulus of 30-200 GPa, and the strengthening layer has through holes. The conductive connecting piece is arranged in the through hole. The top and bottom of the conductive connecting member are exposed outside the strengthening layer, and are electrically connected to the second circuit layer. The first protective layer covers the wafer.

In some embodiments, the first protective layer covers the sidewall of the opening of the inner conductive strengthening element.

In some embodiments, the inner conductive strengthening element surrounds the wafer.

In some embodiments, the reinforcing layer includes, but is not limited to, bismaleimide triazine resin, epoxy resin, glass, or ceramic.

In some embodiments, the upper surface of the inner conductive strengthening element and the upper surface of the first protective layer are coplanar.

In some embodiments, the package structure further includes a conductive member disposed at the bottom of the conductive connecting member and electrically connected to the second circuit layer.

In some embodiments, the packaging structure further includes an electronic component disposed on the first protective layer and electrically connected to the top of the conductive connector.

In some embodiments, the packaging structure further includes a substrate structure and a second protective layer. The substrate structure is arranged between the first protection layer and the electronic element, and the electronic element is electrically connected to the top of the conductive connector through the substrate structure. The second protective layer covers the electronic components.

In some embodiments, the package structure further includes a first protective layer filled in the gap between the chip and the second circuit redistribution layer.

In some embodiments, the first protective layer is filled in the inner conductive Strengthen the gap between the bottom surface of the component part and the second line redistribution layer.

Some embodiments of the present invention further provide a method for manufacturing a package structure, including the following operations: (i) providing a circuit redistribution structure, wherein the circuit redistribution structure includes a first circuit layer and a second circuit layer disposed on the first circuit layer. The circuit layer, and the first circuit layer is electrically connected to the second circuit layer; (ii) forming at least one internal conductive strengthening element on the circuit redistribution structure, wherein the internal conductive strengthening element includes: a strengthening layer with a Young’s of 30~200GPa Modulus, wherein the strengthening layer has a through hole; and a conductive connection member is arranged in the through hole, wherein the top and bottom of the conductive connection member are exposed outside the strengthening layer and are electrically connected to the second circuit layer; (iii) placing the chip in the In the circuit redistribution structure, the chip is electrically connected to the second circuit layer; and (iv) a first protective layer is formed to cover the chip and the internal conductive strengthening element.

In some embodiments, operation (ii) includes the following steps: (a) providing a substrate, wherein the substrate has a Young's modulus of 30 to 200 GPa; (b) performing a drilling process on the substrate to form a strengthening layer with through holes (C) forming a conductive connection member in the through hole to form an inner conductive strengthening element; and (d) setting an inner conductive strengthening element on the line redistribution structure.

In some embodiments, (ii) the step of forming the inner conductive strengthening element on the circuit redistribution structure includes forming a conductive member at the bottom of the conductive connecting member and electrically connecting the second circuit layer.

In some embodiments, the manufacturing method further includes (v) disposing an electronic component on the first protective layer, wherein the electronic component is electrically connected to the top of the conductive connecting member.

In some embodiments, in operation (v), the electronic component is set It is placed on the substrate structure and covered by the second protective layer, and the electronic component is electrically connected to the top of the conductive connector through the substrate structure.

10、10’‧‧‧Packaging structure

100‧‧‧Line re-distribution structure

110‧‧‧The first line re-layout

111‧‧‧First circuit layer

112‧‧‧First insulation layer

112a‧‧‧Through hole

113‧‧‧First conductive contact

120‧‧‧Second line re-layout

121‧‧‧Second circuit layer

122‧‧‧Second insulating layer

122a‧‧‧Through hole

123‧‧‧Second conductive contact

130‧‧‧The third line re-layout

131‧‧‧The third circuit layer

132‧‧‧Third insulation layer

132a‧‧‧Through hole

133‧‧‧The third conductive contact

140‧‧‧Conductive pad

200‧‧‧chip

210‧‧‧Metal bump

220‧‧‧Welding materials

300‧‧‧Inner conductive strengthening element

310‧‧‧Strengthening layer

310a‧‧‧Through hole

320‧‧‧Conductive connector

330‧‧‧Conductive parts

400‧‧‧First protective layer

410‧‧‧Second protective layer

500‧‧‧Solder Ball

510‧‧‧Welding materials

600‧‧‧Electronic components

601‧‧‧Wire

700‧‧‧Substrate structure

710‧‧‧First conductive pad

720‧‧‧Second conductive pad

S‧‧‧Substrate

D1‧‧‧Horizontal distance

The various aspects of the present invention will be most easily understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, according to industry standard operating procedures, various feature structures may not be drawn to scale. In fact, for clarity of discussion, the size of various features can be increased or decreased arbitrarily.

Figure 1 is a schematic cross-sectional view of the package structure of the first embodiment of the present invention.

Figure 2 is a schematic top view of the package structure of the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of the package structure of the second embodiment of the present invention.

4 to 12 are schematic cross-sectional views of various stages of the manufacturing method of the package structure according to the first embodiment of the present invention.

In order to make the description of the present invention more detailed and complete, the following provides an illustrative description for the implementation aspects and specific embodiments of the present invention; this is not the only way to implement or use the specific embodiments of the present invention. The embodiments disclosed below can be combined or substituted with each other under beneficial circumstances, and other embodiments can also be added to an embodiment without further description or description. In the following description, many specific details will be described in detail so that the reader The following examples can be fully understood. However, the embodiments of the present invention may be practiced without these specific details.

Furthermore, spatial relative terms, such as "below", "below", "above", "above", etc., are used to describe the relative relationship between one element or feature and another element or feature. The true meaning of these relative terms in space includes other directions. For example, when the diagram is flipped up and down by 180 degrees, the relationship between one element and another element may change from "below" and "below" to "above" and "above". In addition, the relative narratives in space used in this article should also be interpreted in the same way.

Please refer to FIG. 1, which is a schematic cross-sectional view of the package structure 10 according to the first embodiment of the present invention. The package structure 10 includes a circuit redistribution structure 100, a chip 200, an internal conductive strengthening element 300, a first protective layer 400, and solder balls 500.

In some embodiments, the circuit redistribution structure 100 includes, but is not limited to, one or more circuit redistribution layers, depending on actual design and requirements.

In one embodiment, the circuit redistribution structure 100 includes three circuit redistribution layers. The circuit redistribution structure 100 includes a first circuit redistribution layer 110, a second circuit redistribution layer 120, a third circuit redistribution layer 130, and a conductive pad 140. Specifically, the first circuit redistribution layer 110 includes a first circuit layer 111, a first insulating layer 112, and a first conductive contact 113. In some embodiments, the first circuit layer 111 and the first conductive contact 113 include any conductive material, such as metals such as copper, nickel, or silver. In some embodiments, the line width and line spacing of the first circuit layer 111 are less than 8 micrometers, for example, 7 micrometers, 6 micrometers, 5 micrometers, 4 micrometers, 3 micrometers, 2 micrometers, 1 micrometer or 0.5 micrometers. The first insulating layer 112 covers the first circuit layer 111, and the first insulating layer 112 has a via hole 112a. In some embodiments, the first insulating layer 112 includes a photosensitive dielectric material. The via hole 112 a exposes a part of the first circuit layer 111, and the first conductive contact 113 is formed in the via hole 112 a conformally, so that the first conductive contact 113 contacts the first circuit layer 111.

The second line redistribution layer 120 is disposed on the first line redistribution layer 110. Specifically, the second circuit redistribution layer 120 includes a second circuit layer 121, a second insulating layer 122, and a second conductive contact 123. The second circuit layer 121 contacts the first conductive contact 113, so that the second circuit layer 121 is electrically connected to the first circuit layer 111. In some embodiments, the second circuit layer 121 and the second conductive contact 123 include any conductive material, such as metals such as copper, nickel, or silver. In some embodiments, the line width and line spacing of the second circuit layer 121 are less than 8 micrometers, for example, 7 micrometers, 6 micrometers, 5 micrometers, 4 micrometers, 3 micrometers, 2 micrometers, 1 micrometer or 0.5 micrometers. The second insulating layer 122 covers the second circuit layer 121, and the second insulating layer 122 has a via 122a. In some embodiments, the second insulating layer 122 includes a photosensitive dielectric material. The via hole 122 a exposes a part of the second circuit layer 121, and the second conductive contact 123 is formed in the via hole 122 a conformally, so that the second conductive contact 123 contacts the second circuit layer 121.

The third line redistribution layer 130 is disposed on the second line redistribution layer 120. Specifically, the third circuit redistribution layer 130 includes a third circuit layer 131, a third insulating layer 132, and a third conductive contact 133. The third circuit layer 131 contacts the second conductive contact 123, so that the third circuit layer 131 and The second circuit layer 121 is electrically connected. In some embodiments, the third circuit layer 131 and the third conductive contact 133 include any conductive material, such as metals such as copper, nickel, or silver. In some embodiments, the line width and line spacing of the third circuit layer 131 are less than 8 micrometers, for example, 7 micrometers, 6 micrometers, 5 micrometers, 4 micrometers, 3 micrometers, 2 micrometers, 1 micrometer or 0.5 micrometers. The third insulating layer 132 covers the third circuit layer 131, and the third insulating layer 132 has a via 132a. In some embodiments, the third insulating layer 132 includes a photosensitive dielectric material. The via hole 132 a exposes a part of the third circuit layer 131, and the third conductive contact 133 is formed in the via hole 132 a conformally, so that the third conductive contact 133 contacts the third circuit layer 131.

The conductive pad 140 contacts the third conductive contact 133 so that the conductive pad 140 is electrically connected to the third circuit layer 131. In some embodiments, the conductive pad 140 includes any conductive material, such as metals such as copper, nickel, or silver.

The chip 200 is disposed on the circuit redistribution structure 100 and is electrically connected to the third circuit layer 131. Specifically, the lower surface of the chip 200 is provided with a plurality of metal bumps 210 (such as chip pins), and the metal bumps 210 are bonded to the conductive pad 140 and the third conductive contact 133 via the soldering material 220, so that the chip 200 and the first conductive contact 133 are bonded together. The three circuit layers 131 are electrically connected.

The inner conductive strengthening element 300 is disposed on the line redistribution structure 100, and the inner conductive strengthening element 300 includes a strengthening layer 310 and a conductive connecting member 320. In some embodiments, the conductive connection member 320 includes any conductive material, such as metals such as copper, nickel, or silver. Specifically, the strengthening layer 310 has a through hole 310a, and the conductive connection member 320 is disposed in the through hole 310a. More specifically, the top and bottom of the conductive connection member 320 are exposed outside the strengthening layer 310. In some embodiments In this case, the conductive connecting member 320 and the third circuit layer 131 are electrically connected via the conductive member 330. In an embodiment, the conductive member includes a solder bump, which is disposed at the bottom of the conductive connecting member 320, so that the conductive connecting member 320 is electrically connected to the third circuit layer 131. More specifically, the solder bumps may be solder balls, the materials of which include lead, tin, silver, copper, bismuth, antimony, zinc or other solder metals, but not limited to this. In some embodiments, the inner conductive reinforcing element 300 further includes two protective layers located on the upper surface and the lower surface of the reinforcing layer 310, and the material may be a solder resist material or a resin material, such as epoxy resin. The formation method of the protective layer may be, for example, laminating, printing or coating. More specifically, the top of the conductive connecting member 320 is exposed outside the upper protective layer and coplanar with the protective layer, and the conductive member 330 joined to the bottom of the conductive connecting member 320 protrudes from the lower protective layer. It should be understood that the strengthening layer 310 has a Young's modulus of 30 to 200 GPa, such as 100, 150, or 200 GPa. As mentioned above, the conventional chip package structure often produces severe warpage due to the thermal process. In particular, when the size of the chip package structure reaches a certain range or more, the warpage phenomenon is particularly serious, for example, when the chip package structure has a length of 15 mm or more and a width of 15 mm or more. However, with the arrangement of the strengthening layer 310, the package structure 10 of the present invention is not prone to warpage.

In detail, the strengthening layer 310 has a Young's modulus of 30 to 200 GPa, so that sufficient mechanical strength of the package structure 10 is provided. According to this, even if the thermal expansion coefficients of the component materials in the package structure 10 are very different, the warping phenomenon is unlikely to occur. In some embodiments, the strengthening layer 310 includes, but is not limited to, bismaleimide-tirazine (BT) resin, epoxy resin, solder paste, or copper paste. Preferably, in some embodiments, the strengthening layer 310 and the wafer 200 have There is a horizontal distance D1, and the horizontal distance D1 is 50~1000 microns.

In another embodiment, the circuit redistribution structure 100 includes two circuit redistribution layers. For example, the line redistribution structure 100 includes a first line redistribution layer 110 and a third line redistribution layer 130. The package structure 10 with two circuit redistribution layers or three circuit redistribution layers is electrically connected to the chip 20 by the uppermost circuit redistribution layer, and the internal conductive strengthening element 300 is arranged on the uppermost circuit redistribution layer on. The other components are the same as the implementation of the three-layer line redistribution layer, so they will not be repeated.

FIG. 2 is a schematic top view of the package structure 10 according to an embodiment of the present invention. As shown in FIG. 2, the conductive connecting members 320 of the inner conductive strengthening element 300 are arranged on the four sides adjacent to the package structure 10, and the exposed part is the top of the conductive connecting member 320.

Returning to Figure 1, the first protective layer 400 covers the opening sidewalls and part of the bottom surface of the chip 200 and the inner conductive strengthening element 300, and fills the gap between the chip 200 and the third circuit redistribution layer 130, and the inner conductive strengthening element The gap between the bottom surface of part 300 and the third line redistribution layer 130. Specifically, the upper surface of the inner conductive strengthening element 300 and the upper surface of the first protective layer 400 are coplanar. The first protection layer 400 can protect the bonding between the metal bumps 210, the solder material 220 and the conductive pad 140 of the chip 200, so as to avoid peeling. On the other hand, the first protection layer 400 can also block moisture and prevent oxidation of the metal bump 210, the solder material 220, and the conductive pad 140. In some embodiments, the first protective layer 400 includes resin.

The solder ball 500 is arranged under the line re-distribution structure 100. Specifically, the solder ball 500 contacts the first circuit layer 111, so that the solder ball 500 and the first circuit layer 111 electrical connection. In some embodiments, the solder ball 500 includes lead, tin, silver, copper, bismuth, antimony, zinc, or other solder metals, but not limited thereto.

Please refer to FIG. 3, which is a schematic cross-sectional view of the package structure 10' according to the second embodiment of the present invention. The package structure 10' includes a circuit redistribution structure 100, a chip 200, an internal conductive strengthening element 300, a first protective layer 400, a solder ball 500, and an electronic element 600. For details of the circuit redistribution structure 100, the chip 200, the internal conductive strengthening element 300, the first protective layer 400, and the solder balls 500, please refer to the description in FIG. 1 and the corresponding relevant paragraphs, and will not be repeated here.

The electronic element 600 is disposed on the first protection layer 400 and electrically connected to the top of the conductive connection member 320. Specifically, the electronic component 600 is disposed on a substrate structure 700 and is covered by a second protective layer 410. The substrate structure 700 has a first conductive pad 710, a second conductive pad 720 and internal circuits, and the internal circuit is electrically connected to the first conductive pad 710 and the second conductive pad 720. As shown in FIG. 3, the electronic component 600 is electrically connected to the first conductive pad 710 through a wire 601. In addition, the second conductive pad 720 is electrically connected to the top of the conductive connector 320 through the soldering material 510. In some embodiments, the welding material 510 includes lead, tin, silver, copper, bismuth, antimony, zinc, or other welding metals, but not limited to this.

The second protective layer 410 can block moisture and prevent the wire 601 and the first conductive pad 710 from being oxidized. In some embodiments, the second protective layer 410 includes resin. In some embodiments, the electronic component 600 is a memory.

The present invention also provides a manufacturing method of the package structure. No. 4 FIGS. 12 to 12 are schematic cross-sectional views of various stages of the manufacturing method of the package structure 10 according to the first embodiment of the present invention.

As shown in FIG. 4, a release film is formed on a substrate S, and a first circuit layer 111 is formed on the release film. For example, a conductive material is formed on the release film, and the conductive material is patterned to form the first circuit layer 111. In some embodiments, the method of forming the conductive material includes electroplating, chemical vapor deposition, physical vapor deposition, etc., but it is not limited thereto.

Next, as shown in FIG. 5, a first insulating layer 112 is formed to cover the first circuit layer 111, and the first insulating layer 112 includes a via hole 112a exposing a part of the first circuit layer 111. For example, a dielectric material is formed on the first circuit layer 111, and the dielectric material is patterned to form the via hole 112a. In some embodiments, the method of forming the dielectric material includes chemical vapor deposition, physical vapor deposition, etc., but not limited thereto. In some embodiments, the method of patterning conductive materials and dielectric materials includes depositing a photoresist on the layer to be patterned, and exposing and developing to form a patterned photoresist layer. Then, the patterned photoresist layer is used as an etching mask to etch the layer to be patterned. Finally, the patterned photoresist layer is removed. Alternatively, in an embodiment where the dielectric material is a photosensitive dielectric material, a part of the photosensitive dielectric material may be removed by exposure and development to complete the patterning.

Next, a second circuit layer 121 is formed on the first insulating layer 112, and a first conductive contact 113 is formed in the via hole 112a in a conformal manner. For example, a conductive material is formed on the first insulating layer 112, and is formed in the via hole 112a in a conformal manner. Next, the conductive material is patterned to form the second circuit layer 121 and the first conductive contact 113.

Next, as shown in FIG. 6, a second insulating layer 122 is formed to cover the second circuit layer 121, and the second insulating layer 122 includes a via 122 a exposing a part of the second circuit layer 121. For example, a dielectric material is formed on the second circuit layer 121, and the dielectric material is patterned to form the via 122a.

Next, a third circuit layer 131 is formed on the second insulating layer 122, and a second conductive contact 123 is formed in the via hole 122a in a conformal manner. For example, a conductive material is formed on the second insulating layer 122 and is formed in the via hole 122a in a conformal manner. Next, the conductive material is patterned to form the third circuit layer 131 and the second conductive contact 123.

Next, as shown in FIG. 7, a third insulating layer 132 is formed to cover the third circuit layer 131, and the third insulating layer 132 includes a via hole 132 a exposing a part of the third circuit layer 131. For example, a dielectric material is formed on the third circuit layer 131, and the dielectric material is patterned to form the via hole 132a.

Next, a conductive pad 140 is formed on the third insulating layer 132, and a third conductive contact 133 is formed in the via hole 132a in a conformal manner. For example, a conductive material is formed on the third insulating layer 132 and is formed in the via hole 132a in a conformal manner. Next, the conductive material is patterned to form the conductive pad 140 and the third conductive contact 133. Thus, the circuit re-distribution structure 100 is formed on the substrate S. It is worth mentioning that the conductive pad 140 has a recess to provide a specific technical effect. In detail, when the conductive connector 320 and the conductive pad 140 are joined, the bottom of the conductive connector 320 uses the conductive member 330 to align and squeeze the slope of the recess of the conductive pad 140.

Next, as shown in FIG. 8 and FIG. 9, an inner conductive strengthening element 300 is formed on the circuit redistribution structure 100. For example, the internal conductive strengthening element A plurality of conductive members 330 on the lower surface of the member 300 are joined to the conductive pad 140, and the inner conductive reinforcing element 300 is attached to the third circuit redistribution layer 130 by using the conductive member 330.

Next, as shown in FIG. 8 and FIG. 9, the wafer 200 is placed on the circuit redistribution structure 100. For example, a plurality of metal bumps 210 (such as chip pins) on the lower surface of the chip 200 are bonded to the conductive pad 140 by using the soldering material 220.

Next, as shown in FIG. 10, a first protective layer 400 is formed to cover the wafer 200 and the internal conductive strengthening element 300, and to fill the gap between the wafer 200 and the third circuit redistribution layer 130.

Next, a chemical mechanical polishing (CMP) process is used to remove the top of the first protective layer 400, thereby forming the first protective layer 400 exposing the upper surface of the inner conductive strengthening element 300 as shown in FIG. 11. It should be noted that removing the top of the first protective layer 400 provides specific technical effects. In detail, the thermal expansion coefficient of the material of the first protective layer 400 is generally different from the thermal expansion coefficients of other components. Therefore, the first protective layer 400 that is too thick may easily cause the package structure to warp. By removing the top of the first protection layer 400, the warpage of the package structure can be improved.

Next, the release film and the substrate S are peeled off to expose the first circuit layer 111. Subsequently, as shown in FIG. 12, solder balls 500 contacting the first circuit layer 111 are formed, thereby forming the package structure 10.

The manufacturing method of the package structure 10' according to the second embodiment of the present invention is a schematic cross-sectional view of each stage shown in FIG. 4 to FIG. 11. Take over Then, as shown in FIG. 3, the electronic component 600 is disposed on the first protective layer 400, and the electronic component 600 is electrically connected to the top of the conductive connecting member 320. Specifically, the soldering material 510 is used to join the second conductive pad 720 with the top of the conductive connector 320. The electronic component 600 is electrically connected to the first conductive pad 710 through a wire 601, and the first conductive pad 710 is electrically connected to the second conductive pad 720 through an internal circuit. Therefore, the electronic component 600 is electrically connected to the top of the conductive connector 320.

Next, the release film and the substrate S are peeled off to expose the first circuit layer 111. Subsequently, solder balls 500 contacting the first circuit layer 111 are formed, thereby forming the package structure 10' as shown in FIG. 3.

It can be seen from the foregoing invention embodiments that the packaging structure in some embodiments of the invention has sufficient mechanical strength. Therefore, even if the thermal expansion coefficients of the component materials in the package structure differ greatly, warping is not easy to occur. In addition, since the package structure is not prone to warpage, it is suitable to arrange another package structure on the package structure to form a stacked package structure.

Although the present invention has been disclosed as above in embodiments, other embodiments are also possible. Therefore, the spirit and scope of the requested item are not limited to the description contained in the implementation mode here.

Anyone who is familiar with this technique can understand that various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the appended patent application.

10‧‧‧Packaging structure

100‧‧‧Line re-distribution structure

110‧‧‧The first line re-layout

111‧‧‧First circuit layer

112‧‧‧First insulation layer

112a‧‧‧Through hole

113‧‧‧First conductive contact

120‧‧‧Second line re-layout

121‧‧‧Second circuit layer

122‧‧‧Second insulating layer

122a‧‧‧Through hole

123‧‧‧Second conductive contact

130‧‧‧The third line re-layout

131‧‧‧The third circuit layer

132‧‧‧Third insulation layer

132a‧‧‧Through hole

133‧‧‧The third conductive contact

140‧‧‧Conductive pad

200‧‧‧chip

210‧‧‧Metal bump

220‧‧‧Welding materials

300‧‧‧Inner conductive strengthening element

310‧‧‧Strengthening layer

310a‧‧‧Through hole

320‧‧‧Conductive connector

330‧‧‧Conductive parts

400‧‧‧First protective layer

500‧‧‧Solder Ball

D1‧‧‧Horizontal distance

Claims (14)

A packaging structure includes: a circuit redistribution structure, including a first circuit layer and a second circuit layer disposed on the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer; A chip is arranged on the circuit redistribution structure and electrically connected to the second circuit layer; at least one inner conductive strengthening element is arranged on the circuit redistribution structure, wherein the inner conductive strengthening element includes: a strengthening layer, Having a Young's modulus of 30 to 200 GPa, wherein the strengthening layer has a through hole; and a conductive connecting member is disposed in the through hole, wherein a top and a bottom of the conductive connecting member are exposed outside the strengthening layer, And electrically connected to the second circuit layer; and a first protective layer covering the chip, wherein the first protective layer covers the sidewall of the opening of the inner conductive strengthening element. According to the package structure described in claim 1, wherein the inner conductive strengthening element surrounds the chip. According to the encapsulation structure described in item 1 of the scope of the patent application, the reinforcing layer material includes bismaleimide triazine resin, epoxy resin, glass or ceramic. As the package structure described in item 1 of the scope of patent application, An upper surface of the inner conductive strengthening element and an upper surface of the first protective layer are coplanar. As described in the first item of the scope of patent application, the package structure further includes a conductive member disposed on the bottom of the conductive connecting member and electrically connected to the second circuit layer. The packaging structure as described in the first item of the scope of the patent application further includes an electronic component disposed on the first protective layer and electrically connected to the top of the conductive connecting member. The packaging structure described in item 6 of the scope of the patent application further includes: a substrate structure disposed between the first protective layer and the electronic component, and the electronic component is electrically connected to the conductive connector through the substrate structure And a second protective layer covering the electronic component. The package structure described in item 1 of the scope of the patent application further includes the first protective layer filling the gap between the chip and the second circuit redistribution layer. The package structure described in item 8 of the scope of patent application further includes the first protective layer filling the gap between the bottom surface of the inner conductive strengthening element portion and the second circuit redistribution layer. A manufacturing method of a package structure includes the following operations: (i) providing a circuit redistribution structure, wherein the circuit redistribution structure includes a first circuit layer and a second circuit layer disposed on the first circuit layer, And the first circuit layer is electrically connected to the second circuit layer; (ii) forming at least one internal conductive strengthening element on the circuit redistribution structure, wherein the internal conductive strengthening element includes: a strengthening layer with a thickness of 30~200GPa A Young’s modulus, in which the strengthening layer has a through hole; and a conductive connection member disposed in the through hole, wherein a top and a bottom of the conductive connection member are exposed outside the strengthening layer and are electrically connected to the A second circuit layer; (iii) disposing a chip on the circuit redistribution structure, wherein the chip is electrically connected to the second circuit layer; and (iv) forming a first protective layer to cover the chip and the internal conductive strengthening element The opening side wall. The manufacturing method of the package structure as described in item 10 of the scope of patent application, wherein operation (ii) includes the following steps: (a) providing a substrate, wherein the substrate has a Young's modulus of 30 to 200 GPa; (b) Performing a drilling process on the substrate to form the strengthening layer with the through hole; (c) forming the conductive connection member in the through hole to form an inner conductive strengthening element; and (d) Disposing the inner conductive strengthening element on the line redistribution structure. According to the manufacturing method of the package structure described in claim 11, the operation (ii) includes forming a conductive member on the bottom of the conductive connecting member and electrically connecting the second circuit layer. According to the manufacturing method of the package structure described in claim 10, it further includes (v) disposing an electronic component on the first protective layer, wherein the electronic component is electrically connected to the top of the conductive connecting member. The manufacturing method of the package structure as described in claim 13, wherein in operation (v), the electronic component is disposed on a substrate structure and covered by a second protective layer, and the electronic component passes through the substrate The structure is electrically connected to the top of the conductive connector.

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