JP4525148B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to, for example, a wiring board for flip chip mounting of a semiconductor IC chip, a semiconductor device including the mounting body, and a manufacturing method thereof, and more specifically, stress relaxation made of resin on a connection land for external connection. The present invention relates to a wiring board provided with a protruding electrode having a layer inside, a semiconductor device, and a manufacturing method thereof.

  Conventionally, high lead solder bumps (95Pb-5Sn) have been used for flip chip connection with high reliability. However, in recent years, there has been a movement to use so-called lead-free solder for manufacturing electronic devices due to a demand for reducing environmental burden. It is getting stronger. As lead-free solder materials, for example, Sn-Ag, Sn-Ag-Cu, Sn-Ag-Bi-Cu, Sn-Cu, Sn-Zn, and the like have been proposed. However, in such lead-free solder materials, there is no material having the same melting point and mechanical characteristics as high-lead solder, so it is not easy to lead-free the flip chip connection part.

  In addition, with recent rapid spread and development of digital devices, ICs used tend to be larger and have more pins. This means that the solder joint is subjected to a larger thermal stress with a smaller connection area, and therefore there is an urgent need to establish a reliable solder connection technique.

  On the other hand, for highly reliable connection between the IC chip and the wiring board, it is effective to secure a gap (standoff) between the IC and the wiring board and to form a bump structure that relieves thermal stress. is there. As a means for that, a proposal has been made to provide a stress relaxation layer made of resin in the vicinity of the solder connection portion (see Patent Documents 1 to 3 below).

  Patent Documents 1 and 2 below propose a structure in which such a stress relaxation layer is formed on the wafer side. FIG. 8 is a cross-sectional view of a principal part of a semiconductor package described in Patent Document 2 below. In FIG. 8, 1 is a Si wafer (IC), 2 is an Al pad, 3 is a passivation film, 4 is an insulating layer, 5 is a seed layer for electroplating, 6 is a stress relaxation layer, 7 is a Cu plating layer, 8 is A sealing resin layer, 9 is an external terminal, 10 is a solder bump, and Cu wiring 7 and external terminal 9 are formed on the stress relaxation layer 6 from the electrode pad 2 on the wafer 1 by a wafer level rewiring process. Yes.

  Further, in Patent Document 3 below, as shown in FIG. 9, between the Al pad 12 of the Si wafer (IC) 11 and the connection land 14 of the wiring substrate 13, the conductive material using polyimide resin as the core (core). A structure connected by bumps 15 is disclosed. The conductive bump 15 is composed of a polyimide core 16 constituting a stress relaxation layer and a metal layer 17 covering the periphery thereof. In the wafer process, the polyimide core 16 having a diameter smaller than the pad diameter is formed on the Al pad 12. Then, the Al film 17 is formed by covering the portion of the Al pad 12 not covered with the core 16 and the polyimide core surface. The end of the conductive bump 15 on the connection land 14 side is further covered with a three-layer metal layer 17 of Ti, Ni, and Au for solder connection with the connection land 14 of the wiring board 13.

JP 2003-179183 A International Publication No. 00/077844 Pamphlet JP-A-8-102467

  However, in the configuration of Patent Documents 1 and 2, since the stress relaxation layers 6 and 16 are formed by the wafer process, the tact time of the wafer is long, which can cause a decrease in yield. There is a problem that the cost is high.

  Further, in the configuration of Patent Document 2, since the bump diameter of the conductive bump 15 is smaller than the pad diameter of the electrode pad 12, the bump diameter of the conductive bump 15 is reduced as the electrode pad 12 is reduced in diameter. The connection reliability between the IC chip and the wiring board is lowered. For this reason, the reduction of the pad diameter of the electrode pad 12 is suppressed, which hinders the improvement of the wiring density and has a problem that it becomes difficult to cope with further increase in the number of IC pins and the downsizing of the package in the future. Yes.

  The present invention has been made in view of the above-described problems, and can form a highly reliable solder connection structure at a low cost, and can sufficiently cope with an increase in the number of IC pins, a reduction in package size, and the like. It is an object to provide these manufacturing methods.

  In solving the above problems, the wiring board of the present invention has a connection land for external connection and an insulating layer having an opening for opening the connection land formed on the substrate surface. A wiring board provided with a projecting electrode having a stress relaxation layer formed therein, the projecting electrode comprising: a first connection portion that closes the opening and is connected to a connection land; and And a second connection portion formed on the insulating layer with a large diameter.

  In the method for manufacturing a wiring board according to the present invention, an insulating layer is formed on a substrate surface on which a connection land for external connection is formed, and then an opening for opening the connection land is formed in the insulating layer. The step of covering the connection land with the first conductor layer, the step of patterning the stress relaxation layer having a diameter larger than the opening diameter of the opening after forming the resin layer on the first conductor layer, and the stress Covering the relaxation layer with the second conductor layer.

  In the semiconductor device of the present invention, a connection land connected to the electrode pad of the IC chip and an insulating layer having an opening for opening the connection land are formed on one surface of the wiring board. A semiconductor device in which an electrode pad is connected via a protruding electrode having a stress relaxation layer made of resin therein, and the protruding electrode closes the opening and is connected to a connection land And a second connection portion formed on the insulating layer with a diameter larger than that of the first connection portion.

  According to a method of manufacturing a semiconductor device of the present invention, an insulating layer is formed on a substrate surface on which a connection land for external connection is formed, and then an opening for opening the connection land is formed in the insulating layer. A step of covering the connection land with the first conductor layer, a step of patterning a stress relaxation layer having a diameter larger than the opening diameter of the opening after forming the resin layer on the first conductor layer, A step of covering the relaxation layer with a second conductor layer, and a step of mounting an IC chip on the second conductor layer covering the stress relaxation layer.

  In the present invention, a protruding electrode having a stress relaxation layer is formed on the wiring substrate side, so that the manufacturing cost is reduced as compared with the case where the protruding electrode is formed on the IC chip side. .

  In the wiring board of the present invention, the protruding electrode is composed of a first connection portion and a second connection portion. The formation diameter of the protruding electrode can be set based on the size of the opening of the insulating layer, and does not depend on the formation diameter of the connection land. That is, since the formation diameter of the protruding electrode and the formation diameter of the connection land can be set independently of each other, a highly reliable connection structure can be obtained even for a substrate having a high wiring density.

  As described above, according to the present invention, since the protruding electrode having the stress relaxation layer inside is formed on the wiring board side, the manufacturing cost can be reduced. In addition, since the formation diameter of the protruding electrode can be set independently of the formation diameter of the connection land of the wiring board, a highly reliable connection structure can be obtained even for a board having a high wiring density, It is possible to sufficiently cope with the increase in the number of IC pins and the downsizing of the package.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment]
1 to 3 are process cross-sectional views for explaining a method of manufacturing a wiring board according to the first embodiment of the present invention. First, the insulating base material 21 in which the connection land 22 for external connection and the wiring 23 are formed on one surface is prepared (FIG. 1A).

  In the present embodiment, the insulating base material 21 is made of a resin base material mainly composed of a thermoplastic resin or a thermosetting resin material, and is appropriately selected according to the application object, application, or the like. For example, glass fiber impregnated with epoxy resin or polyimide resin, paper impregnated with phenolic resin, etc. can be applied, and bismaleimide triazine resin, benzocyclobutene resin, liquid crystal polymer, etc. are also applicable It is.

  The connection land 22 and the wiring 23 are made of copper, but of course, other metal materials can be applied without being limited thereto. Moreover, you may form not only in the surface of one side of the insulating base material 21 but in the surface of the other side.

  Next, a photosensitive resin is applied to the processing surface of the insulating base material 21 (formation surface of the connection land 22) to form the insulating layer 24 (FIG. 1B). As the insulating layer 24, a solder resist, a plating resist, or the like can be applied. Then, an appropriate mask is applied to the insulating layer 24 to perform exposure and development processes, thereby forming an opening 24a for opening the connection land 22 (FIG. 1C).

  Here, the opening 24a does not need to be formed to a size that opens the entire region of the connection land 22 and may be a size that opens a part of the connection land 22 as illustrated. The opening diameter of the opening 24a can be arbitrarily set, and can be set according to the size of the formation diameter of the stress relaxation layer 26 described later. Moreover, although the opening part 24a was formed using the photolithographic technique as mentioned above, you may form by laser processing etc. In this case, photosensitivity is not required as a constituent material of the insulating layer 24.

  Next, the entire processing surface including a partial region of the connection land 22 opened through the opening 24a is covered with the Cu plating layer 25 (FIG. 1D). The Cu plating layer 25 corresponds to the “first conductor layer” of the present invention. In this embodiment, the Cu plating layer 25 is formed by forming a seed layer over the entire processing surface by electroless Cu plating and then performing electric field Cu plating. Of course, this is not a limitation.

  Subsequently, the stress relaxation layer 26 is formed on the connection land 22 corresponding to the position where the opening 24a is formed (FIG. 2A).

  The constituent resin material of the stress relaxation layer 26 is not particularly limited as long as it can withstand a reflow temperature (for example, about 250 ° C. to 300 ° C.) at the time of solder connection, and a material having an arbitrary physical property value according to the purpose. For example, polyimide, epoxy resin, divinylbenzene resin, and the like can be used.

  The method of forming the stress relaxation layer 26 is not particularly limited. For example, when the resin material is printed on the opening 24a of the insulating layer 24 with a desired diameter, or when the resin material has photosensitivity, After the entire area is spin-coated, it can be formed by exposure and development so that a resin layer having a target diameter remains on the opening 24a, and the printed or patterned resin layer is cured. Thus, the stress relaxation layer 26 having a predetermined shape can be completed.

  Next, the entire treated surface including the formed stress relaxation layer 26 is coated with an electroless Cu plating layer 27 (FIG. 2B), and then the electroless Cu plating layer 27 is covered with an electrolytic Cu plating layer 28 (FIG. 2). 2C). The electroless Cu plating layer 27 and the electrolytic Cu plating layer 28 correspond to the “second conductor layer” of the present invention, and electrically connect the surface of the stress relaxation layer 26 and the connection land 22.

  Subsequently, a photosensitive resist 29 is applied to the entire processing surface of the insulating base material 21 (FIG. 3A), dried, and then subjected to exposure and development processes, and the upper surface of the stress relaxation layer 26 and its surroundings. A resist pattern 29A is formed by patterning (FIG. 3B). Then, using the resist pattern 29A as a mask, the Cu plating layers 25, 27, and 28 are removed by etching to expose the insulating layer 24, and the stress relaxation layer 26 is electrically separated individually by removing the resist pattern 29A. The protruding electrode 30 thus formed is formed (FIG. 3C).

  If necessary, surface treatment such as electroless Ni / Au plating may be performed on the upper surface of the bump electrode 30. Alternatively, or in addition to this, solder pre-coating can be performed by a dip method or a plating method.

  The bump electrode 30 is configured as a conductive bump having the stress relaxation layer 26 therein, and Cu plating layers 27 and 28 covering the upper surface and the periphery of the stress relaxation layer 26, and the lower surface of the stress relaxation layer 26 and the connection land. For example, an electrode pad of an IC chip soldered to the protruding electrode 30 and the connection land 22 are electrically connected via a Cu plating layer 25 interposed between the connection land 22 and the electrode 22.

  Here, the protruding electrode 30 includes a first connection portion 30A that closes the opening 24a of the insulating layer 24, and a second connection portion 30B having a larger diameter than the first connection portion 30A. The first connection portion 30 </ b> A is smaller than the formation diameter of the connection land 22, and the second connection portion 30 </ b> B is larger than the formation diameter of the connection land 22. The second connection portion 30B is formed on the insulating layer 24 at the periphery of the opening 24a. The formation diameter of the second connection portion 30B is adjusted by the formation diameter of the stress relaxation layer 26 formed larger than the opening diameter of the opening 24a.

  Further, the second connecting portion 30B of the protruding electrode 30 is not limited to the example in which the cross section is uniform in the height direction as shown in the figure, but a table whose top diameter is smaller than the bottom diameter, for example, as shown in FIG. It is good also as a shape, and it becomes effective for joint defect suppression, such as a solder bridge.

  As described above, the wiring board 20 (FIG. 3C) of the present embodiment is manufactured. In the wiring substrate 20 of the present embodiment, the protruding electrode 30 having the stress relaxation layer 26 inside is formed on the wiring substrate 20 side, so that compared to the case where the protruding electrode 30 is formed on the IC chip side. Thus, the manufacturing cost can be reduced.

  In addition, the protruding electrode 30 includes a first connecting portion 30A and a second connecting portion 30B, and the diameter of the protruding electrode 30 can be set based on the size of the opening 24 of the insulating layer 24. It does not depend on the formation diameter of the land 22. That is, since the formation diameter of the projection electrode 30 and the formation diameter of the connection land 22 can be set independently of each other, it is possible to form the projection electrode 30 having a diameter larger than that of the opening 24a as illustrated in FIG. Thereby, a highly reliable connection structure can be obtained even for a substrate having a high wiring density.

[Second Embodiment]
5 and 6 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. In the figure, portions corresponding to those of the first embodiment described above are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor device of this embodiment is configured by flip-chip mounting an IC chip on the surface on which the protruding electrode 30 of the wiring substrate 20 having the above-described configuration is formed. The wiring substrate 20 may be formed individually for each product size, or may be separated into pieces after mounting a plurality of IC chips on a large-area substrate.

  As shown in FIG. 5A, the wiring board 20 in the present embodiment has connection lands 22 and 32 and wirings 23 and 33, respectively, on the upper surface side and the lower surface side thereof. In the connection land 22 on the upper surface side, the protruding electrode 30 having the above-described configuration is connected through the opening 24 formed in the insulating layer 24 covering the upper surface of the wiring substrate 20, and the connection land 32 on the lower surface side is connected. In other words, it is exposed to the outside through an opening 34 a formed in the insulating layer 34 covering the lower surface of the wiring board 20.

  The protruding electrode 30 is formed through the process described in the first embodiment. A portion between the upper surface side wiring 23 and the lower surface side wiring 33 is electrically connected to each other through the interlayer connection portion 35, and the lower surface side opening 34 a has a diameter larger than the diameter of the connection land 32. Of course, it is not limited to this.

  Therefore, first, the solder paste 31 is supplied to the upper surface of the second connection portion 30B of the protruding electrode 30 by, for example, a dispensing method (FIG. 5A). As the solder paste 31, a paste made of a lead-free solder material is used. As the salt-free solder material, for example, Sn—Ag, Sn—Ag—Cu, Sn—Ag—Bi—Cu, Sn—Cu, Sn—Zn, and the like are applicable.

  Subsequently, the IC chip 36 is mounted on the protruding electrode 30 (FIG. 5B). Solder bumps 38 are formed in advance on the electrode pads 37 of the IC chip 36. The solder bump 38 is made of a lead-free solder material similar to that described above, and can be formed by a known method such as plating, printing, or ball mounting. A normally used flip chip mounter can be used for mounting the IC chip 36. The protruding electrodes 30 are arranged corresponding to the positions where the electrode pads 38 are formed. Immediately after mounting, the gap between the bump electrode 30 and the solder bump 38 is temporarily fixed by the adhesive action of the solder paste 31.

  Next, the wiring substrate 20 and the IC chip 36 temporarily fixed thereto are loaded into a reflow furnace, the solder bumps 38 are reflow-heated, and the protruding electrodes 30 and the solder bumps 38 are joined to each other (FIG. 5C). Thereby, the protruding electrode 30 of the wiring board 20 and the electrode pad 37 of the IC chip 36 are mechanically and electrically connected. In this reflow process, the protruding electrode 30 is not melted, and the formation height of the protruding electrode 30 is ensured.

  Subsequently, an underfill resin 39 is injected between the IC chip 36 and the wiring substrate 20, the gap region between the IC chip 36 and the wiring substrate 20 is filled with the under film resin 39, and the mold resin 40 The IC chip 36 is sealed (FIG. 6A). For example, an epoxy resin is applied to the underfill resin 39 and the mold resin 40.

  And the external terminal 41 connected to the connection land 32 through the opening part 34a of the insulating layer 34 is formed in the lower surface side of the wiring board 20 (FIG. 6B). The external terminal 41 is made of, for example, a lead-free solder material and can be formed by a known method such as plating, printing, or ball mounting. As described above, the package type semiconductor device 42 is manufactured.

  In the semiconductor device 42 of the present embodiment, the protruding electrode 30 having the stress relaxation layer 26 therein constitutes a solder connection portion between the connection land 22 of the wiring board 20 and the electrode pad 37 of the IC chip 36. Therefore, a gap (standoff) of a certain level or more can always be stably secured between the connection land 22 and the electrode pad 37, and stress acting on the solder connection portion can be relaxed by the stress relaxation layer 26. Thereby, durability can be given to a solder connection part with respect to the thermal stress which originates in the difference in the thermal expansion coefficient between the wiring board 20 and the IC chip 36, and connection reliability can be improved. it can.

  In the present embodiment, since such protruding electrodes 30 are formed not on the IC chip 36 side but on the wiring substrate 20 side, the manufacturing cost when considering the entire package can be reduced.

  On the other hand, the protruding electrode 30 includes a first connecting portion 30A and a second connecting portion 30B, and the diameter of the protruding electrode 30 can be set based on the size of the opening 24 of the insulating layer 24. It does not depend on the formation diameter of the land 22. That is, since the formation diameter of the projection electrode 30 and the formation diameter of the connection land 22 can be set independently of each other, it is possible to form the projection electrode 30 having a diameter larger than that of the opening 24a as illustrated in FIG. As a result, a highly reliable connection structure can be obtained even on a substrate with high wiring density, and it will be fully compatible with future increases in IC chip size, IC pin count, and package size. It becomes possible.

  Further, the projection electrode 30 is configured by the first connection portion 30A filling the opening 24a and the second connection portion 30B having a diameter larger than the first connection portion 30A, thereby acting on the second connection portion 30B. The stress propagated to the interface between the first connection portion 30A and the connection land 22 is reduced by receiving the stress to be applied on the upper surface of the insulating layer 24 that supports the stress. Thereby, the further improvement of the connection reliability in a solder connection part can be aimed at.

  Furthermore, in the present embodiment, since the hard solder bump 38 is interposed between the electrode pad 37 and the protruding electrode 30 of the IC chip 36, the bonding interface between the electrode pad 37 and the protruding electrode 30 is not affected. The strength can be increased and the influence of the stress acting on the protruding electrode 30 on the electrode pad 37 side can be reduced. That is, when a low-k (low dielectric constant) material that has recently been attracting attention in the field of IC manufacturing is used as an insulating layer between layers, the stress acting on the solder connection portion is directly propagated to the electrode pad, thereby the insulation. Although there is a concern about damage to the layer, according to the present embodiment, this can be avoided by interposing the hard solder bump 38 between the electrode pad 37 and the protruding electrode 30.

[Third Embodiment]
FIG. 7 shows a third embodiment of the present invention. In the figure, portions corresponding to those in the first and second embodiments described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the present embodiment, the surface of the wiring substrate 20 opposite to the surface on which the protruding electrodes 30 are formed is the wire bonding mounting surface of the IC chip 36, and the protruding electrodes 30 are used as external terminals for mounting on a mother substrate (not shown). It is composed. The protruding electrode 30 is manufactured through the same process as in the first embodiment.

  In the semiconductor device 45 having such a configuration, the IC chip 36 is connected between the electrode pad and the connection terminal 43 on the wiring substrate 20 via the bonding wire 44 and sealed with the mold resin 40.

  Further, the surface on the second connection portion 30B side of the protruding electrode 30 configured as an external terminal may be subjected to surface treatment such as Sn plating, solder plating, electroless Ni / Au plating, if necessary, When mounting on the mother substrate, the solder bump 46 may be formed on the tip of the bump electrode 30 by a ball mount method, a plating method, a printing method, or the like.

  As mentioned above, although each embodiment of this invention was described, of course, this invention is not limited to these, A various deformation | transformation is possible based on the technical idea of this invention.

  For example, in the above second and third embodiments, the semiconductor device according to the present invention has been described by taking as an example a semiconductor package component in which a single IC chip 36 is mounted on the wiring board 20. However, the present invention is not limited to this, and the present invention can also be applied to a multi-chip package component in which a plurality of IC chips are mounted on a wiring board.

  In addition, the wiring board according to the present invention is not limited to being configured as an interposer substrate for semiconductor package components, and may be configured as a mother substrate on which semiconductor package components are mounted, for example.

FIG. 2 is a process cross-sectional view illustrating a method for manufacturing a wiring board according to the present invention as a first embodiment of the present invention, wherein A is a preparation process of an insulating base material 21 having a connection land 22, and B is a connection land 22. A process for forming the insulating layer 24 to be covered, C represents a process for forming the opening 24a in the insulating layer 24, and D represents a process for forming the Cu plating layer 25 as the first conductor layer. FIG. 2 is a process cross-sectional view subsequent to FIG. 1 for explaining the method for manufacturing a wiring board according to the present invention, wherein A is a process of forming a stress relaxation layer 26, and B and C are Cu plating layers 27 and 28 as second conductors. Each process is shown. It is process sectional drawing following FIG. 1 explaining the manufacturing method of the wiring board based on this invention, and each shows the removal process of the unnecessary area | region of the 1st, 2nd conductor layers 25, 27, 28 in order of AC. ing. 5 is a cross-sectional side view of a main part showing a modified example of the shape of the protruding electrode 30 in the configuration of the wiring board 20 shown in the first embodiment. FIG. FIG. 4 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention as a second embodiment of the present invention, where A is a solder paste 31 supply process, B is a mounting process of an IC chip 36, and C Indicates the reflow process of the solder connection part. FIG. 6 is a process cross-sectional view subsequent to FIG. 5 for explaining the method for manufacturing a semiconductor device according to the present invention, in which A represents a sealing process and B represents a process for forming an external terminal 41. It is principal part sectional drawing which shows the structure of the semiconductor device by the 3rd Embodiment of this invention. It is principal part sectional drawing which shows the structure of the semiconductor device by a 1st prior art example. It is principal part sectional drawing which shows the structure of the solder connection part of the semiconductor device by a 2nd prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 20 ... Wiring board, 22 ... Connection land, 24 ... Insulating layer, 24a ... Opening, 25 ... Cu plating layer (1st conductor layer), 26 ... Stress relaxation layer, 27 ... Electroless Cu plating layer (2nd Conductor layer), 28 ... Electrolytic Cu plating layer (second conductor layer), 30 ... Projection electrode, 30A ... First connection portion, 30B ... Second connection portion, 36 ... IC chip, 37 ... Electrode pad, 38, 46 ... Solder bumps, 39 ... Underfill resin, 41 ... External terminals, 42, 45 ... Semiconductor devices.

Claims (2)

A substrate having a first surface on which a connection land and an insulating layer having an opening for opening the connection land are formed; and a second surface on which an external terminal is formed;
A first connection portion provided on the connection land, closing the opening and connected to the connection land, and a second connection portion formed on the insulating layer having a diameter larger than that of the first connection portion; A protruding electrode having a resin-made stress relaxation layer formed therein,
An IC chip having electrode pads facing the connection land,
A solder bump which is provided between the protruding electrode and the electrode pad and is harder than the stress relaxation layer;
An underfill resin formed between the IC chip and the first surface;
A mold resin formed on the first surface and sealing the IC chip;
A semiconductor device comprising: Forming an insulating layer on the first surface of the substrate on which a connection land for external connection is formed, and then forming an opening in the insulating layer for opening the connection land;
Covering the opened connection land with a first conductor layer;
After forming a resin layer on the first conductor layer, patterning a stress relaxation layer having a diameter larger than the opening diameter of the opening; and
Coating the stress relaxation layer with a second conductor layer;
Forming a solder bump harder than the stress relaxation layer on the electrode pad of the IC chip;
Mounting the IC chip on the second conductor layer covering the stress relaxation layer via the solder bump ;
Injecting an underfill resin between the first surface and the IC chip;
Forming a mold resin for sealing the IC chip on the first surface;
Forming an external terminal on the second surface of the substrate opposite to the first surface .

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