JPH1050770A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH1050770A JPH1050770A JP8205133A JP20513396A JPH1050770A JP H1050770 A JPH1050770 A JP H1050770A JP 8205133 A JP8205133 A JP 8205133A JP 20513396 A JP20513396 A JP 20513396A JP H1050770 A JPH1050770 A JP H1050770A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- wiring board
- ball
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、特に、表面に複数のボール状電極が
接続された半導体チップが、複数の電極層が表面に形成
されている配線基板上にフリップチップボンディングさ
れる半導体装置に適用して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor chip having a plurality of ball electrodes connected to a surface of a wiring substrate having a plurality of electrode layers formed on the surface. The present invention relates to a technology that is effective when applied to a semiconductor device that is flip-chip bonded to a semiconductor device.
【０００２】[0002]
【従来の技術】半導体装置の代表として知られるＬＳＩ
は、多くの機能が要求されるにつれて集積度はより高ま
って、ますます多ピン化の傾向にある。このような多ピ
ン化に適したＬＳＩとして、ＢＧＡ（Ｂａｌｌ Ｇｒｉ
ｄ Ａｒｒａｙ）構造のパッケージを有するものが知ら
れている。2. Description of the Related Art LSIs known as representatives of semiconductor devices
As the number of functions is required, the degree of integration is increasing and the number of pins is increasing. As an LSI suitable for such multi-pin configuration, BGA (Ball Gri
(d Array) structure is known.
【０００３】例えば、日経ＢＰ社発行、「日経エレクト
ロニクス」、１９９４、２−１４号、Ｐ５９〜Ｐ７３に
は、そのようなＢＧＡ構造に関する技術が詳細に記載さ
れている。[0003] For example, the technology relating to such a BGA structure is described in detail in "Nikkei Electronics", published by Nikkei BP, 1994, 2-14, pp. 59-73.
【０００４】このＢＧＡ構造のパッケージのＬＳＩは、
実装用電極としてリードの代わりにバンプと称される例
えば半田からなるボール状電極を用いるようにしたもの
であり、このボール状電極は複数個がパッケージの一部
を構成する配線基板の裏面に格子状に配置されている。
また、半導体チップは配線基板の表面にフェースアップ
ボンディングされて、その複数のパッド電極は、配線基
板の表面に形成されている複数の電極層にボンディング
ワイヤを介して接続されて、スルーホール配線を通じて
配線基板の裏面の対応したボール状電極に導通されてい
る。[0004] The LSI of the package having the BGA structure is as follows.
Instead of leads, ball electrodes made of, for example, solder, which are called bumps, are used as mounting electrodes, and a plurality of such ball electrodes are formed on a back surface of a wiring board which forms a part of a package. It is arranged in a shape.
Further, the semiconductor chip is face-up bonded to the surface of the wiring board, and the plurality of pad electrodes are connected to a plurality of electrode layers formed on the surface of the wiring board via bonding wires, and are connected through through-hole wiring. It is electrically connected to the corresponding ball-shaped electrode on the back surface of the wiring board.
【０００５】このＢＧＡ構造のパッケージは、ＬＳＩに
おいてこれ以前から知られている代表的なパッケージで
あるＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）に
比較して、より高集積化された場合のピンピッチを小さ
くでき、同じピン数の場合にはパッケージの面積を小さ
くできるという利点がある。[0005] The package of the BGA structure can reduce the pin pitch in the case of higher integration, as compared with QFP (Quad Flat Package), which is a typical package known before in LSI. In the case of the number of pins, there is an advantage that the area of the package can be reduced.
【０００６】このようなＢＧＡ構造のパッケージにおい
て、半導体チップを配線基板にボンディングする場合
に、ワイヤボンディングを不要にしたフリップチップ方
式を採用したタイプが普及している。このフリップチッ
プ方式においては、各パッド電極にボール状電極を接続
して、半導体チップは各ボール状電極を通じて配線基板
の表面にフェースダウンボンディングされる。このフリ
ップチップ方式によれば、半導体チップの全面を利用し
てパッド電極を配置できるので高集積化が容易となり、
また半導体チップの裏面が露出されているので、放熱性
に優れている。In such a package having a BGA structure, when a semiconductor chip is bonded to a wiring board, a type adopting a flip-chip method that does not require wire bonding has become widespread. In the flip chip method, ball electrodes are connected to the pad electrodes, and the semiconductor chip is face-down bonded to the surface of the wiring board through the ball electrodes. According to the flip chip method, pad electrodes can be arranged using the entire surface of the semiconductor chip, so that high integration is facilitated,
Further, since the back surface of the semiconductor chip is exposed, the heat dissipation is excellent.
【０００７】このように半導体チップを配線基板にフリ
ップチップ方式でボンディングしたＢＧＡ構造のパッケ
ージでは、半導体チップの配線基板とのボンディング部
分を周囲雰囲気から保護するために、その部分に樹脂を
充填して封止することが行われている。この樹脂の充填
方法は、半導体チップがボンディングされた配線基板を
傾かせた状態で、液状の樹脂をボンディング部分に流し
込む方法がとられている。In the package of the BGA structure in which the semiconductor chip is bonded to the wiring board by the flip-chip method as described above, in order to protect the bonding part of the semiconductor chip with the wiring board from the surrounding atmosphere, the part is filled with resin. Sealing has been performed. As a method of filling the resin, a method is used in which a liquid resin is poured into the bonding portion while the wiring substrate to which the semiconductor chip is bonded is tilted.
【０００８】[0008]
【発明が解決しようとする課題】前記のように半導体チ
ップの配線基板とのボンディング部分に樹脂を充填して
封止する場合、半導体チップのボンディング部分には多
くのボール状電極が配置されているので、液状の樹脂の
濡れ広がりが不均一になるため、樹脂充填が困難になる
という問題がある。As described above, when the bonding portion of the semiconductor chip to the wiring board is filled with resin and sealed, many ball electrodes are arranged at the bonding portion of the semiconductor chip. Therefore, there is a problem that the wet filling of the liquid resin becomes non-uniform, which makes it difficult to fill the resin.
【０００９】すなわち、半導体チップのボンディング部
分となる表面には、細かいピッチで多くのボール状電極
が配置されているため、各ボール状電極の隙間を通じて
樹脂を均一に流し込むのは困難となる。That is, since many ball-shaped electrodes are arranged at a fine pitch on the surface of the semiconductor chip to be the bonding portion, it is difficult to uniformly flow the resin through the gaps between the ball-shaped electrodes.
【００１０】また、半導体チップのボンディング部分以
外である配線基板の表面には樹脂が充填されないため、
電極層が外部雰囲気に露出されたままになっている。こ
のため、洗浄処理工程などにおいて汚染され易くなって
おり、これらが原因で腐食が生じて劣化するという問題
がある。Further, since the surface of the wiring board other than the bonding portion of the semiconductor chip is not filled with the resin,
The electrode layer remains exposed to the external atmosphere. For this reason, contamination is apt to occur in a cleaning process or the like, and there is a problem that corrosion and deterioration occur due to these.
【００１１】例え配線基板の表面全面に樹脂を濡れ広が
らせようとしても、配線基板の表面がフラットになって
いるので、樹脂は不均一な広がりになり、樹脂ダレなど
が生ずる。Even if the resin is to be spread over the entire surface of the wiring board, the resin is unevenly spread because the surface of the wiring board is flat, and resin dripping occurs.
【００１２】本発明の目的は、半導体チップを配線基板
にフリップチップ方式でボンディングしたＢＧＡ構造の
パッケージにおいて、樹脂充填を容易にするとともに、
配線基板の電極層の劣化を防止することが可能な技術を
提供することにある。An object of the present invention is to facilitate resin filling in a BGA package in which a semiconductor chip is bonded to a wiring board by a flip chip method.
An object of the present invention is to provide a technique capable of preventing deterioration of an electrode layer of a wiring board.
【００１３】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１４】[0014]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記の通りである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.
【００１５】（１）本発明の半導体装置は、表面に複数
のボール状電極が接続された半導体チップが、前記ボー
ル状電極に対応した複数の電極層が表面に形成されてい
る配線基板上にフリップチップボンディングされる半導
体装置であって、前記電極層が形成されている配線基板
の表面の周辺に沿ってダム部が設けられ、このダム部の
内側に前記半導体チップ及び電極層を封止するように樹
脂が充填されている。(1) In a semiconductor device according to the present invention, a semiconductor chip having a plurality of ball-shaped electrodes connected to a surface thereof is formed on a wiring board having a plurality of electrode layers corresponding to the ball-shaped electrodes formed on the surface. A semiconductor device to be flip-chip bonded, wherein a dam portion is provided along a periphery of a surface of a wiring board on which the electrode layer is formed, and the semiconductor chip and the electrode layer are sealed inside the dam portion. So that the resin is filled.
【００１６】（２）本発明の半導体装置の製造方法は、
表面に複数のボール状電極が接続された半導体チップを
用意する工程と、表面に前記ボール状電極に対応した複
数の電極層が表面に形成されるとともに、この表面の周
辺に沿ってダム部が設けられた配線基板を用意する工程
と、前記半導体チップを各ボール状電極が対応する前記
電極層に接続されるように前記配線基板の表面にフリッ
プチップボンディングする工程と、前記ダム部の内側に
前記半導体チップ及び電極層が封止されるように樹脂を
充填する工程とを含んでいる。(2) The method of manufacturing a semiconductor device according to the present invention comprises:
Preparing a semiconductor chip having a plurality of ball-shaped electrodes connected to the surface, forming a plurality of electrode layers corresponding to the ball-shaped electrodes on the surface, and forming a dam portion along the periphery of the surface. A step of preparing a provided wiring board; a step of flip-chip bonding the semiconductor chip to a surface of the wiring board such that each ball-shaped electrode is connected to the corresponding electrode layer; Filling a resin so that the semiconductor chip and the electrode layer are sealed.
【００１７】上述した（１）の手段によれば、本発明の
半導体装置は、半導体チップがフリップチップボンディ
ングされる、電極層が形成された配線基板の表面の周辺
に沿ってダム部が設けられ、このダム部の内側に前記半
導体チップ及び電極層を封止するように樹脂が充填され
るので、半導体チップを配線基板にフリップチップ方式
でボンディングしたＢＧＡ構造のパッケージにおいて、
樹脂充填を容易にするとともに、配線基板の電極層の劣
化を防止することが可能となる。According to the above-mentioned means (1), in the semiconductor device of the present invention, the dam portion is provided along the periphery of the surface of the wiring substrate on which the electrode layer is formed, on which the semiconductor chip is flip-chip bonded. Since the inside of the dam portion is filled with a resin so as to seal the semiconductor chip and the electrode layer, a package having a BGA structure in which the semiconductor chip is bonded to a wiring board by a flip chip method,
In addition to facilitating resin filling, it is possible to prevent deterioration of the electrode layer of the wiring board.
【００１８】上述した（２）の手段によれば、本発明の
半導体装置の製造方法は、まず、表面に複数のボール状
電極が接続された半導体チップ、及び表面に前記ボール
状電極に対応した複数の電極層が表面に形成されるとと
もに、この表面の周辺に沿ってダム部が設けられた配線
基板を用意する。次に、半導体チップを各ボール状電極
が対応する前記電極層に接続されるように、前記配線基
板の表面にフリップチップボンディングした後、ダム部
の内側に前記半導体チップ及び電極層が封止されるよう
に樹脂を充填する。これによって、半導体チップを配線
基板にフリップチップ方式でボンディングしたＢＧＡ構
造のパッケージにおいて、樹脂充填を容易にするととも
に、配線基板の電極層の劣化を防止することが可能とな
る。According to the above-mentioned means (2), the method of manufacturing a semiconductor device according to the present invention firstly corresponds to a semiconductor chip having a plurality of ball-shaped electrodes connected to the surface and a ball-shaped electrode corresponding to the surface. A wiring board is prepared in which a plurality of electrode layers are formed on a surface and a dam portion is provided along the periphery of the surface. Next, after the semiconductor chip is flip-chip bonded to the surface of the wiring board so that each ball-shaped electrode is connected to the corresponding electrode layer, the semiconductor chip and the electrode layer are sealed inside the dam portion. Is filled with resin. Thus, in a package having a BGA structure in which a semiconductor chip is bonded to a wiring board by a flip-chip method, it becomes possible to easily fill the resin and prevent the electrode layer of the wiring board from being deteriorated.
【００１９】以下、本発明について、図面を参照して実
施例とともに詳細に説明する。Hereinafter, the present invention will be described in detail with reference to the drawings and embodiments.
【００２０】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having identical functions are given same symbols and their repeated explanation is omitted.
【００２１】[0021]
（実施形態１）図１は本発明の実施形態１による半導体
装置を示す平面図で、図２は図１のＡ−Ａ断面図であ
る。(Embodiment 1) FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1 of the present invention, and FIG. 2 is a sectional view taken along line AA of FIG.
【００２２】本発明の実施形態１による半導体装置１に
おいて、２はＬＳＩチップからなる半導体チップで、こ
の半導体チップ２の表面には全面にわたって例えばＡｌ
などからなる複数のパッド電極が形成されて、各パッド
電極には例えば半田（Ｐｂ−Ｓｎ合金）からなるボール
状電極３が接続されている。In the semiconductor device 1 according to the first embodiment of the present invention, reference numeral 2 denotes a semiconductor chip composed of an LSI chip, and the surface of the semiconductor chip 2 is made of, for example, Al
A plurality of pad electrodes made of, for example, are formed, and a ball-shaped electrode 3 made of, for example, solder (Pb-Sn alloy) is connected to each pad electrode.
【００２３】４は配線基板で、各種樹脂あるいはセラミ
ックなどの絶縁材料から構成され、この表面にはボール
状電極３に対応した複数の電極層５が形成されている。
また、この配線基板４の裏面には各電極層５とスルーホ
ール配線（図示せず）を通じて導通されている例えば半
田からなる実装用ボール状電極６が配置されている。こ
の実装用ボール状電極６はボール状電極３に比較して、
低い融点を有する成分比の半田が用いられている。Reference numeral 4 denotes a wiring board which is made of an insulating material such as various resins or ceramics, and has a plurality of electrode layers 5 corresponding to the ball electrodes 3 formed on the surface thereof.
On the back surface of the wiring board 4, a mounting ball-shaped electrode 6 made of, for example, solder, which is electrically connected to each electrode layer 5 and through-hole wiring (not shown), is arranged. This mounting ball-shaped electrode 6 is compared with the ball-shaped electrode 3.
A solder having a low melting point and a component ratio is used.
【００２４】半導体チップ２は各ボール状電極３が対応
した各電極層５に接続されることにより、配線基板４の
表面にフリップチップボンディングされている。The semiconductor chip 2 is flip-chip bonded to the surface of the wiring board 4 by connecting each ball-shaped electrode 3 to each corresponding electrode layer 5.
【００２５】配線基板４の表面の周辺に沿ってダム部７
が設けられている。このダム部７は例えばエポキシ樹脂
などの絶縁材料により構成され、高さ寸法はボール状電
極３の厚みを加えた半導体チップ２の厚さ寸法と、ほぼ
等しく設定されている。半導体チップ３の厚さ寸法は約
４００〜６００μｍ、ボール状電極３の厚さ寸法は約８
０〜１５０μｍに設定されている。ボール状電極３の厚
さ寸法は、半導体チップ２のボンディング前後で異なっ
ており、ボンディング後は溶融による変形で多少小さく
なっている。なお、説明を簡単にするために、図２にお
いて、ボール状電極３及び実装用ボール状電極６は、実
際には楕円状に変形しているにもかかわらず、円形状を
維持している例で示している。Along the periphery of the surface of the wiring board 4
Is provided. The dam portion 7 is made of, for example, an insulating material such as an epoxy resin, and has a height dimension substantially equal to the thickness dimension of the semiconductor chip 2 including the thickness of the ball-shaped electrode 3. The thickness of the semiconductor chip 3 is about 400 to 600 μm, and the thickness of the ball electrode 3 is about 8
It is set to 0 to 150 μm. The thickness dimension of the ball-shaped electrode 3 differs before and after bonding of the semiconductor chip 2, and is slightly reduced after bonding due to deformation due to melting. For simplicity, in FIG. 2, the ball-shaped electrode 3 and the mounting ball-shaped electrode 6 maintain a circular shape despite being actually deformed into an elliptical shape. Indicated by.
【００２６】配線基板４のダム部７の内側には樹脂８が
充填されて、半導体チップ２及び電極層５を封止してい
る。この樹脂８としては、例えばエポキシ樹脂、シリコ
ーン樹脂、ポリイミド樹脂、フェノール樹脂などが用い
られる。この樹脂８によって、半導体チップ２の配線基
板４とのボンディング部分が周囲雰囲気から保護されて
いる。ただし、半導体チップ２の裏面は露出されてい
て、放熱性の向上が図られている。なお、図１において
は、実際には電極層５は樹脂８で覆われて見えないが、
発明を理解し易くするために見えるものとして示してい
る。The inside of the dam portion 7 of the wiring board 4 is filled with a resin 8 to seal the semiconductor chip 2 and the electrode layer 5. As the resin 8, for example, an epoxy resin, a silicone resin, a polyimide resin, a phenol resin, or the like is used. The resin 8 protects the bonding portion of the semiconductor chip 2 with the wiring board 4 from the surrounding atmosphere. However, the back surface of the semiconductor chip 2 is exposed to improve heat dissipation. In FIG. 1, the electrode layer 5 is actually covered with the resin 8 and cannot be seen,
It is shown as visible to facilitate understanding of the invention.
【００２７】次に、図３乃至図７を参照して、本実施形
態１による半導体装置の製造方法を工程順に説明する。Next, the method for fabricating the semiconductor device according to the first embodiment will be described with reference to FIGS.
【００２８】まず、図３に示すように、表面の全面にわ
たって例えばＡｌなどからなる複数のパッド電極が形成
され、各パッド電極に例えば半田（Ｐｂ−Ｓｎ合金）か
らなるボール状電極３が接続された半導体チップ２を用
意する。同様にして、表面にボール状電極３に対応した
複数の電極層５が形成されるとともに、この表面の周辺
に沿ってダム部７が設けられた、各種樹脂あるいはセラ
ミックなどの絶縁材料から構成された配線基板４を用意
する。そして、半導体チップ２をフリップチップボンデ
ィングするために、矢印で示すように配線基板４上に位
置決めする。First, as shown in FIG. 3, a plurality of pad electrodes made of, for example, Al are formed over the entire surface, and a ball electrode 3 made of, for example, solder (Pb-Sn alloy) is connected to each pad electrode. A semiconductor chip 2 is prepared. Similarly, a plurality of electrode layers 5 corresponding to the ball-shaped electrodes 3 are formed on the surface, and dam portions 7 are provided along the periphery of the surface. The prepared wiring board 4 is prepared. Then, the semiconductor chip 2 is positioned on the wiring board 4 as shown by an arrow in order to perform flip chip bonding.
【００２９】この場合、配線基板４に設けるダム部７
は、図４に示すように、例えばエポキシ樹脂などの絶縁
材料を用いて予め枠状に成形したものを用いて、接着剤
により配線基板４の所定位置に固着するようにする。こ
のダム部７の高さ寸法は、ボール状電極３の厚みを加え
た半導体チップ２の厚さ寸法とほぼ等しく設定される。In this case, the dam portion 7 provided on the wiring board 4
As shown in FIG. 4, for example, an insulating material such as an epoxy resin or the like is used to form a frame and is fixed to a predetermined position of the wiring board 4 with an adhesive. The height of the dam portion 7 is set substantially equal to the thickness of the semiconductor chip 2 to which the thickness of the ball-shaped electrode 3 is added.
【００３０】次に、図５に示すように、半導体チップ２
を位置決めした配線基板４を、リフロー炉を通過させる
ことにより、所定の温度で熱処理を行う。熱処理温度は
ボール状電極３を構成している半田の成分によって決定
される。これにより、ボール状電極３である半田を溶融
させて、半導体チップ２を配線基板４上にフリップチッ
プボンディングする。実際には、ボール状電極３は楕円
状に変形している。Next, as shown in FIG.
Is passed through a reflow furnace to perform heat treatment at a predetermined temperature. The heat treatment temperature is determined by the components of the solder constituting the ball-shaped electrode 3. Thereby, the solder as the ball-shaped electrode 3 is melted, and the semiconductor chip 2 is flip-chip bonded onto the wiring board 4. Actually, the ball electrode 3 is deformed into an elliptical shape.
【００３１】続いて、図６に示すように、配線基板４の
ダム部７の内側に例えばエポキシ樹脂、シリコーン樹
脂、ポリイミド樹脂、フェノール樹脂などから構成され
た樹脂８を充填して、半導体チップ２及び電極層５を封
止する。樹脂８の充填は、まず液状の樹脂８をダム部７
の内側に流し込み、次に例えば１２０℃〜１５０℃で熱
処理を施すことにより樹脂８を硬化させる。Subsequently, as shown in FIG. 6, the inside of the dam portion 7 of the wiring board 4 is filled with a resin 8 made of, for example, epoxy resin, silicone resin, polyimide resin, phenol resin, etc. And the electrode layer 5 is sealed. To fill the resin 8, first, the liquid resin 8
, And then heat-treated at, for example, 120 ° C. to 150 ° C. to cure the resin 8.
【００３２】このように配線基板４の表面の周辺に沿っ
てダム部７を設けて、ダム部７の内側に液状の樹脂８を
流し込むことにより、樹脂８は確実にダム部７の内側の
領域にのみ充填されるので、半導体チップ２のボンディ
ング部分となる表面に細かいピッチで多くのボール状電
極が配置されていても、各ボール状電極の隙間を通じて
樹脂が均一に流し込まれるようになるため、樹脂充填が
容易になる。また、配線基板４の表面の電極層５も完全
に樹脂８で覆われるので、汚染、腐食などを回避できる
ため、劣化しなくなる。As described above, the dam portion 7 is provided along the periphery of the surface of the wiring board 4, and the liquid resin 8 is poured into the inside of the dam portion 7. Therefore, even if many ball-shaped electrodes are arranged at a fine pitch on the surface serving as the bonding portion of the semiconductor chip 2, the resin is uniformly poured through the gaps between the ball-shaped electrodes. Resin filling becomes easy. In addition, since the electrode layer 5 on the surface of the wiring board 4 is completely covered with the resin 8, contamination, corrosion, and the like can be avoided, so that the electrode layer 5 does not deteriorate.
【００３３】次に、図７に示すように、表面の各電極層
５と導通する裏面の所定位置に実装用ボール状電極６を
位置決めした配線基板４を、リフロー炉を通過させるこ
とにより、所定の温度で熱処理を行う。熱処理温度はボ
ール状電極３を構成している半田の成分によって決定さ
れる。ただし、半導体チップ２のボール状電極３を溶融
させた熱処理温度よりは低い温度に設定して行う。各ボ
ール状電極３、６は予めこの条件に適合するような成分
比の半田が用いられている。これにより、実装用ボール
状電極６である半田を溶融させて、実装用ボール状電極
６を配線基板４の裏面に配置する。実際には、実装用ボ
ール状電極６は楕円状に変形している。Next, as shown in FIG. 7, the wiring substrate 4 having the mounting ball-shaped electrodes 6 positioned at predetermined positions on the back surface electrically connected to the respective electrode layers 5 on the front surface is passed through a reflow furnace so as to have predetermined positions. Heat treatment at a temperature of The heat treatment temperature is determined by the components of the solder constituting the ball-shaped electrode 3. However, the temperature is set lower than the heat treatment temperature at which the ball-shaped electrode 3 of the semiconductor chip 2 is melted. Each of the ball-shaped electrodes 3 and 6 is made of a solder having a component ratio that satisfies this condition in advance. Thus, the solder as the mounting ball electrode 6 is melted, and the mounting ball electrode 6 is arranged on the back surface of the wiring board 4. Actually, the mounting ball electrode 6 is deformed into an elliptical shape.
【００３４】このような各工程を経ることにより、図１
及び図２に示したような半導体装置１が製造される。By going through each of these steps, FIG.
And the semiconductor device 1 as shown in FIG. 2 is manufactured.
【００３５】以上のような実施形態１による半導体装置
１によれば次のような効果が得られる。According to the semiconductor device 1 of the first embodiment, the following effects can be obtained.
【００３６】半導体チップ２がフリップチップボンディ
ングされる、電極層５が形成された配線基板４の表面の
周辺に沿ってダム部７が設けられ、このダム部７の内側
に前記半導体チップ２及び電極層５を封止するように樹
脂８が充填されるので、半導体チップを配線基板にフリ
ップチップ方式でボンディングしたＢＧＡ構造のパッケ
ージにおいて、樹脂充填を容易にするとともに、配線基
板の電極層の劣化を防止することが可能となる。A dam portion 7 is provided along the periphery of the surface of the wiring substrate 4 on which the electrode layer 5 is formed, on which the semiconductor chip 2 is flip-chip bonded, and the semiconductor chip 2 and the electrode are provided inside the dam portion 7. Since the resin 8 is filled so as to seal the layer 5, in a BGA structure package in which a semiconductor chip is bonded to a wiring board by a flip chip method, resin filling is facilitated and deterioration of an electrode layer of the wiring board is prevented. This can be prevented.
【００３７】（実施形態２）図８は本発明の実施形態２
による半導体装置を示す平面図で、図９は図８のＡ−Ａ
断面図である。(Embodiment 2) FIG. 8 shows Embodiment 2 of the present invention.
FIG. 9 is a plan view showing a semiconductor device according to the first embodiment.
It is sectional drawing.
【００３８】本発明の実施形態２による半導体装置１
は、実施形態１による半導体装置１に比較して、半導体
チップ２の裏面に放熱板９を取り付けた構造に特徴を有
している。この放熱板９は、Ａｌ系金属あるいはＣｕ系
金属のように熱伝導性に優れた金属材料から構成され、
厚さ約１．０〜３．０ｍｍ程度で、半導体チップ２を十
分に覆う面積のものが用いられる。Semiconductor device 1 according to Embodiment 2 of the present invention
Is characterized by a structure in which a heat sink 9 is attached to the back surface of the semiconductor chip 2 as compared with the semiconductor device 1 according to the first embodiment. The radiator plate 9 is made of a metal material having excellent thermal conductivity, such as an Al-based metal or a Cu-based metal,
A semiconductor having a thickness of about 1.0 to 3.0 mm and an area sufficiently covering the semiconductor chip 2 is used.
【００３９】このように、特に半導体チップ２の裏面に
放熱板９を取り付ける場合、樹脂８の硬化を利用するこ
とにより、容易に取り付けることができる。As described above, especially when the heat radiating plate 9 is attached to the back surface of the semiconductor chip 2, it can be easily attached by utilizing the curing of the resin 8.
【００４０】次に、図１０乃至図１２を参照して、本実
施形態２による半導体装置の製造方法の主要な工程を順
に説明する。Next, the main steps of the method for fabricating the semiconductor device according to the second embodiment will be described in order with reference to FIGS.
【００４１】まず、図１０に示すように、表面の全面に
わたって例えばＡｌなどからなる複数のパッド電極が形
成され、各パッド電極に例えば半田からなるボール状電
極３が接続された半導体チップ２、及び表面にボール状
電極３に対応した複数の電極層５が形成されるととも
に、この表面の周辺に沿ってダム部７が設けられた、各
種樹脂あるいはセラミックなどの絶縁材料から構成され
た配線基板４を用意する。そして、半導体チップ２を位
置決めした配線基板４をリフロー炉を通過させることに
より、半導体チップ２を配線基板４上にフリップチップ
ボンディングする。First, as shown in FIG. 10, a semiconductor chip 2 in which a plurality of pad electrodes made of, for example, Al is formed over the entire surface, and a ball-shaped electrode 3 made of, for example, solder is connected to each pad electrode. A plurality of electrode layers 5 corresponding to the ball-shaped electrodes 3 are formed on the surface, and a dam portion 7 is provided along the periphery of the surface, and a wiring board 4 made of an insulating material such as various resins or ceramics is provided. Prepare Then, the semiconductor chip 2 is flip-chip bonded onto the wiring board 4 by passing the wiring board 4 on which the semiconductor chip 2 is positioned through a reflow furnace.
【００４２】この場合、配線基板４に設けるダム部７の
高さ寸法は、実施形態１におけるダム部７よりも、大き
く設けるようにする。すなわち、ダム部７の高さ寸法
は、ボール状電極３の厚みを加えた半導体チップ２の厚
さ寸法よりも大きく設定されている。In this case, the height of the dam 7 provided on the wiring board 4 is larger than that of the dam 7 in the first embodiment. That is, the height of the dam portion 7 is set to be larger than the thickness of the semiconductor chip 2 in which the thickness of the ball-shaped electrode 3 is added.
【００４３】次に、図１１に示すように、配線基板４の
ダム部７の内側に例えばエポキシ樹脂、シリコーン樹
脂、ポリイミド樹脂、フェノール樹脂などから構成され
た液状の樹脂８を流し込む。流し込む樹脂８の量は、実
施形態１の場合に比べて多く用いるようにする。これに
より、一部の樹脂８が半導体チップ２の周囲の上方に盛
り上がるようにする。そして、流し込んだ樹脂８の硬化
処理は未だ施さないで、樹脂８を液状状態に維持してお
く。Next, as shown in FIG. 11, a liquid resin 8 made of, for example, epoxy resin, silicone resin, polyimide resin, phenol resin, or the like is poured into the inside of the dam portion 7 of the wiring board 4. The amount of the resin 8 to be poured is larger than that in the first embodiment. As a result, a portion of the resin 8 rises above the periphery of the semiconductor chip 2. Then, the hardening treatment of the poured resin 8 is not performed yet, and the resin 8 is maintained in a liquid state.
【００４４】続いて、図１２に示すように、半導体チッ
プ２の裏面に、必要に応じてシリコーン樹脂のような熱
伝導性に優れた接着剤を介して、例えばＡｌ系金属ある
いはＣｕ系金属のように熱伝導性に優れた金属材料から
構成された、厚さ約１．０〜３．０ｍｍ程度で、半導体
チップ２を十分に覆う面積の放熱板９を取り付ける。Subsequently, as shown in FIG. 12, an Al-based metal or a Cu-based metal, for example, of an Al-based metal or Cu-based metal A heat radiating plate 9 having a thickness of about 1.0 to 3.0 mm and having a sufficient area for covering the semiconductor chip 2 is attached.
【００４５】次に、例えば１２０℃〜１５０℃で熱処理
を施すことにより樹脂８を硬化させる。この硬化のとき
放熱板９も同時に固定されるので、放熱板９は半導体チ
ップ２の裏面に容易に取り付けられることになる。続い
て、実施形態１と同様にして、配線基板４の裏面に実装
用ボール状電極６を配置することによって、図８及び図
９に示したような半導体装置１が製造される。Next, the resin 8 is cured by performing a heat treatment at, for example, 120 ° C. to 150 ° C. At this time, the heat radiating plate 9 is also fixed at the same time, so that the heat radiating plate 9 can be easily attached to the back surface of the semiconductor chip 2. Subsequently, the semiconductor device 1 as shown in FIGS. 8 and 9 is manufactured by arranging the mounting ball electrodes 6 on the back surface of the wiring board 4 in the same manner as in the first embodiment.
【００４６】以上のような実施形態２による半導体装置
１によれば、電極層５が形成された配線基板４の表面の
周辺に沿ってダム部７が設けられ、このダム部７の内側
に前記半導体チップ２及び電極層５を封止するように樹
脂８が充填されるので、実施形態１と同様な効果が得ら
れる他に、樹脂８の硬化を利用することにより、半導体
チップ２の裏面に放熱板９を容易に取り付けることがで
きるという効果が得られる。According to the semiconductor device 1 of the second embodiment as described above, the dam portion 7 is provided along the periphery of the surface of the wiring board 4 on which the electrode layer 5 is formed, and the dam portion 7 is provided inside the dam portion 7. Since the resin 8 is filled so as to seal the semiconductor chip 2 and the electrode layer 5, the same effect as that of the first embodiment can be obtained. The effect that the heat sink 9 can be easily attached is obtained.
【００４７】以上、本発明者によってなされた発明を、
前記実施形態に基づき具体的に説明したが、本発明は、
前記実施形態に限定されるものではなく、その要旨を逸
脱しない範囲において種々変更可能であることは勿論で
ある。As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.
【００４８】例えば、前記実施形態ではダム部を樹脂の
ような絶縁材料で構成する例で説明したが、これに限ら
ずＡｌ、半田などで代表される金属材料を用いることも
可能である。For example, in the above-described embodiment, an example has been described in which the dam portion is made of an insulating material such as a resin. However, the present invention is not limited to this, and a metal material represented by Al, solder, or the like can be used.
【００４９】また、ダム部は予め枠状に成形したものを
用いる例で説明したが、これに限らず、配線基板の表面
の所定位置に直接に樹脂などを枠状に塗布するようにす
ることも可能である。Also, the example in which the dam portion is formed in a frame shape in advance has been described. However, the present invention is not limited to this. Is also possible.
【００５０】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野であるＬＳＩ
に適用した場合について説明したが、それに限定される
ものではない。本発明は、少なくとも周囲雰囲気から保
護するために主要部を樹脂封止することを条件とする電
子部品には適用できる。In the above description, the invention made mainly by the present inventor has been described in the field of application of LSI
Has been described, but the present invention is not limited to this. INDUSTRIAL APPLICABILITY The present invention is applicable to an electronic component provided that at least a main part is sealed with a resin in order to protect it from an ambient atmosphere.
【００５１】[0051]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記の通りである。The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００５２】半導体チップがフリップチップボンディン
グされる、電極層が形成された配線基板の表面の周辺に
沿ってダム部が設けられ、このダム部の内側に前記半導
体チップ及び電極層を封止するように樹脂が充填される
ので、半導体チップを配線基板にフリップチップ方式で
ボンディングしたＢＧＡ構造のパッケージにおいて、樹
脂充填を容易にするとともに、配線基板の電極層の劣化
を防止することが可能となる。A dam portion is provided along the periphery of the surface of the wiring substrate on which the electrode layer is formed, on which the semiconductor chip is flip-chip bonded, and the semiconductor chip and the electrode layer are sealed inside the dam portion. Is filled with resin, so that in a package having a BGA structure in which a semiconductor chip is bonded to a wiring board by a flip-chip method, it is possible to easily fill the resin and prevent deterioration of the electrode layer of the wiring board.
【図１】本発明の実施形態１による半導体装置を示す平
面図である。FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
【図２】図１のＡ−Ａ断面図である。FIG. 2 is a sectional view taken along line AA of FIG.
【図３】本発明の実施形態１による半導体装置の製造方
法の一工程を示す断面図である。FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図４】本発明の実施形態１による半導体装置の製造方
法に用いられるダム部の一例を示す斜視図である。FIG. 4 is a perspective view showing an example of a dam portion used in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
【図５】本発明の実施形態１による半導体装置の製造方
法の他の工程を示す断面図である。FIG. 5 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図６】本発明の実施形態１による半導体装置の製造方
法のその他の工程を示す断面図である。FIG. 6 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図７】本発明の実施形態１による半導体装置の製造方
法のその他の工程を示す断面図である。FIG. 7 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図８】本発明の実施形態２による半導体装置を示す平
面図である。FIG. 8 is a plan view showing a semiconductor device according to a second embodiment of the present invention.
【図９】図８のＡ−Ａ断面図である。FIG. 9 is a sectional view taken along line AA of FIG. 8;
【図１０】本発明の実施形態２による半導体装置の製造
方法の一工程を示す断面図である。FIG. 10 is a cross-sectional view showing a step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
【図１１】本発明の実施形態２による半導体装置の製造
方法の他の工程を示す断面図である。FIG. 11 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
【図１２】本発明の実施形態２による半導体装置の製造
方法のその他の工程を示す断面図である。FIG. 12 is a sectional view illustrating another step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
１…半導体装置（ＬＳＩ）、２…半導体チップ、３…ボ
ール状電極、４…配線基板、５…電極層、６…実装用ボ
ール状電極、７…ダム部、８…樹脂、９…放熱板。DESCRIPTION OF SYMBOLS 1 ... Semiconductor device (LSI), 2 ... Semiconductor chip, 3 ... Ball electrode, 4 ... Wiring board, 5 ... Electrode layer, 6 ... Ball electrode for mounting, 7 ... Dam part, 8 ... Resin, 9 ... Heat sink .
───────────────────────────────────────────────────── フロントページの続き (72)発明者 宝蔵寺 裕之 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hiroyuki Houzoji 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd.
Claims (6)
半導体チップが、前記ボール状電極に対応した複数の電
極層が表面に形成されている配線基板上にフリップチッ
プボンディングされる半導体装置であって、前記電極層
が形成されている配線基板の表面の周辺に沿ってダム部
が設けられ、このダム部の内側に前記半導体チップ及び
電極層を封止するように樹脂が充填されたことを特徴と
する半導体装置。1. A semiconductor device in which a semiconductor chip having a plurality of ball-shaped electrodes connected to a surface thereof is flip-chip bonded to a wiring board having a plurality of electrode layers corresponding to the ball-shaped electrodes formed on the surface. A dam portion is provided along the periphery of the surface of the wiring board on which the electrode layer is formed, and a resin is filled inside the dam portion so as to seal the semiconductor chip and the electrode layer. A semiconductor device characterized by the above-mentioned.
電極の厚みを加えた半導体チップの厚さ寸法よりも大き
く設定されたことを特徴とする請求項１に記載の半導体
装置。2. The semiconductor device according to claim 1, wherein a height dimension of the dam portion is set to be larger than a thickness dimension of the semiconductor chip including a thickness of the ball-shaped electrode.
付け、少なくともこの放熱板の側面部まで樹脂が充填さ
れたことを特徴とする請求項２に記載の半導体装置。3. The semiconductor device according to claim 2, wherein a heat sink is attached to the back surface of the semiconductor chip, and at least a resin is filled up to a side surface of the heat sink.
する請求項１乃至３のいずれか１項に記載の半導体装
置。4. The semiconductor device according to claim 1, wherein the dam portion is made of a resin.
半導体チップを用意する工程と、表面に前記ボール状電
極に対応した複数の電極層が表面に形成されるととも
に、この表面の周辺に沿ってダム部が設けられた配線基
板を用意する工程と、前記半導体チップを各ボール状電
極が対応する前記電極層に接続されるように前記配線基
板の表面にフリップチップボンディングする工程と、前
記ダム部の内側に前記半導体チップ及び電極層が封止さ
れるように樹脂を充填する工程とを含むことを特徴とす
る半導体装置の製造方法。5. A step of preparing a semiconductor chip having a plurality of ball-shaped electrodes connected to a surface thereof, and forming a plurality of electrode layers corresponding to the ball-shaped electrodes on the surface and forming a plurality of electrode layers on the periphery of the surface. Preparing a wiring board provided with a dam portion along, and flip-chip bonding the semiconductor chip to the surface of the wiring board so that each ball-shaped electrode is connected to the corresponding electrode layer; Filling the inside of the dam portion with a resin so that the semiconductor chip and the electrode layer are sealed.
極の厚みを加えた半導体チップの厚さ寸法よりも大きく
設定し、前記樹脂を充填した後に、前記半導体チップの
裏面に樹脂の硬化を利用して放熱板を取り付ける工程を
加えることを特徴とする請求項５に記載の半導体装置の
製造方法。6. The height of the dam portion is set to be larger than the thickness of the semiconductor chip to which the thickness of the ball-shaped electrode is added, and after the resin is filled, the resin is cured on the back surface of the semiconductor chip. 6. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of attaching a heat sink using the method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8205133A JPH1050770A (en) | 1996-08-05 | 1996-08-05 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8205133A JPH1050770A (en) | 1996-08-05 | 1996-08-05 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1050770A true JPH1050770A (en) | 1998-02-20 |
Family
ID=16501981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8205133A Pending JPH1050770A (en) | 1996-08-05 | 1996-08-05 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1050770A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002026250A (en) * | 2000-07-12 | 2002-01-25 | Denso Corp | Manufacturing method of laminated circuit module |
| US6723627B1 (en) | 1999-10-08 | 2004-04-20 | Nec Corporation | Method for manufacturing semiconductor devices |
| JP2005303021A (en) * | 2004-04-13 | 2005-10-27 | Sony Corp | Wiring substrate, semiconductor device and manufacturing method thereof |
| KR100564542B1 (en) * | 1999-02-01 | 2006-03-28 | 삼성전자주식회사 | Chip scale package &method for fabrication thereof |
| US7115444B2 (en) | 2003-02-21 | 2006-10-03 | Fujitsu Limited | Semiconductor device with improved heat dissipation, and a method of making semiconductor device |
| KR100691443B1 (en) | 2005-11-16 | 2007-03-09 | 삼성전기주식회사 | Flip chip package and fabrication method of the same |
| JP2007184400A (en) * | 2006-01-06 | 2007-07-19 | Opnext Japan Inc | Optical transmission module and semiconductor device |
| CN100345267C (en) * | 2003-11-20 | 2007-10-24 | 台湾积体电路制造股份有限公司 | Integrated circuit chip encapsulation and encapsulation method therefor |
| US7304389B2 (en) | 2003-01-30 | 2007-12-04 | Fujitsu Limited | Semiconductor device and supporting plate |
-
1996
- 1996-08-05 JP JP8205133A patent/JPH1050770A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100564542B1 (en) * | 1999-02-01 | 2006-03-28 | 삼성전자주식회사 | Chip scale package &method for fabrication thereof |
| US6723627B1 (en) | 1999-10-08 | 2004-04-20 | Nec Corporation | Method for manufacturing semiconductor devices |
| JP2002026250A (en) * | 2000-07-12 | 2002-01-25 | Denso Corp | Manufacturing method of laminated circuit module |
| US7304389B2 (en) | 2003-01-30 | 2007-12-04 | Fujitsu Limited | Semiconductor device and supporting plate |
| US7115444B2 (en) | 2003-02-21 | 2006-10-03 | Fujitsu Limited | Semiconductor device with improved heat dissipation, and a method of making semiconductor device |
| US7199467B2 (en) | 2003-02-21 | 2007-04-03 | Fujitsu Limited | Semiconductor device with improved heat dissipation, and a method of making semiconductor device |
| US7381592B2 (en) | 2003-02-21 | 2008-06-03 | Fujitsu Limited | Method of making a semiconductor device with improved heat dissipation |
| CN100345267C (en) * | 2003-11-20 | 2007-10-24 | 台湾积体电路制造股份有限公司 | Integrated circuit chip encapsulation and encapsulation method therefor |
| JP2005303021A (en) * | 2004-04-13 | 2005-10-27 | Sony Corp | Wiring substrate, semiconductor device and manufacturing method thereof |
| JP4525148B2 (en) * | 2004-04-13 | 2010-08-18 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
| KR100691443B1 (en) | 2005-11-16 | 2007-03-09 | 삼성전기주식회사 | Flip chip package and fabrication method of the same |
| JP2007184400A (en) * | 2006-01-06 | 2007-07-19 | Opnext Japan Inc | Optical transmission module and semiconductor device |
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