JP2000232186A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JP2000232186A JP2000232186A JP3140399A JP3140399A JP2000232186A JP 2000232186 A JP2000232186 A JP 2000232186A JP 3140399 A JP3140399 A JP 3140399A JP 3140399 A JP3140399 A JP 3140399A JP 2000232186 A JP2000232186 A JP 2000232186A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- opening
- semiconductor chip
- semiconductor device
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、放熱材を有する半
導体装置に係り、特に基板の一側面に複数の端子部が平
面的に配設してあるエリアアレイ型半導体装置およびそ
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a heat dissipating material, and more particularly to an area array type semiconductor device having a plurality of terminals disposed on one side of a substrate in a plane, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】近年、半導体素子の高密度化、高機能化
に伴って、半導体装置（半導体パッケージ）の端子数が
著しく増大している。このため、近年は、半導体装置で
ある半導体パッケージの端子部である球状半田をパッケ
ージの下面にマトリックス状に配列したＢＧＡ（Ｂａｌ
ｌ Ｇｒｉｄ Ａｒｒａｙ）や、端子部をパッケージの
下面に配置し、かつパッケージの大きさが半導体チップ
の大きさとほぼ同じ程度のいわゆるＣＳＰ（Ｃｈｉｐ
Ｓｉｚｅ Ｐａｃｋａｇｅ）などのエリアアレイ型パッ
ケージが用いられるようになっている。そして、エリア
アレイ型半導体装置においては、例えば液晶駆動用など
の発熱量が大きい場合、特開平８−９７３１５号公報に
示されているように、図７のようにして半導体チップか
ら生ずる熱を外部に放散するようにしていた。2. Description of the Related Art In recent years, the number of terminals of a semiconductor device (semiconductor package) has been remarkably increased with the increase in density and function of semiconductor elements. For this reason, in recent years, a BGA (Bal Bal) in which spherical solders, which are terminal portions of a semiconductor package as a semiconductor device, are arranged in a matrix on the lower surface of the package.
l Grid Array or a so-called CSP (Chip) in which a terminal portion is arranged on the lower surface of the package and the size of the package is almost the same as the size of the semiconductor chip.
An area array type package such as Size Package has been used. In an area array type semiconductor device, when a large amount of heat is generated for driving a liquid crystal, for example, as shown in Japanese Patent Application Laid-Open No. 8-97315, heat generated from a semiconductor chip is externally supplied as shown in FIG. Was to be dissipated.
【０００３】図７において、半導体装置１０は、半導体
チップ１２を搭載する基板１４の中央部に基板１４を貫
通した開口１６を形成し、この開口１６内に半導体チッ
プ１２を配置するようになっている。そして、基板１４
の一側面には、開口１６の周囲に端子部となる多数の半
田ボール１８がマトリックス状に配置してあるととも
に、半田ボール１８と接続した配線パターン（図示せ
ず）が設けてあって、この配線パターンのランド部に半
導体チップ１２の図示しないバンプがワイヤ２０によっ
て接続してある。また、基板１４の他側面には、開口１
６を覆って放熱板２２が固着してあり、この放熱板２２
に半導体チップ１２の背面（非能動面）が固定されてい
る。そして、基板１４にワイヤ２０によって接続された
半導体チップ１２は、能動面２４側をワイヤ２０ととも
に封止樹脂２６によって覆ってある。In FIG. 7, an opening 16 penetrating the substrate 14 is formed in the center of a substrate 14 on which the semiconductor chip 12 is mounted, and the semiconductor chip 12 is arranged in the opening 16. I have. And the substrate 14
On one side surface, a large number of solder balls 18 serving as terminals are arranged in a matrix around the opening 16 and a wiring pattern (not shown) connected to the solder balls 18 is provided. A bump (not shown) of the semiconductor chip 12 is connected to a land portion of the wiring pattern by a wire 20. The other side of the substrate 14 has an opening 1
6, a heat sink 22 is fixedly attached.
The back surface (non-active surface) of the semiconductor chip 12 is fixed to the semiconductor chip 12. The semiconductor chip 12 connected to the substrate 14 by the wires 20 has the active surface 24 side and the wires 20 covered by a sealing resin 26.
【０００４】[0004]
【発明が解決しようとする課題】このように構成した従
来の半導体装置１０は、基板１４に半導体チップ１２よ
り大きな開口１６を形成してその内部に半導体チップ１
２を配置するようになっており、半導体装置１０の外形
寸法が大きくなってＣＳＰの実現を困難としている。し
かも、基板１４の一側面に半田ボール１８とワイヤを接
続するためのランドおよび配線パターンが形成してある
ため、基板１４の寸法を小さくすることが極めて困難で
ある。In the conventional semiconductor device 10 configured as described above, an opening 16 larger than the semiconductor chip 12 is formed in the substrate 14, and the semiconductor chip 1 is formed therein.
2, and the external dimensions of the semiconductor device 10 become large, making it difficult to realize a CSP. In addition, since lands and wiring patterns for connecting the solder balls 18 and wires are formed on one side surface of the substrate 14, it is extremely difficult to reduce the dimensions of the substrate 14.
【０００５】本発明は、前記従来技術の欠点を解消する
ためになされたもので、発熱量の大きな半導体チップの
放熱を効率よく行なえ、パッケージサイズを小さくする
ことを目的としている。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned disadvantages of the prior art, and has as its object to efficiently radiate heat from a semiconductor chip having a large amount of heat and to reduce the package size.
【０００６】[0006]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明に係る半導体装置は、一側面に複数の端子
部が配設してある基板に貫通して形成した開口と、基板
の他側面において前記開口の周辺部に周縁部を載置した
半導体チップと、前記開口内に設けた放熱材とを有する
ことを特徴としている。In order to achieve the above object, a semiconductor device according to the present invention comprises: an opening formed through a substrate having a plurality of terminals on one side; The semiconductor device according to claim 1, further comprising a semiconductor chip having a peripheral portion mounted on a peripheral portion of the opening on the other side surface, and a heat dissipating material provided in the opening.
【０００７】このように構成した本発明は、基板に形成
した開口が半導体チップの大きさより小さく形成してあ
るとともに、半導体チップを基板の端子部を設けた一側
と反対側に搭載しているため、基板の一側に配線パター
ンや半導体チップと接続するためのランドを設ける必要
がなく、基板の寸法を小さくすることができてパッケー
ジを小さくすることが可能となる。しかも、開口中に放
熱材を配置してあるため、半導体チップから生ずる熱を
効率よく放散することができる。また、従来、基板の端
子部を形成した一側面と反対側の他側面に半導体チップ
を搭載した半導体装置においては、基板の中央部に存在
する端子部は電気的に接続されない場合もあり、何ら利
用されていないため、開口を基板の中央部に形成して放
熱材を設けることにより、無駄なスペースの有効利用を
図ることができる。According to the present invention, the opening formed in the substrate is formed smaller than the size of the semiconductor chip, and the semiconductor chip is mounted on one side of the substrate opposite to the side on which the terminal portion is provided. Therefore, it is not necessary to provide a land for connecting to a wiring pattern or a semiconductor chip on one side of the substrate, so that the size of the substrate can be reduced and the package can be reduced. Moreover, since the heat dissipating material is arranged in the opening, heat generated from the semiconductor chip can be efficiently dissipated. Conventionally, in a semiconductor device having a semiconductor chip mounted on the other side opposite to one side on which a terminal portion of a substrate is formed, a terminal portion present at a central portion of the substrate may not be electrically connected in some cases. Since it is not used, by providing an opening in the center of the substrate and providing a heat dissipating material, it is possible to effectively use a wasteful space.
【０００８】放熱材は、半導体チップを覆って設けた封
止樹脂より熱伝導率の大きい高放熱性樹脂であってもよ
く、金属であってもよい。特に、放熱材として金属を用
いると、金属は一般に大きな熱伝導率を有しているた
め、放熱効果を大きくすることができる。The heat dissipating material may be a high heat dissipating resin having a higher thermal conductivity than the sealing resin provided over the semiconductor chip, or may be a metal. In particular, when a metal is used as the heat radiating material, the metal generally has a large thermal conductivity, so that the heat radiating effect can be increased.
【０００９】また、放熱材は、開口内に位置する充填部
と、基板の一側面側において開口を覆うフランジ部とか
らなる断面凸状に形成してよい。このように凸状に形成
してフランジ部によって開口の基板一側面側を覆うよう
にすると、大気中の水分が開口に浸入するのを阻止する
ことができ、半導体装置の信頼性を高めることができ
る。また、放熱材を凸状に形成した場合、開口内に配置
する充填部を高放熱性樹脂によって形成し、フランジ部
を金属板によって形成することができる。The heat dissipating material may be formed in a convex shape in cross section comprising a filling portion located in the opening and a flange portion covering the opening on one side surface of the substrate. When such a convex shape is formed so that the flange portion covers one side surface of the opening, the moisture in the air can be prevented from entering the opening, and the reliability of the semiconductor device can be improved. it can. When the heat radiating material is formed in a convex shape, the filling portion arranged in the opening can be formed of a high heat radiating resin, and the flange portion can be formed of a metal plate.
【００１０】なお、半導体チップは、能動面が基板と反
対側とされ、ワイヤを介して基板の他側面に設けたパタ
ーンと電気的に接続するものであってもよく、能動面が
基板側とされ、バンプを介して基板の他側面に設けたパ
ターンと電気的に接続した、いわゆるフェースダウン型
のものであってもよい。The semiconductor chip may have an active surface opposite to the substrate and be electrically connected to a pattern provided on the other side of the substrate via wires. A so-called face-down type, which is electrically connected to a pattern provided on the other side of the substrate via bumps, may be used.
【００１１】そして、本発明に係る半導体装置の製造方
法の第１は、基板に形成した開口に挿入する充填部を有
する断面凸状の放熱板を、複数の端子が配設してある基
板の一側面に固着する放熱板取付け工程と、前記基板の
他側面に前記開口を覆って半導体チップを固着するチッ
プ取付け工程と、このチップ取付け工程と前記放熱板取
付け工程とを任意の順序で行なったのち、前記基板の他
側面に形成したパターンと前記半導体チップとをワイヤ
によって電気的に接続するワイヤボンディング工程と、
ワイヤボンディングした前記半導体チップを覆って樹脂
を塗布する封止工程とを有することを特徴としている。
このように構成した本発明は、放熱材として金属を用い
た半導体装置の製造に好適である。The first aspect of the method of manufacturing a semiconductor device according to the present invention is to provide a method of manufacturing a semiconductor device, in which a heat sink having a convex cross section having a filling portion inserted into an opening formed in the substrate is provided on a substrate having a plurality of terminals. A step of attaching a heat sink to one side, a step of attaching a semiconductor chip to the other side of the substrate to cover the opening, and a step of attaching the chip and the step of attaching the heat sink were performed in any order. Thereafter, a wire bonding step of electrically connecting the pattern formed on the other side surface of the substrate and the semiconductor chip by a wire,
A sealing step of applying a resin so as to cover the wire-bonded semiconductor chip.
The present invention thus configured is suitable for manufacturing a semiconductor device using a metal as a heat radiating material.
【００１２】放熱材は、半導体チップと基板のパターン
とをワイヤによって接続したのちに基板に固着してもよ
いが、ワイヤボンディングを安定して行なうためには、
ワイヤボンディングの前に放熱材を基板に取り付けるこ
とが望ましい。The heat dissipating material may be fixed to the substrate after connecting the semiconductor chip and the pattern of the substrate by wires, but in order to stably perform wire bonding,
It is desirable to attach a heat radiator to the substrate before wire bonding.
【００１３】また、本発明の第２に係る半導体装置の製
造方法は、基板の複数の端子部が配設してある面と反対
側の面に、基板を貫通して形成した開口を覆って半導体
チップを搭載するチップ搭載工程と、前記開口に放熱用
樹脂を充填する放熱樹脂充填工程と、前記半導体チップ
を覆って封止樹脂を塗布する封止工程とを有することを
特徴としている。この発明の製造方法は、放熱材として
樹脂を用いた半導体装置の製造に適している。According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising covering an opening formed through a substrate on a surface of the substrate opposite to a surface on which a plurality of terminals are provided. The method includes a chip mounting step of mounting a semiconductor chip, a heat radiation resin filling step of filling the opening with a heat radiation resin, and a sealing step of applying a sealing resin to cover the semiconductor chip. The manufacturing method of the present invention is suitable for manufacturing a semiconductor device using a resin as a heat radiating material.
【００１４】[0014]
【発明の実施の形態】本発明に係る半導体装置およびそ
の製造方法の好ましい実施の形態を、添付図面に従っ
て、詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.
【００１５】図１は、本発明の第１実施形態に係る半導
体装置の説明図である。図１（１）において、半導体装
置３０は、半導体チップ３２の搭載領域となっている基
板３４の中央部に、基板３４を貫通した開口３６を有し
ている。この開口３６は、半導体チップ３２の大きさよ
り小さく形成してある。基板３４は、ガラス繊維とエポ
キシ樹脂とを積層して形成したものや、セラミックまた
はポリイミドテープなどの絶縁性の基材から形成してあ
って、一側面の開口３６の周囲に端子部となる複数の半
田ボール１８がマトリックス状に配設してある。FIG. 1 is an explanatory diagram of a semiconductor device according to a first embodiment of the present invention. In FIG. 1A, the semiconductor device 30 has an opening 36 penetrating the substrate 34 at the center of the substrate 34 which is a mounting area for the semiconductor chip 32. The opening 36 is formed smaller than the size of the semiconductor chip 32. The substrate 34 is formed by laminating glass fiber and epoxy resin, or is formed from an insulating base material such as ceramic or polyimide tape. Are arranged in a matrix.
【００１６】一方、基板３４は、半田ボール１８を設け
た一側面と反対側の他側面に図示しない回路パターンが
形成してあり、この回路パターンと半田ボール１８とが
基板３４に形成した貫通孔３８を介して電気的に接続し
てある。また、基板３４の他側面には、半導体チップ３
２が搭載してある。半導体チップ３２は、周縁部が基板
３４に形成した開口３６の周辺部に載置してあり、図示
しない接着剤によって基板３４に固着してある。そし
て、半導体チップ３２は、図１の上面である能動面に複
数のパッド（図示せず）が設けてあって、このパッドと
基板３４に形成した回路パターンのランド部とがワイヤ
２０によって接続してある。さらに、半導体チップ３２
および基板３４の他側面とワイヤ２０とは、封止樹脂４
０によって覆われ、保護されている。On the other hand, a circuit pattern (not shown) is formed on one side of the substrate 34 opposite to the side on which the solder balls 18 are provided. 38, it is electrically connected. The semiconductor chip 3 is provided on the other side of the substrate 34.
2 is installed. The semiconductor chip 32 is placed around the periphery of the opening 36 formed in the substrate 34 at the periphery thereof, and is fixed to the substrate 34 by an adhesive (not shown). The semiconductor chip 32 has a plurality of pads (not shown) provided on the active surface, which is the upper surface of FIG. 1, and the pads are connected to the lands of the circuit pattern formed on the substrate 34 by wires 20. It is. Further, the semiconductor chip 32
And the other side of the substrate 34 and the wire 20 are connected to the sealing resin 4
Covered by 0 and protected.
【００１７】開口３６の内部には、放熱部材である放熱
板４２が配置してある。放熱板４２は、銅やアルミニウ
ムなどの熱伝導性のよい金属によって凸状に形成してあ
り、開口３６内に位置して半導体チップ３２の非能動面
と接触している充填部４４と、充填部４４より大きく形
成されて基板３４の一側面において開口３６を覆ってい
るフランジ部４６とからなっている。このフランジ部４
６は、高さが半田ボール１８の高さより低くなってい
て、半導体装置３０をマザーボードなどに実装する際の
妨げとならないようにしてある。A heat radiating plate 42 as a heat radiating member is disposed inside the opening 36. The heat radiating plate 42 is formed in a convex shape with a metal having good thermal conductivity such as copper or aluminum, and is provided in the opening 36 and is in contact with the inactive surface of the semiconductor chip 32. A flange portion 46 is formed larger than the portion 44 and covers the opening 36 on one side surface of the substrate 34. This flange part 4
6 has a height lower than the height of the solder ball 18 so as not to hinder the mounting of the semiconductor device 30 on a motherboard or the like.
【００１８】開口３６の大きさは、半田ボール１８の配
列ピッチによって異なり、実施形態の場合、最大で半田
ボール１８の３列分の寸法にしてある。すなわち、例え
ば図１（２）に示したように、半田ボール１８の配列ピ
ッチｐが０．５ｍｍの場合、開口３６の横寸法ａと縦寸
法ｂとはそれぞれ最大で１.５ｍｍ、ピッチｐが０．８
ｍｍの場合、最大でａ＝２．４ｍｍ、ｂ＝２．４ｍｍで
ある。また、放熱板４２のフランジ部４６の高さは、リ
フロー炉を用いて半導体装置３０をマザーボードに実装
した場合、半田ボールの高さが０．１ｍｍ程度低くなる
ところから、ピッチｐが０．５ｍｍのパッケージの場
合、使用される半田ボール１８の直径が０．３ｍｍであ
るところから、最大で０．１５ｍｍ、ピッチｐが０．８
ｍｍのパッケージの場合、半田ボール１８の直径が０．
５ｍｍであるところから、０．３５ｍｍである。また、
半田ボール１８を設けずに端子部がバンプであるＬＧＡ
（Ｌａｎｄ Ｇｒｉｄ Ａｒｒａｙ）の場合、放熱板４
２のフランジ部の厚さは数１０μｍにする。The size of the openings 36 differs depending on the arrangement pitch of the solder balls 18, and in the case of the embodiment, the size is a maximum of three rows of the solder balls 18. That is, for example, as shown in FIG. 1B, when the arrangement pitch p of the solder balls 18 is 0.5 mm, the horizontal dimension a and the vertical dimension b of the opening 36 are 1.5 mm at the maximum, respectively, and the pitch p is 0.8
In the case of mm, a = 2.4 mm and b = 2.4 mm at the maximum. Also, when the semiconductor device 30 is mounted on a motherboard using a reflow furnace, the height of the flange portion 46 of the heat sink 42 is set to 0.5 mm because the height of the solder balls is reduced by about 0.1 mm. In the case of the package (1), since the diameter of the solder ball 18 used is 0.3 mm, the maximum is 0.15 mm and the pitch p is 0.8.
mm package, the diameter of the solder ball 18 is 0.
From 5 mm, it is 0.35 mm. Also,
LGA in which the terminal portion is a bump without providing the solder ball 18
(Land Grid Array), heat sink 4
The thickness of the flange portion 2 is set to several tens of μm.
【００１９】このように構成した第１実施の形態に係る
半導体装置３０は、開口３６が半導体チップ３２よりも
小さくなっており、しかも半導体チップ３２が基板３４
の半田ボール１８を設けた側と反対側に搭載してあるた
めに基板３４の寸法を小さくすることができ、パッケー
ジの小型化を図ることができる。また、開口３６には、
半導体チップ３２と接触している放熱板４２が配置して
あるため、半導体チップ３２から生ずる熱を効率よく放
散することができる。そして、放熱板４２は、フランジ
部４６が開口３６の寸法より大きく形成してあって、開
口３６を覆っているため、開口内に大気中の水分などが
浸入するのを阻止することができ、半導体装置３０の信
頼性を高めることができる。そして、基板３４の一般に
半田ボール１８を設けた面と反対側の面に半導体チップ
３２を搭載した場合、基板３４の中央部の２列ないし３
列の半田ボール１８は端子と使用されていないため、こ
の部分に開口３６を設けて放熱板４２を配置したことに
より、デッドスペースの有効活用を図ることができる。In the semiconductor device 30 according to the first embodiment thus configured, the opening 36 is smaller than the semiconductor chip 32, and the semiconductor chip 32 is
Since it is mounted on the side opposite to the side on which the solder balls 18 are provided, the size of the substrate 34 can be reduced, and the size of the package can be reduced. Also, in the opening 36,
Since the heat radiating plate 42 in contact with the semiconductor chip 32 is arranged, heat generated from the semiconductor chip 32 can be efficiently dissipated. And since the heat radiation plate 42 has the flange portion 46 formed to be larger than the size of the opening 36 and covers the opening 36, it is possible to prevent moisture or the like in the atmosphere from entering the opening. The reliability of the semiconductor device 30 can be improved. When the semiconductor chips 32 are mounted on the surface of the substrate 34 opposite to the surface on which the solder balls 18 are generally provided, two rows or three at the center of the substrate 34 are provided.
Since the solder balls 18 in the row are not used as terminals, the dead space can be effectively utilized by providing the opening 36 in this portion and disposing the heat radiating plate 42.
【００２０】なお、放熱板４２は、フランジ部４６を設
けずに開口３６内に配置した充填部４４のみによって構
成してもよい。The heat radiating plate 42 may be constituted by only the filling portion 44 disposed in the opening 36 without providing the flange portion 46.
【００２１】図２は、第１実施形態に係る半導体装置３
０を得るための製造方法の概略を示すフローチャートで
ある。まず、図２のステップ５０に示したように、放熱
板取付け工程において、開口３６を有する基板３４に放
熱板４２を固着する。すなわち、基板３４の開口３６に
基板３４の一側面側から凸状放熱板４２の充填部４４を
開口３６に挿入し、放熱板４２のフランジ部４６を開口
３６の周辺部に接着剤を介して貼り付ける。その後、チ
ップ取付け工程において半導体チップ３２を基板３４の
他側面において開口３６を覆うように配置し、半導体チ
ップ３２の非能動面の周縁部を開口３６の周辺部に接着
剤を用いて固着するダイアタッチを行なう（ステップ５
１）。FIG. 2 shows a semiconductor device 3 according to the first embodiment.
5 is a flowchart schematically showing a manufacturing method for obtaining 0. First, as shown in step 50 of FIG. 2, in the heat sink mounting process, the heat sink 42 is fixed to the substrate 34 having the opening 36. That is, the filling portion 44 of the convex radiator plate 42 is inserted into the opening 36 of the substrate 34 from one side surface of the substrate 34, and the flange portion 46 of the radiator plate 42 is attached to the periphery of the opening 36 with an adhesive. paste. After that, in a chip attaching step, the semiconductor chip 32 is arranged so as to cover the opening 36 on the other side surface of the substrate 34, and the periphery of the non-active surface of the semiconductor chip 32 is fixed to the periphery of the opening 36 using an adhesive. Touch (Step 5
1).
【００２２】次に、ステップ５２に示したように、基板
３４の配線パターンのランド部と半導体チップ３２とを
ワイヤ２０によって接続する（ワイヤボンディング工
程）。その後、半導体チップ３２と基板３４の他側面と
に封止樹脂４０を塗布する封止工程を行ない（ステップ
５３）、封止樹脂４０を硬化させる。封止樹脂４０が硬
化したならば、品名やロゴ等を印刷するマーキングを行
なう（ステップ５４）。さらに、ステップ５５に示した
ように、必要に応じて半田ボール１８を搭載して半導体
装置３０を完成させる。Next, as shown in step 52, the lands of the wiring pattern on the substrate 34 and the semiconductor chip 32 are connected by wires 20 (wire bonding step). Thereafter, a sealing step of applying the sealing resin 40 to the semiconductor chip 32 and the other side surface of the substrate 34 is performed (Step 53), and the sealing resin 40 is cured. When the sealing resin 40 is cured, marking for printing a product name, a logo, or the like is performed (step 54). Further, as shown in step 55, the semiconductor device 30 is completed by mounting the solder balls 18 as necessary.
【００２３】なお、前記実施形態においては、放熱板４
２を最初に基板３４に固着する場合について説明した
が、ステップ５１ないしステップ５３の任意の工程の後
に放熱板４２を固着する工程を行なってもよい。しか
し、ワイヤボンディングを安定して行なうために、ステ
ップ５２のワイヤボンディングの前に放熱板４２を基板
３４に取り付けることが望ましい。In the above embodiment, the heat sink 4
Although the case where 2 is first fixed to the substrate 34 has been described, a step of fixing the heat sink 42 may be performed after any of the steps 51 to 53. However, in order to stably perform the wire bonding, it is desirable to attach the heat sink 42 to the substrate 34 before the wire bonding in step 52.
【００２４】図３は、第２実施形態に係る半導体装置の
断面図である。この実施の形態に係る半導体装置５６
は、開口３６の内部に配置した放熱材５８が封止樹脂４
０よりも熱伝導率の大きな高放熱性樹脂（例えば、銀ペ
ーストまたは銀ペーストをまぶしたエポキシ樹脂など）
によって形成してある。そして、放熱材５８は、開口３
６の内部にのみ配置されていて、フランジ部を有してい
ない。他の構成は、第１実施形態と同様である。FIG. 3 is a sectional view of a semiconductor device according to the second embodiment. Semiconductor device 56 according to this embodiment
The heat dissipating material 58 disposed inside the opening 36 is
High heat dissipating resin with thermal conductivity greater than 0 (for example, silver paste or epoxy resin coated with silver paste)
Formed by Then, the heat dissipating material 58
It is arranged only inside 6 and has no flange portion. Other configurations are the same as in the first embodiment.
【００２５】このように構成した第２実施の形態に係る
半導体装置５６においても、第１実施形態の場合とほぼ
同様の効果を得ることができる。なお、破線に示したよ
うに、基板３４の一側面に開口を覆って金属製の放熱板
６０を設けて放熱効果の向上と、開口３６への水分の浸
入とを阻止するようにしてもよい。In the semiconductor device 56 according to the second embodiment configured as described above, substantially the same effects as in the first embodiment can be obtained. As shown by the broken line, a metal heat radiating plate 60 may be provided on one side surface of the substrate 34 so as to cover the opening, thereby improving the heat radiating effect and preventing moisture from entering the opening 36. .
【００２６】図４は、第２実施形態に係る半導体装置５
６の製造方法の概略を示すフローチャートである。ま
ず、図４のステップ６１に示したように、基板３４の他
側面に開口３６を覆って半導体チップ３２の非能動面を
固着し、半導体チップ３２と基板３４とをワイヤ２０に
よって接続するチップ搭載工程を行なう。次に、基板３
４の一側面側から開口３６に高放熱性樹脂を充填する放
熱樹脂充填工程を行い（ステップ６２）、高放熱性樹脂
を硬化させて開口３６内に放熱材５８を形成する。その
後、半導体チップ３２と基板３４の他側面とに封止樹脂
４０を塗布する封止工程を行ない、封止樹脂４０が硬化
したならば、前記と同様にしてマーキング工程（ステッ
プ６４）、半田ボール搭載工程（ステップ６５）を行な
う。なお、ステップ６２の放熱樹脂充填工程をステップ
６３の封止工程のあとに行なってもよい。FIG. 4 shows a semiconductor device 5 according to the second embodiment.
6 is a flowchart illustrating an outline of a manufacturing method of No. 6; First, as shown in step 61 of FIG. 4, a chip mounting for fixing the non-active surface of the semiconductor chip 32 by covering the opening 36 on the other side surface of the substrate 34 and connecting the semiconductor chip 32 and the substrate 34 with the wires 20. Perform the process. Next, the substrate 3
A heat radiation resin filling step of filling the opening 36 with a high heat radiation resin from one side of the side 4 is performed (step 62), and the heat radiation resin 58 is formed in the opening 36 by curing the high heat radiation resin. Thereafter, a sealing step of applying a sealing resin 40 to the semiconductor chip 32 and the other side surface of the substrate 34 is performed. When the sealing resin 40 is cured, a marking step (step 64) is performed in the same manner as described above, A mounting step (step 65) is performed. In addition, the heat radiation resin filling step of step 62 may be performed after the sealing step of step 63.
【００２７】図５は、３実施の形態に係る半導体装置の
断面図である。この実施の形態に係る半導体装置６６
は、基板３４の半導体チップ３２の搭載領域に複数の貫
通孔６８が形成してあり、この貫通孔６８内に放熱材と
して封止樹脂４０より熱伝導率の大きな高放熱性樹脂７
０が埋め込んである。この半導体装置６６においても、
半導体チップ３２の放熱を良好に行なうことができ、基
板３４の寸法を小さくできるとともに、基板３４の無駄
な領域（デッドスペース）を有効利用することができ
る。FIG. 5 is a sectional view of a semiconductor device according to the third embodiment. Semiconductor device 66 according to this embodiment
Has a plurality of through-holes 68 formed in the mounting area of the semiconductor chip 32 of the substrate 34, and a high heat radiation resin 7 having a higher heat conductivity than the sealing resin 40 as a heat radiation material in the through holes 68.
0 is embedded. Also in this semiconductor device 66,
The semiconductor chip 32 can radiate heat well, the size of the substrate 34 can be reduced, and a useless area (dead space) of the substrate 34 can be effectively used.
【００２８】図６は、第４実施形態の半導体装置を示し
たものである。この半導体装置７２は、半導体チップ７
４が能動面に設けたバンプ７６を介して基板３４に形成
した回路パターンと電気的に接続するようになってい
る。すなわち、半導体チップ７４は、能動面が基板３４
の他側面と対向するように配置され、周縁部に設けたバ
ンプ７６が基板他側面に形成した回路パターンに直接接
続される。そして、基板３４に形成した開口３６と、半
導体チップ２３の能動面と基板３６との間の間隙とに
は、放熱材である高放熱性樹脂７０が充填してある。FIG. 6 shows a semiconductor device according to the fourth embodiment. The semiconductor device 72 includes a semiconductor chip 7
4 is electrically connected to a circuit pattern formed on the substrate 34 via a bump 76 provided on the active surface. That is, the active surface of the semiconductor chip 74 is
The bump 76 provided on the peripheral edge portion is directly connected to a circuit pattern formed on the other side surface of the substrate. The openings 36 formed in the substrate 34 and the gap between the active surface of the semiconductor chip 23 and the substrate 36 are filled with a high heat radiation resin 70 as a heat radiation material.
【００２９】このように構成した半導体装置７２は、図
４に示した製造方法のフローチャートのステップ６１に
おいて、ワイヤボンディングの代わりに半導体チップ７
４のフェースダウンボンディングを行なうことにより製
造することができる。この場合においても、ステップ６
２の高放熱性樹脂７０の充填工程をステップ６３の封止
工程の後に行なってもよい。そして、高放熱性樹脂７０
の充填工程を先に行なうと、封止樹脂４０が半導体チッ
プ７４の能動面側に回り込むのを防止することができ、
より放熱性を高めることができる。In the semiconductor device 72 thus configured, in step 61 of the flowchart of the manufacturing method shown in FIG.
4 can be manufactured by performing face-down bonding. Also in this case, step 6
The step of filling the second high heat dissipation resin 70 may be performed after the sealing step of step 63. And the high heat dissipation resin 70
If the filling step is performed first, it is possible to prevent the sealing resin 40 from going around the active surface side of the semiconductor chip 74,
Heat dissipation can be further improved.
【００３０】なお、高放熱性樹脂７０を充填する場合、
最初に半導体チップ７４と基板３４との間隙を埋めるよ
うに充填し、この樹脂が硬化または仮硬化したのちに開
口３６を埋めるように高放熱性樹脂７０を充填してもよ
いし、予め半導体チップ７４の能動面に高放熱性樹脂を
薄く塗布しておき、半導体チップ７４をフェースダウン
ボンディングしたのちに、開口３６内に高放熱性樹脂７
０を充填するようにしてもよい。When the high heat radiation resin 70 is filled,
First, the semiconductor chip 74 may be filled so as to fill the gap between the substrate 34 and the resin, and after the resin has been cured or temporarily cured, the resin may be filled with the high heat radiation resin 70 so as to fill the opening 36. A high heat radiation resin is thinly applied to the active surface of the semiconductor chip 74 and the semiconductor chip 74 is face-down bonded.
Zeros may be filled.
【００３１】[0031]
【発明の効果】以上に説明したように、本発明によれ
ば、基板に形成した開口が半導体チップの大きさより小
さく形成するとともに、半導体チップを基板の端子部を
設けた一側と反対側に搭載したことにより、基板の一側
に配線パターンや半導体チップと接続するためのランド
を設ける必要がなく、基板の寸法を小さくすることがで
きてパッケージを小さくすることが可能となる。しか
も、開口中に放熱材を配置してあるため、半導体チップ
から生ずる熱を効率よく放散することができる。As described above, according to the present invention, the opening formed in the substrate is formed to be smaller than the size of the semiconductor chip, and the semiconductor chip is placed on the side opposite to the side on which the terminal portion of the substrate is provided. By mounting, it is not necessary to provide a land for connecting to a wiring pattern or a semiconductor chip on one side of the substrate, so that the size of the substrate can be reduced and the package can be reduced in size. Moreover, since the heat dissipating material is arranged in the opening, heat generated from the semiconductor chip can be efficiently dissipated.
【図１】本発明の第１実施の形態に係る半導体装置の説
明図であって、（１）は断面図であり、（２）は基板に
形成した開口の大きさの説明図である。FIG. 1 is an explanatory view of a semiconductor device according to a first embodiment of the present invention, in which (1) is a cross-sectional view and (2) is an explanatory view of the size of an opening formed in a substrate.
【図２】第１実施形態に係る半導体装置の製造方法の概
略を説明するフローチャートである。FIG. 2 is a flowchart illustrating an outline of a method of manufacturing the semiconductor device according to the first embodiment.
【図３】第２実施の形態に係る半導体装置の断面図であ
る。FIG. 3 is a sectional view of a semiconductor device according to a second embodiment.
【図４】第２実施形態に係る半導体装置の製造方法の概
略を示すフローチャートである。FIG. 4 is a flowchart schematically showing a method for manufacturing a semiconductor device according to a second embodiment.
【図５】第３実施の形態に係る半導体装置の断面図であ
る。FIG. 5 is a sectional view of a semiconductor device according to a third embodiment.
【図６】第４実施の形態に係る半導体装置の断面図であ
る。FIG. 6 is a sectional view of a semiconductor device according to a fourth embodiment.
【図７】従来の半導体装置の断面図である。FIG. 7 is a sectional view of a conventional semiconductor device.
１８ 端子部（半田ボール） ３０、５６、６６、７２ 半導体装置 ３２、７４ 半導体チップ ３４ 基板 ３６ 開口 ４０ 封止樹脂 ４２、５８ 放熱材 ４４ 充填部 ４６ フランジ部 ７０ 放熱材（高放熱性樹脂） ７６ バンプ Reference Signs List 18 terminal portion (solder ball) 30, 56, 66, 72 semiconductor device 32, 74 semiconductor chip 34 substrate 36 opening 40 sealing resin 42, 58 heat dissipating material 44 filling portion 46 flange portion 70 heat dissipating material (high heat dissipating resin) 76 bump
Claims (9)
板に貫通して形成した開口と、基板の他側面において前
記開口の周辺部に周縁部を載置した半導体チップと、前
記開口内に設けた放熱材とを有することを特徴とする半
導体装置。An opening formed through a substrate having a plurality of terminal portions provided on one side surface, a semiconductor chip having a peripheral portion mounted on a peripheral portion of the opening on another side surface of the substrate, A semiconductor device comprising: a heat dissipating material provided in an opening.
て設けた封止樹脂より熱伝導率の大きい高放熱性樹脂で
あることを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the heat dissipating material is a high heat dissipating resin having a higher thermal conductivity than a sealing resin provided over the semiconductor chip.
する請求項１に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the heat radiating material is a metal.
填部と、前記基板の一側面側において前記開口を覆うフ
ランジ部とからなり、断面凸状に形成してあることを特
徴とする請求項１に記載の半導体装置。4. The heat dissipating material includes a filling portion located in the opening and a flange portion covering the opening on one side surface of the substrate, and is formed to have a convex cross section. The semiconductor device according to claim 1.
填部と、前記基板の一側面側において前記開口を覆うフ
ランジ部とからなり、断面凸状に形成され、前記充填部
が前記半導体チップを覆って設けた封止樹脂より熱伝導
率の大きい高放熱性樹脂であり、前記フランジ部が金属
板であることを特徴とする請求項１に記載の半導体装
置。5. The heat dissipating material includes a filling portion located in the opening and a flange portion covering the opening on one side surface of the substrate, and is formed to have a convex cross section, and the filling portion is formed of the semiconductor. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a high heat radiation resin having a higher thermal conductivity than a sealing resin provided over the chip, and the flange portion is a metal plate. 3.
と反対側とされ、ワイヤを介して前記基板の他側面に設
けたパターンと電気的に接続してあることを特徴とする
請求項１ないし５のいずれかに記載の半導体装置。6. The semiconductor chip according to claim 1, wherein an active surface of the semiconductor chip is opposite to the substrate, and the semiconductor chip is electrically connected to a pattern provided on another side surface of the substrate via a wire. 6. The semiconductor device according to any one of items 5 to 5.
側とされ、バンプを介して前記基板の他側面に設けたパ
ターンと電気的に接続してあることを特徴とする請求項
１ないし５のいずれかに記載の半導体装置。7. The semiconductor chip according to claim 1, wherein an active surface of the semiconductor chip is on the substrate side, and the semiconductor chip is electrically connected to a pattern provided on another side surface of the substrate via bumps. The semiconductor device according to any one of the above.
有する断面凸状の放熱板を、複数の端子が配設してある
基板の一側面に固着する放熱板取付け工程と、前記基板
の他側面に前記開口を覆って半導体チップを固着するチ
ップ取付け工程と、このチップ取付け工程と前記放熱板
取付け工程とを任意の順序で行なったのち、前記基板の
他側面に形成したパターンと前記半導体チップとをワイ
ヤによって電気的に接続するワイヤボンディング工程
と、ワイヤボンディングした前記半導体チップを覆って
樹脂を塗布する封止工程とを有することを特徴とする半
導体装置の製造方法。8. A radiating plate attaching step of fixing a radiating plate having a convex cross section having a filling portion to be inserted into an opening formed in the substrate to one side surface of the substrate on which a plurality of terminals are provided, and A chip mounting step of fixing the semiconductor chip on the other side surface by covering the opening, and performing the chip mounting step and the heat sink mounting step in an arbitrary order; A method of manufacturing a semiconductor device, comprising: a wire bonding step of electrically connecting a chip with a wire; and a sealing step of coating a resin over the wire-bonded semiconductor chip.
面と反対側の面に、基板を貫通して形成した開口を覆っ
て半導体チップを搭載するチップ搭載工程と、前記開口
に放熱用樹脂を充填する放熱樹脂充填工程と、前記半導
体チップを覆って封止樹脂を塗布する封止工程とを有す
ることを特徴とする半導体装置の製造方法。9. A chip mounting step of mounting a semiconductor chip on a surface opposite to one side surface of a substrate on which a plurality of terminal portions are provided, so as to cover an opening formed through the substrate. A method of manufacturing a semiconductor device, comprising: a step of filling a heat dissipation resin with a resin for heat dissipation; and a sealing step of applying a sealing resin to cover the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3140399A JP2000232186A (en) | 1999-02-09 | 1999-02-09 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3140399A JP2000232186A (en) | 1999-02-09 | 1999-02-09 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000232186A true JP2000232186A (en) | 2000-08-22 |
Family
ID=12330304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3140399A Pending JP2000232186A (en) | 1999-02-09 | 1999-02-09 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000232186A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002232009A (en) * | 2001-01-30 | 2002-08-16 | Harison Toshiba Lighting Corp | Light emitting diode array, and light source device |
| JP2007048858A (en) * | 2005-08-09 | 2007-02-22 | Shindo Denshi Kogyo Kk | Semiconductor device and manufacturing method thereof |
| JP2007149814A (en) * | 2005-11-25 | 2007-06-14 | Matsushita Electric Works Ltd | Circuit board and method of manufacturing same |
| CN101584044A (en) * | 2006-12-12 | 2009-11-18 | 艾格瑞系统有限公司 | An integrated circuit package and a method for dissipating heat in an integrated circuit package |
| WO2011013966A2 (en) * | 2009-07-28 | 2011-02-03 | 익스팬테크주식회사 | Method for manufacturing a heat-dissipating substrate for an led, and structure thereof |
| KR101032961B1 (en) | 2009-07-28 | 2011-05-09 | 주식회사 세미라인 | Manufacture method of LED heat dissipation board and its structure |
| JP2011101052A (en) * | 2005-07-20 | 2011-05-19 | Samsung Led Co Ltd | Led package and method of manufacturing the same |
| CN103378012A (en) * | 2012-04-27 | 2013-10-30 | 三星电机株式会社 | Semiconductor package |
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-
1999
- 1999-02-09 JP JP3140399A patent/JP2000232186A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002232009A (en) * | 2001-01-30 | 2002-08-16 | Harison Toshiba Lighting Corp | Light emitting diode array, and light source device |
| JP2011101052A (en) * | 2005-07-20 | 2011-05-19 | Samsung Led Co Ltd | Led package and method of manufacturing the same |
| JP2007048858A (en) * | 2005-08-09 | 2007-02-22 | Shindo Denshi Kogyo Kk | Semiconductor device and manufacturing method thereof |
| JP2007149814A (en) * | 2005-11-25 | 2007-06-14 | Matsushita Electric Works Ltd | Circuit board and method of manufacturing same |
| US9502617B2 (en) | 2006-02-23 | 2016-11-22 | Lg Innotek Co., Ltd. | Light emitting diode package and method of manufacturing the same |
| CN101584044A (en) * | 2006-12-12 | 2009-11-18 | 艾格瑞系统有限公司 | An integrated circuit package and a method for dissipating heat in an integrated circuit package |
| JP2010512658A (en) * | 2006-12-12 | 2010-04-22 | アギア システムズ インコーポレーテッド | Integrated circuit package and method for dissipating heat in an integrated circuit package |
| KR101032961B1 (en) | 2009-07-28 | 2011-05-09 | 주식회사 세미라인 | Manufacture method of LED heat dissipation board and its structure |
| WO2011013966A3 (en) * | 2009-07-28 | 2011-05-19 | 익스팬테크주식회사 | Method for manufacturing a heat-dissipating substrate for an led, and structure thereof |
| WO2011013966A2 (en) * | 2009-07-28 | 2011-02-03 | 익스팬테크주식회사 | Method for manufacturing a heat-dissipating substrate for an led, and structure thereof |
| CN103378012A (en) * | 2012-04-27 | 2013-10-30 | 三星电机株式会社 | Semiconductor package |
| CN103378012B (en) * | 2012-04-27 | 2016-08-17 | 三星电机株式会社 | Semiconductor packages |
| US9391009B2 (en) | 2013-08-21 | 2016-07-12 | Samsung Electronics Co., Ltd. | Semiconductor packages including heat exhaust part |
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