JP2002026250A - Manufacturing method of laminated circuit module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated circuit module which reduces a warpage developed by a thermal shrinkage stress so as to be made thin and which can be mounted at high density, by a constitution wherein a bare chip which is flip-chip-mounted on a multilayer interconnection board is buried by a resin layer. SOLUTION: Bump electrodes 14 and interlayer connection electrodes 16 are formed on the multilayer interconnection board 12 as a substrate (a), and the bare chip 13a is flip-chip-mounted by an anisotropic conductive paste 15 (b). A thermosetting resin 31 is coated (c), and it is heated by a heating tool 32 so as to be thermally cured in every specific region corresponding to the bare chip 13a (d). After that, a part 31b which is not heated in the thermosetting resin 31 is dissolved by acetone or the like, and the resin layer 17 is formed. Since the area of the resin layer 17 is limited, a shrinkage stress in a cooling operation can be reduced, the warpage of the board 12 can be reduced, and the module can be made thin.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a laminated circuit module having a configuration in which a flip-chip mounting is performed on a wiring substrate or another module serving as a base and embedded with a resin layer.

[0002]

In recent years, electronic devices have become smaller and more sophisticated, and the mounting density of circuit components has been required to be higher. In particular, in the field of IC chip mounting, flip-chip mounting in which a semiconductor chip is directly mounted on a mounting substrate without a package has been performed, and thereby miniaturization and high density have been achieved.

In this case, the flip-chip mounting using a bare chip and the use of a high-density laminated substrate ultimately limit the mounting size of the circuit by the occupied area (footprint area) of the mounted components themselves. . Therefore, in order to further reduce the size, it is necessary to use a stacked mounting in which circuit components (bare chips) are stacked in the vertical direction.

In view of the above, the inventors have proposed in the earlier application an invention in which the area of the substrate is reduced by stacking and mounting the bare chips and the thickness in the stacking direction is also reduced. . In this case, with respect to the thickness of the resin layer, the resin is thermally cured, and then a grinding process is performed to grind the resin layer together with the back surface side of the bare chip to reduce the thickness of the resin layer. As a result, a structure in which bare chips are stacked in multiple layers with a minimum thickness dimension can be obtained.

FIG. 16A is a cross-sectional view of the structure, in which a plurality of bare chips 2 are mounted on a mounting board 1 such as a wiring board.
Is flip-chip mounted, the connection electrode 3 is formed, and a resin is applied from above and thermally cured to form the resin layer 4. Thereafter, the resin layer 4 is polished together with the bare chip 2 so that the connection electrodes 3 are exposed. Further, a wiring pattern electrically connected to the connection electrode 3 is formed thereon, and a resin layer is formed in the same manner to form a first layer configuration. If necessary, a layer for mounting a bare chip is further formed thereon, or another mounting board is opposed to and connected to form a laminated circuit module.

However, in the above case, in order to further reduce the overall thickness, it is necessary to reduce the thickness of the mounting substrate 1 itself. By the way, the resin layer 4
As described above, since the resin is formed in multiple stages using the thermosetting resin, contraction stress is generated when the temperature returns to room temperature after the thermosetting. As a result, stress distortion occurs between the mounting substrate 1 and the thermosetting resin due to the difference in the coefficient of thermal expansion between the two.
As shown in (b), the mounting substrate 1 may be warped. This tendency becomes more conspicuous as the mounting substrate 1 is made thinner. Due to the occurrence of this warpage, in a process where the surface of the mounting substrate 1 is required to be parallel in a subsequent process such as a grinding process, the grinding is performed. In addition to the inability to obtain accuracy, there is also a disadvantage that the characteristics of the bare chip are adversely affected.

The present invention has been made in view of the above circumstances, and an object of the present invention is to use a thin mounting substrate and to reduce the coefficient of thermal expansion even when the portion on which a bare chip is mounted is sealed with a thermosetting resin. Provided are a method for manufacturing a semiconductor element mounting structure and a stacked circuit module, and a method for manufacturing a semiconductor element mounting structure, in which the occurrence of warpage due to a difference is suppressed, whereby the overall thickness can be reduced and the mounting density can be increased. It is in.

[0008]

According to the first aspect of the present invention, when a semiconductor element is flip-chip mounted on a base such as a wiring board or another module, and the semiconductor element is integrally embedded with a resin layer. Then, a portion to be embedded by the resin layer is set as a specific region including the semiconductor element. Then, the size of the specific region is set so that the amount of warpage of the base caused by the contraction stress after the thermosetting of the resin layer is equal to or less than an allowable range. In other words, since the size of the specific region is limited within a range including at least one semiconductor element, the generated contraction stress can be reduced, and accordingly, a thinner base such as a wiring substrate is used. Will be able to As a result, the mounting density in the thickness direction is increased, and the stress applied to the flip chip is reduced, so that a highly reliable device can be manufactured.

According to the second aspect of the present invention, in the first aspect of the present invention, the specific region for forming the resin layer is set within a range for individually encapsulating the semiconductor elements. The warpage of the base due to shrinkage stress can be suppressed, and the above-described effects can be further ensured.

According to a third aspect of the present invention, in the step of forming the resin layer according to the first or second aspect of the present invention, the resin is applied over the entire surface of the base, and then the resin is applied to a specific region of the applied resin. The part to be heat-cured is selectively heated, and the resin layer is formed by removing the resin in the part that is not heat-cured.Therefore, the resin layer is selectively applied to the part corresponding to the specific area through a simple process. Can be formed.

According to a fourth aspect of the present invention, in the step of forming the resin layer according to the first or second aspect of the invention, a resin dam is formed so as to surround a periphery of a specific region to be a base.
Since the resin is applied to the inside of the weir and cured by heat, a resin layer can be selectively formed for each specific region, and the amount of resin used can be formed to be a necessary minimum. become.

According to the fifth aspect of the present invention, when a semiconductor element is flip-chip mounted on a base such as a wiring board or another module, and the semiconductor element is integrally embedded with a resin layer, the semiconductor element is flip-chip mounted. A resin is applied to the mounted base to cover the semiconductor element, and then the base side is heated at a temperature lower than the thermosetting temperature of the resin to perform a weak thermosetting treatment. Since the resin is formed by thermosetting at a thermosetting temperature, the shrinkage stress generated by advancing the thermosetting of the resin by a weak thermosetting process can be reduced. The shrinkage stress exerted on the substrate when cooled to room temperature after the curing process can be reduced, and by performing the thermosetting process at the original thermosetting temperature, the stress due to thermal shrinkage is reduced. By performing the thermosetting process of years, it is possible to shorten the required time for heat curing. Then, the wiring board or the like serving as a base can be made thinner by an amount that can reduce the shrinkage stress, and high-density mounting can be performed.

According to a sixth aspect of the present invention, in the first to fourth aspects of the invention, in the step of thermosetting the resin layer, the base side is heated at a temperature lower than the thermosetting temperature of the resin in the same manner as described above. Since it is formed by performing a weak thermosetting process and then performing a thermosetting process at a thermosetting temperature of the resin, in addition to the effect of dividing the resin layer into specific regions and forming a resin layer, as described above, , The shrinkage stress exerted on the substrate can be reduced, the thickness of the underlying wiring board or the like can be reduced, and high-density mounting can be performed.

According to the seventh aspect of the present invention, when a semiconductor element is flip-chip mounted on a base such as a wiring board or another module and the semiconductor element is integrally sealed by a resin layer, the resin layer is formed on the base. Prior to the forming step, a support substrate for preventing warpage is bonded to the back side of the base, so that the base can be prevented from being deformed by the shrinkage stress after applying a resin and performing a thermosetting treatment. Thereby, the inconvenience caused by the warpage of the handling base such as the post-process can be eliminated, and the wiring board or the like serving as the base can be generally reduced in thickness and mounted with high density.

According to an eighth aspect of the present invention, in the first to sixth aspects, the step of forming the resin layer on the underlayer comprises:
The method is performed in a state in which the support substrate for preventing warpage is bonded to the back side of the base, so that the effect of dividing the resin layer into specific regions according to the first to fourth inventions or the heat of the fifth or sixth invention can be obtained. In addition to the effect of performing a weak thermosetting treatment at a temperature lower than the curing temperature and then performing a thermosetting treatment at the thermosetting temperature, the resin is applied by bonding a support substrate for preventing warpage to the back side of the base. After the thermal curing treatment, the underlayer can be more effectively prevented from being deformed by the shrinkage stress, thereby making it possible to reduce the thickness of the underlying wiring board and the like, and to achieve high-density mounting. Will be able to do it.

According to a ninth aspect of the present invention, in the method of the seventh or eighth aspect, in the step of thermosetting the resin layer, the base side is heated at a temperature lower than the thermosetting temperature of the resin to obtain a weak thermosetting. Since the film is formed by performing a heat treatment at the thermosetting temperature of the resin, the adverse effect of the shrinkage stress generation of the resin layer can be further reduced in addition to the above-described effects. It is possible to reduce the thickness and to perform high-density mounting.

According to a tenth aspect of the present invention, in the invention of the seventh to ninth aspects, the step of forming the resin layer on the underlayer comprises:
The support substrate is attached to the base with an adhesive, and a resin is applied by applying a resin corresponding to a region where the semiconductor element of the base is mounted, and the resin layer is heated while being pressed with a pressing substrate. Since the resin layer is thermally cured, and further formed by cooling the resin layer while being pressed by the pressing substrate and then peeling the resin layer from the base, the wiring substrate and the like serving as the base are bonded to the support substrate and supported. In addition to the state, the thermosetting and cooling are performed in a state of being pressed by the pressing substrate, so that the base is prevented from warping due to the shrinkage stress of the resin as much as possible, such as the wiring substrate serving as the base. , And can be adapted for high-density mounting.

According to an eleventh aspect of the present invention, in the above-described tenth aspect, in the step of forming the resin layer on the base, the resin layer is polished together with the semiconductor element until the interlayer connection electrode is exposed. Next, an interlayer wiring of the next stage is formed, and a resin for the next layer is applied by applying a resin for an interlayer wiring, and the wiring resin layer is thermoset by heating while being pressed with a flattening substrate. At the same time, the wiring resin layer is cooled while being pressed by the flattening substrate, and then the flattening substrate is peeled off from the base, so that the semiconductor element provided by flip-chip mounting is embedded in the resin layer. It is possible to obtain a structure in which a similar structure is further laminated on the structure described above, and it is possible to reduce the thickness of the wiring substrate serving as a base and to realize a structure capable of high-density mounting.

According to a twelfth aspect of the present invention, there is provided a method of manufacturing a laminated circuit module in which two laminated circuit modules formed according to the eleventh aspect of the present invention are formed by joining them as a joining laminated circuit module. A bonding bump is formed on one of the bonding laminated circuit modules, a resin is applied so as to cover the formed connection bump, a bonding resin layer is provided, and the other bonding lamination is formed on the bonding resin layer. Circuit modules are stacked and pressurized and heated. After the bonding resin layer is cooled, it is formed by peeling off the support substrate. Therefore, the use of a thinned base wiring board etc. minimizes warpage and minimizes warpage. Density mounting can be enabled.

According to a thirteenth aspect of the present invention, in the seventh to twelfth aspects, a wax having a softening temperature lower than the thermosetting temperature of the resin layer with respect to the base is used as the adhesive. By heating when the support substrate is peeled off after the resin layer has been subjected to the thermosetting treatment, the thermosetting of the resin layer does not proceed, and the generation of shrinkage stress can be suppressed. In this case, at the time of heat curing and cooling,
Since the supporting substrate is in pressure contact with the underlying wiring substrate or the like, the two are not substantially separated from each other. As a result, it is possible to reduce the thickness of the underlying wiring board and to achieve a configuration that enables high-density mounting.

According to the fourteenth aspect of the present invention, in the invention of the seventh to thirteenth aspects, a supporting substrate having a jig for fixing a base is used, so that it can be easily attached and detached without using an adhesive. It is possible to reduce man-hours during manufacturing.

According to a fifteenth aspect of the present invention, in the invention of the fourteenth aspect, a jig constituted by a claw for locking the base and a spring member for pressing the claw is provided as the support substrate, so that it is simple and quick. In addition to being able to fix a wiring substrate or the like as a base to the support substrate, even if there is a slight deviation in the size of the base, the deviation can be absorbed by the force of the spring member to improve the mountability. become able to.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, as a first embodiment of the present invention, one layer of a stacked circuit having a configuration in which a semiconductor element is mounted between wiring boards on the upper and lower sides will be described. FIG. 1 shows a case where the laminated circuit module of FIG.
This will be described with reference to FIG.

FIG. 2 shows a schematic cross section of the overall structure of the laminated circuit module 11, in which a multilayer wiring board 12 is used as a wiring board (base). This multilayer wiring board 12
Is, for example, a thickness dimension of about 0.6 to 0.8 mm, a plurality of conductor layers are formed in a predetermined wiring pattern inside, and the wiring patterns 12a and 12
b.

The multilayer wiring board 12 includes an IC or an LSI.
Chips 13a to 13c (in the figure, three bare chips 1
3a to 13c) are flip-chip mounted. The bare chips 13 a to 13 c are electrically connected via bump electrodes 14 having a height of 20 to 100 μm formed on the multilayer wiring board 12 side, and are fixed using an anisotropic conductive paste 15. .

In the vicinity of the bare chips 13a to 13c, a plurality of interlayer connection electrodes 16 having a height of about 200 μm or less are formed, and are provided between the multilayer wiring board 12 and a multilayer wiring board (not shown) disposed in an upper layer. It is used for interlayer connection. Each of the bare chips 13a to 13c is formed so as to be buried integrally with the resin layer 17 together with the interlayer connection electrode 16 arranged close to each. The resin layer 17 is formed as described later, but by being individually buried, the multilayer wiring board 12 receives a small shrinkage stress when cooled after thermosetting, thereby suppressing the occurrence of warpage. A configuration is employed.

Next, the laminated circuit module 11 having the above configuration
Will be described with reference to FIGS. 1, 3 and 4. FIG. In the first embodiment, the description will focus on the formation of the first layer resin layer 17 in the entire process. In the description of this manufacturing process, three bare chips 13a to 13a to
The portion provided with one bare chip 13a of 13c will be described as a representative.

In the actual manufacture of the multilayer circuit module 11, the size of the multilayer circuit module 11 having a plurality of (for example, six) multilayer wiring boards 12 is set so that a plurality of the multilayer wiring modules 12 can be manufactured at a time. The resulting product is separated by a method such as dicing to finally obtain a laminated circuit module 11.

In the following description, the manufacturing process for forming the resin layer 17 of one laminated circuit module 11 will be described separately in the following four processes and other processes. The respective steps are (a) a base preparation step, (b) an interlayer connection electrode forming step, (c) a chip mounting step, (d) a resin layer forming step, and (e) other steps.

(A) Base Preparation Step First, a multilayer wiring board 12 to be used as a base for forming the laminated circuit module 11 is prepared. The multilayer wiring board 12 is laid out on one side in a wiring pattern corresponding to the flip chip mounting of the bare chip 13a, and on the back side (lower side), a wiring pattern in which input / output electrode pads, pads for mounting discrete components, etc. are arranged. And connected via an internal wiring conductor pattern layer.

(B) Step of forming interlayer connection electrodes Next, the interlayer connection electrodes 16 and the bump electrodes 14 are formed on the multilayer wiring board 12 (see FIG. 1A). These electrodes 16 and 14 are connected to a JPS method (Je
t Printing System; a method of straightening a pattern using ultrafine metal particles) on the upper surface of the multilayer wiring board 12 by Au.
(Gold) is formed as an electrode material.

Here, the height of the interlayer connection electrode 16 to be formed is set, for example, in a range of about 100 μm to 200 μm, and the height of the bump electrode 14 is, for example, 2 μm.
It is set in the range of about 0 μm to 100 μm. The interlayer connection electrodes 16 and the bump electrodes 14 to be formed are formed by adjusting the conditions for deposition so as to have a conical or truncated conical shape.

Next, the JPS method will be briefly described with reference to FIG. The figure shows a schematic configuration of an apparatus for directly drawing ultrafine metal particles by the JPS method. The configuration of the apparatus is divided into a film forming chamber 21 and an ultrafine particle generation chamber 22, and a transport pipe 23 for transporting ultrafine metal particles is connected between them.

An exhaust pipe 24 is connected to the film forming chamber 21 and the ultrafine particle generating chamber 22, and a rotary pump (RP) 25 for depressurizing the inside and a mechanical pump
A booster pump (MBP) 26 is connected.
In this case, the inside of the film forming chamber 21 is, for example, 13.3 Pa.
The pressure is reduced to about (0.1 torr) to form an electrode. The ultra-fine particle generation chamber 22 generates metal ultra-fine particles while keeping the inside thereof pressurized to about 2 atm, for example. Therefore, the ultrafine particle generation chamber 22
A gas supply pipe 27 is connected so as to be filled with an inert gas such as e and pressurized (the He gas flow rate is, for example, 40 liters per minute).

An XY stage 28 for mounting a sample on which an electrode is to be formed is provided in the film forming chamber 21. The XY stage 28 can be moved in the XY direction in the plane when the electrode is formed, and can be moved in the axial direction ( (Z direction), and has a heater inside to set a predetermined substrate temperature.
On the XY stage 28, a nozzle 23a at the tip of the transfer pipe 23 is disposed so as to face the distance of, for example, about 400 μm. The diameter of the nozzle 23a is, for example, 100 μm
It is about.

In the ultrafine particle generation chamber 22, a crucible 29 for melting Au as an electrode material is provided with a heating device 29.
a range from 1500 to 1600 ° C. (for example, 155
0 ° C.). The Au evaporated by heating here is reduced in the film forming chamber 2 through the transfer pipe 21.
The XY stage 28 flows into the XY stage 28 and becomes ultra-fine particles when the pressure is reduced, and is ejected from the nozzle 23a due to a pressure difference.
Adheres to and accumulates on the surface of the sample placed on the substrate.

The nozzle 23a is heated to, for example, about 300 ° C. by a heater (not shown). In this apparatus, by adopting the above configuration and conditions, for example, the drawing speed is 3 to 10 mm / sec and the deposition speed is 1
It is about 0 μm / sec. The positioning accuracy of the XY stage 28 is about ± 2 μm. Since the formation of the interlayer connection electrode 16 and the bump electrode 14 by the above-described JPS method can be all performed as a dry process, the steps such as pre-processing and post-processing can be simplified as a whole.

(C) Chip Mounting Step Next, as shown in FIG. 1B, the bare chip 13a is mounted on the multilayer wiring board 12. Here, since the bump electrode 14 is made of Au (gold), the solder reflow process can be performed. Therefore, flip-chip mounting is performed using, for example, an anisotropic conductive paste 15. An anisotropic conductive paste 15 is applied to a portion of the multilayer wiring board 12 where the bare chip 13a is to be mounted and placed. In this state, heating is performed while applying a force of several hundred to several hundreds of mN (millinewton) per one bump electrode 14 to thermally cure the anisotropic conductive paste 15.
The curing temperature is, for example, 120C to 140C.

The thickness of the bare chip 13a is, for example, 300 μm to 6 μm for a wafer having a diameter of 15 cm.
The thickness is about 00 μm, and when supplied in a chip state, it is generally at least about 300 μm. Also, even if the thickness in the wafer state is relatively thick,
In some cases, it is ground to be thin before cutting into chips.

(D) Step of Forming Resin Layer Next, as shown in FIG. 1C, a thermosetting resin 31 is applied to the entire surface so as to cover the bare chip 13a mounted with flip chips and the interlayer connection electrodes 16. Thermosetting resin 31
For example, a resin used for an epoxy-based adhesive or the like can be used, or polyimide or the like can be used. The thermosetting resin 31 has a designated thermosetting temperature of 100 ° C. and a designated thermosetting time of about 30 seconds. Then, after application, the heat tool 32
The thermosetting resin 31 is applied to bare chips 13a to 13c.
Are selectively heat-cured in a corresponding region, that is, a specific region (see FIG. 4D).

In this case, as shown in FIG. 4, the heat tool 32 is composed of an upper heating plate 33a and a lower heating plate 33b, and the heating plates 33a and 33b correspond to a plurality of laminated circuit modules 11, respectively. The heating heads 34a, 34 each having a size corresponding to a specific area
Many b are formed. And this heat tool 3
Reference numeral 2 is mounted on a commonly used flip chip bonder, and the heating heads 34a and 34b are heated from the main body side. When the layered wiring board 12 coated with the thermosetting resin 31 is set on a holding unit (not shown) to start the heating processing operation, the upper heating plate 33a and the lower heating plate 3
3b moves so as to sandwich the multilayer wiring board 12, so that the heating heads 34a and 34b face each other and pressurize.

Thus, the thermosetting resin 31 applied to the upper portion of the bare chip 13 is pressure-formed by the heating head 34a so as to be flattened. Heating is performed by heating at an appropriate temperature in the range of 150 ° C., for example, 110 ° C. for 30 seconds. As a result, only the thermosetting resin 31a in the portion where the heating heads 34a and 34b face each other and heated is selectively thermoset, and the thermosetting resin 31b in the other portions remains unheated. Become.

Thereafter, the thermosetting resin 31 is cooled to room temperature while the heat tool 32 is mounted, that is, while being pressed by the heating heads 34a and 34b. The lower heating plate 33b is removed and released. At this time, a release agent 35 is applied to each of the heating heads 34a and 34b on a surface facing the multilayer wiring board 12 so as to facilitate release.

Next, portions 31b where the thermosetting resin 31 has not been thermoset are selectively removed from the entire multilayer wiring board 12 using a solvent such as acetone. As a result, the heat-cured portion 31a remains and is thereby formed as the resin layer 17 (see FIG. 3E). In addition, as a solvent used when removing the portion 31b that is not thermally cured, methanol or the like can be used instead of acetone.

(E) Other Steps The laminated circuit module 11 on which the resin layer 17 has been formed as described above is thereafter subjected to other steps such as a grinding step, a wiring electrode forming step, and a wiring resin layer forming step. By performing the above, it can be formed as a base for forming the second layer resin layer.

In the grinding step, the resin layer 17 in which the bare chip 13 and the interlayer connection electrode 16 are embedded is ground from the upper surface side. Here, the resin layer 17 is ground from the surface using a grinding machine, and the bare chip 13 and the interlayer connection electrode 16 are ground.
Is exposed, grinding is performed until the thickness of the bare chip 13 becomes about 100 μm. At this time, if the interlayer connection electrode 16 is ground to the height or less, the interlayer connection electrode 16 is also ground and is exposed on the surface of the resin layer 17.

The back surface of the bare chip 13 and the interlayer connection electrode 16 are exposed on the surface of the resin layer 17 after the grinding. Thereby, the interlayer connection electrode 16 penetrating the front and back surfaces of the resin layer 17 can be formed, and the first resin layer in which the bare chip 13 is embedded can be formed. When the bare chip 13 having a small thickness (for example, a thickness of about 100 μm) is mounted in the flip chip mounting process, only the interlayer connection electrodes 16 may be exposed.

Next, a wiring electrode is formed on the surface of the resin layer 17. Here, a wiring electrode is formed on the ground resin exposed portion of the interlayer connection electrode 16 on the resin layer 17 by the above-described JPS method. The wiring electrodes are for connecting to the next-stage laminated circuit module or multilayer wiring board. The height dimension of the wiring electrode 21 is, for example, in a range of 40 to 60 μm.
It is desirable to set the aspect ratio of the columnar portion to be 1 or less. This is to prevent the wiring electrode 21 from falling down or buckling when being pressed in a later step.

Subsequently, a second resin layer is formed by embedding the wiring electrodes. An epoxy-based thermosetting resin is applied so as to cover the wiring electrodes on the surface of the ground resin layer 17, and the wiring electrodes are crushed and electrically connected so as to be sandwiched by a laminated circuit module or a multilayer wiring board formed thereon. . The force applied to the wiring electrode is about 1 N (Newton) per one columnar electrode of the wiring electrode. Thereafter, a thermosetting treatment is performed in the same manner as described above to form a second resin layer.

Through the above-described steps, the first resin layer 17 in which the bare chips 13a to 13c are individually embedded and the second resin layer 17 in which the wiring electrodes are embedded are formed in the multilayer wiring board 12.
A resin layer is formed by lamination. Thereafter, the circuit module 11 is divided into individual circuit modules 11 through a dicing process and the like. Finally, other semiconductor elements and surface mount components such as discrete components are mounted and arranged on the multilayer wiring board 12 to complete the circuit module 11. .

According to the present embodiment, the bare chips 13a to 13e mounted on the multilayer wiring board 12 by flip chip mounting are described.
By forming the resin layer 17 individually on the substrate 13c,
Since the area of the resin layer 17 is limited, shrinkage stress generated when the thermosetting resin 31 is cooled after thermosetting can be reduced. As a result, the multilayer circuit board 1
2 can be reduced, and a decrease in accuracy due to a warp in a post-process or the like can be prevented. And
As a result, the multilayer wiring board 12 can be made thinner, and the mounting density in the thickness direction can be increased.

In this case, the extent to which the multilayer wiring board 12 can be made thin depends largely on the area in which the resin layer 17 is formed. Thermosetting resin 31
The shrinkage stress generated when the substrate is thermally hardened and cooled also varies depending on the thickness dimension and material of the multilayer wiring board 12 itself, the thickness dimension, area, and material of the resin layer 17. Therefore, when the thickness and the material are constant, the shrinkage stress of the resin layer 17 increases as the area of the resin layer 17 increases.

That is, by limiting the area of the resin layer 17, the warpage generated in the multilayer wiring board 12 can be reduced. Conversely, by limiting the area of the resin layer 17, the thickness of the multilayer wiring board 12 can be reduced, and as in this embodiment, the bare chips 13a to 13c are formed. Are individually embedded in the resin layer 17, the area as the specific region can be reduced, whereby the thickness dimension of the multilayer wiring board 12 can be relatively reduced. This makes it possible to achieve a configuration that enables high-density mounting with respect to the height dimension.

(Second Embodiment) FIG. 5 shows a second embodiment of the present invention. The difference from the first embodiment is a method of forming a resin layer 17. That is, the first
In the embodiment, the thermosetting resin is applied to the multilayer wiring board 1.
2 is formed by applying a heat-curing process to only the necessary portions and removing the other portions. In the second embodiment, the thermosetting resin is applied only to the necessary portions. The difference is that the resin layer 36 is thus formed.

FIG. 5D shows the configuration. In a specific region corresponding to the resin layer 17 in the first embodiment, a bank 37 as a resin dam is disposed so as to surround the outer periphery thereof. The bank 37 is, for example, 1 mm thick.
This is formed by cutting out a resin film of a desired size into a desired shape and having a height higher than the height of the bare chip 13a. Then, an internal region surrounded by the bank 37 is filled with a thermosetting resin having high fluidity, and a thermosetting process is performed in this state to form a resin layer 36.
Is formed.

The manufacturing process of the resin layer 36 is as shown in FIG. That is, in the same manner as in the first embodiment, the bare chip 13a is mounted on the multilayer wiring board 12 by performing the base preparation step, the interlayer connection electrode forming step, and the chip mounting step (see FIGS. b)).

Next, in the resin layer forming step, first, a bank 37 is disposed so as to surround each of the bare chips 13a to 13c and the interlayer connection electrode 16 disposed in the vicinity thereof (see FIG. 3C). As described above, the bank 37 is made of a resin film or the like, and is disposed by being attached to a specific area. Thereafter, the area surrounded by the bank 37 is filled with a thermosetting resin to fill the bare chip 13a.
And the interlayer connection electrodes 16 are buried together. Thereafter, the thermosetting resin is heated at a predetermined temperature, for example, in a range of 100 ° C. to 150 ° C., for example, at 110 ° C. to thermally cure the thermosetting resin, thereby forming the resin layer 36. Subsequent steps are as described in the first embodiment.

According to the second embodiment, when the resin layer 36 is formed, the portion corresponding to the specific region is surrounded by the bank 37, so that the thermosetting resin filling the internal region does not flow. As a result, the thermosetting resin can be provided only in the necessary portions, and the same effect as in the first embodiment can be obtained.

In the above embodiment, the bank 37
Has been described using a resin film, but in addition to this, it can be formed by applying an ultraviolet curable resin or the like and then irradiating ultraviolet rays to selectively cure the resin, or by forming the resin. It can also be formed by printing on the multilayer wiring board 12.

(Third Embodiment) FIG. 6 shows a third embodiment of the present invention. The difference from the first embodiment is a method of forming a resin layer. In this embodiment, the thermosetting resin is not limited to a specific area, but is applied over almost the entire surface of the multilayer wiring board 12. In the thermosetting process, heating is performed in two stages, a weak thermosetting process and a normal thermosetting process.

First, in the same manner as in the first embodiment, a base preparation step, an interlayer connection electrode forming step, and a chip mounting step are performed, so that the bare chip 13 a is mounted on the multilayer wiring board 12. Thereafter, in the resin layer forming step, FIG.
As shown in (a), a thermosetting resin 38 is applied over the entire surface. At this time, the thermosetting resin 38 is applied so as to cover at least the bare chip 13a and the interlayer connection electrode 16.

Next, a heat tool 39 is disposed below the multilayer wiring board 12 (see FIG. 4B), and a weak thermosetting treatment is performed at 10 which is the designated thermosetting temperature of the thermosetting resin 38.
The heating temperature lower than 0 ° C. is set in a range of 50 ° C. to 100 ° C., preferably in a range of 70 ° C. to 80 ° C., for example, 70 ° C., and the heating is performed, for example, with a heating time of 10 minutes. The heating time can be appropriately changed within a range from about 5 minutes to about several tens minutes. As a result, the thermosetting resin 38 undergoes weak thermosetting, and a small amount of thermosetting proceeds on the side where the heat tool 39 is in contact, that is, on the thin layer portion 38a on the multilayer wiring board 12 side (FIG. 3C). reference). The designated heating temperature of the thermosetting resin 38 is 100 ° C., and the designated heating time is 30 seconds. Therefore, in the above-mentioned weak thermosetting treatment, although a slight thermosetting proceeds, the generation of shrinkage stress is reduced because the thermosetting temperature is low.

Thereafter, by performing a thermosetting treatment at 110 ° C., which is the above-mentioned normal thermosetting temperature, for 30 seconds, the entire thermosetting proceeds, thereby forming the resin layer 38 (FIG. 4D). )reference). At this time, the portion 38a of the thin layer that has already been thermally cured undergoes thermal expansion by being raised above the temperature of the weak thermal curing treatment. And
As a result, the whole can be heat-cured, and the occurrence of shrinkage stress during cooling can be reduced to reduce the multilayer wiring board 1.
2 can be reduced.

In the above case, the case where the weak thermosetting treatment is performed at 70 ° C. for about 10 minutes has been described. From the viewpoint of reducing the warpage, it is effective to perform the weak thermosetting treatment at a temperature as low as possible for a long time. However, performing a weak thermosetting treatment at a low temperature requires a considerable amount of time to thermally cure the whole. Therefore, in reality, the most appropriate thermosetting treatment can be obtained by using the weak thermosetting process and the ordinary thermosetting process together.

In this embodiment, unlike the first embodiment, the case where the resin layer 38 is formed in a region over the entire surface of the multilayer wiring board 12 has been described, but in the same manner as in the first embodiment. Alternatively, a heat tool in which the resin layer 38 is provided separately for each specific region may be used. As a result, the occurrence of shrinkage stress due to the thermosetting resin can be further reduced, and the warpage of the multilayer wiring board 12 can be reduced, so that a further reduction in thickness can be achieved.

(Fourth Embodiment) FIGS. 7 to 10 show a fourth embodiment of the present invention, which is different from the first embodiment in that the resin layer 40 is formed with a warp preventing structure. This is where the supporting substrate is used.
In the resin layer forming step in which the warpage of the multilayer wiring board 12 is expected to occur, the rigid support substrate 41 is bonded to the resin substrate in advance, so that even if shrinkage stress of the thermosetting resin is generated, This is to prevent the wiring board 12 from warping.

FIGS. 7 to 9 show the manufacturing steps. In the same manner as in the first embodiment,
The interlayer connection electrode forming step and the chip mounting step are performed, and the bare chip 13a is mounted on the multilayer wiring board 12 (see FIG. 7A). Thereafter, in the resin layer forming step, first, as shown in FIG.
The support substrate 41 is bonded to the back surface side of the substrate 2.

For the supporting substrate 41, for example, a material having high rigidity and high thermal conductivity is suitable. For example, carbon steel or a copper alloy is effective, and one having a thickness of about 1 to 2 mm is used. The thickness dimension can be selected as required, but is set to such a degree that the operability in handling is good and the effect of preventing warpage can be ensured. The fixing of the support substrate 41 to the multilayer wiring board 12 is performed using, for example, a wax 42 having a softening point of about 140 ° C.

Next, a thermosetting resin 40 is applied over the entire surface of the multilayer wiring board 12. At this time, the thermosetting resin 40 is applied so as to cover at least the bare chip 13a and the interlayer connection electrode 16 (see FIG. 3C). Subsequently, the glass flat plate 43 for pressing is pressed from above the thermosetting resin 40 with the release agent 44 applied thereto,
For example, pressure is applied so that the load per flip-chip mounting bump electrode 14 is about 1N (see FIG. 4D).

Then, while maintaining this state, the thermosetting resin 40 is heated at a thermosetting temperature of 150 ° C. for 30 seconds to perform a thermosetting process of the thermosetting resin 40. Thereafter, the glass plate 4 is cooled to room temperature while being pressed by the glass plate 41 for pressing.
1 is peeled off (see FIG. 8A). As a result, the bare chip 13a is embedded in a state of being surrounded by the resin layer 40.

Next, the bare chip 13a is formed together with the resin layer 40.
Then, the interlayer connection electrode 16 is ground (see FIG. 3B). As described above, the resin layer 40 is ground from the surface using a grinding machine, and after the bare chip 13a and the interlayer connection electrode 16 are exposed, the thickness of the bare chip 13a becomes 100.
Grind to about μm. At this time, the interlayer connection electrode 16 is also ground at the same time, so that the height becomes lower than the initially formed height. In this grinding step, since the multilayer wiring board 12 is in a state of being supported by the support substrate 41, the precision of the grinding amount does not decrease due to adverse effects such as warpage, and the grinding processing is performed with a uniform grinding amount over the entire surface. Can be performed.

The back surface of the bare chip 13a and the interlayer connection electrode 16 are exposed on the surface of the resin layer 40 after the grinding. Thereby, the interlayer connection electrode 16 penetrating the front and back surfaces of the resin layer 40 can be formed, and the resin layer 40a in which the bare chip 13a is embedded can be formed. When the bare chip 13a has a small thickness (for example, a thickness of about 100 μm), only the interlayer connection electrode 16 may be exposed.

Subsequently, as shown in FIG. 7C, wiring electrodes 45a and 45b are formed on the surface of the resin layer 40a by using the JPS method as described above. Here, the wiring electrode 45 is used.
a has a configuration in which a conductor portion connected to the exposed portion of the interlayer connection electrode 16 of the ground resin layer 40a and a columnar electrode portion for connection to the next-stage multilayer wiring board 47 are formed. Has a configuration in which only columnar electrode portions are provided. The height dimension of the wiring electrodes 45a and 45b is such that the wiring electrodes 45a and 45b can be prevented from falling or buckling when the wiring electrodes 45a and 45b are pressurized in a later step.
It is set in the range.

Subsequently, as shown in FIG. 9A, a second resin layer 46 is formed by embedding the wiring electrodes 45a and 45b. An epoxy-based thermosetting resin 46 is applied so as to cover the wiring electrodes 45a and 45b on the surface of the ground first resin layer 40a. Then, the wiring electrodes 45a and 45a are sandwiched by the multilayer wiring board 47 to be superposed thereon.
b is crushed (see FIG. 3B).

The multilayer wiring board 47 has wiring electrodes 45a,
Since a connection electrode pad is formed in advance at a portion corresponding to 45b, when the crushing process is advanced, the wiring electrodes 45a and 45b come into electrical contact with each other. Here, the force applied to the wiring electrodes 45a and 45b was about 1 N (Newton) per one columnar electrode of the wiring electrodes.

At this time, the space between the ground surface of the resin layer 40a of the first layer and the multilayer wiring board 47 is sufficiently filled with the thermosetting resin 47 so as to be filled to every corner. In this state, heating is performed to thermally cure the epoxy-based thermosetting resin 46. The thermosetting temperature is about 100 ° C. Note that the pressurizing and heating processes are performed simultaneously using a flip chip bonder. Thereafter, when the thermosetting resin 46 is thermoset, the pressurized state is released and the wax is melted by heating to about 140 ° C., and the support substrate 41 is removed.

As a result, the second resin layer 46 is formed in a state in which it is in close contact with the multilayer wiring board 47 and is electrically connected thereto, and has a laminated circuit having a structure as shown in FIG. A module 48 can be obtained. In the above-described manufacturing process, since the flip-chip bonder is used, when the multilayer wiring board 47 is mounted on the surface of the resin layer 46, it has a parallelism, a pressurizing function, and a heating function. The process can be performed simply and quickly.

Through the above steps, the resin layers 40a in which the bare chips 13a to 13c are embedded and the wiring electrodes 45a, 45
The second resin layer 46 in which the multilayer wiring board 5b is embedded is formed between the resin layers 40a and 46 and the second wiring layer 1b.
The structure between 2 and 47 can be obtained as a structure connected by the interlayer connection electrode 16 and the columnar electrode of the wiring electrode.

FIG. 10 shows the result of measuring the entire amount of warpage of the multilayer wiring board 12 for the one manufactured as described above. The warpage data was measured at a measurement distance of 10 mm.
In the case where the support substrate 41 is used (see FIG. 3A).
And a case where a conventional method without using a supporting substrate is used (see FIG. 3B). As a result, in the case of using the supporting substrate 41, 7 μm at 15 mm from the center.
In the case of using no supporting substrate measured for comparison, the warpage was measured as about 190 μm at 15 mm from the center. Therefore, it was found that there was a large difference in the occurrence of warpage between the two, and it was confirmed that the effects of the present embodiment were greatly exhibited.

(Fifth Embodiment) FIG. 11 shows a fifth embodiment of the present invention.
This embodiment is different from the fourth embodiment in that the manufacturing method of the present invention is applied to a laminated circuit module 49 configured by laminating a plurality of laminated circuit modules 11. That is, the laminated circuit module 49 is a laminated circuit module 50 (FIG. 9A) formed using the fourth embodiment shown in FIG.
11) and a laminated circuit module 51 (corresponding to the configuration of FIG. 8B) shown in FIG. 11B.

In this case, as shown in FIG. 11C, the laminated circuit modules 50 and 51 are overlapped in a state of facing each other, and heated at a thermosetting temperature while applying pressure in this state. The heating temperature is 100 ° C. and the heating time is 30 seconds. The pressing force is about 1 N per one interlayer connection bump electrode 14. After thermosetting of the thermosetting resin 46, the whole is heated to 140 ° C. to melt the wax 42, and the two support substrates 41 are removed. Thus, a laminated circuit module 49 in which the laminated circuit module 50 having the bare chip 13a and the laminated circuit module 51 having the bare chip 13d are formed in two layers is obtained.

According to the present embodiment, the resin layers 40a, 46
In the step of forming the multilayer circuit modules 50 and 5, the warpage of the multilayer wiring substrate 12 is reduced by the support substrate 41.
In a state where the substrates 1 are bonded to each other, they act so as to cancel each other out of the contraction stress, so that warpage due to the stress can be prevented as a whole. Thereby, the thinning of the multilayer wiring board 12 can be further promoted, and high-density mounting in the thickness direction becomes possible.

(Sixth Embodiment) FIG. 12 shows a sixth embodiment of the present invention.
The third embodiment is different from the third embodiment in that a resin layer is formed using a detachable support substrate 52 without using wax, instead of the support substrate 41. The support substrate 52 has a configuration in which a claw portion 52 that can lock a peripheral portion in a state where the multilayer wiring substrate 12 is in close contact when the multilayer wiring substrate 12 is mounted is provided.

The claw portions 52a are continuously provided at a plurality of positions or corresponding to each side portion at positions corresponding to the outer shape of the multilayer wiring board 12, and are locked by being spread outward when mounting. Attach to Such a supporting substrate 5
By using 2, the multilayer wiring board 12 can be easily attached and detached without using the wax 42, and the warpage at the time of forming the resin layer can be prevented while improving the workability.

(Seventh Embodiment) FIGS. 13 to 15 show a seventh embodiment of the present invention. The difference from the sixth embodiment is that a support substrate 53 is used instead of the support substrate 52.
Is used to perform the resin layer forming step. As shown in FIG. 13, the support substrate 53 mounts the multilayer wiring substrate 12 with four claws 53 a provided on four sides thereof. The claw portion 53a is supported by the support substrate 5
3 is mounted so as to be movable along a guide groove 53b provided on the base 3. FIG. 15 shows the guide groove 5 viewed from the moving direction.
3b is shown.

As shown in FIG. 14, a spring member 53d is provided between the claw portion 53a and an outer frame 53c erected so as to surround the entire periphery of the support substrate 53. The wiring boards 12 are urged to press each other. When the multilayer wiring board 12 is mounted, when the claws 53a are pushed outward and inserted, the spring member 5 is always mounted in the mounted state.
3d can prevent falling off in a state of being biased,
The multilayer wiring board 12 can be reliably mounted.

(Other Embodiments) The present invention is not limited to the above embodiment, but can be modified or expanded as follows. The manufacturing method of forming the resin layer 17 for each specific region adopted in the first and second embodiments can be applied to the manufacturing methods of the third and subsequent embodiments. In that case, both effects can be obtained and the multilayer wiring board 1 can be obtained.
2 can be further reduced.

Although the specific area has been described in the case where the bare chips 13a to 13c are individually embedded, the present invention is not limited to this, and the specific area may be a plurality of specific units.

The interlayer connection electrodes, wiring electrodes and bump electrodes are
Other metals such as Cu (copper) and Al (aluminum) can be used instead of Au (gold).

When forming the second resin layer, instead of crushing with a flat plate or the like, the second resin layer 4 is ground by grinding the heat-cured resin layer.
6 may be formed.

The first resin layer 17 and the second resin layer 46
The same means that the same resin may be used or different kinds of resins may be used. For their selection, optimal ones can be used from various viewpoints such as the relationship of stress, affinity, and electrical characteristics.

Although not shown, a bump electrode for a flip chip may be replaced with a stud bump or an electrode formed of a conductive paste in a conical shape by using a printing method.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view corresponding to a processing step showing a first embodiment of the present invention.

FIG. 2 is a longitudinal side view of the entire configuration.

FIG. 3 is a diagram illustrating the principle of an electrode forming apparatus.

FIG. 4 is an external perspective view schematically showing a heat tool part.

FIG. 5 is a schematic sectional view corresponding to a processing step showing a second embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view corresponding to a processing step according to a third embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view (part 1) corresponding to a processing step according to a fourth embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view corresponding to a processing step (part 2).

FIG. 9 is a schematic cross-sectional view corresponding to a processing step (part 3).

FIG. 10 is a diagram showing a measurement result of a warp;

FIG. 11 is a schematic cross-sectional view corresponding to a processing step according to a fifth embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view showing a mounting state of a support substrate according to a sixth embodiment of the present invention.

FIG. 13 is a view corresponding to FIG. 12, showing a seventh embodiment of the present invention;

FIG. 14 is a top view showing a state in which a support substrate is mounted.

FIG. 15 is a cross-sectional view of the supporting substrate as viewed from the moving direction of the claw portion.

FIG. 16 is a diagram corresponding to FIG. 2 showing a conventional example.

[Explanation of symbols]

11 is a laminated circuit module, 12 is a multilayer wiring board (base), 13a to 13d are bare chips (semiconductor elements), 1
4 is a bump electrode, 15 is an anisotropic conductive paste, 16 is an interlayer connection electrode, 17 is a resin layer, 31 is a thermosetting resin, 32
Is a heat tool, 33a is an upper heating plate, 33b is a lower heating plate, 34a and 34b are heating heads, 36 is a resin layer, 3
7 is a bank (weir), 38 is a thermosetting resin, 39 is a heat tool, 40 is a resin layer, 41 is a support substrate, 42 is wax, 43 is a flat glass plate, 45a and 45b are wiring electrodes,
46 is a resin layer, 47 is a multilayer wiring board, 48, 49, 5
Reference numerals 0 and 51 are laminated circuit modules, and 52 and 53 are support substrates.

Claims (15)

[Claims] 1. A method of manufacturing a laminated circuit module in which a semiconductor element is flip-chip mounted on a wiring board or another module as a base. A step of integrally burying and forming the resin layer is provided, and the size of the specific region is set to an area where the amount of warpage of the base caused by contraction stress after thermosetting of the resin layer is equal to or less than an allowable range. A method for manufacturing a laminated circuit module, comprising: 2. The method for manufacturing a laminated circuit module according to claim 1, wherein the specific region in which the resin layer is formed is set in a range where the semiconductor elements are individually sealed. A method for manufacturing a circuit module. 3. The method for manufacturing a laminated circuit module according to claim 1, wherein the step of forming the resin layer includes a step of applying a resin over the entire surface of the base, and a step of applying the resin to the base. A method for manufacturing a laminated circuit module, comprising: a step of heating and thermally curing a portion of the resin corresponding to the specific region; and a step of removing the resin in a portion which is applied to the base and is not thermally cured. . 4. The method for manufacturing a laminated circuit module according to claim 1, wherein the step of forming the resin layer includes the steps of: forming a resin dam surrounding a periphery of the specific region; A method for manufacturing a laminated circuit module, comprising: a step of applying a resin to an inside of a weir formed in each region; and a step of thermally curing the applied resin. 5. A method of manufacturing a laminated circuit module in which a semiconductor element is flip-chip mounted on a wiring board or another module as a base, wherein a resin is applied to the base to cover the semiconductor element. A step of applying, a step of heating the base side at a temperature lower than the thermosetting temperature of the resin to perform a weak thermosetting treatment, and a step of thermosetting at a temperature equal to or higher than the thermosetting temperature of the resin. A method for manufacturing a laminated circuit module, comprising: 6. The method for manufacturing a laminated circuit module according to claim 1, wherein in the step of thermosetting the resin layer, the base side is heated at a temperature lower than a thermosetting temperature of the resin. A method of performing a weak thermosetting process, and a step of performing thermosetting at a temperature equal to or higher than a thermosetting temperature of the resin. 7. A method for manufacturing a laminated circuit module, wherein a semiconductor element is flip-chip mounted on a wiring board or another module serving as a base and the semiconductor element is embedded by a resin layer. The method of manufacturing a laminated circuit module, wherein the forming step is performed in a state where a support substrate for preventing warpage is bonded to the back side of the base. 8. The method for manufacturing a laminated circuit module according to claim 1, wherein in the step of forming a resin layer on the base, a support substrate for preventing warpage is bonded to a back side of the base. A method for manufacturing a laminated circuit module, which is performed in a state. 9. The method for manufacturing a laminated circuit module according to claim 7, wherein in the step of thermosetting the resin layer, the base side is weakened by heating at a temperature lower than a thermosetting temperature of the resin. A method for manufacturing a laminated circuit module, comprising: performing a thermosetting process; and performing a thermosetting process at a temperature equal to or higher than a thermosetting temperature of the resin. 10. The method for manufacturing a laminated circuit module according to claim 7, wherein the step of forming a resin layer on the base includes the step of attaching the support substrate to the base with an adhesive. Applying a resin corresponding to a region where the semiconductor element is mounted on the base to form a resin layer; heating the resin layer while pressing the resin layer with a pressing substrate to thermally cure the resin layer A method for manufacturing a laminated circuit module, comprising: a step of cooling the resin layer while being pressed by the pressing substrate, and then peeling the resin layer from the base. 11. The method of manufacturing a laminated circuit module according to claim 10, wherein the step of forming a resin layer on the base includes polishing the resin layer together with the semiconductor element until an electrode for interlayer connection is exposed. Subsequently, a step of forming a next-stage interlayer wiring, a step of applying a resin for a next-layer interlayer wiring to provide a wiring resin layer, and a step of heating the wiring under pressure with a flattening substrate. Manufacturing a laminated circuit module, comprising: a step of thermally curing the resin layer for wiring; and a step of cooling the resin layer for wiring while being pressed with the flattening substrate, and then peeling the wiring resin layer from the base. Method. 12. A method of manufacturing a laminated circuit module, wherein two laminated circuit modules produced by the method of producing a laminated circuit module according to claim 11 are formed by joining them as a joining laminated circuit module. Forming a connection bump on one of the bonding stacked circuit modules; applying a resin so as to cover the formed connection bump to provide a bonding resin layer; and forming the connection resin layer on the bonding resin layer. A method for manufacturing a laminated circuit module, comprising: a step of laminating and heating the other laminated circuit module for bonding and a step of peeling off the support substrate after the resin layer for bonding is cooled. 13. The method for manufacturing a laminated circuit module according to claim 7, wherein the support substrate adheres a wax having a softening temperature lower than a thermosetting temperature of the resin layer to the base. A method for producing a laminated circuit module, wherein the method is used as an agent. 14. The method of manufacturing a laminated circuit module according to claim 7, wherein the support substrate includes a jig for fixing the base. Production method. 15. The method for manufacturing a laminated circuit module according to claim 14, wherein the support substrate includes the jig constituted by a claw portion for locking the base and a spring member for pressing the claw portion. A method for manufacturing a laminated circuit module, characterized in that: