JP2009200067A - Semiconductor chip and semiconductor device - Google Patents

Semiconductor chip and semiconductor device Download PDF

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JP2009200067A
JP2009200067A JP2008036749A JP2008036749A JP2009200067A JP 2009200067 A JP2009200067 A JP 2009200067A JP 2008036749 A JP2008036749 A JP 2008036749A JP 2008036749 A JP2008036749 A JP 2008036749A JP 2009200067 A JP2009200067 A JP 2009200067A
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semiconductor chip
insulating film
electrode pad
metal layer
electrode
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Takatoshi Osumi
貴寿 大隅
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Panasonic Corp
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Panasonic Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To surely suppress cracking or peeling of a pad portion and prevent shortcircuiting among metal bumps. <P>SOLUTION: In the structure of a semiconductor chip electrode, the level of the surface of a base metal layer is made lower by 0.0-0.4 μm than that of a second insulation film, so that a stress by a flux print mask can be dispersed and cracking or peeling of an electrode pad can be suppressed in circuits in the periphery of the electrode pad. In addition, no flux is supplied to the outer side than a diameter of the base metal layer, so as to prevent shortcircuiting among metal bumps. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体チップをフリップチップ実装してなる半導体装置および実装される半導体チップに関する。   The present invention relates to a semiconductor device formed by flip-chip mounting a semiconductor chip and a semiconductor chip to be mounted.

近年、情報通信機器や事務用電子機器の小型化および高機能化が進展するのに伴って、これらの機器に搭載される半導体集積回路装置等の半導体装置について、小型化とともに、入出力のための外部端子の数を増加することが要求されている。しかし、半導体装置に搭載される半導体チップの周辺に電極パッドを形成してワイヤボンディング方式で外部回路と接続する方式では、外部端子数の増加と半導体チップの小型化の両立が困難になってきている。   In recent years, as information communication equipment and office electronic equipment have been reduced in size and functionality, semiconductor devices such as semiconductor integrated circuit devices mounted on these equipment have been reduced in size and input / output. There is a demand to increase the number of external terminals. However, in the method in which electrode pads are formed around a semiconductor chip mounted on a semiconductor device and connected to an external circuit by a wire bonding method, it is difficult to simultaneously increase the number of external terminals and downsize the semiconductor chip. Yes.

これらの要求を実現させる技術として、電極パッドを能動領域上に形成し、ワイヤボンディングやインナーリードボンディングを行うパッドオンエレメントと呼ばれる技術がある。さらに、能動領域上に形成された電極パッド上にバンプと呼ばれる外部接続端子を形成し、バンプを介して外部回路と接続するフリップチップ技術が採用されるようになってきた。   As a technique for realizing these requirements, there is a technique called a pad-on element in which an electrode pad is formed on an active region and wire bonding or inner lead bonding is performed. Furthermore, flip-chip technology has been adopted in which external connection terminals called bumps are formed on electrode pads formed on the active region and are connected to external circuits via the bumps.

以下、図６〜図１２を用いて従来の半導体装置について説明する。
図６は従来の半導体チップの電極構造におけるクラック発生状況を説明する断面図、図７は従来の半導体チップの電極構造におけるショート発生状況を説明する断面図である。図８，図９は従来の半導体チップにおける金属バンプの形成工程を示す工程断面図である。図１０は従来の半導体装置の製造工程を説明する工程断面図である。図１１は従来のＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型の半導体チップの電極構造を示す断面図である。図１２は従来のＢＧＡ型半導体装置の構造を示す断面図であり、図１１に示す電極を備えた半導体チップ１を配線基板１２にフリップチップ実装し、アンダーフィル（ｕｎｄｅｒ ｆｉｌｌ）樹脂１３を注入した状態を示す断面図である。 A conventional semiconductor device will be described below with reference to FIGS.
FIG. 6 is a cross-sectional view for explaining the occurrence of cracks in the electrode structure of a conventional semiconductor chip, and FIG. 8 and 9 are process cross-sectional views showing a process of forming metal bumps in a conventional semiconductor chip. FIG. 10 is a process cross-sectional view illustrating a manufacturing process of a conventional semiconductor device. FIG. 11 is a cross-sectional view showing an electrode structure of a conventional BGA (Ball Grid Array) type semiconductor chip. FIG. 12 is a cross-sectional view showing the structure of a conventional BGA type semiconductor device. The semiconductor chip 1 having the electrodes shown in FIG. 11 is flip-chip mounted on a wiring board 12, and an underfill resin 13 is injected. It is sectional drawing which shows a state.

図１１に示すように、半導体チップ１には、半導体チップ１上に形成される半導体素子に電気的に接続された電極パッド２と、この電極パッド２の上側に開口部を有する第１絶縁膜３と第２絶縁膜４が形成されている。第２絶縁膜４の上部および開口部を含む電極パッド２上に下地金属層５が形成されている。下地金属層５上には、半田からなる金属バンプ１４が形成されている。半導体チップ１は、図１２に示すように、配線基板１２にフェイスダウン搭載され、半導体チップ１の電極パッド２と配線基板１２の電極ランド１２ａとが金属バンプ１４を介して機械的および電気的に接続されている。そして、半導体チップ１と配線基板１２との隙間で金属バンプ１４間にアンダーフィル樹脂１３が充填されている。また、配線基板１２の半導体チップ搭載面に対する反対側の面には半田ボール１０が形成されている。   As shown in FIG. 11, the semiconductor chip 1 includes an electrode pad 2 electrically connected to a semiconductor element formed on the semiconductor chip 1, and a first insulating film having an opening above the electrode pad 2. 3 and the second insulating film 4 are formed. A base metal layer 5 is formed on the electrode pad 2 including the upper portion of the second insulating film 4 and the opening. Metal bumps 14 made of solder are formed on the base metal layer 5. As shown in FIG. 12, the semiconductor chip 1 is mounted face-down on the wiring board 12, and the electrode pads 2 of the semiconductor chip 1 and the electrode lands 12 a of the wiring board 12 are mechanically and electrically connected via metal bumps 14. It is connected. An underfill resin 13 is filled between the metal bumps 14 in the gap between the semiconductor chip 1 and the wiring board 12. Solder balls 10 are formed on the surface of the wiring board 12 opposite to the semiconductor chip mounting surface.

アンダーフィル樹脂１３を充填するのは、次の理由による。半導体チップ１と配線基板１２とでは熱膨張係数に差があることから、熱履歴等を受けた場合には、接合部とりわけ金属バンプ１４のチップ側根元部分に応力がかかることになる。この応力集中を緩和するため、半導体チップ１と配線基板１２との間の金属バンプ１４以外の部分に封止樹脂としてアンダーフィル樹脂１３を注入し、硬化することによって補強している。このアンダーフィル樹脂１３には、エポキシ系樹脂などのベースとなる樹脂１３ａの他に、半導体チップ１の熱膨張係数と似た熱膨張係数とするための適当な大きさのフィラー成分１３ｂが添加されている（ｆｉｌｌｅｒ：詰め物）。そして、フィラー成分１３ｂの添加量や粒径を調整することによって熱膨張係数を調整している。アンダーフィル樹脂１３には、外部からの水分の浸入を抑制し、耐湿性を高める役割もある。   The underfill resin 13 is filled for the following reason. Since there is a difference in coefficient of thermal expansion between the semiconductor chip 1 and the wiring substrate 12, when a thermal history is received, stress is applied to the joint, particularly the chip-side root portion of the metal bump 14. In order to alleviate this stress concentration, the underfill resin 13 is injected as a sealing resin into a portion other than the metal bumps 14 between the semiconductor chip 1 and the wiring board 12 and is reinforced by curing. In addition to the resin 13a serving as a base such as an epoxy resin, the underfill resin 13 is added with a filler component 13b having an appropriate size for making the thermal expansion coefficient similar to that of the semiconductor chip 1. (Filler). And the thermal expansion coefficient is adjusted by adjusting the addition amount and particle size of the filler component 13b. The underfill resin 13 also has a role of suppressing moisture permeation from the outside and improving moisture resistance.

ここで、ボール搭載方式による半導体チップの金属バンプ形成方法について、図８，図９を用いて説明する。
まず、図８（ａ）に示すように、上述の電極パッド２，第１絶縁膜３，第２絶縁膜４および下地金属層５を形成した後、電極パッド２上が開口したフラックス印刷マスク８を設置する。 Here, a method for forming metal bumps on a semiconductor chip by a ball mounting method will be described with reference to FIGS.
First, as shown in FIG. 8A, after the electrode pad 2, the first insulating film 3, the second insulating film 4 and the base metal layer 5 are formed, the flux printing mask 8 having an opening on the electrode pad 2 is formed. Is installed.

次に、図８（ｂ）に示すように、スキージ７にてフラックス６をフラックス印刷マスク８開口部に入れ込み印刷する。
次に、図８（ｃ）に示すように、フラックス印刷マスク８を取り除く。 Next, as shown in FIG. 8 (b), the squeegee 7 puts the flux 6 into the opening of the flux printing mask 8 for printing.
Next, as shown in FIG. 8C, the flux printing mask 8 is removed.

次に、図８（ｄ）に示すように、フラックス６が印刷された電極パッド２上が開口したボール搭載マスク９を搭載する。
次に、図９（ａ）に示すように、金属バンプ１４をボール搭載マスク９開口部に入れ込み仮接合する。 Next, as shown in FIG. 8D, a ball mounting mask 9 having an opening on the electrode pad 2 on which the flux 6 is printed is mounted.
Next, as shown in FIG. 9A, the metal bumps 14 are inserted into the openings of the ball mounting mask 9 and temporarily joined.

次に、図９（ｂ）に示すように、フラックス６で仮接着された金属バンプ１４を、図９（ｃ）に示すように、リフローにより電極パッド２に接合する。
最後に、図９（ｄ）に示すように、洗浄により余分なフラックス６を除去する。 Next, as shown in FIG. 9B, the metal bumps 14 temporarily bonded with the flux 6 are joined to the electrode pad 2 by reflow as shown in FIG. 9C.
Finally, as shown in FIG. 9D, excess flux 6 is removed by cleaning.

以上により、電極へのバンプ形成が完成する。
また、前述したようなフリップチップ実装方式による半導体装置の製造方法について、図１０を用いて説明する。 Thus, bump formation on the electrode is completed.
Further, a method for manufacturing a semiconductor device by the flip chip mounting method as described above will be described with reference to FIG.

まず、図１０（ａ）に示すように、電極パッド２上に電気めっき法や印刷法やボール搭載法などの方法で金属バンプ１４を形成したバンプ付の半導体チップ１と、金属バンプ１４に対応する位置に金属パッド１２ａが形成された配線基板１２とを用意する。そして、半導体チップ１を配線基板１２に対してフリップチップで搭載する。   First, as shown in FIG. 10A, the bumped semiconductor chip 1 in which the metal bumps 14 are formed on the electrode pads 2 by a method such as electroplating, printing, or ball mounting, and the metal bumps 14 are supported. A wiring board 12 on which metal pads 12a are formed is prepared. Then, the semiconductor chip 1 is mounted on the wiring substrate 12 by flip chip.

次に、図１０（ｂ）に示すように、半導体チップ１の金属バンプ１４をリフローすることにより、半田を溶融し、金属バンプ１４により半導体チップ１と配線基板１２とを接続する。   Next, as shown in FIG. 10B, the solder bumps are melted by reflowing the metal bumps 14 of the semiconductor chip 1, and the semiconductor chip 1 and the wiring substrate 12 are connected by the metal bumps 14.

その後、図１０（ｃ）に示すように、半導体チップ１と配線基板１２との隙間を清浄化し、ディスペンサ１１を用いてその隙間にアンダーフィル樹脂１３を注入する。注入はチップの周辺部から行うが、毛細管現象により全面に浸入し、半導体チップ１と配線基板１２との隙間にアンダーフィル樹脂１３が充填される。   Thereafter, as shown in FIG. 10C, the gap between the semiconductor chip 1 and the wiring substrate 12 is cleaned, and the underfill resin 13 is injected into the gap using the dispenser 11. The injection is performed from the peripheral portion of the chip, but it enters the entire surface by a capillary phenomenon, and the gap between the semiconductor chip 1 and the wiring substrate 12 is filled with the underfill resin 13.

その後、熱処理を行い、アンダーフィル樹脂１３を硬化することによって封止する。
最後に、図１０（ｄ）に示すように、チップ搭載面と反対側の面に引き出された金属パッドに半田ボール１０を形成し、リフローする。 Thereafter, heat treatment is performed, and the underfill resin 13 is cured to be sealed.
Finally, as shown in FIG. 10 (d), solder balls 10 are formed on the metal pads drawn out on the surface opposite to the chip mounting surface and reflowed.

以上により、ＢＧＡ型の半導体装置が完成する。
特開平１１−３４０２６５号公報 Thus, a BGA type semiconductor device is completed.
Japanese Patent Laid-Open No. 11-340265

前述したような半田ボール搭載方式では、図６（ａ）のように下地金属層５が第２保護膜４より高い場合、図６（ｂ）に示すようにフラックス６を供給する際にフラックス印刷マスク８の開口径を下地金属層５の全径より小さくし、フラックス印刷マスク８と下地金属層５が接触するようにしている。これは、フラックス６の供給量が過多になり、周辺の電極にフラックス６がブリッジしてリフロー時に金属バンプ１４同士がショートすることを防ぐために供給量を制御するためである。一方、半導体製造プロセスの著しい進化に伴って、半導体チップの構造も微細化、高集積化が進み、配線材料として比較的抵抗の小さい銅配線が用いられたり、層間絶縁膜として比誘電率の低い、いわゆる低誘電率（ｌｏｗ−ｋ）材料が用いられたりするケースが多くなってきている。しかし、低誘電率材料は機械的強度が弱いため、実装後に低誘電率膜にクラックや剥離が生じてしまうことが多くなってきた。そのため、フラックス印刷マスク８と下地金属層５が局所的に接触するようにしていると、図６（ｃ）のように下部に応力が集中し、結果として図６（ｄ）のようにクラック１５が発生する可能性がある。   In the solder ball mounting method as described above, when the base metal layer 5 is higher than the second protective film 4 as shown in FIG. 6A, the flux printing is performed when the flux 6 is supplied as shown in FIG. 6B. The opening diameter of the mask 8 is made smaller than the entire diameter of the base metal layer 5 so that the flux printing mask 8 and the base metal layer 5 are in contact with each other. This is because the supply amount of the flux 6 is excessive, and the supply amount is controlled in order to prevent the flux 6 from bridging to peripheral electrodes and short-circuiting the metal bumps 14 during reflow. On the other hand, with the remarkable progress of the semiconductor manufacturing process, the structure of the semiconductor chip is also miniaturized and highly integrated, and copper wiring having a relatively low resistance is used as a wiring material, and the relative dielectric constant is low as an interlayer insulating film. In many cases, so-called low dielectric constant (low-k) materials are used. However, since the low dielectric constant material has low mechanical strength, the low dielectric constant film is often cracked or peeled after mounting. Therefore, if the flux printing mask 8 and the underlying metal layer 5 are in local contact, stress concentrates in the lower portion as shown in FIG. 6C, and as a result, cracks 15 as shown in FIG. May occur.

クラック１５の発生を抑制する方法として、図７（ａ），図７（ｂ）に示すように、下地金属層５より第２絶縁膜４を高く調整する方法がある（例えば、特許文献１参照）。フラックス印刷マスク８と下地金属層５が局所的に接触せず、第２絶縁膜４と接触していることから応力が分散しクラックは低減できる。しかし、図７（ｃ）に示すようにフラックス６を印刷すると、下地金属層５の径より外側にフラックス６が供給されるために必要量以上のフラックス６が多量に供給されることになり、図７（ｄ）に示すようにフラックス印刷マスク８を取り除いた際にフラックス６が電極周辺に濡れ広がり、周辺電極に供給されたフラックス６とブリッジすることでリフロー時に金属バンプ１４同士がショートする可能性がある。   As a method of suppressing the generation of the crack 15, there is a method of adjusting the second insulating film 4 higher than the base metal layer 5 as shown in FIGS. 7A and 7B (for example, see Patent Document 1). ). Since the flux printing mask 8 and the underlying metal layer 5 are not in local contact but in contact with the second insulating film 4, stress is dispersed and cracks can be reduced. However, when the flux 6 is printed as shown in FIG. 7 (c), the flux 6 is supplied outside the diameter of the base metal layer 5, so that a larger amount of flux 6 than necessary is supplied. As shown in FIG. 7D, when the flux printing mask 8 is removed, the flux 6 wets and spreads around the electrode, and the metal bumps 14 can be short-circuited during reflow by bridging with the flux 6 supplied to the peripheral electrode. There is sex.

本発明は、このような事情に鑑みて創作したものであり、パッド部のクラックや剥離の発生を確実に抑制し、かつ金属バンプ間のショートを防止することを目的としている。   The present invention has been created in view of such circumstances, and an object thereof is to reliably suppress the occurrence of cracks and peeling of the pad portion and to prevent a short circuit between metal bumps.

上記目的を達成するために、請求項１記載の半導体チップは、配線基板に金属バンプを介して接続されることにより半導体装置が形成される半導体チップであって、前記金属バンプと接続する電極部が、前記半導体チップの外部端子となる電極パッドと、前記電極パッド上の少なくとも一部を開口するように形成される第１絶縁膜と、前記第１絶縁膜上に少なくとも前記電極パッド上を開口するように形成される第２絶縁膜と、前記電極パッド上および前記第１絶縁膜の一部の上に形成される下地金属層とを有し、前記下地金属層の前記電極パッド表面からの表面高さが前記第２絶縁膜の前記電極パッド表面からの表面高さより０．０〜０．４μｍ低いことを特徴とする。   To achieve the above object, a semiconductor chip according to claim 1 is a semiconductor chip in which a semiconductor device is formed by being connected to a wiring board via a metal bump, and an electrode portion connected to the metal bump. An electrode pad serving as an external terminal of the semiconductor chip, a first insulating film formed so as to open at least a part on the electrode pad, and an opening on at least the electrode pad on the first insulating film. And a base metal layer formed on the electrode pad and on a part of the first insulating film, the base metal layer extending from the surface of the electrode pad. The surface height is 0.0 to 0.4 μm lower than the surface height of the second insulating film from the electrode pad surface.

請求項２記載の半導体チップは、請求項１記載の半導体チップにおいて、前記電極パッドの端部が前記下地金属層の端部より隣接する電極部方向に突出することを特徴とする。
請求項３記載の半導体チップは、請求項２記載の半導体チップにおいて、前記第２絶縁膜の端部が前記電極パッドの端部より内側に形成されることを特徴とする。 According to a second aspect of the present invention, in the semiconductor chip according to the first aspect, an end portion of the electrode pad protrudes in an adjacent electrode portion direction from an end portion of the base metal layer.
According to a third aspect of the present invention, in the semiconductor chip according to the second aspect, the end of the second insulating film is formed inside the end of the electrode pad.

請求項４記載の半導体チップは、請求項３記載の半導体チップにおいて、前記第２絶縁膜の端部が前記第１絶縁膜の端部より前記下地金属層の膜厚の２倍の長さだけ内側に形成されることを特徴とする。   The semiconductor chip according to claim 4 is the semiconductor chip according to claim 3, wherein an end portion of the second insulating film is twice as long as a thickness of the base metal layer from an end portion of the first insulating film. It is formed inside.

請求項５記載の半導体装置は、請求項１から請求項４のいずれかに記載の半導体チップを前記配線基板に前記金属バンプを介して機械的および電気的に接続して搭載することを特徴とする。   A semiconductor device according to a fifth aspect is characterized in that the semiconductor chip according to any one of the first to fourth aspects is mounted on the wiring board through mechanical and electrical connection via the metal bumps. To do.

以上により、パッド部のクラックや剥離の発生を確実に抑制し、かつ金属バンプ間のショートを防止することができる。   By the above, the generation | occurrence | production of the crack of a pad part and peeling can be suppressed reliably, and the short circuit between metal bumps can be prevented.

以上のように、半導体チップの電極構造において、下地金属層の表面高さを第２絶縁膜の表面高さより０．０〜０．４μｍ低く構成し、マスク設置時にはマスクが下地金属層と第２絶縁膜との両方に接触するようにすることにより、フラックス印刷マスクによる応力が分散され、電極パッド部の周辺の回路部でのクラックや剥離を確実に抑制することができ、かつ、フラックスが下地金属層の径より外側に供給されることがないため、余分なフラックスの供給が抑制され、金属バンプ間のショートを防止することができる。   As described above, in the electrode structure of the semiconductor chip, the surface height of the base metal layer is configured to be 0.0 to 0.4 μm lower than the surface height of the second insulating film. By making contact with both of the insulating films, the stress due to the flux printing mask is dispersed, and cracks and peeling in the circuit portion around the electrode pad portion can be reliably suppressed, and the flux is the base. Since it is not supplied outside the diameter of the metal layer, supply of excess flux is suppressed, and a short circuit between metal bumps can be prevented.

以下、本発明にかかわる半導体チップの電極構造と半導体装置の実施の形態について図面を用いて詳細に説明する。
（実施の形態１）
図１は実施の形態１における半導体チップの電極構造を示す断面図である。図２は実施の形態１における半導体装置の構造を示す断面図であり、図１に示す半導体チップを配線基板にフリップチップ実装し、アンダーフィル樹脂を注入した状態を示す断面図である。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor chip electrode structure and a semiconductor device according to the present invention will be described below in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is a sectional view showing an electrode structure of a semiconductor chip in the first embodiment. FIG. 2 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment, and is a cross-sectional view showing a state where the semiconductor chip shown in FIG. 1 is flip-chip mounted on a wiring board and underfill resin is injected.

半導体チップ１には複数の半導体素子が形成されており、図１に示すように、各半導体素子とそれに電気的に接続されて外部端子となり、アルミニウム（Ａｌ）からなる端子部分の表面形状が円形の電極パッド２と、この電極パッド２の上側に円形の開口部を有し、チッ化シリコンからなる第１絶縁膜３とが形成されている。また、第１絶縁膜３の上側にはさらに第１絶縁膜３上に円形の開口部を有し、ポリイミドからなる第２絶縁膜４が形成されている。この第２絶縁膜４は、電極パッド２の上部領域にかぶらないように、電極パッド２の外側で電極パッド２の近傍に形成されている。また、第１絶縁膜３の上部の一部および開口部を含む電極パッド２上に電極パッド２に接する面の裏面の平面形状が円形の下地金属層５が形成されている。下地金属層５は、第２絶縁膜４に接しないように形成され、例えばスパッタ法によって形成されたチタン（Ｔｉ）からなるバリアメタルと胴（Ｃｕ）からなる下部金属膜と、その上方に電気めっき法によって形成されたニッケル（Ｎｉ）からなる上部金属膜によって構成されている。または、無電解めっき法によって形成されたニッケル（Ｎｉ／Ａｕ）からなる金属膜によって構成されている。さらに、下地金属層５上には、半田からなる金属バンプが形成される（図示せず）。   The semiconductor chip 1 is formed with a plurality of semiconductor elements. As shown in FIG. 1, each semiconductor element is electrically connected to an external terminal, and the surface shape of a terminal portion made of aluminum (Al) is circular. The electrode pad 2 and a first insulating film 3 having a circular opening on the upper side of the electrode pad 2 and made of silicon nitride are formed. Further, on the upper side of the first insulating film 3, a second insulating film 4 having a circular opening on the first insulating film 3 and made of polyimide is formed. The second insulating film 4 is formed outside the electrode pad 2 and in the vicinity of the electrode pad 2 so as not to cover the upper region of the electrode pad 2. A base metal layer 5 having a circular planar shape on the back surface of the surface in contact with the electrode pad 2 is formed on the electrode pad 2 including a part of the upper portion of the first insulating film 3 and the opening. The base metal layer 5 is formed so as not to be in contact with the second insulating film 4. For example, a barrier metal made of titanium (Ti) and a lower metal film made of a body (Cu) formed by sputtering, for example, and an electric power above the lower metal film The upper metal film made of nickel (Ni) formed by plating is used. Or it is comprised by the metal film which consists of nickel (Ni / Au) formed by the electroless-plating method. Further, metal bumps made of solder are formed on the base metal layer 5 (not shown).

なお、第１絶縁膜３を構成する材料はチッ化シリコンに限られず、酸化シリコンやポリイミドなどでもよい。第２絶縁膜４を構成する材料についてもポリイミドに限られず、ＢＣＢ（ベンゾシクロブテン）膜などでもよい。下部金属層５ａのバリアメタルを構成する材料はＴｉに限られず、第１絶縁膜３との強い密着性を有する材料であればよく、例えばＴｉＷやＣｒ等を用いてもよい。また、下地金属層５の構成要素のＣｕについてもこれに限られず、導電性を有する材料であればよい。   The material constituting the first insulating film 3 is not limited to silicon nitride, and may be silicon oxide, polyimide, or the like. The material constituting the second insulating film 4 is not limited to polyimide, but may be a BCB (benzocyclobutene) film. The material constituting the barrier metal of the lower metal layer 5a is not limited to Ti, and any material having strong adhesion to the first insulating film 3 may be used. For example, TiW or Cr may be used. Further, Cu as a constituent element of the base metal layer 5 is not limited to this, and any material having conductivity may be used.

以上の本実施の形態において、下地金属層５の表面高さを第２絶縁膜４の表面高さより０．０〜０．４μｍ低くすることにより、フラックス印刷時に、フラックス印刷マスク上よりスキージ圧力が加わったときに、フラックス印刷マスクを下地金属層５だけでなく第２絶縁膜４にも接触させることができるため、応力を分散することができる。その結果として、半導体チップ１の内部に進展するようなクラックや低誘電率膜の剥離の発生が抑制される。   In the present embodiment described above, the squeegee pressure is higher than that on the flux printing mask during flux printing by making the surface height of the base metal layer 5 0.0 to 0.4 μm lower than the surface height of the second insulating film 4. When applied, the flux printing mask can be brought into contact not only with the underlying metal layer 5 but also with the second insulating film 4, so that the stress can be dispersed. As a result, occurrence of cracks that progress inside the semiconductor chip 1 and peeling of the low dielectric constant film are suppressed.

さらに、フラックスが下地金属層５の径より外側に供給されることがないことから、下地金属層が絶縁膜より大幅に低い場合のフラックス供給量過多とリフロー時のフラックスの粘性低下による周辺電極のフラックスまでのはい上がりとブリッジすることが無くなるため、リフロー時に金属バンプ同士がショートすることを抑制することができる。   Furthermore, since the flux is not supplied to the outside of the diameter of the base metal layer 5, an excess of the flux supply amount when the base metal layer is significantly lower than the insulating film, and the peripheral electrode due to the decrease in the viscosity of the flux during reflow. Since it does not bridge with the rising up to the flux, it is possible to suppress short circuit between the metal bumps during reflow.

以上の説明では、電極パッド２，下地金属層５，第１絶縁膜３の開口部ならびに第２絶縁膜４の開口部が円形の場合を例に説明したが、必ずしも円形にする必要はなく、半導体素子から金属バンプ１４の接続が十分確保できれば平面形状は任意である。   In the above description, the case where the electrode pad 2, the base metal layer 5, the opening of the first insulating film 3 and the opening of the second insulating film 4 are circular has been described as an example. The planar shape is arbitrary as long as the connection of the metal bumps 14 from the semiconductor element can be secured sufficiently.

（実施の形態２）
図３は実施の形態２における半導体チップの電極構造を示す断面図である。図３において、実施の形態１の図１におけるのと同じ符号は同一構成要素を指している。本実施の形態に特有の構成は、次のとおりである。 (Embodiment 2)
FIG. 3 is a cross-sectional view showing the electrode structure of the semiconductor chip in the second embodiment. In FIG. 3, the same reference numerals as those in FIG. 1 of the first embodiment indicate the same components. The configuration specific to the present embodiment is as follows.

実施の形態１の構成において、さらに、下地金属層５の径を、電極パッド２の径より小さくし、電極パッド２の端部が下地金属層５の端部より隣接する電極方向に突出する構成とする。その他の構成については、実施の形態１と同様であるので、説明を省略する。   In the configuration of the first embodiment, the diameter of the base metal layer 5 is further smaller than the diameter of the electrode pad 2, and the end of the electrode pad 2 protrudes in the direction of the adjacent electrode from the end of the base metal layer 5. And Since other configurations are the same as those in the first embodiment, description thereof is omitted.

本実施の形態においては、フラックス印刷マスクが電極パッド２上の下地金属層５および第２絶縁膜４上に形成されるため、フラックス印刷マスクの開口端直下に電極パッド２が存在して応力を支え、半導体チップ内部に応力が伝わりにくくなり、半導体チップ内部に進展するようなクラックや低誘電率膜の剥離の発生がより抑制される。その他の効果については、実施の形態１の場合と同様である。   In the present embodiment, since the flux printing mask is formed on the base metal layer 5 and the second insulating film 4 on the electrode pad 2, the electrode pad 2 exists just below the opening end of the flux printing mask and stress is applied. The stress is less likely to be transmitted to the inside of the semiconductor chip, and the occurrence of cracks that progress into the semiconductor chip and the peeling of the low dielectric constant film are further suppressed. Other effects are the same as those in the first embodiment.

（実施の形態３）
図４は実施の形態３における半導体チップの電極構造を示す断面図である。図４において、実施の形態１の図１におけるのと同じ符号は同一構成要素を指している。本実施の形態に特有の構成は、次のとおりである。 (Embodiment 3)
FIG. 4 is a cross-sectional view showing the electrode structure of the semiconductor chip in the third embodiment. In FIG. 4, the same reference numerals as those in FIG. 1 of the first embodiment indicate the same components. The configuration specific to the present embodiment is as follows.

実施の形態１の構成において、さらに、下地金属層５の径が電極パッド２の径より小さく、かつ第２絶縁膜４の開口径を電極パッド２の径より小さくして第２絶縁膜４の端部が電極パッド２の端部より内側となる構成とする。その他の構成については、実施の形態１と同様であるので、説明を省略する。   In the configuration of the first embodiment, the diameter of the base metal layer 5 is further smaller than the diameter of the electrode pad 2 and the opening diameter of the second insulating film 4 is smaller than the diameter of the electrode pad 2 so that the second insulating film 4 The end portion is configured to be inside the end portion of the electrode pad 2. Since other configurations are the same as those in the first embodiment, description thereof is omitted.

本実施の形態においては、実施の形態２と同様に、第２絶縁膜の開口端直下に電極パッドが存在して応力を支え、半導体チップ内部に応力が伝わりにくくなるため、半導体チップ内部に進展するようなクラックや低誘電率膜の剥離の発生がより抑制される。その他の効果については、実施の形態１の場合と同様である。   In the present embodiment, as in the second embodiment, the electrode pad exists immediately below the opening end of the second insulating film to support the stress, and it is difficult for the stress to be transmitted to the inside of the semiconductor chip. Occurrence of cracks and peeling of the low dielectric constant film are further suppressed. Other effects are the same as those in the first embodiment.

（実施の形態４）
図５は実施の形態４における半導体チップの電極構造を示す断面図である。図５において、実施の形態１の図１におけるのと同じ符号は同一構成要素を指している。本実施の形態に特有の構成は、次のとおりである。 (Embodiment 4)
FIG. 5 is a sectional view showing an electrode structure of a semiconductor chip in the fourth embodiment. In FIG. 5, the same reference numerals as those in FIG. 1 of the first embodiment indicate the same components. The configuration specific to the present embodiment is as follows.

実施の形態１の構成において、さらに、下地金属層５の径が電極パッド２の径より小さく、かつ第２絶縁膜４の開口径が電極パッド２の径より小さく、かつ第２絶縁膜４の開口径＝第１絶縁膜の開口径３＋下地金属層５の膜厚×２となり、第２絶縁膜４の端部が第１絶縁膜３の端部より下地金属層５の膜厚の２倍の長さだけ内側に形成される構成とする。その他の構成については、実施の形態１と同様であるので、説明を省略する。   In the configuration of the first embodiment, the diameter of the base metal layer 5 is smaller than the diameter of the electrode pad 2, the opening diameter of the second insulating film 4 is smaller than the diameter of the electrode pad 2, and the second insulating film 4 The opening diameter = the opening diameter 3 of the first insulating film + the film thickness of the base metal layer 5 × 2. The end of the second insulating film 4 is twice the film thickness of the base metal layer 5 from the end of the first insulating film 3. It is set as the structure formed inside only the length of. Since other configurations are the same as those in the first embodiment, description thereof is omitted.

本実施の形態においては、無電解めっき方法の場合に膜厚方向と平面方向の金属成長が等距離であることから、第２絶縁膜の開口径の内部に隙間無く下地金属層が形成され、かつ表面高さが同様であることから、より半導体チップ内部に応力が伝わりにくくなるため、半導体チップ内部に進展するようなクラックや低誘電率膜の剥離の発生が抑制される。さらに、フラックスが下地金属層の径より外側に供給されることがないため、余分なフラックスの供給が抑制され、金属バンプ間のショートを防止することができる。その他の効果については、実施の形態１の場合と同様である。   In the present embodiment, in the case of the electroless plating method, since the metal growth in the film thickness direction and the planar direction is equidistant, the base metal layer is formed without a gap inside the opening diameter of the second insulating film, Moreover, since the surface height is the same, stress is less likely to be transmitted to the inside of the semiconductor chip, so that the occurrence of cracks that progress inside the semiconductor chip and the peeling of the low dielectric constant film are suppressed. Furthermore, since the flux is not supplied to the outside of the diameter of the base metal layer, the supply of excess flux is suppressed and a short circuit between the metal bumps can be prevented. Other effects are the same as those in the first embodiment.

本発明は、パッド部のクラックや剥離の発生を確実に抑制し、かつ金属バンプ間のショートを防止することができ、半導体チップをフリップチップ実装してなる半導体装置および実装される半導体チップ等に有用である。の半導体装置の電極構造は、電極パッド部近傍および周辺の回路部でのクラックや剥離を抑制することが可能になるので、信頼性の高い半導体装置を歩留まり良く製造するための技術として有用である。   INDUSTRIAL APPLICABILITY The present invention can reliably suppress the occurrence of cracks and peeling of the pad portion and prevent shorts between metal bumps. Useful. The electrode structure of this semiconductor device is useful as a technique for manufacturing a highly reliable semiconductor device with high yield because cracks and separation in the vicinity of the electrode pad portion and in the peripheral circuit portion can be suppressed. .

実施の形態１における半導体チップの電極構造を示す断面図Sectional drawing which shows the electrode structure of the semiconductor chip in Embodiment 1 実施の形態１における半導体装置の構造を示す断面図Sectional drawing which shows the structure of the semiconductor device in Embodiment 1 実施の形態２における半導体チップの電極構造を示す断面図Sectional drawing which shows the electrode structure of the semiconductor chip in Embodiment 2 実施の形態３における半導体チップの電極構造を示す断面図Sectional drawing which shows the electrode structure of the semiconductor chip in Embodiment 3 実施の形態４における半導体チップの電極構造を示す断面図Sectional drawing which shows the electrode structure of the semiconductor chip in Embodiment 4 従来の半導体チップの電極構造におけるクラック発生状況を説明する断面図Sectional drawing explaining the crack generation situation in the electrode structure of the conventional semiconductor chip 従来の半導体チップの電極構造におけるショート発生状況を説明する断面図Sectional drawing explaining the short circuit occurrence situation in the electrode structure of the conventional semiconductor chip 従来の半導体チップにおける金属バンプの形成工程を示す工程断面図Process cross-sectional view showing the process of forming metal bumps in a conventional semiconductor chip 従来の半導体チップにおける金属バンプの形成工程を示す工程断面図Process cross-sectional view showing the process of forming metal bumps in a conventional semiconductor chip 従来の半導体装置の製造工程を説明する工程断面図Process sectional view explaining the manufacturing process of a conventional semiconductor device 従来のＢＧＡ型の半導体チップの電極構造を示す断面図Sectional drawing which shows the electrode structure of the conventional BGA type semiconductor chip 従来のＢＧＡ型半導体装置の構造を示す断面図Sectional drawing which shows the structure of the conventional BGA type semiconductor device

符号の説明Explanation of symbols

１ 半導体チップ
２ 電極パッド
３ 第１絶縁膜
４ 第２絶縁膜
５ 下地金属層
６ フラックス
７ スキージ
８ フラックス印刷マスク
９ ボール搭載マスク
１０ 半田ボール
１１ ディスペンサ
１２ 配線基板
１２ａ 電極ランド
１３ アンダーフィル樹脂
１３ａ 樹脂
１３ｂ フィラー成分
１４ 金属バンプ
１５ クラック DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Electrode pad 3 1st insulating film 4 2nd insulating film 5 Base metal layer 6 Flux 7 Squeegee 8 Flux printing mask 9 Ball mounting mask 10 Solder ball 11 Dispenser 12 Wiring board 12a Electrode land 13 Underfill resin 13a Resin 13b Filler component 14 Metal bump 15 Crack

Claims (5)

配線基板に金属バンプを介して接続されることにより半導体装置が形成される半導体チップであって、前記金属バンプと接続する電極部が、
前記半導体チップの外部端子となる電極パッドと、
前記電極パッド上の少なくとも一部を開口するように形成される第１絶縁膜と、
前記第１絶縁膜上に少なくとも前記電極パッド上を開口するように形成される第２絶縁膜と、
前記電極パッド上および前記第１絶縁膜の一部の上に形成される下地金属層と
を有し、前記下地金属層の前記電極パッド表面からの表面高さが前記第２絶縁膜の前記電極パッド表面からの表面高さより０．０〜０．４μｍ低いことを特徴とする半導体チップ。 A semiconductor chip in which a semiconductor device is formed by being connected to a wiring board via a metal bump, and an electrode portion connected to the metal bump is
An electrode pad serving as an external terminal of the semiconductor chip;
A first insulating film formed so as to open at least part of the electrode pad;
A second insulating film formed on the first insulating film so as to open at least the electrode pad;
A base metal layer formed on the electrode pad and on a part of the first insulating film, and a surface height of the base metal layer from the surface of the electrode pad is the electrode of the second insulating film A semiconductor chip characterized by being 0.0 to 0.4 μm lower than the surface height from the pad surface. 前記電極パッドの端部が前記下地金属層の端部より隣接する電極部方向に突出することを特徴とする請求項１記載の半導体チップ。   2. The semiconductor chip according to claim 1, wherein an end portion of the electrode pad protrudes toward an adjacent electrode portion from an end portion of the base metal layer. 前記第２絶縁膜の端部が前記電極パッドの端部より内側に形成されることを特徴とする請求項２記載の半導体チップ。   The semiconductor chip according to claim 2, wherein an end portion of the second insulating film is formed inside an end portion of the electrode pad. 前記第２絶縁膜の端部が前記第１絶縁膜の端部より前記下地金属層の膜厚の２倍の長さだけ内側に形成されることを特徴とする請求項３記載の半導体チップ。   4. The semiconductor chip according to claim 3, wherein an end portion of the second insulating film is formed inside the end portion of the first insulating film by a length twice as long as a thickness of the base metal layer. 請求項１から請求項４のいずれかに記載の半導体チップを前記配線基板に前記金属バンプを介して機械的および電気的に接続して搭載することを特徴とする半導体装置。   5. A semiconductor device, wherein the semiconductor chip according to claim 1 is mounted on the wiring board in a mechanically and electrically connected manner via the metal bumps.
JP2008036749A 2008-02-19 2008-02-19 Semiconductor chip and semiconductor device Pending JP2009200067A (en)

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Cited By (7)

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WO2011058680A1 (en) * 2009-11-12 2011-05-19 パナソニック株式会社 Semiconductor device
JP2012253058A (en) * 2011-05-31 2012-12-20 Mitsubishi Electric Corp Semiconductor device
CN107346743A (en) * 2016-05-06 2017-11-14 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and its manufacture method
CN110379717A (en) * 2015-12-31 2019-10-25 台湾积体电路制造股份有限公司 Connecting-piece structure and forming method thereof
US10461049B2 (en) 2015-12-14 2019-10-29 Mitsubishi Electric Corporation Semiconductor device and manufacturing method therefor
US10693438B2 (en) 2017-01-05 2020-06-23 Samsung Electro-Mechanics Co., Ltd. Acoustic wave resonator and method for manufacturing the same
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011058680A1 (en) * 2009-11-12 2011-05-19 パナソニック株式会社 Semiconductor device
JP2012253058A (en) * 2011-05-31 2012-12-20 Mitsubishi Electric Corp Semiconductor device
US10461049B2 (en) 2015-12-14 2019-10-29 Mitsubishi Electric Corporation Semiconductor device and manufacturing method therefor
CN110379717A (en) * 2015-12-31 2019-10-25 台湾积体电路制造股份有限公司 Connecting-piece structure and forming method thereof
US10861811B2 (en) 2015-12-31 2020-12-08 Taiwan Semiconductor Manufacturing Company Ltd. Connector structure and method of forming same
CN110379717B (en) * 2015-12-31 2021-06-15 台湾积体电路制造股份有限公司 Connector structure and forming method thereof
US11824026B2 (en) 2015-12-31 2023-11-21 Taiwan Semiconductor Manufacturing Company Ltd. Connector structure and method of forming same
CN107346743A (en) * 2016-05-06 2017-11-14 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and its manufacture method
US10693438B2 (en) 2017-01-05 2020-06-23 Samsung Electro-Mechanics Co., Ltd. Acoustic wave resonator and method for manufacturing the same
JP2021034557A (en) * 2019-08-23 2021-03-01 三菱電機株式会社 Semiconductor device
JP7226186B2 (en) 2019-08-23 2023-02-21 三菱電機株式会社 semiconductor equipment

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