JP4963890B2 - Resin-sealed circuit device - Google Patents

Resin-sealed circuit device Download PDF

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Publication number
JP4963890B2
JP4963890B2 JP2006207092A JP2006207092A JP4963890B2 JP 4963890 B2 JP4963890 B2 JP 4963890B2 JP 2006207092 A JP2006207092 A JP 2006207092A JP 2006207092 A JP2006207092 A JP 2006207092A JP 4963890 B2 JP4963890 B2 JP 4963890B2
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resin
semiconductor device
chip electronic
solder
electronic component
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JP2008016785A (en
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岳彦 甲斐
道夫 村井田
雅哉 島村
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Wire Bonding (AREA)

Description

本発明は、コンデンサ、インダクタ、抵抗器等のチップ電子部品を実装した回路基板上に、半導体装置を実装して、外装樹脂にて封止した回路装置に関するものである。  The present invention relates to a circuit device in which a semiconductor device is mounted on a circuit board on which chip electronic components such as a capacitor, an inductor, and a resistor are mounted and sealed with an exterior resin.

近年、電子機器の小型化及び高機能化に伴い、各種の機能をモジュール化した回路装置が採用されている。このような回路装置は、例えば、特開２００５−１２３９０９号公報にあるように、配線基板上にＩＣ等の半導体装置とコンデンサ、インダクタや抵抗器等のチップ電子部品とを実装して構成される。半導体装置は半田バンプやＡｕバンプ等でフリップチップ実装される。  2. Description of the Related Art In recent years, circuit devices in which various functions are modularized have been adopted as electronic devices have become smaller and more sophisticated. Such a circuit device is configured, for example, by mounting a semiconductor device such as an IC and a chip electronic component such as a capacitor, an inductor, or a resistor on a wiring board as disclosed in JP-A-2005-123909. . The semiconductor device is flip-chip mounted with solder bumps, Au bumps, or the like.

また、近年では、さらなる小型化を目的として、例えば特開２００２−２４６７４５号公報に示すように、部品を実装した基板にスペーサーを配置してその上に別の基板を積み重ねて半導体装置を実装する方法や、特開２００４−２４７６３７号公報に示すように、フリップチップ実装用の半田バンプをスペーサーとして、チップ部品を実装したその上に半導体装置を実装する三次元実装が採用されている。  In recent years, for the purpose of further miniaturization, for example, as shown in Japanese Patent Application Laid-Open No. 2002-246745, a spacer is arranged on a substrate on which components are mounted, and another substrate is stacked thereon to mount a semiconductor device. As shown in Japanese Patent Application Laid-Open No. 2004-247637, three-dimensional mounting in which a semiconductor device is mounted on a chip component mounted thereon using a solder bump for flip chip mounting as a spacer is employed.

また、半導体装置としてはベアチップＩＣ（シリコンウェハから切り出したままのＩＣチップ）やＣＳＰ（Ｃｈｉｐ−Ｓｉｚｅ−Ｐａｃｋａｇｅ）等の再配線されたＩＣが用いられている。  Further, as a semiconductor device, a re-wired IC such as a bare chip IC (an IC chip cut out from a silicon wafer) or a CSP (Chip-Size-Package) is used.

特開２００５−１２３９０９号公報JP 2005-123909 A 特開２００２−２４６７４５号公報JP 2002-246745 A 特開２００４−２４７６３７号公報Japanese Patent Application Laid-Open No. 2004-247637

半導体装置を配線基板に実装した場合、半導体装置と配線基板との間に空間が生じる。例えばバンプによるフリップチップ実装では、バンプの高さ分の空間が生じる。また、三次元実装の場合、半導体装置下のチップ電子部品間の空間が生じる。回路装置を外装用樹脂で被覆する場合、外装用樹脂の粘度やフィラー含有量によっては、上記のような空間に樹脂が充填されないことがあった。回路装置にかかる機械応力や熱応力を緩和するためにこの空間に樹脂を充填することが必要であるため、外装用樹脂に用いる樹脂よりも低粘度かつ低フィラー充填率の樹脂をアンダーフィルとして用い、上記のような空間への樹脂の充填が行われてきた。  When the semiconductor device is mounted on the wiring board, a space is generated between the semiconductor device and the wiring board. For example, in flip chip mounting using bumps, a space corresponding to the height of the bumps is generated. In the case of three-dimensional mounting, a space between chip electronic components under the semiconductor device is generated. When a circuit device is covered with an exterior resin, the space may not be filled with the resin depending on the viscosity of the exterior resin and the filler content. Since it is necessary to fill this space with resin in order to relieve mechanical stress and thermal stress applied to the circuit device, a resin having a lower viscosity and a lower filler filling rate than the resin used for the exterior resin is used as the underfill. The filling of the resin into the space as described above has been performed.

しかしながら、このアンダーフィル用の樹脂は、外装用樹脂よりも低粘度かつ低フィラー充填率であるため、硬化時の収縮率が大きい。また、硬化後も回路装置として実装される際のリフロー（二次リフロー）時の熱によってアンダーフィル用の樹脂は収縮しようとするが、その際の収縮も外装用樹脂よりも大きくなる。そのため、図３に示すように、アンダーフィル６用の樹脂とチップ電子部品４との界面及びアンダーフィル６用の樹脂と配線基板２との界面で剥離が発生してしまう。  However, since this underfill resin has a lower viscosity and a lower filler filling rate than the exterior resin, the shrinkage rate upon curing is large. Further, the resin for underfill tends to shrink due to heat during reflow (secondary reflow) when mounted as a circuit device even after curing, but the shrinkage at that time is larger than that of the exterior resin. Therefore, as shown in FIG. 3, peeling occurs at the interface between the resin for the underfill 6 and the chip electronic component 4 and at the interface between the resin for the underfill 6 and the wiring board 2.

このような剥離が発生した場合、二次リフロー時にチップ電子部品４を配線基板２に接合している半田９が再溶融し、この剥離部分に半田の溶融流出１０が起こる。流れ出した半田は、他のチップ電子部品または半導体装置３の端子に達して短絡を起こしてしまう。  When such peeling occurs, the solder 9 that joins the chip electronic component 4 to the wiring board 2 at the time of secondary reflow is re-melted, and a melt outflow 10 of the solder occurs at this peeled portion. The solder that has flowed out reaches the other chip electronic component or the terminal of the semiconductor device 3 and causes a short circuit.

このような問題を解消するために、フリップチップ実装の場合では、図４に示すように、アンダーフィル６の必要な半導体装置３とチップ電子部品４との間隔Ｇを空けて、チップ電子部品４にアンダーフィル６がかからないようにする方法がある。しかし、この間隔Ｇにより回路装置１の小型化が困難になってしまうという問題があった。また、アンダーフィル６をチップ電子部品４にかからないようにするために樹脂の粘度やフィラー充填率、塗布量等の調整に高い精度が要求されるため、コストがかかるという問題があった。  In order to solve such a problem, in the case of flip chip mounting, as shown in FIG. 4, the gap G between the semiconductor device 3 that requires the underfill 6 and the chip electronic component 4 is provided, and the chip electronic component 4 is removed. There is a method to prevent underfill 6 from being applied. However, there is a problem that it is difficult to reduce the size of the circuit device 1 due to the gap G. In addition, in order to prevent the underfill 6 from being applied to the chip electronic component 4, high accuracy is required for adjusting the viscosity of the resin, the filler filling rate, the coating amount, and the like.

本発明は、上記のような問題を解決して、二次リフロー時の短絡の発生が少なく、より小型の樹脂封止回路装置を低コストで得るものである。  The present invention solves the above-described problems and provides a smaller resin-encapsulated circuit device at a lower cost with less occurrence of short circuit during secondary reflow.

本発明は、第一の発明として、配線基板と、前記配線基板上に実装された半導体装置と、前記半導体装置の周囲に配置されたランドに半田接合された１つ以上のチップ電子部品と、前記半導体装置及び前記チップ電子部品を被覆する外装樹脂と、を有する樹脂封止回路装置において、前記半導体装置の下面と前記配線基板との空間と、前記チップ電子部品の少なくとも一部に接する部分と、に外装樹脂よりも低粘度かつ低フィラー充填率である樹脂からなるアンダーフィルが形成されており、前記アンダーフィルが形成されている部分の前記チップ電子部品の半田接合に、１度目の加熱による溶融温度よりも再度加熱した時の溶融温度が高くなる半田が用いられていることを特徴とする樹脂封止回路装置を提案する。この発明に用いられる半田は、一度目の加熱のよって溶融する溶融成分と、この溶融成分と合金化する母材を含むもので、一度目の溶融により溶融成分と母材が全てまたは部分的に合金化し、溶融成分がなくなるかまたは減少することによって、全体として溶融温度が高くなって溶融しにくくなるものである。 The present invention provides, as a first invention, a wiring board, a semiconductor device mounted on the wiring board, one or more chip electronic components solder-bonded to lands disposed around the semiconductor device, In a resin-encapsulated circuit device having an exterior resin covering the semiconductor device and the chip electronic component, a space between the lower surface of the semiconductor device and the wiring board, and a portion in contact with at least a part of the chip electronic component; The underfill made of a resin having a lower viscosity and a lower filler filling rate than the exterior resin is formed, and the soldering of the chip electronic component in the portion where the underfill is formed is performed by the first heating. The present invention proposes a resin-encapsulated circuit device characterized by using solder whose melting temperature becomes higher when heated again than the melting temperature. The solder used in the present invention includes a molten component that is melted by the first heating and a base material that is alloyed with the molten component, and the molten component and the base material are wholly or partly melted by the first melting. By alloying and eliminating or reducing the melting component, the melting temperature becomes high as a whole and it becomes difficult to melt.

上記第一の発明によれば、半導体装置周囲のチップ電子部品にアンダーフィルがかからないようにするための間隔を必要としないので、より小型化された回路装置を得ることができる。また、二次リフロー時に半田の再溶融が起こりにくいので、アンダーフィルに剥離が生じても、半田の溶融流出による短絡の発生を防止することができる。  According to the first aspect of the present invention, there is no need for an interval for preventing underfilling of the chip electronic components around the semiconductor device, so that a more compact circuit device can be obtained. In addition, since remelting of the solder hardly occurs at the time of secondary reflow, even if the underfill is peeled off, it is possible to prevent occurrence of a short circuit due to melting out of the solder.

また、本発明では、第二の発明として、配線基板と、前記配線基板上のランドに半田接合された１つ以上のチップ電子部品と、前記チップ電子部品の一部の上に実装された半導体装置と、前記半導体装置及び前記チップ電子部品とを被覆する外装樹脂と、を有する樹脂封止回路装置において、前記半導体装置の下面と前記配線基板との間に、外装樹脂よりも低粘度かつ低フィラー充填率である樹脂からなるアンダーフィルが形成されており、前記アンダーフィルが形成されている部分の前記チップ電子部品の半田接合に、１度目の加熱による溶融温度よりも再度加熱した時の溶融温度が高くなる半田が用いられていることを特徴とする樹脂封止回路装置を提案する。 In the present invention, as a second invention, a wiring board, one or more chip electronic components solder-bonded to a land on the wiring board, and a semiconductor mounted on a part of the chip electronic component In a resin-encapsulated circuit device having a device and an exterior resin that covers the semiconductor device and the chip electronic component, a lower viscosity and lower than the exterior resin are provided between the lower surface of the semiconductor device and the wiring board. An underfill made of a resin having a filler filling rate is formed, and the melting when the soldering of the chip electronic component in the portion where the underfill is formed is heated again from the melting temperature by the first heating. The present invention proposes a resin-encapsulated circuit device characterized by using solder whose temperature increases.

上記第二の発明によれば、三次元実装の半導体装置の下に実装されているチップ電子部品の間に充填されたアンダーフィルに剥離が生じても、半田の溶融流出による短絡の発生を防止することができる。  According to the second aspect of the present invention, even if peeling occurs in the underfill filled between the chip electronic components mounted under the three-dimensionally mounted semiconductor device, occurrence of a short circuit due to melting out of the solder is prevented. can do.

以上のように、本発明によれば、アンダーフィルの形成に、粘度やフィラー充填率、塗布量等に高い精度を要求されず、アンダーフィルがチップ電子部品にかからないようにする必要もないので、樹脂封止回路装置を低コストで得ることができる。また、チップ電子部品にアンダーフィルがかからないようにするための間隔を必要としないので、より小型化された回路装置を得ることができる。また、二次リフロー時に半田の再溶融が起こりにくいので、アンダーフィルに剥離が生じても、半田の溶融流出による短絡を生じない。  As described above, according to the present invention, the formation of the underfill does not require high accuracy in viscosity, filler filling rate, coating amount, etc., and it is not necessary to prevent the underfill from being applied to the chip electronic component. A resin-sealed circuit device can be obtained at low cost. In addition, since an interval for preventing underfill from being applied to the chip electronic component is not required, a more miniaturized circuit device can be obtained. Further, since remelting of the solder hardly occurs during the secondary reflow, even if the underfill is peeled off, a short circuit due to the melting out of the solder does not occur.

本発明に係る樹脂封止回路装置の第一の実施形態を、以下に説明する。図１は樹脂封止回路装置の横式断面図である。回路装置１は、配線基板２上に半導体装置３及びチップ電子部品４を実装している。半導体装置３は、配線基板２上に形成されているランド７とバンプ８で接合され、チップ電子部品４はランド７とリフロー半田９によって接合されている。半導体装置３と配線基板２の間の空間に、アンダーフィル６が形成されており、このアンダーフィル６は半導体装置３付近のチップ電子部品４にかかっている。半導体装置３チップ電子部品４及びアンダーフィル６が形成されている面には、さらに外装樹脂５が被覆されている。配線基板２の外周部には外部回路と接続するための導電端子（図示せず）が形成されている。  A first embodiment of a resin-encapsulated circuit device according to the present invention will be described below. FIG. 1 is a horizontal sectional view of a resin-sealed circuit device. In the circuit device 1, a semiconductor device 3 and a chip electronic component 4 are mounted on a wiring board 2. The semiconductor device 3 is bonded to the lands 7 formed on the wiring board 2 by bumps 8, and the chip electronic component 4 is bonded to the lands 7 by reflow solder 9. An underfill 6 is formed in a space between the semiconductor device 3 and the wiring substrate 2, and the underfill 6 is applied to the chip electronic component 4 in the vicinity of the semiconductor device 3. The surface on which the semiconductor device 3 chip electronic component 4 and the underfill 6 are formed is further covered with an exterior resin 5. Conductive terminals (not shown) for connecting to an external circuit are formed on the outer periphery of the wiring board 2.

チップ電子部品４は、例えば整合回路やフィルター回路などを形成するために回路基板２上に必要種類のものが必要個数実装される。しかし、回路基板２上に実装されるチップ電子部品４は一個でも良い。  For example, a necessary number of chip electronic components 4 are mounted on the circuit board 2 to form a matching circuit, a filter circuit, and the like. However, only one chip electronic component 4 may be mounted on the circuit board 2.

外装樹脂５とアンダーフィル６は、例えばエポキシ樹脂などの熱硬化性樹脂に、シリカやアルミナ等のフィラーを充填したものを用いる。アンダーフィル６には、例えば粘度は外装樹脂５の７０％、フィラー充填率は外装樹脂５の７０％など、外装樹脂５よりも低粘度かつ低フィラー充填率のものを用いる。アンダーフィル６は、図１に示すように、半導体装置３と配線基板２との間の空間及びその周囲に形成されるが、配線基板２の部品実装面全面に形成しても良い。  As the exterior resin 5 and the underfill 6, for example, a thermosetting resin such as an epoxy resin filled with a filler such as silica or alumina is used. For the underfill 6, for example, a material having a viscosity lower than that of the exterior resin 5 and a lower filler filling ratio such as 70% of the viscosity of the exterior resin 5 and 70% of the filler resin 5 of the exterior resin 5 is used. As shown in FIG. 1, the underfill 6 is formed in and around the space between the semiconductor device 3 and the wiring board 2, but may be formed over the entire component mounting surface of the wiring board 2.

半導体装置３と配線基板２との接合は、バンプ８で行われる。バンプ接合としては、例えば超音波接合によるＡｕバンプや、リフローによる半田バンプ接合が挙げられる。また、チップ電子部品４と配線基板２との接合は、リフローによる半田９によって行われる。ここで、半田バンプによる半導体装置３の接合及びチップ電子部品４の接合に用いる半田として、本発明では１度目の加熱による溶融温度よりも再度加熱した時の溶融温度が高くなる半田を用いる。具体的に言えば、配線基板２上に半導体装置３及びチップ電子部品４を実装するときのリフロー（一次リフロー）では通常のリフロー温度である２９０℃以下詳しくは２５０℃付近の温度で溶融し、回路装置として外部回路に実装されるときのリフロー（二次リフロー）では合金化して融点が上昇して溶融しにくくなる半田を用いる。  Bonding of the semiconductor device 3 and the wiring board 2 is performed by the bumps 8. Examples of the bump bonding include Au bumps by ultrasonic bonding and solder bump bonding by reflow. Further, the chip electronic component 4 and the wiring board 2 are joined by solder 9 by reflow. Here, as the solder used for joining the semiconductor device 3 by the solder bumps and joining the chip electronic component 4, in the present invention, solder whose melting temperature is higher when heated again than the melting temperature by the first heating is used. Specifically, in the reflow (primary reflow) when mounting the semiconductor device 3 and the chip electronic component 4 on the wiring board 2, it is melted at a normal reflow temperature of 290 ° C. or lower, more specifically, at a temperature around 250 ° C. In reflow (secondary reflow) when mounted on an external circuit as a circuit device, solder that is alloyed to increase the melting point and hardly melt is used.

このような半田材としては、例えば溶融成分としてＳｎ−Ａｇ−Ｃｕ系合金粉、母材としてＣｕ粉を混合させた接合材が挙げられる。このような半田材は、アンダーフィル６が形成される領域にある半導体装置３とチップ電子部品４の接合のみにもちいても足りるが、全部の部品の実装に用いても良い。  As such a solder material, for example, a bonding material in which Sn—Ag—Cu-based alloy powder as a melting component and Cu powder as a base material are mixed can be cited. Such a solder material may be used only for joining the semiconductor device 3 and the chip electronic component 4 in the region where the underfill 6 is formed, but may be used for mounting all components.

上記の構成であれば、まず、二次リフロー時に半田の再溶融が起こらないので、半田の溶融流出による短絡が防止される。また、アンダーフィル６の剥離が起こっても半田の溶融流出の発生がない。そのためアンダーフィル６の形成に関して粘度やフィラー充填率、塗布量等に高い精度を要求しなくてもよく、全面に形成してもよくなる。これにより、回路装置１の製造コストを低減することが可能となる。また、半導体装置３とチップ電子部品４を近接させて実装してもよくなるので、回路装置１をより小型化することが可能となる。  If it is said structure, since the remelting of solder does not occur first at the time of secondary reflow, the short circuit by the melting outflow of solder is prevented. Moreover, even if the underfill 6 is peeled off, there is no occurrence of melting out of the solder. Therefore, the formation of the underfill 6 does not need to require high accuracy in viscosity, filler filling rate, coating amount, etc., and may be formed over the entire surface. Thereby, the manufacturing cost of the circuit device 1 can be reduced. Further, since the semiconductor device 3 and the chip electronic component 4 may be mounted close to each other, the circuit device 1 can be further downsized.

なお、配線基板２は、通常ランド７の部分を除いてソルダーレジストが形成されている。これにより、接合部に供給した半田の過剰な配線部への濡れ拡がりや、配線間の絶縁性低下を防止することができる。しかし、半田ペーストを印刷供給する際に、ソルダーレジストによって生ずる段差によって、印刷性が悪化する場合がある。この様な場合、本発明で使用している半田の使用により過剰な配線部への濡れ拡がりを少なくすることができるため、配線基板２として配線同士または配線とランドが近接している部分や配線とランドとの境界付近以外のソルダーレジストを除去したものを用いることができる。この様な配線基板を用いることによってレジストの段差による印刷性の低下を防止することや配線基板の製造コストの削減が可能となる。  Note that the solder resist is formed on the wiring board 2 except for the normal land 7 portion. As a result, it is possible to prevent wetting and spreading of the solder supplied to the joint part to the excessive wiring part and a decrease in insulation between the wirings. However, when the solder paste is printed and supplied, the printability may be deteriorated due to a step generated by the solder resist. In such a case, the use of the solder used in the present invention can reduce excessive wetting and spreading to the wiring portion. It is possible to use a solder resist other than the vicinity of the boundary between the land and the land. By using such a wiring board, it is possible to prevent a decrease in printability due to a resist step and to reduce the manufacturing cost of the wiring board.

次に、本発明に係る樹脂封止回路装置の第二の実施形態を、以下に説明する。図２は三次元実装で構成された樹脂封止回路装置の模式断面図である。回路装置１１は、配線基板１２上に複数のチップ電子部品１４が実装している。この複数のチップ電子部品１４のうちの一部の上に半導体装置１３がダイアタッチフィルム等の接着フィルム（図示せず）によって実装されている。この半導体装置１３は、配線基板２上に形成されているランド１７とワイヤ１８で電気的に接続されている。チップ電子部品１４はランド１７とリフロー半田１９によって接合されている。半導体装置３と配線基板２の間の空間に、アンダーフィル１６が形成されており、このアンダーフィル１６は半導体装置３の下のチップ電子部品１４を覆っている。半導体装置１３、チップ電子部品１４及びアンダーフィル１６が形成されている面には、さらに外装樹脂１５が被覆されている。配線基板１２の外周部には外部回路と接続するための導電端子（図示せず）が形成されている。  Next, a second embodiment of the resin-encapsulated circuit device according to the present invention will be described below. FIG. 2 is a schematic cross-sectional view of a resin-encapsulated circuit device configured by three-dimensional mounting. In the circuit device 11, a plurality of chip electronic components 14 are mounted on a wiring board 12. A semiconductor device 13 is mounted on a part of the plurality of chip electronic components 14 with an adhesive film (not shown) such as a die attach film. The semiconductor device 13 is electrically connected to the lands 17 formed on the wiring board 2 by wires 18. The chip electronic component 14 is bonded to the land 17 by reflow solder 19. An underfill 16 is formed in a space between the semiconductor device 3 and the wiring substrate 2, and the underfill 16 covers the chip electronic component 14 under the semiconductor device 3. The surface on which the semiconductor device 13, the chip electronic component 14, and the underfill 16 are formed is further covered with an exterior resin 15. Conductive terminals (not shown) for connection to an external circuit are formed on the outer peripheral portion of the wiring board 12.

本実施形態では、半導体装置１３の下のチップ電子部品１４と、配線基板１２との接合に用いられる半田１９として、１度目の加熱による溶融温度よりも再度加熱した時の溶融温度が高くなる半田を用いる。半導体装置１３の下はアンダーフィル１６が形成されるので、従来の半田では半田の溶融流出による短絡が起こる可能性がある。よって、１度目の加熱による融点よりも再度加熱した時の融点が高くなる半田を用いることによってこのような問題を解決することができる。  In the present embodiment, the solder 19 used for joining the chip electronic component 14 under the semiconductor device 13 and the wiring board 12 has a higher melting temperature when heated again than the melting temperature due to the first heating. Is used. Since the underfill 16 is formed under the semiconductor device 13, there is a possibility that a short circuit occurs due to melting and outflow of the solder in the conventional solder. Therefore, such a problem can be solved by using solder whose melting point becomes higher when heated again than the melting point caused by the first heating.

以上より、本発明によれば、短絡等の故障の少ない信頼性の高い小型の樹脂封止回路装置を低コストで得ることができる。なお、本発明の実施形態は上記の例に限定されるものではなく、本発明の範囲内で、１度目の加熱による融点よりも再度加熱した時の融点が高くなる半田とアンダーフィルの組み合わせであれば種々の変形例も含まれる。  As described above, according to the present invention, it is possible to obtain a small resin-sealed circuit device with high reliability with few failures such as a short circuit at a low cost. The embodiment of the present invention is not limited to the above example, and within the scope of the present invention, it is a combination of solder and underfill that has a higher melting point when heated again than the melting point by the first heating. Various modifications are also included, if any.

樹脂封止回路装置の模式断面図である。It is a schematic cross section of a resin sealing circuit device. 三次元実装で構成された樹脂封止回路装置の模式断面図である。It is a schematic cross section of the resin-sealed circuit device configured by three-dimensional mounting. 従来の樹脂封止回路装置の問題点を示す断面の拡大図である。It is an enlarged view of a section showing a problem of a conventional resin-encapsulated circuit device. 従来の樹脂封止回路装置の問題点を示す断面の拡大図である。It is an enlarged view of a section showing a problem of a conventional resin-encapsulated circuit device.

符号の説明Explanation of symbols

１、１１ 回路装置
２、１２ 配線基板
３、１３ 半導体装置
４、１４ チップ電子部品
５、１５ 外装樹脂
６、１６ アンダーフィル
７、１７ ランド
８ バンプ
９、１９ 半田
１０ 半田の溶融流出
１８ ワイヤDESCRIPTION OF SYMBOLS 1, 11 Circuit device 2, 12 Wiring board 3, 13 Semiconductor device 4, 14 Chip electronic component 5, 15 Exterior resin 6, 16 Underfill 7, 17 Land 8 Bump 9, 19 Solder 10 Solder melt outflow 18 Wire

Claims (2)

配線基板と、前記配線基板上に実装された半導体装置と、前記半導体装置の周囲に配置されたランドに半田接合された１つ以上のチップ電子部品と、前記半導体装置及び前記チップ電子部品を被覆する外装樹脂と、を有する樹脂封止回路装置において、
前記半導体装置の下面と前記配線基板との空間と、前記チップ電子部品の少なくとも一部に接する部分と、に外装樹脂よりも低粘度かつ低フィラー充填率である樹脂からなるアンダーフィルが形成されており、
前記アンダーフィルが形成されている部分の前記チップ電子部品の半田接合に、１度目の加熱による溶融温度よりも再度加熱した時の溶融温度が高くなる半田が用いられている
ことを特徴とする樹脂封止回路装置。 A wiring substrate; a semiconductor device mounted on the wiring substrate; one or more chip electronic components solder-bonded to lands disposed around the semiconductor device; and the semiconductor device and the chip electronic component are covered In a resin-sealed circuit device having an exterior resin,
An underfill made of a resin having a lower viscosity and a lower filler filling rate than the exterior resin is formed in a space between the lower surface of the semiconductor device and the wiring board and a portion in contact with at least a part of the chip electronic component. And
Resin characterized in that a solder whose melting temperature becomes higher when heated again than the melting temperature by the first heating is used for solder bonding of the chip electronic component in the portion where the underfill is formed Sealed circuit device. 配線基板と、前記配線基板上のランドに半田接合された１つ以上のチップ電子部品と、前記チップ電子部品の一部の上に実装された半導体装置と、前記半導体装置及び前記チップ電子部品を被覆する外装樹脂と、を有する樹脂封止回路装置において、
前記半導体装置の下面と前記配線基板との間に、外装樹脂よりも低粘度かつ低フィラー充填率である樹脂からなるアンダーフィルが形成されており、
前記アンダーフィルが形成されている部分の前記チップ電子部品の半田接合に、１度目の加熱による溶融温度よりも再度加熱した時の溶融温度が高くなる半田が用いられている
ことを特徴とする樹脂封止回路装置。 A wiring substrate, one or more chip electronic components solder-bonded to lands on the wiring substrate, a semiconductor device mounted on a part of the chip electronic component, the semiconductor device and the chip electronic component In a resin-sealed circuit device having an exterior resin to be coated,
Between the lower surface of the semiconductor device and the wiring board, an underfill made of a resin having a lower viscosity than the exterior resin and a low filler filling rate is formed,
Resin characterized in that a solder whose melting temperature becomes higher when heated again than the melting temperature by the first heating is used for solder bonding of the chip electronic component in the portion where the underfill is formed Sealed circuit device.
JP2006207092A 2006-06-30 2006-06-30 Resin-sealed circuit device Expired - Fee Related JP4963890B2 (en)

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