JP2011071378A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2011071378A
JP2011071378A JP2009221977A JP2009221977A JP2011071378A JP 2011071378 A JP2011071378 A JP 2011071378A JP 2009221977 A JP2009221977 A JP 2009221977A JP 2009221977 A JP2009221977 A JP 2009221977A JP 2011071378 A JP2011071378 A JP 2011071378A
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chip
solder bump
terminal
solder
main surface
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Tetsuya Yokoi
哲哉 横井
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To establish excellent face-to-face bump connection regardless of the shape of solder bump. <P>SOLUTION: The semiconductor device 80 includes a first chip 2 and a second chip 3. The first chip 2 is provided to cover a signal terminal 26A provided on a first insulating film, a solder bump 52A provided on the signal terminal 26A, and an aperture 222B formed on the first insulating film, includes a power supply terminal 26B which is larger than the signal terminal 26A and a solder bump 52B which is provided on the power supply terminal 26B, and is placed on a circuit board 1 via a bonding layer 11. The second chip 3 includes a signal terminal 32A provided on a second insulating film, a solder bump 53A provided on the signal terminal 32A, a power supply terminal 32B which is provided on the first insulating film and is larger than the signal terminal 32A, and a solder bump 53B provided on the power supply terminal 32B. The first chip and the second chip are face-to-face bonded with the solder. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

携帯電話、情報端末機器、モバイル機器などでは小型軽量化要求が強い。この要求に対応するために、積層形成された半導体チップが気密封止されたＢＧＡ（Ball Grid Array）、ＬＧＡ（Land Grid Array）、スタックドＭＣＰ（Stacked Multi Chip Package）、ＴＡＢ（Tape Automated Bonding）、ＣＳＰ（Chip Size Package）、ＭＣＭ（Multi Chip Module）などの半導体装置が使用される。回路基板と半導体チップ間、或いは積層形成される半導体チップ間は、半田バンプや金バンプを用いてバンプ接続される。各種電子機器の多機能化、複合化、小型化の進展に伴い、バンプ接続される信号及び電源本数が増加し、形状の異なる半田バンプや金バンプが使用されている（例えば、特許文献１参照。）。   There is a strong demand for miniaturization and weight reduction in cellular phones, information terminal devices, mobile devices, and the like. In order to meet this requirement, BGA (Ball Grid Array), LGA (Land Grid Array), stacked MCP (Stacked Multi Chip Package), TAB (Tape Automated Bonding), in which stacked semiconductor chips are hermetically sealed, Semiconductor devices such as CSP (Chip Size Package) and MCM (Multi Chip Module) are used. A bump connection is made between the circuit board and the semiconductor chip or between the stacked semiconductor chips using solder bumps or gold bumps. With the progress of multifunction, compounding, and miniaturization of various electronic devices, the number of signals connected to bumps and the number of power supplies increase, and solder bumps and gold bumps having different shapes are used (for example, see Patent Document 1). .)

特許文献１に記載される半導体装置では、半田バンプの形状が変化すると、半田バンプ高さが変化する。このため、形状の異なる半田バンプを有する半導体チップをフェースツーフェース（Face to Face）でバンプ接続した場合、半田バンプ間の間隔を一定にすることが困難となるという問題点がある。半田バンプ間の間隔を一定にできないと、近接配置される半田バンプの部分で余分な半田が外に広がり半導体装置のショート不良の危険性が増大する。   In the semiconductor device described in Patent Document 1, when the shape of the solder bump changes, the solder bump height changes. For this reason, when semiconductor chips having solder bumps having different shapes are bump-connected by face-to-face, there is a problem that it is difficult to make the interval between the solder bumps constant. If the interval between the solder bumps cannot be made constant, excess solder spreads out at the solder bump portions arranged close to each other, increasing the risk of a short circuit failure of the semiconductor device.

特開２００４―３４２９０４号公報JP 2004-342904 A

本発明は、半田バンプの形状によらずフェースツーフェースで良好なバンプ接続することができる半導体装置を提供することにある。   An object of the present invention is to provide a semiconductor device capable of good bump connection face-to-face regardless of the shape of solder bumps.

本発明の一態様の半導体装置は、第１の絶縁膜の第１主面上に設けられる第１のチップ端子と、前記第１のチップ端子の第１主面上に設けられる第１の半田バンプと、前記第１の絶縁膜に形成される開口部を覆うように設けられ、前記第１のチップ端子よりも大きい第２のチップ端子と、前記第２のチップ端子の第１主面上に設けられ、前記第１の半田バンプよりも大きい第２の半田バンプとを有する第１のチップと、第２の絶縁膜の第１主面上に設けられる第３のチップ端子と、前記第３のチップ端子の第１主面上に設けられる第３の半田バンプと、前記第２の絶縁膜の第１主面上に設けられ、前記第３のチップ端子よりも大きい第４のチップ端子と、前記第４のチップ端子の第１主面上に設けられ、前記第３の半田バンプよりも大きい第４の半田バンプとを有する第２のチップとを具備し、前記第１の半田バンプと前記第３の半田バンプ、及び前記第２の半田バンプと前記第４の半田バンプがそれぞれフェースツーフェースでバンプ接合され、前記第１のチップと前記第２のチップが封止されていることを特徴とする。   The semiconductor device of one embodiment of the present invention includes a first chip terminal provided on the first main surface of the first insulating film, and a first solder provided on the first main surface of the first chip terminal. Bumps are provided so as to cover the openings formed in the first insulating film, the second chip terminals larger than the first chip terminals, and the first main surface of the second chip terminals A first chip having a second solder bump larger than the first solder bump, a third chip terminal provided on a first main surface of a second insulating film, and the first chip A third solder bump provided on the first main surface of the third chip terminal, and a fourth chip terminal provided on the first main surface of the second insulating film and larger than the third chip terminal Provided on the first main surface of the fourth chip terminal and larger than the third solder bump. A second chip having a plurality of solder bumps, wherein the first solder bump and the third solder bump, and the second solder bump and the fourth solder bump are bumped face-to-face, respectively. The first chip and the second chip are sealed and bonded.

更に、本発明の他態様の半導体装置は、第１の絶縁膜の第１主面上に設けられる第１のチップ端子と、前記第１のチップ端子の第１主面上に設けられる第１の半田バンプと、前記第１の絶縁膜に形成される第１の開口部を覆うように設けられ、前記第１のチップ端子よりも大きい第２のチップ端子と、前記第２のチップ端子の第１主面上に設けられ、前記第１の半田バンプよりも大きい第２の半田バンプとを有する第１のチップと、第２の絶縁膜の第１主面上に設けられる第３のチップ端子と、前記第３のチップ端子の第１主面上に設けられる第３の半田バンプと、前記第２の絶縁膜に形成される第２の開口部を覆うように設けられ、前記第３のチップ端子よりも大きい第４のチップ端子と、前記第４のチップ端子の第１主面上に設けられ、前記第３の半田バンプよりも大きい第４の半田バンプとを有する第２のチップとを具備し、前記第１の半田バンプと前記第３の半田バンプ、及び前記第２の半田バンプと前記第４の半田バンプがそれぞれフェースツーフェースでバンプ接合され、前記第１のチップと前記第２のチップが封止されていることを特徴とする。   Furthermore, a semiconductor device according to another aspect of the present invention includes a first chip terminal provided on the first main surface of the first insulating film, and a first chip provided on the first main surface of the first chip terminal. A solder bump and a first opening formed in the first insulating film so as to cover the second chip terminal larger than the first chip terminal, and the second chip terminal A first chip provided on the first main surface and having a second solder bump larger than the first solder bump, and a third chip provided on the first main surface of the second insulating film A terminal, a third solder bump provided on the first main surface of the third chip terminal, and a second opening formed in the second insulating film; A fourth chip terminal that is larger than the chip terminal, and a first main surface of the fourth chip terminal, And a second chip having a fourth solder bump larger than the third solder bump, the first solder bump, the third solder bump, the second solder bump, and the second solder bump. Each of the four solder bumps is bump-bonded face-to-face, and the first chip and the second chip are sealed.

本発明によれば、半田バンプの形状によらずフェースツーフェースで良好なバンプ接続することができる半導体装置を提供することができる。   According to the present invention, it is possible to provide a semiconductor device capable of performing good bump connection face-to-face regardless of the shape of solder bumps.

本発明の実施例１に係る半導体装置を示す平面図。1 is a plan view showing a semiconductor device according to Embodiment 1 of the present invention. 図１のＡ−Ａ線に沿う半導体装置の断面図。FIG. 2 is a cross-sectional view of the semiconductor device along the line AA in FIG. 1. 本発明の実施例１に係る半田バンプ形状を説明する断面図。Sectional drawing explaining the solder bump shape which concerns on Example 1 of this invention. 本発明の実施例１に係る半田バンプ高さと半田バンプ幅の関係を示す図。The figure which shows the relationship between the solder bump height and solder bump width which concern on Example 1 of this invention. 本発明の実施例４に係るチップ端子直下に開口部を設けた場合の半田バンプ形状を説明する断面図。Sectional drawing explaining the solder bump shape at the time of providing an opening part directly under the chip terminal which concerns on Example 4 of this invention. 本発明の実施例１に係る半田バンプ高さと開口部幅の関係を示す図。The figure which shows the relationship between the solder bump height and opening part width | variety which concern on Example 1 of this invention. 本発明の実施例１に係る半導体装置の製造工程を示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例１に係る半導体装置の製造工程を示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例１に係る半導体装置の製造工程を示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例１に係る半導体装置の製造工程を示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例１に係る半導体装置の製造工程を示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例２に係る半導体装置を示す断面図。Sectional drawing which shows the semiconductor device which concerns on Example 2 of this invention. 本発明の実施例２に係る半導体装置の製造工程を示す断面図。Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 2 of this invention.

以下本発明の実施例について図面を参照しながら説明する。   Embodiments of the present invention will be described below with reference to the drawings.

まず、本発明の実施例１に係る半導体装置について、図面を参照して説明する。図１は半導体装置を示す平面図、図２は図１のＡ−Ａ線に沿う半導体装置の断面図。本実施例では、半田バンプ面積に応じてチップ端子直下の開口部面積を可変し、半田バンプの高さを適宜調整している。   First, a semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing a semiconductor device, and FIG. 2 is a cross-sectional view of the semiconductor device along the line AA in FIG. In this embodiment, the opening area directly under the chip terminal is varied according to the solder bump area, and the height of the solder bump is adjusted appropriately.

図１に示すように、半導体装置８０には、回路基板１、第１のチップ（メモリチップ）２、第２のチップ（logicチップ）３、ボンディングワイヤ４、封止材５、接続端子Ｐａｄ１、及びチップ端子Ｐａｄ１１が設けられる。半導体装置８０は、フェースツーフェース（以降Face to Faceと呼称する）でバンプ接続されるＢＧＡ（Ball Grid Array）である。半導体装置８０は、例えば携帯電話機器に使用される。   As shown in FIG. 1, the semiconductor device 80 includes a circuit board 1, a first chip (memory chip) 2, a second chip (logic chip) 3, a bonding wire 4, a sealing material 5, a connection terminal Pad1, And a chip terminal Pad11. The semiconductor device 80 is a BGA (Ball Grid Array) bump-connected by face-to-face (hereinafter referred to as “Face to Face”). The semiconductor device 80 is used in, for example, a mobile phone device.

第１のチップ（メモリチップ）２は、回路基板１の第１主面（表面）上に載置される。回路基板１の第１主面（表面）上に設けられる接続端子Ｐａｄ１は、第１のチップ（メモリチップ）２の第１主面（表面）上に設けられるチップ端子Ｐａｄ１１とボンディングワイヤ４を介して電気的に接続される。第２のチップ（logicチップ）３は、第１のチップ（メモリチップ）２の第１主面（表面）上に、第１主面（表面）が第１のチップ（メモリチップ）２の第１主面（表面）と相対向するように載置される。第２のチップ（logicチップ）３は、Face to Faceで第１のチップ（メモリチップ）２とバンプ接続される。   The first chip (memory chip) 2 is placed on the first main surface (front surface) of the circuit board 1. The connection terminal Pad 1 provided on the first main surface (front surface) of the circuit board 1 is connected to the chip terminal Pad 11 provided on the first main surface (front surface) of the first chip (memory chip) 2 via the bonding wire 4. Are electrically connected. The second chip (logic chip) 3 has a first main surface (front surface) on the first main surface (front surface) of the first chip (memory chip) 2 and the first main surface (front surface) of the first chip (memory chip) 2. It is placed so as to face one main surface (surface). The second chip (logic chip) 3 is bump-connected to the first chip (memory chip) 2 by Face to Face.

回路基板１、第１のチップ（メモリチップ）２、及び第２のチップ（logicチップ）３は、矩形形状を有する。回路基板１は第１のチップ（メモリチップ）２よりも大きい。第１のチップ（メモリチップ）２は第２のチップ（logicチップ）３よりも大きい。   The circuit board 1, the first chip (memory chip) 2, and the second chip (logic chip) 3 have a rectangular shape. The circuit board 1 is larger than the first chip (memory chip) 2. The first chip (memory chip) 2 is larger than the second chip (logic chip) 3.

回路基板１の第１主面、第１のチップ（メモリチップ）２、第２のチップ（logicチップ）３、ボンディングワイヤ４接続端子Ｐａｄ１、及びチップ端子Ｐａｄ１１は、封止材５で封止される。   The first main surface, the first chip (memory chip) 2, the second chip (logic chip) 3, the bonding wire 4 connection terminal Pad 1 and the chip terminal Pad 11 of the circuit board 1 are sealed with a sealing material 5. The

図２に示すように、回路基板１の第１主面（表面）上に接着層１１を介して第１のチップ（メモリチップ）２が載置される。第１のチップ（メモリチップ）２は、接着層１１により回路基板１に固定される。回路基板１の第１主面（表面）と相対向する第２主面（裏面）上には外部端子としてのボール端子６が複数設けられる。   As shown in FIG. 2, the first chip (memory chip) 2 is placed on the first main surface (front surface) of the circuit board 1 via the adhesive layer 11. The first chip (memory chip) 2 is fixed to the circuit board 1 by an adhesive layer 11. A plurality of ball terminals 6 as external terminals are provided on the second main surface (back surface) opposite to the first main surface (front surface) of the circuit board 1.

第１のチップ（メモリチップ）２には、シリコン基板２０の第１主面（表面）上に図示しない絶縁膜を介して配線層２２が設けられる。配線層２２は、寸法の異なるパターンを有する。配線層２２の両端側には絶縁膜２１が設けられる。絶縁膜２１及び配線層２２の第１主面（表面）上には、絶縁膜２３が設けられる。   In the first chip (memory chip) 2, a wiring layer 22 is provided on the first main surface (front surface) of the silicon substrate 20 via an insulating film (not shown). The wiring layer 22 has patterns with different dimensions. Insulating films 21 are provided on both ends of the wiring layer 22. An insulating film 23 is provided on the first main surface (front surface) of the insulating film 21 and the wiring layer 22.

絶縁膜２３には、大きさの異なる開口部２２２Ａと開口部２２２Ｂが設けられる。開口部２２２Ｂは、開口部２２２Ａよりも大きい。開口部２２２Ａは、直下の配線層２２と同じ大きさを有する。開口部２２２Ｂは、直下の配線層２２よりも小さく、且つ内側に形成される。開口部２２２Ａには、配線層２４が設けられる。開口部２２２Ｂには、電源端子２６Ｂとして用いられる配線層２４が開口部２２２Ｂを覆うように設けられる（配線層２４の端部が絶縁膜２３上にせり出すように設けられる）。   The insulating film 23 is provided with an opening 222A and an opening 222B having different sizes. The opening 222B is larger than the opening 222A. The opening 222A has the same size as the wiring layer 22 immediately below. The opening 222B is smaller than the wiring layer 22 directly below and is formed inside. The wiring layer 24 is provided in the opening 222A. In the opening 222B, the wiring layer 24 used as the power supply terminal 26B is provided so as to cover the opening 222B (provided so that the end of the wiring layer 24 protrudes onto the insulating film 23).

絶縁膜２３の第１主面（表面）上に信号端子２６Ａとしての配線層２４が設けられる。配線層２４の両端側には絶縁膜２５が設けられる。つまり、信号端子２６Ａは電源端子２６Ｂよりも小さく、且つ絶縁膜２３の第１主面（表面）上に設けられ、直下には開口部２２２Ａが設けられていない。一方、電源端子２６Ｂは信号端子２６Ａよりも大きく、且つ開口部２２２Ｂを覆うように設けられ、底部が信号端子２６Ａよりも高さが低くなっている。   A wiring layer 24 as a signal terminal 26 </ b> A is provided on the first main surface (front surface) of the insulating film 23. Insulating films 25 are provided on both ends of the wiring layer 24. That is, the signal terminal 26A is smaller than the power supply terminal 26B, is provided on the first main surface (front surface) of the insulating film 23, and the opening 222A is not provided immediately below. On the other hand, the power terminal 26B is larger than the signal terminal 26A and is provided so as to cover the opening 222B, and the bottom is lower than the signal terminal 26A.

第２のチップ（logicチップ）３には、シリコン基板３０の第１主面（表面）上に図示しない絶縁膜を介して信号端子３２Ａとしての配線層２２と電源端子３２Ｂとしての配線層２２が設けられる。配線層２２の両端側には絶縁膜３１が設けられる。電源端子３２Ｂは信号端子３２Ａよりも大きい。第２のチップ（logicチップ）３の第１主面（表面）と相対向する第２主面（裏面）上には、封止材５が設けられる。   The second chip (logic chip) 3 includes a wiring layer 22 as a signal terminal 32A and a wiring layer 22 as a power supply terminal 32B on an insulating film (not shown) on the first main surface (front surface) of the silicon substrate 30. Provided. Insulating films 31 are provided on both ends of the wiring layer 22. The power supply terminal 32B is larger than the signal terminal 32A. A sealing material 5 is provided on a second main surface (back surface) opposite to the first main surface (front surface) of the second chip (logic chip) 3.

第１のチップ（メモリチップ）２の信号端子２６Ａと第２のチップ（logicチップ）３の信号端子３２Ａは、半田接合部１１１ＡによりFace to Faceでバンプ接続される。第１のチップ（メモリチップ）２の電源端子２６Ｂと第２のチップ（logicチップ）３の電源端子３２Ｂは、半田接合部１１１ＢによりFace to Faceでバンプ接続される。半田接合部１１１Ａ及び半田接合部１１１Ｂの周囲にはアンダーフィル樹脂１２が充填される。   The signal terminal 26A of the first chip (memory chip) 2 and the signal terminal 32A of the second chip (logic chip) 3 are bump-connected face-to-face by a solder joint 111A. The power supply terminal 26B of the first chip (memory chip) 2 and the power supply terminal 32B of the second chip (logic chip) 3 are bump-connected face-to-face by a solder joint 111B. The underfill resin 12 is filled around the solder joint portion 111A and the solder joint portion 111B.

なお、第１のチップ（メモリチップ）２には図示しない接地端子が設けられる。接地端子は、信号端子よりも大きく、且つ直下に開口部が設けられる。第１のチップ（メモリチップ）２の接地端子と第２のチップ（logicチップ）３の接地端子は、図示しない半田接合部よりFace to Faceでバンプ接続される。半導体装置８０に、形状に異なる半田接合部を複数設ける理由は、電子機器の多機能化、複合化、小型化の進展に伴い、バンプ接続される信号及び電源本数の増加に対応するためである。信号端子には、比較的少ない電流が流れ、電源端子や接地端子には比較的大きい電流が流れる。このため、信号端子の形状やピッチを小さくすることにより、信号端子数を増大させることができる。   The first chip (memory chip) 2 is provided with a ground terminal (not shown). The ground terminal is larger than the signal terminal, and an opening is provided immediately below. The ground terminal of the first chip (memory chip) 2 and the ground terminal of the second chip (logic chip) 3 are bump-connected by face-to-face from a solder joint (not shown). The reason why a plurality of solder joints having different shapes are provided in the semiconductor device 80 is to cope with an increase in the number of signals and power supplies to be bump-connected with the progress of multi-function, composite, and miniaturization of electronic devices. . A relatively small current flows through the signal terminal, and a relatively large current flows through the power supply terminal and the ground terminal. For this reason, the number of signal terminals can be increased by reducing the shape and pitch of the signal terminals.

ここで、ボール端子６には、Ｐｂ（鉛）フリー半田を用いているが、金（Ａｕ）などを代わりに用いてもよい。回路基板１は、積層形成されるガラスエポキシ基板（ガラエポ基板とも呼称される）を用いている。配線層２２には、Ａｌ（アルミニウム）配線を用いている。配線層２４には、Ｃｕ（銅）配線を用いている。   Here, Pb (lead) free solder is used for the ball terminal 6, but gold (Au) or the like may be used instead. The circuit board 1 uses a laminated glass epoxy substrate (also called a glass epoxy substrate). Al (aluminum) wiring is used for the wiring layer 22. For the wiring layer 24, Cu (copper) wiring is used.

次に、半田バンプの形状について図３乃至図６を参照して説明する。図３は半田バンプの形状を説明する断面図、図４は半田バンプ高さと半田バンプ幅の関係を示す図、図５はチップ端子直下に開口部を設けた場合の半田バンプの形状を説明する断面図、図６は半田バンプ高さと開口部の関係を示す図である。   Next, the shape of the solder bump will be described with reference to FIGS. 3 is a cross-sectional view illustrating the shape of the solder bump, FIG. 4 is a diagram illustrating the relationship between the solder bump height and the solder bump width, and FIG. 5 is a diagram illustrating the shape of the solder bump when an opening is provided immediately below the chip terminal. FIG. 6 is a sectional view showing the relationship between the solder bump height and the opening.

図３に示すように、チップ端子上に、例えばメッキ法で形成された半田をリフロー加熱し、半田バンプを形成した場合、半田バンプ幅が変化すると半田バンプ高さも変化する（ここでは、半田バンプ長は一定としている）。半田バンプ幅Ｗ１、半田バンプ幅Ｗ２、半田バンプ幅Ｗ３の関係が、
W1＜W2＜W3・・・・・・・・・・・・・・・・式（１）
と設定されると、
半田バンプ高さＨ１、半田バンプ高さＨ２、半田バンプ高さＨ３の関係が、
H1＜H2＜H3・・・・・・・・・・・・・・・・式（２）
となる。 As shown in FIG. 3, when solder bumps are formed on a chip terminal by reflow heating, for example, by plating, the solder bump height changes as the solder bump width changes (here, the solder bumps). The length is constant). The relationship between the solder bump width W1, the solder bump width W2, and the solder bump width W3 is
W1 <W2 <W3 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (1)
Is set,
The relationship between the solder bump height H1, the solder bump height H2, and the solder bump height H3 is
H1 <H2 <H3 ... Formula (2)
It becomes.

なお、メッキ法以外、例えば半田ペーストや半田蒸着法の用いた場合でも同様な傾向があり、チップ端子が大きくなると半田バンプが高くなる。   In addition to the plating method, there is a similar tendency even when, for example, a solder paste or a solder vapor deposition method is used, and the solder bump becomes higher as the chip terminal becomes larger.

図４に示すように、半田バンプ幅或いは半田バンプ面積が比較的大きな領域では、半田バンプ高さが一定である。半田バンプ幅或いは半田バンプ面積が徐々に小さくなると、半田バンプ高さが低下し始める。半田バンプ幅が例えば、２０μになると、半田バンプ幅が大きな領域（例えば、１００μｍ）と比較して半田バンプ高さが２．５μｍ低下する。半田バンプ幅が２０μｍ以下になると、半田バンプ高さはより低下する。   As shown in FIG. 4, the solder bump height is constant in a region where the solder bump width or the solder bump area is relatively large. As the solder bump width or solder bump area gradually decreases, the solder bump height begins to decrease. When the solder bump width is 20 μm, for example, the solder bump height is reduced by 2.5 μm compared to a region having a large solder bump width (for example, 100 μm). When the solder bump width is 20 μm or less, the solder bump height is further reduced.

本実施例では、比較的面積の大きな電源端子には直下に開口部を設けている。図５に示すように、開口部幅を変化させると半田バンプ高さが変化する（ここでは、開口部長は一定としている）。半田バンプ幅Ｗａ、開口部幅Ｗ１１、開口部幅Ｗ１２、開口部幅Ｗ１３の関係が、
Wa＞W11＞W12＞W13・・・・・・・・・・・・式（３）
と設定されると、
半田バンプ高さＨ１１、半田バンプ高さＨ１２、半田バンプ高さＨ１３の関係が、
H11＜H12＜H13・・・・・・・・・・・・・・・式（４）
となる。 In this embodiment, the power supply terminal having a relatively large area is provided with an opening immediately below. As shown in FIG. 5, when the opening width is changed, the solder bump height changes (here, the opening length is constant). The relationship among the solder bump width Wa, the opening width W11, the opening width W12, and the opening width W13 is as follows.
Wa>W11>W12> W13 ... Formula (3)
Is set,
The relationship between the solder bump height H11, the solder bump height H12, and the solder bump height H13 is
H11 <H12 <H13 ... Formula (4)
It becomes.

図６に示すように、開口部が設けられていない電源端子部の半田バンプ高さが一番高い。開口部幅或いは開口部面積を徐々に大きくすると電源端子部の半田バンプ高さが低下する。開口部幅或いは開口部面積が電源端子幅或いは電源端子面積よりも大きく（開口部に電源端子が埋設された場合）なると半田バンプ高さは一定となる。つまり、比較的大きな電源端子に開口部を設けることにより、半田バンプ高さを任意に下げることが可能となる。   As shown in FIG. 6, the height of the solder bump of the power supply terminal portion where no opening is provided is the highest. When the opening width or opening area is gradually increased, the solder bump height of the power supply terminal portion is lowered. When the opening width or the opening area is larger than the power supply terminal width or the power supply terminal area (when the power supply terminal is embedded in the opening), the solder bump height becomes constant. That is, by providing an opening in a relatively large power supply terminal, the height of the solder bump can be arbitrarily reduced.

次に、半導体装置の製造方法について図７乃至１１を参照して説明する。図７乃至１１は半導体装置の製造工程を示す断面図である。   Next, a method for manufacturing a semiconductor device will be described with reference to FIGS. 7 to 11 are cross-sectional views showing the manufacturing process of the semiconductor device.

図７に示すように、まず、前工程（ウェハ製造工程）が終了した第１のウェハ（メモリウェハ）４１を用意する。第１のウェハ（メモリウェハ）４１では、シリコン基板２０の第１主面（表面）上に図示しない絶縁膜を介して形状の異なる配線層２２が複数設けられる。配線層２２の両端側には絶縁膜２１が設けられる。絶縁膜２１には、第１のウェハ（メモリウェハ）４１の表面を保護する保護膜である、例えばプラズマシリコン窒化膜（P−SiN膜）を用いている。   As shown in FIG. 7, first, a first wafer (memory wafer) 41 that has completed the previous process (wafer manufacturing process) is prepared. In the first wafer (memory wafer) 41, a plurality of wiring layers 22 having different shapes are provided on the first main surface (front surface) of the silicon substrate 20 via an insulating film (not shown). Insulating films 21 are provided on both ends of the wiring layer 22. As the insulating film 21, for example, a plasma silicon nitride film (P-SiN film) that is a protective film for protecting the surface of the first wafer (memory wafer) 41 is used.

次に、図８に示すように、絶縁膜２１の第１主面（表面）上に絶縁膜２３を形成する。配線層２２の第１主面（表面）上の絶縁膜２３に開口部を設ける。比較的形状の小さい配線層２２の第１主面（表面）上には開口部２２２Aを設ける。比較的形状の大きい配線層２２の第１主面（表面）上には、配線層２２よりも小さな開口部２２２Bを設ける。絶縁膜２３には、例えばポリイミド膜を用いている。開口部形成後、レジスト膜（メッキ対応）４２を選択的に形成する。   Next, as shown in FIG. 8, the insulating film 23 is formed on the first main surface (front surface) of the insulating film 21. An opening is provided in the insulating film 23 on the first main surface (front surface) of the wiring layer 22. An opening 222A is provided on the first main surface (front surface) of the wiring layer 22 having a relatively small shape. An opening 222B smaller than the wiring layer 22 is provided on the first main surface (front surface) of the wiring layer 22 having a relatively large shape. For the insulating film 23, for example, a polyimide film is used. After the opening is formed, a resist film (for plating) 42 is selectively formed.

開口部２２２Aには、レジスト膜（メッキ対応）４２をマスクとして配線層２４を埋め込むように形成する。絶縁膜２３の第１主面（表面）上には、信号端子２６Aとしての配線層２４を形成する。開口部２２２Bには、開口部２２２Bを覆うように電源端子２６Ｂとしての配線層２４を設ける。   In the opening portion 222A, the wiring layer 24 is embedded using the resist film (for plating) 42 as a mask. On the first main surface (front surface) of the insulating film 23, a wiring layer 24 as a signal terminal 26A is formed. A wiring layer 24 as a power supply terminal 26B is provided in the opening 222B so as to cover the opening 222B.

ここで、配線層２４は、例えば回路基板１の接続端子Ｐａｄ１を伝送する信号を第１のチップ（メモリチップ）２を介して第２のチップ（Logicチップ）３に伝達する。配線層２４は、例えば回路基板１の接続端子Ｐａｄ１を伝送する信号を第１のチップ（メモリチップ）２から第２のチップ（Logicチップ）３を介して、再度第１のチップ（メモリチップ）２に伝達する。配線層２４は、配線層２２とは異なる材料を用いている。配線層２４には、例えばＴｉ（チタン）／Ｃｕ（銅）を用いている。Ｔｉ（チタン）はバリアメタル膜であり、代わりにＴｉＮ（窒化チタン）などを用いてもよい。Ｃｕ（銅）は、電界メッキ法を用いて形成しているが、代わりに無電界メッキ法を用いてもよい。   Here, the wiring layer 24 transmits, for example, a signal transmitted through the connection terminal Pad 1 of the circuit board 1 to the second chip (Logic chip) 3 via the first chip (memory chip) 2. For example, the wiring layer 24 transmits a signal transmitted through the connection terminal Pad1 of the circuit board 1 from the first chip (memory chip) 2 to the first chip (memory chip) again via the second chip (logic chip) 3. 2 is transmitted. The wiring layer 24 is made of a material different from that of the wiring layer 22. For example, Ti (titanium) / Cu (copper) is used for the wiring layer 24. Ti (titanium) is a barrier metal film, and TiN (titanium nitride) or the like may be used instead. Cu (copper) is formed using an electroplating method, but an electroless plating method may be used instead.

続いて、図９に示すように、レジスト膜（メッキ対応）４２を剥離し、配線層２４の両端側に絶縁膜２５を形成する。絶縁膜２５には、例えばポリイミド膜を用いている。   Subsequently, as shown in FIG. 9, the resist film (for plating) 42 is peeled off, and insulating films 25 are formed on both ends of the wiring layer 24. As the insulating film 25, for example, a polyimide film is used.

絶縁膜２５形成後、レジスト膜（メッキ対応）４３を選択的に形成し、信号端子２６Ａ及び電源端子２６Ｂの第１主面（表面）上に半田５１を形成する。半田５１には、例えばＴｉ（チタン）／Ｃｕ（銅）／Ｓｎ（錫）を用いている。Ｔｉ（チタン）はバリアメタル膜である。Ｃｕ（銅）及びＳｎ（錫）は、電界メッキ法を用いて形成しているが、代わりに無電界メッキ法を用いてもよい。また、Ｔｉ（チタン）とＣｕ（銅）の間に、Ｃｕ（銅）／Ｎｉ（ニッケル）などを挿入してもよい。   After the insulating film 25 is formed, a resist film (for plating) 43 is selectively formed, and solder 51 is formed on the first main surfaces (front surfaces) of the signal terminal 26A and the power supply terminal 26B. For example, Ti (titanium) / Cu (copper) / Sn (tin) is used for the solder 51. Ti (titanium) is a barrier metal film. Cu (copper) and Sn (tin) are formed using an electroplating method, but an electroless plating method may be used instead. Further, Cu (copper) / Ni (nickel) or the like may be inserted between Ti (titanium) and Cu (copper).

そして、図１０に示すように、レジスト膜（メッキ対応）４３を剥離する。半田５１をリフロー加熱させて信号端子２６Ａの第１主面（表面）上に半田バンプ５２Ａ、電源端子２６Ｂの第１主面（表面）上に半田バンプ５２Ｂを形成する。   Then, as shown in FIG. 10, the resist film (corresponding to plating) 43 is peeled off. The solder 51 is reflow heated to form solder bumps 52A on the first main surface (front surface) of the signal terminal 26A and solder bumps 52B on the first main surface (front surface) of the power terminal 26B.

このとき、電源端子２６Ｂには、開口部２２２Ｂが設けられているので、半田バンプ５２Ａの半田バンプ高さＨ２１、半田バンプ５２Ｂの半田バンプ高さＨ２２、高低差ΔＨ１の関係が、
H21＝H22＋ΔH1・・・・・・・・・・・・・・・式（５）
となる。つまり、電源端子２６B上の半田バンプ５２Bが信号端子２６A上の半田バンプ５２Aよりも低く設定される。 At this time, since the opening 222B is provided in the power supply terminal 26B, the relationship between the solder bump height H21 of the solder bump 52A, the solder bump height H22 of the solder bump 52B, and the height difference ΔH1 is
H21 = H22 + ΔH1 ... Formula (5)
It becomes. That is, the solder bump 52B on the power terminal 26B is set lower than the solder bump 52A on the signal terminal 26A.

一方、図示しないが前工程（ウェハ製造工程）が終了した第２のウェハ（logicウェハ）では、形状の大きな電源端子には開口部が設けられていないので、はんだバンプ形成後、電源端子上の半田バンプ高さが高くなる。   On the other hand, in the second wafer (logic wafer), which is not shown, but the pre-process (wafer manufacturing process) is completed, the large-sized power supply terminal is not provided with an opening. Solder bump height increases.

次に、図１１に示すように、半田バンプが形成された第１のウェハ（メモリウェハ）４１をダイシング処理により、個片化して第１のチップ（メモリチップ）２を形成する。半田バンプが形成された第２のウェハ（logicウェハ）をダイシング処理により、個片化して第２のチップ（logicチップ）３を形成する。   Next, as shown in FIG. 11, the first wafer (memory wafer) 41 on which the solder bumps are formed is separated into pieces by a dicing process to form the first chip (memory chip) 2. The second wafer (logic wafer) on which the solder bumps are formed is separated into pieces by a dicing process to form a second chip (logic chip) 3.

個片化された第１のチップ（メモリチップ）２は、回路基板１の第１主面（表面）上に接着層１１により載置され、固定される。回路基板１に載置された第１のチップ（メモリチップ）２と個片化された第２のチップ（logicチップ）３をFace to Faceで相対向するように配置する。このとき、第２のチップ（logicチップ）３の信号端子３２Ａ上の半田バンプの半田バンプ高さＨ３１、電源端子３２Ｂ上の半田バンプの半田バンプ高さＨ３２の関係が、
H32−H31＝ΔH1・・・・・・・・・・・・・・・式（６）
に設定されている。このため、半田バンプ高さＨ２１、半田バンプ高さＨ２２、半田バンプ高さＨ３１、半田バンプ高さＨ３２の関係が、
H21＋H31＝H22＋H32・・・・・・・・・・・・式（７）
に設定される。したがって、信号端子の半田バンプの接触部と電源端子の半田バンプの接触部が、半田バンプを接触された場合つぶされることなく良好に接触することができるので、半田接合時に余分な半田が流れ出すことがない。 The separated first chip (memory chip) 2 is placed on the first main surface (front surface) of the circuit board 1 by the adhesive layer 11 and fixed. The first chip (memory chip) 2 placed on the circuit board 1 and the separated second chip (logic chip) 3 are arranged so as to face each other face to face. At this time, the relationship between the solder bump height H31 of the solder bump on the signal terminal 32A of the second chip (logic chip) 3 and the solder bump height H32 of the solder bump on the power supply terminal 32B is as follows.
H32−H31 = ΔH1 Expression (6)
Is set to Therefore, the relationship between the solder bump height H21, the solder bump height H22, the solder bump height H31, and the solder bump height H32 is
H21 + H31 = H22 + H32 ... Formula (7)
Set to Therefore, the contact part of the solder bump of the signal terminal and the contact part of the solder bump of the power supply terminal can be satisfactorily contacted without being crushed when the solder bump is contacted, so that excess solder flows out during solder joining. There is no.

続いて、図示していないが、半田を溶融（例えば、半田リフロー処理）させて半田接合部１１１Ａ及び半田接合部１１１Ｂを形成する。回路基板１の接続端子Ｐａｄ１と第１のチップ（メモリチップ）２のチップ端子Ｐａｄ１１をボンディングワイヤ４で接続する。第１のチップ（メモリチップ）２と第２のチップ（logicチップ）３の間の空隙部にアンダーフィル樹脂１２を充填する。回路基板１の第１主面（表面）、接続端子Ｐａｄ１、第１のチップ（メモリチップ）２、第２のチップ（logicチップ）３を封止する封止材５を形成する。封止材５形成後、回路基板１の第１主面（表面）と相対向する第２主面（裏面）上にボール端子６を形成する。   Subsequently, although not shown, the solder is melted (for example, solder reflow process) to form the solder joint 111A and the solder joint 111B. The connection terminal Pad 1 of the circuit board 1 and the chip terminal Pad 11 of the first chip (memory chip) 2 are connected by bonding wires 4. An underfill resin 12 is filled in a gap between the first chip (memory chip) 2 and the second chip (logic chip) 3. A sealing material 5 for sealing the first main surface (front surface) of the circuit board 1, the connection terminal Pad 1, the first chip (memory chip) 2, and the second chip (logic chip) 3 is formed. After the sealing material 5 is formed, the ball terminals 6 are formed on the second main surface (back surface) opposite to the first main surface (front surface) of the circuit board 1.

上述したように、本実施例の半導体装置では、第１の絶縁膜上に設けられる信号端子２６Ａと、信号端子２６Ａ上に設けられる半田バンプ５２Ａと、第１の絶縁膜上に形成される開口部２２２Ｂを覆うように設けられ、信号端子２６Ａよりも大きな電源端子２６Ｂと、電源端子２６Ｂ上に設けられる半田バンプ５２Ｂとを有し、回路基板１上に接着層１１を介して載置される第１のチップ２と、第２の絶縁膜上に設けられる信号端子３２Ａと、信号端子３２Ａ上に設けられる半田バンプ５３Ａと、第１の絶縁膜上に設けられ、信号端子３２Ａよりも大きな電源端子３２Ｂと、電源端子３２Ｂ上に設けられる半田バンプ５３Ｂとを有する第２のチップ３とを具備する。信号端子２６Ａ上の半田バンプ５２Ａと信号端子３２Ａの半田バンプ５３Ａが相対向して配置される。電源端子２６Ｂ上の半田バンプ５２Ｂと電源端子３２Ｂ上の半田バンプ５３Ｂが相対向して配置される。半田バンプ５２Ａと半田バンプ５２Ｂの高低差は、半田バンプ５３Ｂと半田バンプ５３Ａの高低差と同じ値に設定される。第１のチップ２と第２のチップ３がFace to Faceで半田接合される。   As described above, in the semiconductor device of this embodiment, the signal terminal 26A provided on the first insulating film, the solder bump 52A provided on the signal terminal 26A, and the opening formed on the first insulating film. The power supply terminal 26B larger than the signal terminal 26A and the solder bump 52B provided on the power supply terminal 26B are provided so as to cover the portion 222B, and are placed on the circuit board 1 via the adhesive layer 11. The first chip 2, the signal terminal 32A provided on the second insulating film, the solder bump 53A provided on the signal terminal 32A, and the power source provided on the first insulating film and larger than the signal terminal 32A A second chip 3 having terminals 32B and solder bumps 53B provided on the power supply terminal 32B is provided. A solder bump 52A on the signal terminal 26A and a solder bump 53A on the signal terminal 32A are arranged to face each other. Solder bumps 52B on power supply terminal 26B and solder bumps 53B on power supply terminal 32B are arranged opposite to each other. The height difference between the solder bump 52A and the solder bump 52B is set to the same value as the height difference between the solder bump 53B and the solder bump 53A. The first chip 2 and the second chip 3 are soldered by face to face.

このため、半田バンプ形状が異なっても半田バンプ間の間隔を一定にすることができる。したがって、半田接合した場合、半田バンプの部分で余分な半田が外に広がることがないので半田起因による半導体装置８０のショート不良を防止することができる。   For this reason, even if the solder bump shapes are different, the interval between the solder bumps can be made constant. Therefore, when solder bonding is performed, excess solder does not spread outside at the solder bump portion, so that short circuit failure of the semiconductor device 80 due to solder can be prevented.

なお、本実施例では、半田バンプをＳｎ（錫）−Ｃｕ（銅）系Ｐｂ（鉛）フリー半田を用いているが、代わりにＳｎ（錫）−Ａｇ（銀）系のＰｂ（鉛）フリー半田、Ｓｎ（錫）−Ｚｎ（亜鉛）系のＰｂ（鉛）フリー半田、Ｓｎ（錫）−Ｂｉ（ビスマス）系のＰｂ（鉛）フリー半田、或いはＳｎ（錫）Ｐｂ（鉛）共晶半田などを用いてもよい。   In this embodiment, Sn (tin) -Cu (copper) -based Pb (lead) -free solder is used for the solder bumps, but Sn (tin) -Ag (silver) -based Pb (lead) -free solder is used instead. Solder, Sn (tin) -Zn (zinc) -based Pb (lead) -free solder, Sn (tin) -Bi (bismuth) -based Pb (lead) -free solder, or Sn (tin) -Pb (lead) eutectic solder Etc. may be used.

また、回路基板１上の第１のチップ（メモリチップ）２側に開口部を設け、電源端子上の半田バンプの高さを低くしているが、代わりに第２のチップ（logicチップ）側に開口部を設け、電源端子上の半田バンプの高さを低くしてもよい。   In addition, an opening is provided on the first chip (memory chip) 2 side on the circuit board 1 to reduce the height of the solder bump on the power supply terminal, but instead the second chip (logic chip) side. An opening may be provided on the solder bump to reduce the height of the solder bump on the power supply terminal.

また、半田をメッキ法で形成しているが、代わりに半田ペーストを用いたり、或いは蒸着法を用いてもよい。   Moreover, although the solder is formed by the plating method, a solder paste may be used instead, or a vapor deposition method may be used.

更に、半導体装置８０では半導体チップがFace to Faceでバンプ接続されるＢＧＡを使用しているが、代わりにＬＧＡ（Land Grid Array）、ＴＡＢ（Tape Automated Bonding）、ＣＳＰ（Chip Size Package）、ＭＣＭ（Multi Chip Module）などに適用してもよい。   Further, the semiconductor device 80 uses a BGA in which the semiconductor chip is bump-connected by face to face. Instead, the LGA (Land Grid Array), TAB (Tape Automated Bonding), CSP (Chip Size Package), MCM ( Multi Chip Module) may be applied.

次に、本発明の実施例２に係る半導体装置について、図面を参照して説明する。図１２は半導体装置を示す断面図である。本実施例では、Face to Faceでバンプ接合される２つの半導体チップにおいて、半田バンプ面積に応じてチップ端子直下の開口部面積を可変し、半田バンプの高さを適宜調整している。   Next, a semiconductor device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 12 is a cross-sectional view showing a semiconductor device. In this embodiment, in two semiconductor chips that are bump-bonded by face to face, the opening area directly under the chip terminal is varied according to the solder bump area, and the height of the solder bump is adjusted accordingly.

以下、実施例１と同一構成部分には、同一符号を付してその部分の説明を省略し、異なる部分のみ説明する。   In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

図１２に示すように、半導体装置８１は、Face to Faceでバンプ接続されるＢＧＡ（Ball Grid Array）である。半導体装置８１は、例えば携帯電話機器に使用される。   As shown in FIG. 12, the semiconductor device 81 is a BGA (Ball Grid Array) that is bump-connected by Face to Face. The semiconductor device 81 is used in, for example, a mobile phone device.

第１のチップ（ASICチップ）２ａは、回路基板１の第１主面（表面）上に接着層１１を介して載置される。接着層１１は、第１のチップ（ASICチップ）２ａを回路基板１に固定する。   The first chip (ASIC chip) 2 a is placed on the first main surface (front surface) of the circuit board 1 via the adhesive layer 11. The adhesive layer 11 fixes the first chip (ASIC chip) 2 a to the circuit board 1.

第１のチップ（ASICチップ）２ａには、シリコン基板２０の第１主面（表面）上に図示しない絶縁膜を介して配線層２２が設けられる。配線層２２は、寸法の異なるパターンを有する。配線層２２の両端側には絶縁膜２１が設けられる。配線層２２及び絶縁膜２１の第１主面（表面）上には絶縁膜２３が設けられる。絶縁膜２３には、大きさの異なる開口部２２２Ａと開口部２２２Ｃが設けられる。開口部２２２Ｃは、開口部２２２Ａよりも大きく、且つ実施例１の開口部２２Ｂよりも小さい。開口部２２２Ｃは、直下の配線層２２よりも小さく、且つ配線層２２の端部よりも内側に形成される。開口部２２２Ｃには、電源端子２６Ｂとして用いられる配線層２４が開口部２２２Ｃを覆うように設けられる（配線層２４の端部が絶縁膜２３上にせり出すように設けられる）。   In the first chip (ASIC chip) 2a, a wiring layer 22 is provided on the first main surface (front surface) of the silicon substrate 20 via an insulating film (not shown). The wiring layer 22 has patterns with different dimensions. Insulating films 21 are provided on both ends of the wiring layer 22. An insulating film 23 is provided on the first main surface (front surface) of the wiring layer 22 and the insulating film 21. The insulating film 23 is provided with an opening 222A and an opening 222C having different sizes. The opening 222C is larger than the opening 222A and smaller than the opening 22B of the first embodiment. The opening 222 </ b> C is smaller than the wiring layer 22 directly below and is formed inside the end of the wiring layer 22. In the opening 222C, the wiring layer 24 used as the power supply terminal 26B is provided so as to cover the opening 222C (the end of the wiring layer 24 is provided so as to protrude onto the insulating film 23).

第２のチップ（メモリチップ）３ａには、シリコン基板３０の第１主面（表面）上に図示しない絶縁膜を介して形状の異なる配線層２２ａが設けられる。配線層２２ａの両端側には、絶縁膜３１が設けられる。配線層２２ａ及び絶縁膜３１の第１主面（表面）上には、絶縁膜２３ａが設けられる。絶縁膜２３ａには、開口部２２３Ａと開口部２２３Ｃが設けられる。開口部２２３Ａは、比較的形状の小さい配線層２２ａ上に設けられる。開口部２２３Ｃは、比較的形状の大きい配線層２２ａ上の内側に設けられる。開口部２２３Ｃは開口部２２２Ａよりも大きい。   In the second chip (memory chip) 3a, wiring layers 22a having different shapes are provided on the first main surface (front surface) of the silicon substrate 30 via an insulating film (not shown). Insulating films 31 are provided on both ends of the wiring layer 22a. An insulating film 23 a is provided on the first main surface (front surface) of the wiring layer 22 a and the insulating film 31. The insulating film 23a is provided with an opening 223A and an opening 223C. The opening 223A is provided on the wiring layer 22a having a relatively small shape. The opening 223C is provided on the inner side of the wiring layer 22a having a relatively large shape. The opening 223C is larger than the opening 222A.

開口部２２３Ａには、配線層２４ａが設けられる。絶縁膜２３ａの第１主面（表面）上には、信号端子２６ＡＡとしての配線層２４ａが設けられる。開口部２２３Ｃには、電源端子２６ＢＢとしての配線層２４ａが開口部２２３Ｃを覆うように設けられる（端部が絶縁膜２３ａ上に設けられる）。配線層２４ａの両端側には絶縁膜２５ａが設けられる。   A wiring layer 24a is provided in the opening 223A. On the first main surface (front surface) of the insulating film 23a, a wiring layer 24a as the signal terminal 26AA is provided. In the opening 223C, a wiring layer 24a as the power supply terminal 26BB is provided so as to cover the opening 223C (an end is provided on the insulating film 23a). Insulating films 25a are provided on both ends of the wiring layer 24a.

第１のチップ（ASICチップ）２ａの信号端子２６Ａと第２のチップ（メモリチップ）３ａの信号端子２６ＡＡは、半田接合部１１１ＡＡによりFace to Faceでバンプ接続される。第１のチップ（ASICチップ）２ａの電源端子２６Ｂと第２のチップ（メモリチップ）３ａの電源端子２６ＢＢは、半田接合部１１１ＢＢによりFace to Faceでバンプ接続される。   The signal terminal 26A of the first chip (ASIC chip) 2a and the signal terminal 26AA of the second chip (memory chip) 3a are bump-connected by face-to-face by a solder joint 111AA. The power supply terminal 26B of the first chip (ASIC chip) 2a and the power supply terminal 26BB of the second chip (memory chip) 3a are bump-connected face-to-face by the solder joint portion 111BB.

なお、第１のチップ（ASICチップ）２ａの図示しない接地端子も信号端子よりも大きく、且つ直下に開口部が設けられる。第２のチップ（メモリチップ）３ａの図示しない接地端子も信号端子よりも大きく、且つ直下に開口部が設けられる。第１のチップ（ASICチップ）２ａの接地端子と第２のチップ（メモリチップ）３ａの接地端子は、図示しない半田接合部よりFace to Faceでバンプ接続される。   Note that a ground terminal (not shown) of the first chip (ASIC chip) 2a is also larger than the signal terminal, and an opening is provided immediately below. A ground terminal (not shown) of the second chip (memory chip) 3a is also larger than the signal terminal, and an opening is provided immediately below. The ground terminal of the first chip (ASIC chip) 2a and the ground terminal of the second chip (memory chip) 3a are bump-connected by face-to-face from a solder joint (not shown).

次に、半導体装置の製造方法について図１３を参照して説明する。図１３は半導体装置の製造工程を示す断面図である。半導体装置８１では、第１のチップ（ASICチップ）２ａと第２のチップ（メモリチップ）３ａが実施例１の第１の半導体チップ２と同様な方法で製造される。   Next, a method for manufacturing a semiconductor device will be described with reference to FIG. FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor device. In the semiconductor device 81, the first chip (ASIC chip) 2a and the second chip (memory chip) 3a are manufactured by the same method as the first semiconductor chip 2 of the first embodiment.

図１３に示すように、半田バンプが形成された第１のウェハ（ASICウェハ）をダイシング処理により、個片化して第１のチップ（ASICチップ）２ａを形成する。半田バンプが形成された第２のウェハ（メモリウェハ）をダイシング処理により、個片化して第２のチップ（メモリチップ）３ａを形成する。   As shown in FIG. 13, the first wafer (ASIC wafer) on which the solder bumps are formed is separated into pieces by a dicing process to form a first chip (ASIC chip) 2a. The second wafer (memory wafer) on which the solder bumps are formed is separated into pieces by a dicing process to form a second chip (memory chip) 3a.

個片化された第１のチップ（ASICチップ）２ａは、回路基板１の第１主面（表面）上に接着層１１により載置され、固定される。回路基板１に載置された第１のチップ（ASICチップ）２ａと個片化された第２のチップ（メモリチップ）３ａをFace to Faceで相対向するように配置する。このとき、電源端子２６Ｂ上の半田バンプ５２Ｂを信号端子２６Ａ上の信号端子５２Ａと同一な高さになるように、第１のチップ（ASICチップ）２ａの開口部２２２Ｃの面積を設定している。電源端子２６ＢＢ上の半田バンプ５２ＢＢを信号端子２６ＡＡ上の信号端子５２ＡＡと同一な高さになるように、第２のチップ（メモリチップ）３ａの開口部２２３Ｃの面積を設定している。   The separated first chip (ASIC chip) 2 a is placed on the first main surface (front surface) of the circuit board 1 by the adhesive layer 11 and fixed. The first chip (ASIC chip) 2a placed on the circuit board 1 and the separated second chip (memory chip) 3a are arranged so as to face each other face to face. At this time, the area of the opening 222C of the first chip (ASIC chip) 2a is set so that the solder bump 52B on the power supply terminal 26B has the same height as the signal terminal 52A on the signal terminal 26A. . The area of the opening 223C of the second chip (memory chip) 3a is set so that the solder bump 52BB on the power supply terminal 26BB has the same height as the signal terminal 52AA on the signal terminal 26AA.

この設定により、信号端子の半田バンプの接触部と電源端子の半田バンプの接触部が、半田バンプを接触した場合つぶされることなく良好に接触することができるので、半田接合時での余分な半田が流れ出すことがない。   With this setting, the contact part of the solder bump of the signal terminal and the contact part of the solder bump of the power supply terminal can be satisfactorily contacted without being crushed when the solder bump is contacted. Will not flow out.

上述したように、本実施例の半導体装置では、第１の絶縁膜上に設けられる信号端子２６Ａと、信号端子２６Ａ上に設けられる半田バンプ５２Ａと、第１の絶縁膜上に形成される開口部２２２Ｃを覆うように設けられ、信号端子２６Ａよりも大きな電源端子２６Ｂと、電源端子２６Ｂ上に設けられる半田バンプ５２Ｂとを有し、回路基板１上に接着層１１を介して載置される第１のチップ２ａと、第２の絶縁膜上に設けられる信号端子２６ＡＡと、信号端子２６ＡＡ上に設けられる半田バンプ５２ＡＡと、第１の絶縁膜上に形成される開口部２２３Ｃを覆うように設けられ、信号端子２６ＡＡよりも大きな電源端子２６ＢＢと、電源端子２６ＢＢ上に設けられる半田バンプ５２ＢＢとを有する第２のチップ３ａとを具備する。信号端子２６Ａ上の半田バンプ５２Ａと信号端子２６ＡＡの半田バンプ５２ＡＡが相対向して配置される。電源端子２６Ｂ上の半田バンプ５２Ｂと電源端子２６ＢＢ上の半田バンプ５２ＢＢが相対向して配置される。半田バンプ５２Ａと半田バンプ５２Ｂは同じ高さに設定される。半田バンプ５２ＡＡと半田バンプ５２ＢＢは同じ高さに設定される。第１のチップ２ａと第２のチップ３ａがFace to Faceで半田接合される。   As described above, in the semiconductor device of this embodiment, the signal terminal 26A provided on the first insulating film, the solder bump 52A provided on the signal terminal 26A, and the opening formed on the first insulating film. The power supply terminal 26B larger than the signal terminal 26A and the solder bump 52B provided on the power supply terminal 26B are provided so as to cover the portion 222C, and are placed on the circuit board 1 via the adhesive layer 11. The first chip 2a, the signal terminal 26AA provided on the second insulating film, the solder bump 52AA provided on the signal terminal 26AA, and the opening 223C formed on the first insulating film are covered. And a second chip 3a having a power terminal 26BB larger than the signal terminal 26AA and a solder bump 52BB provided on the power terminal 26BB. The solder bump 52A on the signal terminal 26A and the solder bump 52AA of the signal terminal 26AA are arranged to face each other. Solder bumps 52B on power supply terminal 26B and solder bumps 52BB on power supply terminal 26BB are arranged to face each other. The solder bump 52A and the solder bump 52B are set to the same height. The solder bump 52AA and the solder bump 52BB are set to the same height. The first chip 2a and the second chip 3a are soldered by face to face.

このため、半田バンプの形状が異なっても半田バンプ間の間隔を一定にすることができる。したがって、半田接合した場合、半田バンプの部分で余分な半田が外に広がることがないので半田起因による半導体装置８１のショート不良を防止することができる。   For this reason, even if the shape of the solder bumps is different, the interval between the solder bumps can be made constant. Therefore, when solder bonding is performed, excess solder does not spread outside at the solder bump portion, so that short circuit failure of the semiconductor device 81 due to solder can be prevented.

本発明は、上記実施例に限定されるものではなく、発明の趣旨を逸脱しない範囲で、種々、変更してもよい。   The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

例えば、実施例１では、第１のウェハ（メモリ）４１の前工程（ウェハ製造工程）後に、Ｃｕ（銅）配線を用いて信号端子２６Ａや電源端子２６Ｂを設けているが、第１のウェハ（メモリ）４１の前工程中で最上層のＡｌ（アルミニウム）配線で信号端子や電源端子を形成してもよい。この場合、電源端子直下に開口部を設け、電源端子の中央部を信号端子よりも低くするのがよい。また、半導体装置を携帯電話機器に用いているが、情報端末機器、モバイル機器などにも使用できる。また、チップ端子直下に開口部が設けられる第１のチップとＴＳＶ（ 貫通電極）を有する第２のチップがFace to Backでバンプ接続される半導体装置にも適用できる。   For example, in the first embodiment, after the first process (wafer manufacturing process) of the first wafer (memory) 41, the signal terminal 26A and the power supply terminal 26B are provided using Cu (copper) wiring. In the previous process of the (memory) 41, the signal terminal and the power supply terminal may be formed by the uppermost Al (aluminum) wiring. In this case, it is preferable that an opening is provided immediately below the power supply terminal, and the central portion of the power supply terminal is made lower than the signal terminal. Moreover, although the semiconductor device is used for the mobile phone device, it can also be used for an information terminal device, a mobile device, and the like. Further, the present invention can also be applied to a semiconductor device in which a first chip having an opening immediately below a chip terminal and a second chip having a TSV (through electrode) are bump-connected by face to back.

本発明は、以下の付記に記載されているような構成が考えられる。
（付記１） 第１の絶縁膜の第１主面上に設けられる第１のチップ端子と、前記第１のチップ端子の第１主面上に設けられる第１の半田バンプと、前記第１の絶縁膜に形成される開口部を覆うように設けられ、前記第１のチップ端子よりも幅或いは面積が大きい第２のチップ端子と、前記第２のチップ端子の第１主面上に設けられ、前記第１の半田バンプよりも幅或いは面積が大きい第２の半田バンプとを有する第１のチップと、第２の絶縁膜の第１主面上に設けられる第３のチップ端子と、前記第３のチップ端子の第１主面上に設けられる第３の半田バンプと、前記第２の絶縁膜の第１主面上に設けられ、前記第３のチップ端子よりも幅或いは面積が大きい第４のチップ端子と、前記第４のチップ端子の第１主面上に設けられ、前記第３の半田バンプよりも幅或いは面積が大きい第４の半田バンプとを有する第２のチップと、第１主面が、前記第１のチップの第１主面と相対向する第２主面と接着層を介して接着され、接続端子が前記第１のチップの第５のチップ端子とボンディングワイヤを介して電気的に接続される回路基板と、前記回路基板の第１主面、前記第１のチップ、及び前記第２のチップを覆うように設けられる封止材とを具備し、前記第１の半田バンプと前記第３の半田バンプ、及び前記第２の半田バンプと前記第４の半田バンプがそれぞれフェースツーフェースでバンプ接合される半導体装置。 The present invention can be configured as described in the following supplementary notes.
(Appendix 1) A first chip terminal provided on the first main surface of the first insulating film, a first solder bump provided on the first main surface of the first chip terminal, and the first A second chip terminal having a width or an area larger than that of the first chip terminal and a first main surface of the second chip terminal. A first chip having a second solder bump having a width or area larger than that of the first solder bump, a third chip terminal provided on the first main surface of the second insulating film, Third solder bumps provided on the first main surface of the third chip terminal and provided on the first main surface of the second insulating film, and having a width or an area larger than that of the third chip terminal. A fourth chip terminal which is large and provided on the first main surface of the fourth chip terminal; A second chip having a fourth solder bump having a larger width or area than the field bump, and a first main surface and an adhesive layer that is opposite to the first main surface of the first chip; A circuit board that is bonded via a connection terminal and electrically connected to a fifth chip terminal of the first chip via a bonding wire, a first main surface of the circuit board, and the first chip And a sealing material provided so as to cover the second chip, the first solder bump and the third solder bump, and the second solder bump and the fourth solder bump. Each semiconductor device is bump-bonded face-to-face.

（付記２） 前記半田バンプは、Ｓｎ（錫）−Ｃｕ（銅）系半田、Ｓｎ（錫）−Ａｇ（銀）系半田、Ｓｎ（錫）−Ｚｎ（亜鉛）系半田、Ｓｎ（錫）−Ｂｉ（ビスマス）系半田、或いはＳｎ（錫）Ｐｂ（鉛）共晶半田から構成される付記１に記載の半導体装置。 (Appendix 2) The solder bumps are Sn (tin) -Cu (copper) based solder, Sn (tin) -Ag (silver) based solder, Sn (tin) -Zn (zinc) based solder, Sn (tin)- The semiconductor device according to appendix 1, which is composed of Bi (bismuth) solder or Sn (tin) Pb (lead) eutectic solder.

（付記３） 前記半導体装置は、ＢＧＡ、ＬＧＡ、スタックドＭＣＰ、ＭＣＭ、或いはＴＡＢである付記１又は２に記載の半導体装置。 (Additional remark 3) The said semiconductor device is a semiconductor device of Additional remark 1 or 2 which is BGA, LGA, stacked MCP, MCM, or TAB.

（付記４） 前記半田バンプと前記チップ端子の間には、バリアメタルが設けられる付記１乃至３いずれかに記載の半導体装置。 (Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, wherein a barrier metal is provided between the solder bump and the chip terminal.

1 回路基板
２ 第１のチップ（メモリチップ）
２ａ 第１のチップ（ASICチップ）
３ 第２のチップ（logicチップ）
３ａ 第２のチップ（メモリチップ）
４ ボンディングワイヤ
５ 封止材
６ ボール端子
１１ 接着層
１２ アンダーフィル樹脂
２０、３０ シリコン基板
２１、２３、２３ａ、２５、２５ａ、３１ 絶縁膜
２２、２２ａ、２４、２４ａ 配線層
２６Ａ、２６ＡＡ、３２Ａ 信号端子
２６Ｂ、２６ＢＢ、３２Ｂ 電源端子
４１ 第１のウェハ（メモリウエハ）
４２、４３ レジスト膜（メッキ対応）
５１ 半田
５２Ａ、５２ＡＡ、５２Ｂ、５２ＢＢ、５３Ａ、５３Ｂ 半田バンプ
８０、８１ 半導体装置
１１１Ａ、１１１ＡＡ、１１１Ｂ、１１１ＢＢ 半田接合部
２２２Ａ、２２２Ｂ、２２２Ｃ、２２３Ａ、２２３Ｂ 開口部
Ｈ１〜Ｈ３、Ｈ１１〜Ｈ１３、Ｈ２１、Ｈ２２、Ｈ３１、Ｈ３２ 半田バンプ高さ
Ｗ１〜Ｗ３、Ｗ１１〜Ｗ１３ 半田バンプ幅
Ｗａ 半田バンプ幅
Ｐａｄ１ 接続端子
Ｐａｄ１１ 接続端子
ΔＨ１ 高低差 1 Circuit board 2 First chip (memory chip)
2a First chip (ASIC chip)
3 Second chip (logic chip)
3a Second chip (memory chip)
4 Bonding wire 5 Sealing material 6 Ball terminal 11 Adhesive layer 12 Underfill resin 20, 30 Silicon substrate 21, 23, 23a, 25, 25a, 31 Insulating film 22, 22a, 24, 24a Wiring layer 26A, 26AA, 32A Signal Terminal 26B, 26BB, 32B Power supply terminal 41 First wafer (memory wafer)
42, 43 Resist film (for plating)
51 Solder 52A, 52AA, 52B, 52BB, 53A, 53B Solder bump 80, 81 Semiconductor devices 111A, 111AA, 111B, 111BB Solder joints 222A, 222B, 222C, 223A, 223B Openings H1 to H3, H11 to H13, H21 , H22, H31, H32 Solder bump heights W1 to W3, W11 to W13 Solder bump width Wa Solder bump width Pad1 Connection terminal Pad11 Connection terminal ΔH1 Height difference

Claims (5)

第１の絶縁膜の第１主面上に設けられる第１のチップ端子と、前記第１のチップ端子の第１主面上に設けられる第１の半田バンプと、前記第１の絶縁膜に形成される開口部を覆うように設けられ、前記第１のチップ端子よりも大きい第２のチップ端子と、前記第２のチップ端子の第１主面上に設けられ、前記第１の半田バンプよりも大きい第２の半田バンプとを有する第１のチップと、
第２の絶縁膜の第１主面上に設けられる第３のチップ端子と、前記第３のチップ端子の第１主面上に設けられる第３の半田バンプと、前記第２の絶縁膜の第１主面上に設けられ、前記第３のチップ端子よりも大きい第４のチップ端子と、前記第４のチップ端子の第１主面上に設けられ、前記第３の半田バンプよりも大きい第４の半田バンプとを有する第２のチップと、
を具備し、前記第１の半田バンプと前記第３の半田バンプ、及び前記第２の半田バンプと前記第４の半田バンプがそれぞれフェースツーフェースでバンプ接合され、前記第１のチップと前記第２のチップが封止されていることを特徴とする半導体装置。 A first chip terminal provided on the first main surface of the first insulating film, a first solder bump provided on the first main surface of the first chip terminal, and the first insulating film A second chip terminal larger than the first chip terminal; and a first main surface of the second chip terminal, the first solder bump being provided to cover the opening to be formed. A first chip having a second solder bump larger than the first chip;
A third chip terminal provided on the first main surface of the second insulating film, a third solder bump provided on the first main surface of the third chip terminal, and the second insulating film. A fourth chip terminal provided on the first main surface and larger than the third chip terminal, and provided on the first main surface of the fourth chip terminal and larger than the third solder bump. A second chip having a fourth solder bump;
The first solder bump and the third solder bump, and the second solder bump and the fourth solder bump are bump-bonded face-to-face, respectively, and the first chip and the first solder bump are bonded. 2. A semiconductor device, wherein two chips are sealed. 前記第１のチップは、前記第２のチップとバンプ接合される第１主面と相対向する第２主面が接着層を介して回路基板に接着されることを特徴とする請求項１に記載の半導体装置。   2. The first chip, wherein a second main surface opposite to the first main surface bump-bonded to the second chip is bonded to a circuit board through an adhesive layer. The semiconductor device described. 前記第２のチップは、前記第１のチップとバンプ接合される第１主面と相対向する第２主面が接着層を介して回路基板に接着されることを特徴とする請求項１に記載の半導体装置。   2. The second chip, wherein a second main surface opposite to a first main surface bump-bonded to the first chip is bonded to a circuit board through an adhesive layer. The semiconductor device described. 第１の絶縁膜の第１主面上に設けられる第１のチップ端子と、前記第１のチップ端子の第１主面上に設けられる第１の半田バンプと、前記第１の絶縁膜に形成される第１の開口部を覆うように設けられ、前記第１のチップ端子よりも大きい第２のチップ端子と、前記第２のチップ端子の第１主面上に設けられ、前記第１の半田バンプよりも大きい第２の半田バンプとを有する第１のチップと、
第２の絶縁膜の第１主面上に設けられる第３のチップ端子と、前記第３のチップ端子の第１主面上に設けられる第３の半田バンプと、前記第２の絶縁膜に形成される第２の開口部を覆うように設けられ、前記第３のチップ端子よりも大きい第４のチップ端子と、前記第４のチップ端子の第１主面上に設けられ、前記第３の半田バンプよりも大きい第４の半田バンプとを有する第２のチップと、
を具備し、前記第１の半田バンプと前記第３の半田バンプ、及び前記第２の半田バンプと前記第４の半田バンプがそれぞれフェースツーフェースでバンプ接合され、前記第１のチップと前記第２のチップが封止されていることを特徴とする半導体装置。 A first chip terminal provided on the first main surface of the first insulating film, a first solder bump provided on the first main surface of the first chip terminal, and the first insulating film A second chip terminal larger than the first chip terminal; and a first main surface of the second chip terminal, the first chip terminal being formed so as to cover the first opening formed. A first chip having a second solder bump larger than the first solder bump;
A third chip terminal provided on the first main surface of the second insulating film, a third solder bump provided on the first main surface of the third chip terminal, and the second insulating film A fourth chip terminal larger than the third chip terminal, provided on the first main surface of the fourth chip terminal, and so as to cover the second opening to be formed; A second chip having a fourth solder bump larger than the solder bump of
The first solder bump and the third solder bump, and the second solder bump and the fourth solder bump are bump-bonded face-to-face, respectively, and the first chip and the first solder bump are bonded. 2. A semiconductor device, wherein two chips are sealed. 半導体ウェハの第１主面上に第１の絶縁膜を介して設けられる第１のチップ端子と、
前記第１のチップ端子の第１主面上に設けられる第１の半田バンプと、
前記第１の絶縁膜に形成される開口部を覆うように設けられ、前記第１のチップ端子よりも大きい第２のチップ端子と、
前記第２のチップ端子の第１主面上に設けられ、前記第１の半田バンプより大きい第２の半田バンプと、
を具備することを特徴とする半導体装置。 A first chip terminal provided on a first main surface of a semiconductor wafer via a first insulating film;
A first solder bump provided on the first main surface of the first chip terminal;
A second chip terminal that is provided so as to cover an opening formed in the first insulating film and is larger than the first chip terminal;
A second solder bump provided on the first main surface of the second chip terminal and larger than the first solder bump;
A semiconductor device comprising:
JP2009221977A 2009-09-28 2009-09-28 Semiconductor device Pending JP2011071378A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014132635A (en) * 2012-12-05 2014-07-17 Murata Mfg Co Ltd Electronic component with bump and manufacturing method of electronic component with bump

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014132635A (en) * 2012-12-05 2014-07-17 Murata Mfg Co Ltd Electronic component with bump and manufacturing method of electronic component with bump
US9343360B2 (en) 2012-12-05 2016-05-17 Murata Manufacturing Co., Ltd. Bump-equipped electronic component and method for manufacturing bump-equipped electronic component

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