TW201225209A - Semiconductor device and method of confining conductive bump material with solder mask patch - Google Patents

Abstract

A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate.

Description

201225209 VI. INSTRUCTIONS: [Priority Claim] This application is part of the continuation of US Application No. 12/633, 53 1 of December 28, 2009, and claims the foregoing basis in accordance with Article 12 of the US Patent Law. Priority of the application. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to semiconductor devices and, more particularly, to a semiconductor device and method for confining conductive bump materials during solder reflow using solder mask patches. [Prior Art] Semiconductor devices are found in modern electronic products. Semiconductor devices differ in the number and density of electrical components. Discrete semiconductor devices typically include one type of electrical component, such as a light-emitting diode (LED), a small-signal transistor, a resistor, a capacitor, an inductor. And power metal oxide semiconductor field effect transistors (M〇SFE1> integrated semiconductor devices usually contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors , charge coupled device (ccd), solar cell, and digital micromirror device (DMD). The semiconductor device can perform a wide range of high-speed calculations, transmit and receive electromagnetic signals, and generate electricity for the electrical semiconductor device. Communication, functions 'eg signal processing, number, control electronics, visible projection of the visual display. Power conversion 'network, computer to 4 201225209 and consumer products in the field. Semiconductor 穸 * dry etc. It can also be found in military applications, automotive, industrial controllers, and office equipment. The electrical properties of a semiconductor material. The atomic structure of a semiconductor material allows its conductivity to be manipulated by the application of an electric field or base current or by a doping process. Doping introduces impurities into the semiconductor material to manipulate and control the semiconductor. Conductivity of the device - The semiconductor device contains active and passive electrical structures. The active structure containing the bipolar and field effect transistors controls the flow of current by varying the degree of doping and the application of the electric or base current. The level of transistor growth is limited by the flow of current. The passive structure of resistors, capacitors and inductors produces a voltage and current relationship necessary to perform various electrical functions. The passive and active structures are electrically connected. Forming a circuit that enables semiconductor devices to perform high-speed calculations and other useful functions. Semiconductor devices are typically fabricated using two complex processes, namely front-end manufacturing and back-end manufacturing, each of which involves a possible number. A hundred steps. The front-end manufacturing system involves the surface of the semiconductor wafer. The formation of a plurality of dies. Each dies are generally identical and comprise circuitry formed by electrically connecting active and passive components. The back end fabrication involves singulating individual dies and packages from wafer fabrication. The die provides structural support and environmental isolation. One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume lower power, are more efficient, and are more efficient. The ground is produced. In addition, the smaller the semiconductor device has a smaller footprint of 201225209, j; [• the smaller grain size of the enamel system for the smaller final product can be 丨A 丨In the process of force and process, the smaller and higher-density active and passive components are used to produce the suppression of the ^, the birthday of the door, and the improvement of the birthday. The back-end process can be modified to produce smaller semiconductor device packages by improving the electrical interconnect and packaging materials. The picture of the complex surplus k! And the __ portion of the two-layer flip-chip type semiconductor die 1() is metallurgically and electrically connected to the bump pad formed on the semiconductor die 1 (), and the line wires 2 and 22 formed on the board 30 thereof A cross-sectional view of the interconnection or bump & The line conductors 22 are wound between the line conductors 2 and the bumps 12 on the substrate 3A. The line conductors 20 and 22 are and have an optional electrical signal conductor for mating to the bump pads of the bumps 12-14. The solder mask 26 covers the line conductors 2G and 22. A material or alignment opening (SRO) 28 is formed over the substrate 3 to expose the line conductors 2 and & SRO 28 series to limit the conductive bump material on the bump pads of the line conductors 2 and 22 during reflow. And avoiding the molten bump material from penetrating over the line conductors, which can cause electrical shorts to adjacent structures. The sr〇 28 series is made larger than the line conductor or bump pad. The SR0 28 is typically circular in shape and made as small as possible to reduce the spacing of the line conductors 2 and 22 and increase the winding density. In a typical sf rule, the minimum escape spacing of the line conductor 3 is defined by P = (l.lD + W) / 2 + L, where d is the diameter of the bump base and W is the line width 'And L is the ligament spacing between the SRO and adjacent structures. Using the upper 30 micron (μηι) solder alignment design rule, ΙΟΟμπι D, 20μηη W, and L 30μιη, the minimum escape spacing of the line conductor 3〇_34 201225209 is (1 1 *100+20)/ 2+30=95μηι. The SRO 28 system around the bump pads limits the escape pitch and the winding density of the semiconductor die. [Invention] There is a need to minimize the escape pitch of the line conductors to obtain a higher winding density. . Thus, in one embodiment, the invention is a method of fabricating a semiconductor device comprising the steps of: providing a semiconductor die having a plurality of die bump pads; providing a plurality of conductive traces having interconnected locations a substrate; forming a solder mask patch at the gap between the die bump pads or interconnect locations; depositing a conductive bump material on the interconnect locations or the die bump pads; mounting the semiconductor die to The substrate is such that the conductive bump material is disposed between the die bump pads and the interconnection locations; the conductive bumps (four) are reflowed without a solder mask around the die bump pads or interconnection locations Forming an interconnect structure between the semiconductor die and the substrate; and depositing an encapsulation material between the semiconductor die and the substrate. The solder mask patch confines the conductive bump material to the die bump pads or interconnect locations. In another embodiment, the invention is a method of fabricating a semiconductor device comprising the steps of: providing a first semiconductor structure having a plurality of first interconnect locations; providing a second having a plurality of second interconnect locations a semiconductor structure; forming a solder mask patch between the first interconnect locations or the second interconnect locations; depositing a conductive bump material between the first and second interconnect locations; from the conductive bumps The material forms an interconnect structure to bond (4)-7 201225209 and the second semiconductor structure; and depositing the encapsulation material in the first and second semiconductors. The solder mask # θ hood patch confines the conductive bump material to some of the first interconnect locations or the second interconnect locations. In an embodiment, the present invention is a method of fabricating a semiconductor device, comprising the steps of: providing a first semiconductor structure having a plurality of first interconnect locations; providing a plurality of second interconnect locations a semiconductor structure; a plurality of solder mask patches are interposed between the first interconnects, and an interconnect structure is formed to connect the first and second semiconductor structures. The solder mask patch confines the interconnect structure to the first interconnect locations or the second interconnect locations. In another embodiment, the invention is a semiconductor device comprising a first semiconductor structure having a plurality of first interconnect locations and a second semiconductor structure having a plurality of second interconnect locations. A solder mask patch is formed between the first interconnected locations or the second interconnected locations. An interconnect structure connects the first and second semiconductor structures. The solder mask patch confines the interconnect structure to the first interconnect locations or the second interconnect locations. An encapsulation material is deposited between the first and second semiconductor structures. The invention is described in one or more embodiments in the following description with reference to the drawings, wherein the same element symbols represent the same or similar elements. Although the present invention has been described in terms of the best mode of the present invention, those skilled in the art will appreciate that the invention is intended to cover alternatives as may be included in the spirit and scope of the invention as defined by the appended claims. , Modifications, and equivalents of 201225209 and equivalents as supported by the following disclosure and drawings. Semiconductor devices are typically fabricated using two complex processes [front end manufacturing and back end manufacturing. Front end manufacturing involves the formation of multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, resistors, and transformers produce a relationship between voltage and current necessary to perform circuit functions. The passive and active components are formed on the surface of the semiconductor wafer by a series of processing steps including doping, deposition, lithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process changes the conductivity of the semiconductor material in the active device, thereby converting the semiconductor material into an insulator, a conductor, or dynamically changing the conductivity of the semiconductor material in response to an electric field or base current. The transistor contains regions of varying doping type and extent that are optionally matched to enable the transistor to promote or limit current flow when an electric or base current is applied. Active and passive components are formed from layers of material having different electrical properties. The layers can be formed by a variety of deposition techniques that are determined in part by the type of material being deposited. For example, thin film deposition can include chemical vapor deposition (CVD), physical vapor deposition (pVD), electrolytic plating, and electroless electrical recording. Each layer is generally patterned to form an active member, a passive member, or a portion that is electrically connected between the members. The layers can be patterned using lithography, which involves depositing the photosensitive material 9 201225209 on the layer to be rounded and transferring it onto the photoresist to first use the film to self-illuminate. Use a solvent to remove the light and expose the portion of the Dingsi, which is to be rounded, and the first part of the system. ^ ^ ^ The lower layer is 。. The rest of the photoresist is removed leaving a patterned layer.哎,坌敁#s 丨 留下 的 及 及 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷Chemical. Case: Seeing a film deposited on top of the material may magnify the image below: two flat surfaces. Produce a smaller and denser packaged main round surface to remove material and table: Make: ... the seat is scoop + tanned surface. The planarization involves polishing the surface of the wafer with a polishing pad. Abrasive materials and corrosive chemicals are added to the surface of the wafer during polishing. The mechanical action and chemistry of the abrasive. The combination of the button action removes any irregular surface configuration resulting in a uniformly flat surface. “Back-end manufacturing refers to cutting or simply cutting a finished wafer into individual dies and encapsulating the dies to provide structural support and environmental isolation. For single-cut dies' along the non-functional area of the wafer The wafer is scratched and cut for cutting or scribing. The wafer is cut by a laser cutting tool or a saw blade. After the single cutting, the individual die is mounted on the package substrate. Or contacting the germanium for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to the contact pads in the package. The electrical connections may be by solder bumps, stud bumps, conductive paste or bonding wires ( Wirebond) is formed by depositing a packaging material or other molding material on the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system, and the function of the semiconductor device 10 201225209 is available for other systems. Figure 3 is a depiction of a wafer "substrate or printed circuit board (pcB) 52 having a plurality of semiconductor packages mounted on its surface. The electronic device 50 may have one type depending on the application. A semiconductor package or a plurality of types of semiconductor packages. Different types of semiconductor packages are shown in Fig. 3 for illustrative purposes. The electronic device 5G may be an independent system that uses the semiconductor packages to perform one or one kind of electrical work. Alternatively, the electronic device can be a sub-component of a larger system. For example, the electronic device can be a mobile phone, a personal digital assistant (PDA), a digital video camera (7) V, or a direct electronic device. A portion of the communication device. Alternatively, the electronic device 50 can be a display card, a network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include a microprocessor, a memory, and a special application integrated body. Circuits (ASICs), logic circuits, analog circuits, rf circuits, discrete devices or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices must be Shortened to achieve higher density. In Figure 3, PCB 52 provides a general substrate for mounting in the junction of the pcB ^ semiconductor package. Branches and electrical interconnections. Conductive signal lines = 形成 formed on a surface of PCB 52 by evaporation, electrolytic electrowinning, electroless ore, screen printing, or a suitable metal deposition process thereof Within the layer, the signal line 54 provides electrical communication between the semiconductor package, the mounted component, and each of the other external system components. The line 54 also provides power and ground connections to each semiconductor package. 201225209 In certain embodiments, the semiconductor device has two package levels. The first level package is a technique for mechanically and electrically attaching a semiconductor die to an intermediate carrier. A second level of package is involved. To the intermediate carrier is mechanically and electrically attached to the PCB. In other embodiments, a semiconductor device may have only the first level of packaging, wherein the die is directly mechanically and electrically mounted to the PCB. For purposes of illustration, a plurality of types of first-level packages including wire bond package % and flip chip 58 are shown on the coffee maker 52. In addition, a ball grid array (BGA) 6G and a bump wafer carrier (Bee) are included. , Double-row package (DIP) 64, platform grid array (LGA) 66, multi-chip package (MCM) 68, four-sided flat leadless package (QFN) 7-inch and four-sided flat package Μ several types of A two-level package is shown installed on pcB ^ ^. Any combination of semiconductor packages and other electronic components configured in any combination of package types of the first and second levels may be coupled to PCB 52, depending on system requirements. In some embodiments, the electronic device 5A includes a conductor package and other embodiments require a plurality of interconnected packages. Manufacturers prefabricated components are incorporated into electronic devices and systems by combining one or more semiconductor packages on a single-substrate. Since semiconductor packages include complex functions, electronic devices can be fabricated using less expensive components and streamlined processes. The resulting device is less likely to fail and is less expensive to manufacture, thereby reducing consumer costs. 4a-4C show an exemplary semiconductor package. Figure 4a depicts further details of trace 64 on PCB 52. The semiconductor die includes three active regions having analog or digital circuits, and the analog or digital 12 201225209 circuit is implemented as an active device, a passive device, a conductive layer, and a dielectric layer formed in the die and according to the die Electrically designed and electrically interconnected. For example, the circuit can include one or more of a transistor, a diode, an inductor, a capacitor, a resistor, and the like: formed in the active region of the semiconductor die 74. The contact pad 76 is one or more layers of a conductive material such as aluminum (A1), copper (Cu), tin (Sn), nickel (Ni), gold (Au) or silver (Ag), and is electrically connected to the semiconductor crystal. Circuit components within the particles 74. The semiconductor die 74 is mounted to the intermediate carrier 78 during the assembly of the Dip® by means of a gold eutectic layer or an adhesive material such as a thermal epoxy resin. The package main system comprises an insulating encapsulating material such as a polymer or ceramic. Wire (9) and wire 82 provide electrical interconnection between semiconductor die 74 and pCB 52. The encapsulation material 84 is deposited over the package for environmental protection to prevent moisture and particulates from entering the package and contaminating the die 74 or bond wires 82. Figure 4b depicts a further detail of Bcc 62 mounted on pCB 52. The semiconductor die 88 is mounted on the carrier 9 by padding with a primer or epoxy resin. Wire bond 94 provides a first level of package interconnection between contact pads % and 98. A molding compound or encapsulating material 1 is deposited on the semiconductor substrate 88 and bond wires 94 to provide physical support and electrical isolation to the device. The contact pads 1 2 are formed over the surface of the PCB 52 using a suitable metal deposition process such as an electrolytic clock or an electroless bond to avoid oxidation. The contact pads 1 2 are electrically connected to the PCB 52 (four) - or a plurality of conductive signal lines M. The bumps 1〇4 are formed between the contact pads 98 of the BCC 62 and the contact pads 1〇2 of the PCB 52. In Fig. 4c, the semiconductor die 58 is mounted face down to the intermediate carrier 1〇6 in a flip-chip type first package 13 201225209. The active region 1 〇 8 of the semiconductor die 58 includes analog or digital circuitry that is implemented as an active device, a passive device, a conductive layer, and a dielectric layer formed in accordance with the electrical design of the die. For example, the circuit can include one or more of a transistor body, an inductor, a capacitor, a resistor, and other circuit components within the active region 108. Semiconductor die 58 is electrically and mechanically coupled to carrier 106 via bumps i 10 . The BGA 60 is electrically and mechanically connected to the PCB by bumps 112 in a BGA type second level package. The semiconductor die 58 is electrically connected to the conductive signal lines in the PcB 52 through the bumps, the signal lines 114 and the bumps 112. 54. A molding compound or encapsulating material i 16 is deposited over the semiconductor bismuth S particles 58 and the carrier 106 to provide physical support and electrical isolation to the device. The flip chip semiconductor device provides a short conductive path from the active device on the semiconductor die 58 to the conductive traces on the PCB 52 to reduce signal propagation distance, reduce capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 can be directly and mechanically and electrically connected to the PCB 52 using a flip-chip type 1 package without the intermediate carrier 1〇6. In another embodiment, the active region 1 〇 8 of the semiconductor die 58 is mounted directly down to the PCB 115, i.e., directly down without the intermediate carrier, as shown in Figure 4d. The bump pads are formed on the active regions 1 〇 8 by a vapor deposition, electrolytic plating, electroless plating, screen printing or other suitable metal deposition process. The bump pads ηι are connected to the active and passive circuits by conductive traces in the active region 108. The bump pad Π 1 may be Al, Sn, Ni, Au, Ag or Cu. A conductive bump material 14 201225209 is deposited on the bump m 导电 conductive trace ιι8 using - money, electrolyzed electromine, electroless ore, ball drop (drop) or screen printing process. The bump material may be Babu Sn, Ni, Au, ", Lead, Bi Cu solder, and combinations thereof, having an optional fiux material. For example, the bump material may be eutectic Sn /pb, high (four) solder or no-ship solder. The haihai & block material is bonded between the die bump pads 111 and the conductive traces 118 on the PCB 115 using a suitable attachment or bonding process. In the example, the bump material is reflowed by heating the material beyond its melting point to form a ball or bump 1 丨 7. The flip chip semiconductor device is provided from the active device on the semiconductor die 58 to the pcB 115. One of the conductive traces ι 8 has a short conductive path to facilitate signal propagation, reduce capacitance, and achieve overall better circuit performance. Figure 5 depicts a portion of a flip-chip type semiconductor die 12 with a bump pad 122 Cross-sectional views of the portions. The line conductors 13 and 132 are formed on the substrate 136. The line conductors 130 and 132 are straight electrical conductors having integrated bump pads 138, as shown in FIG. The integrated bump pad 138 and the line conductors 13 and 132 Alternatively, the line conductors 130 and 132 may have a circular integral bump pad 139 as shown in Figure 6b, or a rectangular integral bump pad 140 as shown in Figure 6c. The integral bump pads are typically arranged in an array for maximum interconnect density and capacity. In Figure 7, the solder mask 142 is deposited on one of the conductive traces 13 and 132. However, the solder mask 42 is not formed over the integral bump pad 138. Therefore, each bump pad on the substrate does not have the SRO as seen in Figure 2 of the prior art as in 15 201225209. A non-wetting solder mask patch 144 is formed on the substrate 136 and in the voids within the array of integral bump pads 138, that is, between adjacent bump pads. Sheets may also be formed on the semiconductor die 1 且 and in the voids within the array of die bump pads 122. More generally, the solder mask patches are formed in any configuration - body bump pads Nearby to avoid spilling into less humid areas. Figure 8 shows the formation of a one-piece bump pad Bumps 15 and 152 overlying 138 and limited by solder mask patch 144. A conductive bump material utilizes an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing The process is deposited on the die bump pad 122 or the integrated bump pad 138. The bump material may be Bab Sn, Ni, Au, Ag' Pb, Bi, Cu, solder, and combinations thereof, which have an option A fluxing solvent, for example, the bump material may be a eutectic Sn/pb, a high lead solder or a lead-free solder. The bump material is bonded to the integral bump pad using a suitable attachment or bonding process. 138. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form balls or bumps 150 and 152. In some applications, the bumps 15 and 152 are secondarily reflowed to improve the electrical contact between the die bump pads 122 and the integral bump pads 138. The bumps can also be compression bonded to the die bumps. Block 塾 1 22 and integral bump 塾 138. Bumps 150 and 152 represent one type of interconnect structure that can be formed over integral bump 138. The interconnect structure can also use stud bumps, microbumps, or other electrical interconnects. It is desirable to minimize the escape spacing at high winding density applications. In order to reduce the spacing between the line conductors 13G*132, the bump material 16 201225209 is reflowed around the body-shaped bumps I 138 without a solder mask. The dissipation spacing between the line conductors 130 and 132 can be achieved by eliminating the solder mask and associated #sr〇 used for solder reflow restrictions around the integral bump 〇, ie, by no solder mask Reflow the bump material to reduce it. A solder mask 142 may be formed over the line conductors 13 and 132 and a portion of the substrate 136 that is further away from the body bumps 138, as shown in FIG. However, the solder mask 142 is not formed on the integral type bar (four) 138. The portion of the line conductor i3〇 & i 32 that is designed to mate with the bump material does not form sr〇 in the solder mask 142. In addition, solder mask patches 144 are formed on substrate 136 and in voids within the array of body-type bump pads 138. The solder mask...44 is a non-wetting material. The solder mask (four) 144 may be the same material as the solder mask M2 and applied during the same processing step, or applied for different materials during different processing steps. The solder mask patch 144 can be formed by selective oxidation, electroplating, or other processing of portions of the lines or pads within the array of body-type bump pads 138. The solder mask patch U4 is a localized solder that flows to the integral bump (four) 138 and prevents the conductive bump material from seeping into adjacent structures. When the bump material is reflowed using solder mask fills 144 disposed in the voids in the array of integral bumps 138, the wetting and surface tension are such that the bump material is confined and remains in the grain bump (d) 122 "in the space between the body bump pads 138 and the substrate 136 adjacent to the line conductors 13 and 132 and substantially in the portion of the footprint of the body-type bump pad 138. To achieve this desired property, convex The bulk material may be immersed in a fluxing solvent prior to placement on the crystal 17 201225209 grain bump pad 122 or the integral bump pad 138 to selectively contact the area of the bump material with the line conductor 130. The area around 132 is more humid. The molten bump material is maintained confined within the area substantially defined by the bump pads due to the wettability of the fluxing solvent. The bump material does not spill to less humid. A thin oxide layer or other insulating layer may be formed over the region where the bump material is not intended to make the region less humid. Therefore, the die bump pad 122 or the integral bump pad There is no need to have around 138 The material mask 142. Since no SRO is formed around the grain bump pad 22 or the integral bump pad 138, the line wires 13 and 132 can be formed with a fine pitch, that is, the line wires 13〇 And 132 can be placed closer to the adjacent structure without contact and forming an electrical short. Assuming the same solder alignment design rule, the spacing between line conductors 130 and 132 is given as P = (^1D + W / 2, where D is the base diameter of the bump 15 〇 152 and w is the width of the line conductors 130 and 132. In one embodiment, given the bump diameter of μηι and the line width of 2 〇 pm, The minimum escape spacing of the line conductors 1% and 132 is 65 μm. This bump formation eliminates the need to consider the hole spacing of the solder mask material between adjacent openings as is known in the prior art and minimally resolvable Figure 9-14 illustrates other embodiments having various interconnect structures that can be applied to an interconnect structure using a dip mask patch as described in Figure 5-8. 9a shows - has _ species such as Shi Xi, wrong, gallium in the stone, indium or The fossil eve body substrate material is, for example, a semiconductor wafer 220 for the structure. A plurality of semiconductor dies or members 224 are formed on the 18 201225209 wafer 220 and separated by a scribe line 2 26 as described above. Figure 9b is a cross-sectional view showing a portion of a semiconductor wafer 220. Each semiconductor die 224 has a back surface 228 and an active surface 230' including an analog or digital circuit that is implemented to be formed in An active fruit, a passive device, a conductive layer, and a dielectric layer within the die and electrically interconnected according to electrical design and function of the die. For example, the circuit can include a plurality of transistors, diodes, and others Circuit elements formed within active surface 23A to implement analog circuits or digital circuits, such as digital signal processors (DSPs), ASICs, memory, or other signal processing circuits. The semiconductor die 224 may also include integrated passive devices, such as inductors, capacitors, and resistors, for use in RF signal processing. In one embodiment, the semiconductor crystal grain 224 is a flip chip type semiconductor die. - Conductive layer 232 is formed over active surface 230 by PVD, CVD 'electrolytic plating, electroless plating process, or other suitable metal deposition process. The conductive layer 232 can be an octa-Cu, a ruin, an A"

Ag, or one or more layers of other suitable electrically conductive materials. Conductive layer 232 operates as contact pads 3 or die bump pads that are electrically connected to circuitry on the active meter® 23®. Figure 9c shows a portion of a semiconductor wafer 220 having an interconnect structure formed over a contact pad 232. The conductive bump material 234 is fine; with - evaporation, electrolysis (4), electroless ore, ball Dropping (4)^), or a screen printing process, is deposited on the contact pad 232. The bump material ^ may be A, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and illusion, which has an optional flux dissolve, for example, bump material Mi 19 201225209 It can be a eutectic Sn/Pb, a solder to the ship, or a solder without a button. The bump material 234 is substantially compliant and undergoes a plastic deformation of greater than about 25 μη under a force corresponding to a vertical load of about 2 gram. The bump 234 is bonded to the contact pad 232 by a suitable attachment or bonding process. For example, the bump material 234 can be compressively bonded to the contact pad 232. The bump material 234 can also be reflowed by heating the material beyond its melting point to form a ball or bump 236', as shown in Figure 9d. In some applications, bumps 236 are subjected to secondary reflow to improve electrical connection to contact pads 232. Bump 236 represents a type of interconnect structure that can be formed over contact pads 232. The interconnect structure can also use stud bumps, microbumps, or other electrical interconnects. Figure 9e shows another embodiment of an interconnect structure formed with a composite bump 238 over a contact pad 232 that includes a non-refinable or indecomposable portion 240 and a fusible or decomposable portion. Part 242. The fusible or decomposable trait and the non-meltable or non-decomposable trait are defined for the bump 238 with respect to the reflow condition. The non-meltable portion 2 may be Au, Cu, Ni, high lead solder, or a lead tin alloy. The fusible portion 242 can be Sn, a lead-free alloy, a Sn_Ag alloy, an alloy, a Sn-Ag-indium alloy, a eutectic solder, a tin and an Ag, an alloy, or other relatively low temperature. Melted solder. In one embodiment, given: the width or diameter of the contact pad 232 1 〇〇 η ι η η η η η π π π π π π π π π π π π π π π π π π π π π π π π π π π Figure 9f shows another embodiment of an interconnect structure formed over bumps 232 to form bumps 244 over conductive pillars 246. The bumps 244 are fusible or decomposable and the conductive posts 246 are non-meltable or non-decomposable. 20 201225209 The fusible or solvable 4 temples and the insoluble or indecomposable traits are defined in terms of reflow conditions. The bumps 244 may be Sn, a lead-free alloy, a Sn-Ag alloy, a Sn.Ag_Cu alloy, a Sn Agin alloy eutectic solder, an alloy of tin and Ag, Cu or Pb, or other relatively low temperature molten solder. The conductive pillars 246 may be Au, Cu, Ni, high-error bars, or mis-tin alloys. In the embodiment the conductive pillar 246 is a Cu pillar and the bump 244 is a solder cap. Given the width or diameter of a contact pad 232 ΙΟΟμπι, the height of the conductive post 246 is approximately 45 μm, and the height of the bump 244 is approximately 35 μm. Figure 9g shows another embodiment of an interconnect structure formed over contact pads 232 and having bump material 248 having an aperture 25 turns. Similar to bump material 234', bump material 248 is soft and deformable under reflow conditions, has low yield strength and high elongation to failure. The bumps 250 are formed by electroplated surface treatment and are shown exaggerated in the drawings for purposes of illustration. The level of the bump 250 is generally on the order of magnitude. The bumps can also be formed on the bumps 236, the composite bumps 238, and the bumps 244. In Figure 9h, the semiconductor wafer 22 is individually diced into individual semiconductor dies 224 through a scribe line 226 using a saw blade or laser cutting tool 252. Figure 10A shows a substrate or crucible having a conductive trace 256 (: β 254. The substrate 254 can be a single-sided FR5 laminate or a double-sided BT_resin laminate. The semiconductor die 224 is configured such that the bumps are The material 234 is aligned with the interconnect locations on the conductive traces 256, see Figures 6a-6c, 7-8, and 18a-18c. Alternatively, the bump material 234 can be aligned with conductive pads or other interconnect locations formed on the substrate 254. The bump material 234 is wider than the conductive traces 256. 21 201225209 In one embodiment, for a bump pitch of 150 μηη, the bump material 234 has a width less than ΙΟΟμηη, and the conductive traces or pads 256 have a width of 35 μm. An interconnect structure formed using a solder mask patch as described in Figures 5-8 can be applied. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 234 to Above the conductive line 256, the force F can be applied at a high temperature. Due to the compliant nature of the bump material 234, the bump material is deformed or protrudes around the top surface and the side surface of the conductive line 256, which is called BOL. Especially, At a force F corresponding to a vertical load of about 200 grams, the pressure is applied such that the bump material 234 undergoes plastic deformation greater than about 25 μm and covers the top and side surfaces of the conductive trace, as shown in FIG. The bump material 234 can also be metallurgically bonded to the conductive traces 256 by contacting the bump material with the conductive traces and then reflowing the bump material at a reflow temperature. The block material 234 is narrow and the pitch of the conductive traces can be lowered to increase the wire density and the number of turns. The narrower conductive traces 256 reduce the force F required to deform the bump material 234 around the conductive traces. The necessary force F may be 3 所需 required to deform the bump material against a conductive line or pad wider than the bump material. The smaller pressure F has a fine pitch interconnect and a small die retention - Specifying the coplanarity of the tolerances and achieving a z-direction deformation of the uniform sentence and a high-reliability interconnection combination is used. Further, the bump material 234 is deformed in the conductive line 25 to mechanically lock the bump Go to the line to avoid = moving or grain floating. Between the epochs and the granules 22 201225209 Figure 10c shows the bumps 236 formed over the contact pads 232 of the semiconductor die 224. The semiconductor die 224 is arranged such that the bumps 236 is aligned with the interconnection locations on conductive traces 256. Alternatively, bumps 236 can be aligned with conductive pads or other interconnect locations formed on substrate 254. Bumps 236 are wider than conductive traces 256. Conductive traces 256 An interconnect structure formed using a solder mask patch as described in Figures 5-8 can be applied. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump 236 to the conductive Above line 256. This force F can be applied at high temperatures. Due to the compliant nature of the bumps 236, the bumps deform or protrude around the top and side surfaces of the conductive traces 256. In particular, the application of pressure causes the bump material 236 to plastically deform and cover the top and side surfaces of the conductive traces 256. Bumps 236 can also be metallurgically connected to conductive traces 256 by physically contacting the bumps with the conductive traces at reflow temperatures. By making the conductive traces 256 narrower than the bumps 236, the spacing of the conductive traces can be reduced to increase the winding density and the number of turns. The narrower conductive line 256 reduces the force f required to deform the bump 236 around the conductive trace. For example, the necessary force F may be 3 〇 5 % of the force required to deform a bump against a conductive line or pad wider than the bump. The lower pressure "is useful for fine-pitch interconnects and small die-maintained--coplanarity within specified tolerances and for achieving a combination of uniformity and high reliability interconnects. The bump 236 is shaped to mechanically lock the bump around the conductive trace 256 to avoid grain movement or grain floating during reflow. 1 〇 d shows a composite bump 238 formed on the contact 232 of the semiconductor die 224 23 201225209. The semiconductor die 224 is arranged such that the composite bumps 238 and the interconnect locations on the conductive traces 256 are aligned. Alternatively, the composite bumps 238 can be aligned with conductive pads or other interconnect locations formed on the substrate 254. The composite bumps 238 are wider than the conductive traces 256. Conductive lines 256 can be applied to interconnect structures formed using solder mask patches as described in Figures 5-8. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the fusible portion 242 onto the conductive trace 256. This force F can be applied at high temperatures. Due to the compliant nature of the fusible portion 242, the fusible portion is deformed or protrudes around the top and side surfaces of the conductive trace 256. In particular, the application of pressure causes the fusible portion 242 to be plastically deformed and covers the top surface and the side surface of the conductive trace 256. The composite bump 238 can also be made by remelting the portion 242 at the reflow temperature. The conductive traces are physically contacted to metallurgically connected to conductive traces 256. The non-fusible portion 24 is not melted or deformed during application of pressure or temperature, and maintains its height and shape as a vertical gap between the semiconductor die 224 and the substrate 254. This additional displacement between the semiconductor die 224 and the substrate 254 provides a greater coplanarity tolerance between the mated surfaces. The height or amount of fusible bump material relative to the non-fusible base material is selected to ensure limitations by surface tension. During reflow, the fusible base material is confined around the non-fusible base material due to the solder mask patch. "The fusible bump material around the non-fusible substrate also maintains the grain during reflow. setting. In general, the height of the composite interconnect and the diameter of the D meta-bump are the same or smaller than the diameter of the bump. In some 24 201225209 cases the height of the composite interconnect is greater than the diameter of the interconnect. In one embodiment, the diameter of the bump base of a given 丨00 μηη is about 45 (im' in the degree of difference and the thickness of the fusible cover is about 35 μm in height. Because of the solder mask patch And the amount of bump material deposited to form the composite bump (including the non-meltable substrate and the fusible cover) is selected such that the resulting surface tension is sufficient to substantially retain the bump material in the bump pad Within the footprint and avoid spilling into undesired adjacent or nearby regions' so the molten bump material remains substantially confined within the area defined by the bump pads. Therefore, the array gap in the bump pads The solder mask patch formed in the system reduces the line conductor pitch and increases the winding density. A large number (e.g., thousands) of composite bumps 238 on the semiconductor die 224 are attached during a reflow process. The interconnection locations on the conductive traces 256 of the substrate 254. Some of the bumps 238 may not be properly connected to the conductive traces 256', particularly when the die 224 is twisted. Recall that the composite bumps 238 are more conductive than the conductive traces. The path 256 is wide. Under application of a suitable force, the fused portion 242 is deformed or protrudes around the top surface and side surfaces of the conductive trace 256, and the composite bump 238 is mechanically locked to the conductive The mechanically tight connection is formed by the nature of the fusible portion 242, which is softer and more compliant than the conductive trace 256, thus deforming over the top surface of the conductive trace and at the conductive The side surface of the line is surrounded by a larger contact surface area. The mechanically tight connection between the composite bump 238 and the conductive line 256 <RTIgt; is held during reflow, the conductive line, i.e. The bump and the conductive line do not lose contact. In the meantime, the composite bump 238 is coupled to the conductive line 256 to reduce the failure of the bump 25 201225209. Figure 10e shows the contact pad formed on the semiconductor die 224 Conductive posts 246 and bumps 244 over 232. Semiconductor die 224 is disposed to align bumps 244 with interconnect locations on conductive traces 256. Alternatively, bumps 244 can be formed on substrate 254. Conductive pad or The interconnect locations are aligned. The bumps 244 are wider than the conductive traces 256. The conductive traces 256 can be applied to interconnect structures formed using solder mask patches as described in Figures 5-8. A back surface 228 is applied to the semiconductor die 224 to press the bumps 244 onto the conductive traces 256. The force f can be applied at high temperatures. Due to the compliant nature of the bumps 244, the bumps are deformed or protruded The top surface and the side surface of the conductive line 256. In particular, the pressure is applied such that the bump 244 is plastically deformed and covers the top surface and the side surface of the conductive line 256. The conductive post 246 and the bump 244 can also be reflowed. The bump is in physical contact with the conductive trace to metallurgically connect to the conductive trace 256. The conductive post 246 does not melt or deform during application of pressure or temperature and maintains its height and shape to become a vertical gap between the semiconductor die 224 and the substrate 254. This additional displacement between semiconductor die 224 and substrate 254 provides a greater coplanar tolerance between the mated surfaces. The wider bumps 244 and the narrower conductive traces 256 have similar low pressure and mechanical locking characteristics and advantages as described above for the bump material 234 and the bumps 236. 1 shows a bump material 248 having bumps 250 formed over contact pads 232 of semiconductor die 224. The semiconductor die 224 is disposed such that the bump material 248 and the interconnect location on the conductive trace 256 are aligned or 疋, and the bump material 248 can be aligned with the conductive or gossip interconnect formed on the substrate 254. quasi. The bump material 248 is wider than the conductive trace 256. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 = the bump material 248 is pressed onto the conductive trace 256. This force f can be applied under a high shirt. Due to the compliant nature of the bump material 248, the bumps are deformed or canineed around the top and side surfaces of the conductive traces 256. In particular, the application of pressure causes the bump material 248 to plastically deform and cover the top and side surfaces of the conductive line 256. In addition, the bumps 25 are metallurgically connected to the conductive traces 256. The size of the bump 250 is approximately the order of magnitude. Figure 10g shows a substrate or PCB 258 having an angled or slanted side of the trapezoidal conductive line 26A. A bump material 261 is formed over the contact pads 232 of the semiconductor wafer 224. The semiconductor die 224 is arranged to align the bump locations on the bump material 261 and the conductive traces 260. Alternatively, the ' bump material 261 can be aligned with conductive pads or other interconnect locations formed on the substrate 258. The bump material 261 is wider than the conductive trace 260. Conductive line 260 can be applied to an interconnect structure formed using a solder mask patch as described in Figures 5-8. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 261 over the conductive traces 260. This force F can be applied at a high temperature. Due to the compliant nature of the bump material 261, the bump material is deformed or protrudes around the top and side surfaces of the conductive trace 260. In particular, the application of pressure causes the bump material 261 to plastically deform under force F to cover the top surface of the conductive trace 260 and the inclined side surface. The bump 27 201225209 block material 261 can also be metallurgically connected to the normal line 260 by physically contacting the bump material with the conductive traces and then reflowing the ghost material at a mesh soldering temperature. 11 a-11 d show a BOL embodiment of a semiconductor die 224 and an ancient π -, a non-meltable or indecomposable portion 264 and a fusible or decomposable 66 elongated δ bump 262 . The non-fusible portion 264 can be Au, Cu, Ni, high lead solder, or a lead tin alloy. The fusible = 266 may be Sn 'lead-free alloy, Sn-Ag alloy, Sn_Ag Cu human gold, Sn-Ag-In alloy 'eutectic solder, tin and Ag, Cu or other human gold or other relative Low temperature melting solder. The infusible portion ratio = the fusible portion 266 constitutes a larger one of the composite bumps 262 - the non-meltable portion 264 is fixed to the contact of the semiconductor die 224 7 semiconductor die 224 It is arranged such that the composite bumps 262 are aligned with the interconnections formed on the conductive traces 268 on the substrate 270, as shown in Figure 1 la. The composite bumps 262 are tapered along the conductive traces 268, i.e., the composite bumps have a wedge shape that is longer along the length of the conductive traces 268 and narrower across the conductive traces. The tapered features of the composite bumps 262 appear along the length of the conductive traces. The drawing in Figure 1U shows that the shorter feature or the narrowed taper is collinear with the conductive traces 268. The drawing in the figure 丨b perpendicular to the figure 丨la shows the longer features of the wedge-shaped composite bump 262. The shorter features of the composite bumps 262 are wider than the conductive traces 268. The fusible portion 266 is decomposed around the conductive traces during pressure application and/or thermal reflow, i.e., as shown in Figures 1 lc and 1 ld. The non-meltable portion 264 28 201225209 does not refine or deform during reflow, and maintains its shape and shape. The insoluble portion 264 can be sized to provide a gap-to-gap distance between the semiconductor wafer 224 and the substrate 270. - A process such as CuOSP can be applied to the substrate 270. Conductive traces 268 can be applied to interconnect structures formed using solder mask patches as described in Figures 5-8. During a reflow process, a large number (e.g., thousands) of composite bumps 262 on semiconductor die 224 are attached to interconnect locations on conductive traces 268 of substrate 27. Some of the bumps 262 may not be properly connected to the conductive traces 268', particularly when the semiconductor die 224 is distorted. Recall that the composite bump 262 is wider than the conductive trace 268. The fusible portion 266 is deformed or protruded around the top and side surfaces of the conductive trace (10) and a composite bump @262 is mechanically locked to the conductive trace under application of a suitable force. The mechanically tight connection is formed by the nature of the fusible portion. 'The essence is softer and more conformable than the conductive line $ 268, and thus deformed around the tantalum conductive, the tantalum and side surfaces of the line to obtain Large contact area. The wedge shape of the composite bump 262 increases the contact area between the bump and the conductive line, for example, increases along the longer characteristic direction of the figures i lb and i 丨 d without sacrificing along the figures Ua and Uc The spacing in the shorter characteristic direction. The mechanically tight connection between the composite bumps 262 and the conductive traces 268 maintains the bumps on the conductive traces during reflow, i.e., the bumps and conductive traces do not lose contact. Thus, the composite bumps 262 that are coupled to the conductive traces 268 reduce the failure of the bump interconnects. 12a-12d show an embodiment of a semiconductor die 224 in which a bump material 274 is formed over contact pad 232, similar to Fig. 9c'. 29 201225209 In Figure 12a, the bump material 274 is substantially conformable and undergoes a plastic deformation of greater than about 25 μηη under a force equivalent to a vertical load of about 200 grams. The bump material 2 7 4 is wider than the conductive line 276 on the substrate 278. A plurality of bumps 280 are formed on the conductive line 276 at a height on the order of about 1-25 μτη. The semiconductor die 224 is arranged to align the bump locations on the bump material 274 and the conductive traces 276. Alternatively, bump material 274 can be aligned with conductive pads or other interconnect locations formed on substrate 278. - Pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 274 over the conductive traces 276 and bumps 280, as shown in Figure 12b. sH force F can be applied to the temperature. Due to the compliant nature of the bump material 274, the bump material deforms or protrudes around the top and side surfaces of the conductive traces 276 and around the bumps 280. In particular, the application of pressure causes the bump material 274 to plastically deform and cover the top and side surfaces of the conductive traces 276 and the bumps 280. The plastic flow of the bump material 274 creates a giant mechanically tight junction between the bump material and the top and side surfaces of the conductive traces 276 and the bumps 280. The plastic flow of the bump material 274 occurs around the top and side surfaces of the conductive traces 276 and around the bumps 280' but does not excessively extend over the substrate 278, which can otherwise cause electrical shorts and other defects. The mechanically tight connection between the bump material and the top and side surfaces of the conductive traces 276 and the bumps 280 provides a robust contact area with a large contact area between the individual surfaces without significantly increasing the bonding force. Connection. The mechanically tight connection between the bump material and the top and side surfaces of the conductive traces 276 and the bumps 280 also reduces the lateral grain movement during subsequent processes such as packaging. Figure 12c shows another BOL embodiment in which the bump material 274 is narrower than the conductive traces 276. A pressure or force F is applied to the responsible surface 228 of the semiconductor die 224 to press the bump material 274 onto the conductive traces 276 and the bumps 280. This force F can be applied at the temperature. Due to the compliant nature of the bump material, the bump material deforms or protrudes above the top surface of the conductive trace 276 and over the bump 280. In particular, the application of pressure causes the bump material 274 to plastically deform and cover the top surface of the conductive trace 276 and the bump 280. The plastic flow of the bump material 274 creates a giant mechanically tight joint between the bump material and the top surface of the conductive trace 276 and the bump 28〇. The mechanically tight connection between the bump material and the top surface of the conductive trace 276 and the bump 28 提供 provides a robust connection with a large contact area between the individual surfaces without significantly increasing the bonding force. . The mechanically tight connection between the bump material and the top surface of the conductive traces 276 and the bumps 28A also reduces lateral grain movement during subsequent processes such as packaging. Figure 12d shows an alternative embodiment in which the bump material π is formed over an edge of the conductive trace 276, i.e., a portion of the bump material is over the conductive trace and a portion of the bump The block material is not above the conductive trace. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 274 onto the conductive traces 276 and the bumps 28A. This force F can be applied at high temperatures. Due to the compliant nature of the bump material 274, the bump material deforms or protrudes above the top and side surfaces of the conductive traces 276 and over the bumps 280. In particular, the application of pressure causes the bump material "4 31 201225209 to plastically deform and cover the top and side surfaces of the conductive traces 276 and the bumps 280. The plastic flow of the bump material 274 is between the bump material and the conductive traces 276. A mechanically tight connection between the top surface and the side surfaces and the bumps 28A. The mechanically tight connection between the bump material and the top and side surfaces of the conductive traces 276 and the bumps 280 is Providing a robust connection with a large contact area between individual surfaces without significantly increasing the bonding force. A mechanically tight connection between the bump material and the top and side surfaces of the conductive traces 276 and the bumps 280 The lateral grain movement during subsequent processes such as encapsulation is also reduced. Figure 1 3a-1 3c shows a b〇l embodiment of a semiconductor die 224, wherein similar to Figure 9c, bump material 284 is formed in the contact pad. Above the 232. A tip 286 extends from the body of the bump material 284 to a stepped bump 'where the tip 286 is narrower than the body of the bump material 284, as shown in Figure 13a. The bulk die 224 is configured to align the bump material 284 with the interconnect locations on the conductive traces 288 on the substrate 290. More specifically, the tip 286 is disposed centrally at the interconnect location on the conductive traces 288. Alternatively, the bump material 284 and the tip 286 can be aligned with conductive pads or other interconnect locations formed on the substrate 290. The bump material 284 is wider than the conductive traces 288 on the substrate 290. The conductive traces 288 are substantially Compliant, and plastic deformation greater than about 25 μm is performed under a force corresponding to a vertical load of about 2 gram. A waste force or force F is applied to the back surface 228 of the semiconductor die 224 to bring the tip 284 Pressed onto conductive line 288. This force f can be applied at high temperatures. Due to the compliant nature of conductive line 288, the conductive line is deformed around tip 32, 201225209 end 286, as shown in Figure 3b. In particular, the application of pressure causes the conductive traces 288 to plastically deform and cover the top and side surfaces of the tip 286. Figure 1c shows another embodiment of the BOL in which a circular bump material 294 is formed in contact. Above the 232. A tip 296 extends from the body of the bump material 294 to form a stud bump, wherein the tip is narrower than the body of the bump material 294. The semiconductor die 224 is configured such that the bump material 294 and The interconnections on the conductive traces 298 on the substrate 300 are aligned. More specifically, the 'tips 296 are disposed on the center of the interconnect locations on the conductive traces 298. Alternatively, the bump material 294 and the tips 296 can The conductive pads or other interconnects formed on the substrate 300 are aligned. The bump material 294 is wider than the conductive traces 298 on the substrate 300. Conductive line 298 is generally compliant and undergoes a plastic deformation of greater than about 25 μηη under a force corresponding to a vertical load of about 2 gram. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the tip 296 onto the conductive trace 298. This force f can be applied at high temperatures. Due to the compliant nature of the conductive traces 298, the conductive traces are deformed around the tips 296. In particular, the application of pressure causes the conductive traces 298 to plastically deform and cover the top and side surfaces of the tip 296. The conductive traces described in Figures 10a-10g, 1 la-1 Id and 12a-12d may also be compliant materials as described in Figures 13a-13c. Figures 14a-14b illustrate a BOL embodiment of a semiconductor die 224 in which a bump material 304 is formed over contact pad 232, similar to Figure 9c'. The bump material 304 is substantially compliant' and undergoes a plastic deformation greater than about 25 μιη under a force corresponding to a vertical load of about 2 gram 33 201225209. The bump material 304 is wider than the conductive traces 3〇6 on the substrate 308. A conductive via 31 having an opening 312 and a conductive sidewall 314 is formed through the conductive traces 3, 6 as shown in Figure 14a. Conductive lines 3〇6 can be applied to interconnect structures formed using solder mask patches as described in Figures 5-8. The semiconductor die 224 is arranged to align the bump locations on the bump material 3〇4 and the conductive traces 306. See Figures 6a, 6c, 7-8, and 18a-18c. Alternatively, the bump material 3〇4 can be aligned with the conductive pads or other interconnect locations formed on the substrate 3〇8. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 304 over the conductive traces 306 and into the openings 312 of the conductive vias 31'. This force f can be applied at high temperatures. Due to the compliant nature of the bump material 3〇4, the bump material is deformed or protrudes around the top surface and the side surface of the conductive trace 3〇6 and into the opening 312 of the conductive via 31〇, as in the figure The one shown in the summer servant. In particular, the application of pressure causes the bump material 3〇4 to be plastically deformed and covers the top and side surfaces of the conductive traces 3〇6 and into the openings 312 of the conductive vias 310. Thus, the bump material 3〇4 is electrically connected to the conductive traces 306 and the conductive sidewalls 314 for use in the z-direction vertical interconnect through the substrate 3〇8. The plastic flow of the bump material 3〇4 creates a mechanically tight connection between the bump material and the top and side surfaces of the conductive traces 306 and the openings 312 of the conductive vias 3丄〇. The mechanically tight connection between the bump material and the top and side surfaces of the conductive traces 306 and the openings 312 of the conductive vias 31 is provided to provide a larger surface between the individual surfaces without significantly increasing the bonding force. A robust connection to the contact area. The mechanically tight connection between the bumps of the 201225209 block material and the top and side surfaces of the conductive traces 306 and the openings 3 12 of the conductive vias 3 i 亦 also reduces lateral grain movement during subsequent processes such as packaging. . Since the conductive via 3 and the bump material 304 are formed together within the interconnection position, the total substrate interconnection/area is reduced. In the BOL embodiments of Figures 10a-10g, Ua_lld, 12a-12d, (1), (1), and 14a l4b, by making the conductive traces narrower than the interconnect structure, the pitch of the conductive traces can be reduced to increase the wire density and the number of turns. The narrower conductive circuitry reduces the force F required to deform the interconnect structure around the conductive traces. For example, the necessary force F may be such that a bump abuts a width wider than the bump

The force required to deform the conductive line or pad is 3〇_5〇%. This lower pressure F is useful for fine pitch interconnects and for the coplanarity of small grains to maintain within a specified tolerance and to achieve uniform Z-direction deformation and high reliability interconnect bonding. In addition, deforming the interconnect structure around the conductive trace mechanically locks the bump to the trace to avoid grain movement or die floating during reflow. Figures 15a-15c illustrate a mold underfill (Muf) process for depositing a package material around a bump between a semiconductor die and a substrate. Figure 15a shows the semiconductor die 224 mounted to the substrate 254 using the bump material m of _ 1 () b and disposed over the upper mold support 316 and the lower mold support 318 of the chase mold 32 〇 between. The other semiconductor die and substrate combination of the drawings i〇ai〇g, (1)(1), 12a-12d, 13a-13c and 14a-14b may also be disposed on the upper mold support 316 and the lower mold branch of the groove mold 32〇. Between pieces 318. The upper mold support 316 comprises a release film 322 that is compressible by 35 201225209. In Figure 15b, the upper mold support 316 and the lower mold support 318 are placed together to enclose the semiconductor die 224 and the substrate 254 having an open space over the substrate and between the semiconductor die and the substrate. . A compressible release film 322 conforms to the back surface 228 and side surfaces of the semiconductor die 224 to block the formation of the encapsulating material on these surfaces. A liquid encapsulating material 324 is injected into one side of the groove mold 320 using the nozzle 326, and an optional vacuum assist 328 is sucked from the opposite side to uniformly fill the encapsulating material into the substrate 254. The open space above and the open space between the semiconductor die 224 and the substrate 254. The encapsulating material 324 may be a polymer composite (e.g., an epoxy resin having a filler, an epoxy acrylate having a filler), or a polymer having a suitable filler. The encapsulation material 324 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. The compressible material 322 prevents the encapsulation material 324 from flowing over the back surface 228 of the semiconductor die 224 and around the side surfaces. The encapsulating material 324 is cured. The back surface 228 and side surfaces of the semiconductor wafer 224 remain exposed from the encapsulation material 324. Figure 15c shows an embodiment of MUF and mold overfill (MOF), i.e., without compressible material 322. The semiconductor die 224 and the substrate 254 are disposed between the upper mold support 316 and the lower mold support 318 of the groove mold 32A. The upper mold support 316 and the square mold support 318 are placed together to enclose the semiconductor die 224 and the substrate 254 having an open space over the substrate, around the semiconductor die, and at the semiconductor Between the die and the substrate. The liquid-filled package 36 201225209 material 324 is injected into one side of the groove mold 32 by nozzle 326, and an optional vacuum assist 328 is sucked from the opposite side to evenly fill the package material. An open space is formed around the semiconductor die 224 and over the substrate 254 and an open space between the semiconductor die 224 and the substrate 254. The encapsulating material 324 is cured. Figure 16 illustrates another embodiment of depositing an encapsulation material around the semiconductor die 224 and in the gap between the semiconductor die 224 and the substrate 254. Semiconductor die 224 and substrate 254 are enclosed by a dam 33 (). The encapsulation material 332 is dispensed from the nozzle 334 into the barrier 33A in a liquid state to fill the open space above the substrate 254 and the open space between the semiconductor die 224 and the substrate 254. The tether of the encapsulating material 332 dispensed from the nozzle 334 is controlled to fill the barrier 330 under the back surface 228 or side surface that does not cover the semiconductor die 224. The encapsulating material 332 is cured. 17 shows the semiconductor die 224 and the substrate 25 package material 324 after the MUF process of FIGS. 16a, 16c, and 17 are uniformly spread over the substrate 254 and between the semiconductor die 224 and the substrate 254. Around material 234. Figures 18a-18c are top plan views showing various conductive line layouts on a substrate or PCB 34. In Figure 18a, conductive trace 342 is a straight conductor formed on substrate 340 having an integral bump pad or interconnect location 344. The sides of the substrate bump pads 344 may be collinear with the conductive traces 342. In the prior art, an SRO is typically formed over the interconnect location to limit the bump material during reflow. This SR〇 increases the interconnect spacing and reduces the number of "〇. In contrast, the mask layer 346 can be formed on a portion of the substrate 34 37 37 201225209; however, the mask layer is not formed around the substrate bump pads 344 of the conductive traces 342. In other words, the portion of conductive trace 342 that is designed to mate with the bump material does not have any SRO that would otherwise be used for bump-limited masking layer 346 during reflow. Semiconductor die 224 is disposed over substrate 34A and the bump material is aligned with substrate bump 344. The bump material is electrically and metallurgically bonded to the substrate bump pad 344 by physically contacting the bump material with the bump pad and then reflowing the bump material at a reflow temperature. In another embodiment, a conductive bump material is deposited over the substrate bumps 344 by an evaporation, electrolytic plating, electroless plating, ball dropping or screen printing process. The & block material can be M, I, PA, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional fluxing agent. For example, the bump material can be a eutectic Sn/pb, a high lead solder, or a lead free solder. The bump material is bonded to the substrate bump pad 344 by a suitable attachment or bonding process. In one embodiment, the bump material is soldered back and forth by heating the material beyond its melting point to form bumps or interconnects 34, i.e., as shown in Figure m. In some applications, the bumps > 1 are subjected to a second reflow to improve electrical contact to the substrate bump pads 344. The bump material around the narrow substrate bumps 344 is the most desirable in the application of the wire-wound density during reflow, the most important, and the most desirable. The escape spacing between the conductive traces 342 can be used by layers: the mask layer for reflow soldering purposes, i.e., by reflow solder bump material without masking. Since no SR is formed around the bump pad 232 or the substrate bump pad 344, the conductive traces 342 can be formed with a fine pitch 'that is, the conductive traces 342 can be placed closer together or Closer to the nearby structure. Under the absence of SRO around the substrate bump pad 344, the spacing between the conductive lines 342 is given as P = D + PLT + W / 2, where D is the base diameter of the bump 348 and pLT is the die set tolerance. And W is the width of the conductive line 342. In one embodiment, given the bump base diameter of ΙΟΟμιη, the PLT of 1 μm, and the line width of 30 μm, the minimum escape pitch of the conductive trace 342 is 125 pm. The shovel-free bump formation eliminates the need to consider the hole spacing, the solder mask alignment tolerance (SRT), and the minimum resolvable of the mask material between adjacent openings as seen in the prior art. Sr〇. When the bump material is reflowed without the mask layer to metallurgically and electrically connect the die bump pads 232 to the substrate bump pads 344, wetting and surface tension are such that the bump material maintains self-limiting (self And being held in the space between the die bump pad 232 and the substrate bump pad 344 and the substrate 340 adjacent to the conductive trace 342 and passing through the portion of the bump pad. To achieve the desired self-limiting nature, the bump material can be immersed in a fluxing agent prior to placement on the die bump pad 232 or the substrate bump pad 344 to selectively cause the bump material to be The area of contact is more humid than the area around the conductive line 342. The molten bump material is maintained confined within the area substantially defined by the bump pads due to the wettability of the fluxing solvent. The bump material does not spill into the less humid areas. A thin oxide layer or other insulating layer may be formed over the area of 201225209 where no bump material is intended to make the area less humid. Therefore, the mask layer 340 is not required around the die bump 塾2 3 2 or the substrate bump pad 344. Figure 18c shows another embodiment of a parallel conductive track 352 being a straight conductor' wherein an integral rectangular bump pad or interconnect location 354 is formed on substrate 350. In this example, the substrate bump pads 354 are wider than the conductive traces 352, but less than the mated bump widths. The sides of the substrate bump pads 354 may be parallel to the conductive traces 352. A mask layer 356 can be formed over a portion of the substrate 350; however, the mask layer is not formed around the substrate bump pads 354 of the conductive traces 352. In other words, the portion of the conductive trace 352 that is designed to mate with the bump material does not have any SRO that would otherwise be used for the bump layer 356 that was bump-limited during reflow. 19 shows a stacked package (PoP) 4〇5 in which semiconductor dies 4〇6 are stacked on a semiconductor die 4〇8 using a die attach adhesive 410. The semiconductor bb particles 406 and 408 each have an active surface including an analog or digital circuit, and the analog or digital circuit is implemented as an active device and passively formed within the die and electrically interconnected according to electrical design and function of the die. Device, conductive layer and dielectric layer. For example, the circuit can include one or more transistors, diodes, and other circuit components formed within the active surface to implement analog or digital circuitry, such as Dsp, ASIC, memory, or other signal processing circuitry. Semiconductor dies 406 and 408 may also include IPDs such as inductors, capacitors, and resistors for use in RF signal processing. The semiconductor die 406 is made by using FIG. 1〇a_1〇g, Ua Ud, 12a l2d,

Any of the embodiments of Ba-Ud 14a.14b, (iv) the germanium block material 416 formed on the contact pads 4A8, is mounted to the conductive traces 412 formed on the substrate 414 40 201225209 » conductive traces 412 It can be applied to an interconnect structure formed using a solder mask patch as described in Figures 5-8. The semiconductor die 408 is electrically connected to the contact pads 420 formed on the substrate 414 by bond wires 422. The opposite end of the bond wire 422 is bonded to the contact pad 424 of the semiconductor die 406. The mask layer 426 is formed over the substrate 414 and extends beyond the footprint of the semiconductor die 406. Although the mask layer 426 does not limit the bump material 416 to the conductive traces 412 during reflow, the open mask can function as a barrier to avoid migration of the encapsulation material 428 to the contact pads 42 or bond wires 422 during the MUF. The encapsulation material 428 is deposited between the semiconductor die 4'8 and the substrate 414 similar to Figures 15a-15c. Mask layer 426 blocks muf seal material 428 from contact & 42() and bond wire 422, which may otherwise cause defects. Mask I 426 allows larger semiconductor dies to be placed on a particular substrate without the risk of encapsulation material 428 flowing over contact pads 420. Although one or more embodiments of the present invention have been described in detail, those skilled in the art will recognize that the invention may be practiced without departing from the scope of the invention as set forth below. EXAMPLES Modifications and Adjustments [Simple Description of the Drawings] The wiring diagram 1 on the substrate depicts a cross-sectional view of a conventional interconnection formed between the semiconductor die and the - line; the green is formed through the solder mask opening Figure 41 above the line conductor 201225209 The top view of the conventional interconnection; Figure 3 is a description of the continued *, an An Meng 5 丨丨 甘 主 主 主 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Package

Figures 4a-4c are further details of the PCB for the teaching of the trace; "The representative semiconductor package of Figure 5 is a diagram depicting the interconnection between the line conductors formed on a semiconductor die and a substrate; Figure 6a 6c is an integrated bump pad along the line conductor; FIG. 7 is a solder mask patch in the gap of the integrated bump pad array formed on the substrate; FIG. 8 is formed in the body convex Bumps on the block pad wherein the bump material is limited during solder reflow by solder mask patches; Figures 9a-9h depict various types of conductive traces formed over a semiconductor die for bonding to a substrate Figure 10a-1 shows the semiconductor die and the interconnect structure connected to the conductive traces; Figure 11 a-11 d depicts a wedge-shaped interconnect structure bonded to the conductive traces The semiconductor die; FIGS. 12a-12d depict another embodiment of the semiconductor die and the interconnect structure bonded to the conductive traces; FIG. 1 3 a - 13 c is used to lift the ladder connected to the conductive traces Bump and column bump interconnect structure; Figures 14a-14b depict conductive traces with conductive vias; Figure 15 a-15 c depicts the mold underfill between the semiconductor die and the substrate; 42 201225209 Figure: Glue fill; 16 is depicted in the semiconductor Another mold base between the die and the substrate. FIG. 17 is a view showing a package of a conductive line having a solder-aligned semiconductor die and a substrate after the mold underfill is filled. material

POP 〇Μ during mold base filling [Main component symbol description] 10 flip chip type semiconductor die 12 interconnect or bump 14 bump 18 bump pad 20 line wire 22 line wire 26 solder mask 28 solder mask Shield or alignment opening 30 substrate., 50 electronic device 52 printed circuit board 54 line 5 6 wire bonding package ^ 58 flip-chip spherical thumb matrix 歹 ij 43 201225209 62 bump wafer carrier 64 double row package 66 platform grid Array 68 Multi-Chip Module 70 Quad Flat No-Lead Package 72 Quad Flat Package 74 Semiconductor Die 76 Contact Pad 78 Intermediate Carrier 80 Conductor 84 Bond Wire 84 Packaging Material 88 Semiconductor Die 90 Carrier 92 Primer Fill or Epoxy Adhesive material 94 Bonding wire 96 Contact pad 98 Contact pad 100 Molding compound or encapsulating material 102 Contact pad 104 Bump 106 Intermediate carrier 108 Active area 110 Bump 44 201225209

111 bump pad 11 2 bump 114 signal line 115 PCB 116 molding compound or encapsulation material 11 7 ball or bump 118 conduction line 120 flip chip type semiconductor die 122 bump pad 130 line wire 132 line wire 136 substrate 1 3 8 bump pad 139 bump pad 140 bump pad 142 solder mask 144 non-wetting solder mask patch 150 ball or bump 152 ball or bump 220 semiconductor wafer 222 body substrate material 324 semiconductor die or member 226 Cutting surface 228 back surface 45 201225209 230 active surface 232 conductive layer 234 bump material 236 ball or bump 238 composite bump 240 non-fusible portion 242 fusible portion 244 bump 246 conductive column 248 bump material 2 50 0-bump 252 saw blade or laser cutting tool 254 substrate 256 conductive line

258 substrate or PCB 260 conductive line 261 bump material 262 composite bump 264 non-meltable or indecomposable portion 266 fusible or decomposable portion 268 conductive line 270 substrate 274 bump material 276 conductive line 46 201225209 278 substrate 2 8 0 bump 284 bump material 286 tip 288 conductive line 290 substrate 294 bump material 296 tip 298 conductive line 300 substrate 304 bump material 306 conductive line 308 substrate 3 10 conductive through hole 312 opening 314 conductive side wall 3 16 above Mold support 318 lower mold support 320 groove mold 322 compressible release film 324 encapsulation material 326 nozzle 328 auxiliary 330 barrier 47 201225209 332 encapsulation material 334 nozzle 340 substrate 342 conductive line 344 substrate bump pad 346 mask layer 348 Bump or interconnect 350 substrate 352 conductive line 354 substrate bump pad 3 5 6 mask layer 405 stacked package 406 semiconductor die 408 semiconductor die 4 1 0 die attach adhesive 4 1 2 conductive trace 414 substrate 416 convex Block material 4 1 8 contact pad 420 contact pad 422 bond wire 424 contact pad 426 mask layer 428 encapsulation material 48

Claims (1)

201225209 VII. Patent Application Range: 1. A method of fabricating a semiconductor device, comprising: providing a semiconductor die having a plurality of die bump pads; providing a substrate having a plurality of conductive traces with interconnect locations; Forming a solder mask patch in the gap between the die bump pads or interconnect locations; depositing a conductive bump material on the interconnect locations or the die bump pads; mounting the semiconductor die to the substrate Having the conductive bump material disposed between the die bumps and the interconnect locations; soldering the conductive bump material under the die bump pad or interconnect locations without solder masking Forming an interconnect structure between the semiconductor die and the substrate, wherein the solder mask patch confines the conductive bump material to the die bump or interconnect location; and between the semiconductor die and the substrate Deposit packaging material. 2. The method of claim 2, wherein the solder mask patch comprises a non-wetting material. 3. If you apply for a patent range! The side of the item; going further includes immersing the conductive bump material in a solubilizing solvent to increase wettability. 4. The method of claim 1, further comprising selecting an amount of conductive bump material deposited between the die bump pads and the interconnect locations such that surface tension maintains the conductive bump material substantially It is limited to the coverage areas of the die bump pads and interconnection locations. The method of claim 1, wherein the interconnect structure covers a top surface and a side surface of the die pad pad or interconnection location. 49 201225209 6. The method of claim </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Providing a second semiconductor structure having a plurality of: interconnection locations; biting the shield patch at the first interconnect locations; forming a solder between the first interconnect locations to cover the first and second inter Forming a bump material from the conductive bump material, the semiconductor structure, wherein the smear mask = 连结 to connect the first and second limits to the first interconnect locations or the second interconnect locations; The Ghost Materials Bureau deposits an encapsulation material between the first and second semiconductor structures. 8. The method of claim 7, comprising a non-wetting material. The solder bump mask patch 9 is as claimed in claim 7, wherein the further bump material is immersed in the flux solvent to increase the thirst. In the method of derivative deposition = profit range item 7, the further step includes selecting &quot;hoarding the first and second mutual inspections in § hai, to 4 - between the conductive bump materials - * The tension maintains the coverage area of the conductive bump material in the first-interconnecting position or the second interconnecting position. The method of claim 7 wherein the interconnecting structure is: 4 the first interconnecting location or the top surface of the second interconnecting location and the side table 12. The method of claim 7 Where the interconnect structure 50 201225209 comprises a fusible portion and a non-fusible portion. 1 3 • The method of claim 7 includes a conductive post and a method of forming the same, wherein the interconnect structure is a bump above the post. 14. A method of fabricating a semiconductor device, comprising: providing a first semiconductor structure having a plurality of first interconnect locations; providing a second semiconductor structure having a plurality of second interconnect locations; and wherein the first interconnects Forming a solder mask patch between the locations or the second interconnect locations; and forming an interconnect structure to bond the first and second semiconductor structures, wherein the solder mask patch limits the interconnect structure to the An interconnected location or a second interconnected location. The method of claim 14, further comprising depositing a package material between the first semiconductor structure. The method of claim 14, wherein the solder mask patch comprises a non-wetting material. 17. The method of claim 14, further comprising immersing the bump material in a fluxing solvent to increase wettability. (4) The method of claim 14, wherein the interconnection structure is a top surface and a side surface of the interconnection location or the second interconnection location. 19. The method of claim 14, wherein the interconnect structure is a fusible portion and a non-fusible portion. The method of claim 14, wherein the interconnect structure is electrically conductive and "bumps formed over the conductive pillars. 21" is a semiconductor device comprising: 51 201225209 "there are a plurality of a first half of the interconnect structure; a second semiconductor structure having a plurality of second interconnect locations. a mask = solder joint between the first or second interconnect locations, ''Heil-and second semiconductor structure interconnect structure, == confining the interconnect structure to the first _interconnect: set: first interconnect position; and p-product at β _ and second The encapsulating material between the semiconductor structures. 2. The semiconductor-mounted mask patch according to claim 21 of the patent application includes non-four materials. 23_ As disclosed in the patent application scope g 2135, the structural structure covers (4) - the interconnection position or the Erhai interconnect surface. The top surface and side of the Incheon position. 24. The structure of the 21st structure of the patent application is the sentence 人 卞 卞 卞 , device, where the interconnection ', package 3 fusible part and not The part of the fusion. 2 For example, the half-structure of the 21st patent application area The utility model comprises a training device, wherein the interconnection ... the electric column and the bump formed on the conductive column. 8. Drawing: (such as the next page) 52