JP2002118210A - Interposer for semiconductor device and semiconductor using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interposer for a semiconductor device which is suited to miniaturization and is inexpensive by carrying out flip-chip bonding without bumps. SOLUTION: The interposer has a wiring layer 5 in which a wiring pattern 51 is formed on one surface of an adhesive 4 which is an insulator having adhesive properties. Metallic columns 3 electrically connected are arranged perpendicularly to the layer 5. The columns 3 are insulated from each other by the adhesive 4 in the transverse direction (direction of a plane). On the surface not contacting with the columns 3 of the layer 5, gold is plated on a nickel plated base layer. The end surface of the columns 3 other than the layer 5 side is plated with any of gold, tin, silver and solder.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interposer for relaying between an LSI chip and an external terminal, and more particularly, to a chip size package (hereinafter, abbreviated as CSP) having a size substantially equal to the size of the LSI chip. The present invention relates to a semiconductor device interposer and a semiconductor device using the same.

[0002]

2. Description of the Related Art Semiconductor packages are continually becoming thinner and smaller. Recently, a package called a CSP (chip size package) having the same size as a semiconductor chip is often used.

Conventionally, the types of such CSP semiconductor devices include those using a ceramic wiring board (Ceramics) as an interposer between an LSI chip and external terminals (CCSP), TAB (Tape Automated Bonding) and TCP (TCP). A device using a flexible wiring board (TCSP) similar to that of a tape carrier package (TCSP) is known.

FIG. 4 shows a typical CSP structure. In each case, an insulating base material 21 such as an insulating film made of a polyimide resin is used.
A wiring board 20 having a structure in which a wiring layer 22 having a predetermined pattern is formed thereon is used as an interposer. Then, the electrodes 25 of the semiconductor chip 24 mounted thereon and the wiring board 2
For connection to the wiring layer 22 of No. 0, a wire bonding method using a bonding wire 23 as shown in FIG. 4A or a bump 27 at the tip of an inner lead 26 as shown in FIG. The TAB bonding method of providing and connecting to the electrode 25 is employed. Further, in order to make a connection at a narrow pitch, a wiring layer 22 as shown in FIG.
A flip-chip connection method has been considered in which a bump 28 is provided on the upper surface, and the bump 28 is directly connected to the electrode 25 via the bump 28.

FIG. 5 shows the flip chip connection method.
As shown in (a) to (f), various methods have been proposed (FIG. 5, Journal of Electronics Packaging Society, Vol, 1N).
o, 5 (1998) p423-p428) are common in that in each case, bumps (protruding electrodes) 28a to 28f need to be formed on the semiconductor chip 21 side.

In FIG. 5, (a) shows a Sn-Pb bump or A
Metal bonding by u bump 28a (solder or gold bump)
(B) is an example of conductive paste bonding (ball bump) using a ball bump 28b and a conductive paste 29, and (c) is an Au bump 28c and a photocurable resin 30.
(D) is an example of metal bonding (alloy bump) using a ball bump 28d and an In alloy solder 31, and (e) is an Au bump 28e.
(F) shows an example of conductive paste bonding (gold bump) using a conductive paste 29 and an Au bump 28f and an ACF.
(Anisotropic Conductive Film
) 32 is an example of ACF bonding.

[0007]

As described above, in the conventional flip chip connection method, it is necessary to form bumps on a semiconductor chip in any case. The bump forming method includes a plating method, a wire bonding method, a transfer method, and the like, all of which require a long process and time, and cause an increase in cost. Therefore, there is a need for a method capable of flip-chip connection without bumps.

As a solution to this problem, for example, as shown in FIG.
4, the metal pillars 15 are aligned in the thickness direction, and each metal pillar 15 is insulated in the horizontal direction (planar direction), and each metal pillar 15 is insulated from the film ( Hereinafter referred to as “metal pillar embedded anisotropic conductive film”) 1
A method of connecting the bonding pads 10 on the semiconductor chip 9 side to the bonding pads 16 on the wiring pattern 13 on the wiring substrate 14 side by interposing the semiconductor chip 9 between the semiconductor chip 9 and the wiring substrate 14 is conceivable.

However, the configuration shown in FIG. 3 requires both the metal pillar buried anisotropic conductive film 12 and the wiring board 14 as an interposer for a semiconductor device, and is not suitable for miniaturization and cost reduction. Also, if the pitch of the bonding pads on the semiconductor chip becomes narrower, the pitch of the bonding pads on the wiring board also needs to be narrowed, but it is not possible to form fine pitch wiring on the wiring board compared to the semiconductor chip. It is difficult, and it is necessary to enlarge (pitch conversion) to the wiring pitch corresponding to the wiring board by some method.

It is an object of the present invention to solve the above-mentioned problems and to provide an inexpensive semiconductor device interposer which can be flip-chip connected without bumps and is suitable for miniaturization, and a semiconductor device using the same. It is in.

[0011]

Means for Solving the Problems In order to achieve the above object, the present invention is configured as follows.

(1) The interposer for a semiconductor device of the present invention has a wiring layer in which a pattern is formed on one surface of an insulating layer having adhesiveness, and is electrically connected to the wiring layer vertically. The metal pillars are aligned, and in the horizontal direction (plane direction), the metal pillars are insulated from each other by the adhesive green body, and the surface of the wiring layer that is not in contact with the metal pillar has a nickel plating base layer. The upper surface is plated with gold, and the end surface of the metal column other than the wiring layer side is plated with any one of gold, tin, silver, and solder.

In the present invention, the glass transition temperature of the above-mentioned adhesive insulating layer is in the range of 100 ° C. to 200 ° C. (claim 2), and the elasticity of the above-mentioned insulating layer having adhesiveness is 1000 MPa. It is preferable that the ratio be in the following range (Claim 3), and that the thermal expansion coefficient of the insulating layer having the adhesiveness be in the range of 20 ppm to 100 ppm (Claim 4).

(2) The semiconductor device according to the present invention is characterized in that
The metal pillar is connected to an electrode of a semiconductor chip by using plating of an end face of the metal pillar using the interposer for a semiconductor device according to any one of 2, 3, and 4, and the insulating layer having the adhesive property is formed. The semiconductor chip is bonded to the semiconductor device interposer by using adhesiveness, and solder balls are provided at predetermined positions of the wiring layer.

<The gist of the invention> In the present invention, a conductive layer is formed on one surface of the anisotropic conductive film embedded with metal pillars,
An anisotropic conductive film embedded with metal pillars having a structure in which one end of a metal pillar in the metal pillar embedded anisotropic conductive film is electrically connected to the conductor layer is used. Then, the conductor layer of the metal pillar buried anisotropic conductive film is formed in a predetermined wiring pattern,
It is possible to match the connection pitch with the mounting wiring board. The connection with the mounting wiring board is performed using a solder ball or the like. The other side is connected to the bonding pad of the semiconductor chip by using the plating at the tip of the metal pillar, and the film and the chip are connected by an adhesive.

Although the material of the metal layer is optimally Cu, when considering the coincidence of the thermal expansion coefficient with that of the semiconductor chip, Fe-
The use of a 42Ni alloy is also conceivable.

As the metal pillar, Cu is the most common, but other metals such as Au and Ag having a small electric resistance may be used.

An insulator having an adhesive property, that is, an adhesive, has an elastic modulus at room temperature of 1000 MPa or less at a normal temperature in order to exhibit a function of relieving a stress generated by a mismatch in thermal expansion between a semiconductor chip and a wiring board. is necessary. When the elastic modulus exceeds 1000 MPa, it cannot sufficiently serve as a stress buffer.

The adhesive has a coefficient of thermal expansion of from 20 ppm to 10 ppm.
It must be in the range of 0 ppm. If it is out of this range, the difference in thermal expansion from the chip becomes remarkable, and peeling or the like occurs in a temperature cycle test or the like.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the illustrated embodiment.

The interposer shown in FIG. 1 has a wiring pattern 5 on one surface of a layer of an adhesive 4 which is an insulator having adhesive properties.
1 are formed, metal columns 3 made of Cu electrically connected perpendicularly to the wiring layer 5 are aligned, and each metal column 3 is arranged in the horizontal direction (in the plane direction). There is an anisotropic conductive film 50 buried in a metal column having a structure in which the three are insulated by an adhesive 4 which is a chloroplast having adhesiveness. Then, the metal pillar 3 of the wiring layer 5 on which the wiring pattern 51 is formed
Gold plating (Ni, Au plating 7) is applied on the nickel plating base layer on the surface not in contact with the metal plating layer 3 and gold, tin, silver, solder It has a structure in which any one type of plating, here, gold plating (Au plating 6) is applied.

The above-mentioned adhesive 4 as an insulator having adhesive properties
The layer has a glass transition temperature in the range of 100 to 200 ° C.,
Those having an elastic modulus of 1000 MPa or less are suitable. Further, as the adhesive 4 as an insulator having the above adhesive property, an adhesive having a coefficient of thermal expansion in the range of 20 ppm to 100 ppm is suitable. Specifically, an epoxy-based, polyimide-based, polyamide-imide-based resin, or the like is used as the adhesive 4.

FIG. 1 also shows an example of a CSP semiconductor device using the interposer.

That is, Au plating 6 is applied to the surface of the metal pillar buried anisotropic conductive film 50 where the end faces of the metal pillars 3 made of Cu pillars are exposed, and the Au plating 6 is used to form the semiconductor chip 9. The bonding pad 10 and the metal pillar 3 are connected. The semiconductor chip 9 is adhered to the metal pillar buried anisotropic conductive film 50 using the adhesive property of the adhesive 4 which is an insulator having adhesive property. On the surface of the metal pillar 3 connected to the bonding pad 10 of the semiconductor chip 9 opposite to the semiconductor chip 9, the wiring layer 5 made of Cu is formed.
Are connected in advance. The wiring layer 5 is obtained by forming a wiring pattern 51 by etching a conductor layer made of Cu, and is subjected to Ni plating and Au plating (Ni and Au plating 7), and is used for connection with a mounting wiring board. The solder ball 11 is mounted.

As a method of forming the metal pillar 3 electrically connected to the wiring layer 5, the metal pillar is etched by etching a metal plate.
, A method of growing the metal column 3 by plating on a metal plate, a method of forming a groove by forming a groove by cutting the metal plate, and the like, and any method can be used.

Next, an embodiment of the semiconductor device interposer having the above structure and a method of manufacturing a semiconductor device using the same will be described with reference to FIG.

First, a photoresist 2 is applied to an electrolytic Cu foil 1 having a thickness of 18 μm, and has a diameter of 20 μm and a pitch of 50 μm.
The pattern was exposed and developed to form a mask (FIG. 2).
(A) (b)). A metal column 3 made of a Cu column having a height of 50 μm was formed on the Cu foil 1 by electroplating.
(C)). After plating, the photoresist 2 was removed (FIG. 2D), and the Cu foil 1 was 20 μm in diameter and 50 μm in height.
A metal column (Cu column) 3 of m and a pitch of 50 μm was obtained (FIG. 2D).

A varnish of an adhesive 4 is applied to the Cu foil 1 (FIG. 2E), and the varnish is dried under heating conditions of 90 ° C. for 4 hours (h) and 150 ° C. for 4 hours (h). ,
The thickness was the same as that of the metal pillar (Cu pillar) 3 (FIG. 2 (f): uniform surface). At this time, the end surface of the metal column (Cu column) 3 is flush with the adhesive 4. As the varnish of the adhesive 4, a varnish formed by dissolving a resin in which NBR rubber particles were dispersed in an epoxy-based adhesive in a solvent was used.

A predetermined wiring pattern 51 was formed on the Cu foil 1 of the metal pillar buried anisotropic conductive film 50 configured as described above by a normal etching method (FIG. 2 (g)). On the wiring pattern 51 side, a solder resist 8 was applied to other portions except for the solder ball mounting pads 52 (FIG. 2).
(H)).

An Au plating 6 was applied to the end face of the metal pillar (Cu pillar) 3 of the film at 3 μm (FIG. 2 (h)).

The wiring pattern 51 has a thickness of 2 μm.
m Ni plating, and a 1 μm thick Au plating (N
i, Au plating 7) was formed by electroplating (FIG. 2 (h)).

The metal pillar buried anisotropic conductive film 50 on which the wiring pattern 51 is formed is cut into a predetermined size.
It was attached to the semiconductor chip 9 by thermocompression. On this occasion,
Positioning is performed so that the bonding pads 10 of the semiconductor chip 9 and the solder ball mounting pads 52 of the wiring pattern 51 match. By heating and pressing, the bonding pad 1 of the Au plating 6 on the Cu column end face and the semiconductor chip 9 is formed.
Al of 0 is thermocompression-bonded, and at the same time, anisotropic conductive film 50 buried with metal pillars is bonded to semiconductor chip 9 via adhesive 4 (FIG. 2 (i)). Thereafter, 150 ° C. for 2 hours (h)
To cure the adhesive 4. The modulus at room temperature after curing is 400 MPa, the glass transition temperature is 110 ° C,
The coefficient of thermal expansion is 50 ppm.

Then, the metal column buried anisotropic conductive film 12
The solder ball 11 is mounted on the solder ball mounting pad 52 provided on the wiring pattern 51 side, thereby completing the CSP semiconductor device.

<Basis for Optimum Conditions> (1) An anisotropic conductive film 50 buried with metal pillars was manufactured in the same process as in the above embodiment. However, the elasticity of the adhesive 4 after curing is 400, 800, 1000, 1500, 200.
An adhesive changed to 0 MPa was used. Using the anisotropic conductive film 50 with the metal pillars embedded therein, a CSP semiconductor device was manufactured in the same manner as in the example. This CSP semiconductor device is mounted on a mounting wiring board and subjected to a temperature cycle test (−25 ° C.).
(−30 min, 125 ° C.−30 min, 500 cycles). The connection state between the semiconductor chip and the film after the temperature cycle test was observed. Table 1 shows the results of a temperature cycle test of a film using an adhesive having a changed elastic modulus.

[0035]

[Table 1]

As a result, as shown in Table 1, the elastic modulus was 1
Regarding the anisotropic conductive film 50 buried in metal pillars using an adhesive having a value exceeding 000 MPa, a connection failure (open) occurred at the connection portion by 500 cycles (Table 1).
This is presumably because the stress generated during the temperature cycle test could not be sufficiently absorbed due to the high elastic modulus, and peeling occurred between the semiconductor chip and the film or the wiring board and the film. Therefore, the adhesive 4 has an elastic modulus of 10
It turns out that the range below 00 MPa is appropriate.

(2) Next, the metal column buried anisotropic conductive film 50 was manufactured in the same process as in the above embodiment. However, the coefficient of thermal expansion of the adhesive 4 after curing is 10, 20, 50, 1
The adhesive used was changed to 00 and 200 MPa. Using the anisotropic conductive film 50 with the metal pillars embedded therein, a CSP semiconductor device was manufactured in the same manner as in the example. This CSP
The semiconductor device was mounted on a mounting wiring board and subjected to a temperature cycle test (−25 ° C. for 30 minutes, 125 ° C. for 30 minutes, 500 cycles). The connection state between the semiconductor chip and the film after the temperature cycle test was observed. Table 2 shows the results of a temperature cycle test of a film using an adhesive having a different coefficient of thermal expansion.

[0038]

[Table 2]

As a result, in the anisotropic conductive film 50 buried in a metal pillar using an adhesive having a coefficient of thermal expansion of less than 20 ppm or more than 100 ppm, a connection failure (open) occurred at the connection portion by 500 cycles. (Table 2). This is presumably because the difference in thermal expansion coefficient between the semiconductor chip and the wiring board was large, so that the stress generated during the temperature cycle test was large, and peeling occurred between the semiconductor chip and the film or the wiring board and the film. Therefore, the adhesive 4 has a thermal expansion coefficient of 20 ppm or more and 100 pp.
It turns out that the range below m is appropriate.

In the above embodiment, Cu is used as an example of the metal pillar 3. However, Au and Ag can be used instead of Cu.

[0041]

As described above, according to the present invention, a wiring layer having a pattern formed on one surface of an insulating layer having adhesiveness is provided, and is electrically connected to the wiring layer vertically. Metal pillars are aligned, and between the metal pillars are insulated in the lateral direction by the above-mentioned adhesive green body. On the surface of the wiring layer not in contact with the metal pillars, gold is placed on a nickel plating base layer. Since the metal pillar is plated with an end face other than the wiring layer side of the metal column, a gold or tin, silver or solder interposer is used. Flip-chip connection can be performed without using the same, and a flip-chip-connected CSP semiconductor device having excellent electric characteristics and suitable for miniaturization can be obtained at low cost.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device interposer of the present invention and a semiconductor device having a CSP structure using the same.

FIG. 2 is a view showing a manufacturing process of a semiconductor device interposer of the present invention and a semiconductor device having a CSP structure using the same.

FIG. 3 is a cross-sectional view showing a connection method using an anisotropic conductive film embedded in a metal column.

FIG. 4 shows a conventional typical CSP connection structure.

FIG. 5 is a diagram showing types of a conventional flip chip connection method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Cu foil 2 Photoresist 3 Metal pillar 4 Adhesive (insulator with adhesiveness) 5 Wiring layer 6 Au plating 7 Ni, Au plating 8 Solder resist 9 Semiconductor chip 10 Bonding pad 11 Solder ball 50 Metal pillar burying anisotropy Conductive film 51 Wiring pattern 52 Solder ball mounting pad

Claims (5)

[Claims] 1. A wiring layer having a pattern formed on one surface of an insulating layer having adhesiveness, and metal columns electrically connected to the wiring layer are aligned vertically and in a horizontal direction. The metal pillars are insulated from each other by the adhesive green body, and the surface of the wiring layer that is not in contact with the metal pillars is plated with gold on a nickel plating base layer, and the wiring of the metal pillars is An interposer for a semiconductor device, wherein an end face other than the layer side is plated with one of gold, tin, silver, and solder. 2. The interposer for a semiconductor device according to claim 1, wherein a glass transition temperature of said insulating layer having adhesiveness is in a range of 100 ° C. to 200 ° C. 3. An adhesive layer having an elastic modulus of 1
2. The pressure range of 000 MPa or less.
An interposer for a semiconductor device as described in the above. 4. The interposer for a semiconductor device according to claim 1, wherein the thermal expansion coefficient of the insulating layer having adhesiveness is in a range of 20 ppm to 100 ppm. 5. The method according to claim 1, wherein the metal pillar is connected to an electrode of a semiconductor chip by using plating of an end face of the metal pillar, using the interposer for a semiconductor device according to claim 1. A semiconductor device, wherein a semiconductor chip is bonded to a semiconductor device interposer using the adhesiveness of the insulating layer having adhesiveness, and a solder ball is provided at a predetermined position of the wiring layer.