JP2001007155A - Flip chip connection structure body - Google Patents
Flip chip connection structure bodyInfo
- Publication number
- JP2001007155A JP2001007155A JP11173847A JP17384799A JP2001007155A JP 2001007155 A JP2001007155 A JP 2001007155A JP 11173847 A JP11173847 A JP 11173847A JP 17384799 A JP17384799 A JP 17384799A JP 2001007155 A JP2001007155 A JP 2001007155A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- bump
- connection
- semiconductor chip
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、フリップチップ接
続構造体に関するものであり、特に、半導体チップを複
数のバンプ電極を介して回路基板上にフェースダウンボ
ンディングした接続構造体において、接続部の信頼性を
向上させるフリップチップ接続構造体に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip connection structure, and more particularly to a flip-chip connection structure in which a semiconductor chip is face-down bonded onto a circuit board via a plurality of bump electrodes. The present invention relates to a flip-chip connection structure for improving operability.
【０００２】[0002]
【従来の技術】昨今、電子機器は製品競争力強化のた
め、軽薄短小化、低価格化がますます熾烈をきわめてい
る。その中で、ＬＳＩデバイス等の半導体チップは、高
集積化、小型薄型化が進み、実装面でもより高機能化、
高密度化、高信頼化が強く求められている。そこで、こ
れらの要求に対応した実装方法として、回路基板面に対
し半導体チップをフェースダウンにて直接実装する、い
わゆるフリップチップ接続の実用化が進められている。2. Description of the Related Art In recent years, in order to enhance the competitiveness of electronic devices, the reduction in size, weight, and price has become increasingly intense. Among them, semiconductor chips such as LSI devices are becoming more highly integrated, smaller and thinner, and are more sophisticated in terms of mounting.
There is a strong demand for higher density and higher reliability. Therefore, as a mounting method corresponding to these demands, practical use of a so-called flip-chip connection in which a semiconductor chip is directly mounted face-down on a circuit board surface is being promoted.
【０００３】フリップチップ接続は、半導体チップと回
路基板の電極との電気的接続を、はんだ、Ａｕ等の材料
から構成される金属バンプを介して一括接続で行なうこ
とができる。そのため、ワイヤボンディング法に比べ、
作業性の点で優れている。また、電極配置が半導体チッ
プの周辺に限定されないため、大幅に接続端子数を増大
することができる。さらに、半導体チップの内部の配線
長を短くすることができるため、高速化を促進すること
ができるという特徴も有している。[0003] In flip-chip connection, electrical connection between a semiconductor chip and electrodes of a circuit board can be made in a lump through metal bumps made of a material such as solder or Au. Therefore, compared to the wire bonding method,
Excellent workability. Further, since the electrode arrangement is not limited to the periphery of the semiconductor chip, the number of connection terminals can be greatly increased. Furthermore, since the length of wiring inside the semiconductor chip can be shortened, there is also a feature that high speed operation can be promoted.
【０００４】以下、代表的なフリップチップ接続方式に
ついて簡潔に説明する。図４は、従来のフリップチップ
接続構造体の一例を模式的に示す断面図である。Hereinafter, a typical flip-chip connection method will be briefly described. FIG. 4 is a cross-sectional view schematically showing one example of a conventional flip-chip connection structure.
【０００５】図４を参照して、この接続方式によれば、
半導体チップ１１上の電極１２に形成された金属バンプ
１３を、回路基板２１の表層配線２２上に当接させ、樹
脂３１の硬化時の収縮力によりこれらに圧力が加わり、
金属バンプ１３と回路基板２１とが表層配線２２を介し
て機械的に接触し、電気的接続が得られる構造である。Referring to FIG. 4, according to this connection method,
The metal bumps 13 formed on the electrodes 12 on the semiconductor chip 11 are brought into contact with the surface wirings 22 of the circuit board 21, and a pressure is applied to them by the contraction force of the resin 31 during curing.
The structure is such that the metal bumps 13 and the circuit board 21 are in mechanical contact with each other via the surface wirings 22 and electrical connection is obtained.
【０００６】金属バンプ１３が一定の高さを有してお
り、半導体チップ１１の回路基板２１への接続時におけ
る荷重として、各金属バンプ１３に対して一様な圧力が
加われば、理論的には、各金属バンプ１３が一定量変形
して、半導体チップ１１と回路基板２１との確実な接続
を得ることが可能である。If the metal bumps 13 have a fixed height and a uniform pressure is applied to each metal bump 13 as a load when the semiconductor chip 11 is connected to the circuit board 21, theoretically The metal bumps 13 can be deformed by a certain amount, and a reliable connection between the semiconductor chip 11 and the circuit board 21 can be obtained.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、従来の
フリップチップ接続構造体は、次のような欠点を有して
いる。However, the conventional flip chip connection structure has the following disadvantages.
【０００８】すなわち、樹脂３１の熱膨張係数は金属バ
ンプ１３の熱膨張係数に比べて大きいため、温度変化が
生じると、樹脂３１の膨張により金属バンプ１３と回路
基板２１との接触圧力が弱まる。その結果、金属バンプ
１３と回路基板２１との接触が不安定になり、接続信頼
性に欠けるおそれがある。また、実際の生産工程におい
ては、一定の高さを得るために設けられた各金属バンプ
１３の高さにばらつきが存在してしまうおそれがある。
さらに、半導体チップ１１に対して荷重を印加する加圧
治具においても、加圧面に対して完全な平衡度を確保す
ることは困難である。その結果、金属バンプ１３と回路
基板２１上の電極２２との接続に関し、均一かつ確実な
接続を確保することが困難であるという問題点があっ
た。That is, since the coefficient of thermal expansion of the resin 31 is larger than the coefficient of thermal expansion of the metal bumps 13, when a temperature change occurs, the contact pressure between the metal bumps 13 and the circuit board 21 weakens due to expansion of the resin 31. As a result, contact between the metal bumps 13 and the circuit board 21 becomes unstable, and connection reliability may be lacking. In the actual production process, there is a possibility that the height of each metal bump 13 provided to obtain a certain height may vary.
Furthermore, even with a pressing jig for applying a load to the semiconductor chip 11, it is difficult to ensure a perfect balance with the pressing surface. As a result, there is a problem that it is difficult to ensure uniform and reliable connection between the metal bump 13 and the electrode 22 on the circuit board 21.
【０００９】特に、半導体チップを搭載する回路基板と
してセラミック厚膜基板を使用する場合には、セラミッ
ク厚膜基板は、半導体チップと比べて、反り、うねりが
大きく、回路基板の高さ方向の膜厚ばらつきも大きいた
め、金属バンプと回路基板上の電極とをフリップチップ
接続する際に、接続のばらつきが大きくなるといった問
題を有していた。このように接続のばらつきが大きいと
いうことは、接続後の歩留まりの低下を招く原因の１つ
であり、また、回路動作上からも好ましいものではな
い。In particular, when a ceramic thick film substrate is used as a circuit board on which a semiconductor chip is mounted, the ceramic thick film substrate has a larger warp and undulation than a semiconductor chip, and a film in the height direction of the circuit board. Since the thickness variation is large, the flip-chip connection between the metal bump and the electrode on the circuit board has a problem that the connection variation becomes large. Such a large variation in connection is one of the causes of a decrease in the yield after connection, and is not preferable in terms of circuit operation.
【００１０】本発明の目的は、これらの欠点を除くため
になされたものであり、反り、うねりの大きい回路基板
上に半導体チップをフェースダウンボンディングする場
合にも、電気的接続および機械的接続の信頼性をさらに
向上させることができる、フリップチップ接続構造体を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate these drawbacks. Even when a semiconductor chip is face-down bonded on a circuit board having a large warp or undulation, electrical and mechanical connections can be made. An object of the present invention is to provide a flip chip connection structure that can further improve reliability.
【００１１】[0011]
【課題を解決するための手段】この発明によるフリップ
チップ接続構造体は、複数のバンプ電極を介して、半導
体チップを回路基板上の電極にフェースダウンボンディ
ングする接続構造体であって、複数のバンプ電極は、相
互間の距離が等間隔で形成され、バンプ電極と回路基板
上の電極との接続により生じる接続面積の異なる部分
が、回路基板上で存在することを特徴としている。A flip-chip connection structure according to the present invention is a connection structure for face-down bonding a semiconductor chip to an electrode on a circuit board via a plurality of bump electrodes. The electrodes are formed so that the distance between the electrodes is equal, and portions having different connection areas caused by the connection between the bump electrodes and the electrodes on the circuit board are present on the circuit board.
【００１２】具体的には、たとえば、回路基板の反り、
うねりの傾向が大きい場所に対接する部分の半導体チッ
プの電極上、もしくは回路基板の表層配線上に、接続面
積が大きいバンプ電極を形成するとよい。More specifically, for example, warping of a circuit board,
It is preferable to form a bump electrode having a large connection area on the electrode of the semiconductor chip in a portion in contact with a place where the tendency of undulation is large, or on the surface wiring of the circuit board.
【００１３】回路基板の反り、うねりの影響が大きい傾
向がある部分では、接続部が未接着、傾き等のために不
安定となる。そのため、本願発明によれば、該部分に接
続面積が大きいバンプ電極を設けることにより、回路基
板の反り等が大きい端子部でも回路基板と半導体チップ
との接続部は十分な接続面積が確保される。その結果、
機械的強度が増し、良好な接続性が期待でき、導通不良
が生じることがない。In a portion where the influence of the warpage and undulation of the circuit board tends to be large, the connection portion becomes unstable due to non-adhesion, inclination and the like. Therefore, according to the present invention, by providing a bump electrode having a large connection area in this portion, a sufficient connection area is secured in the connection portion between the circuit board and the semiconductor chip even in a terminal portion where the warpage of the circuit board is large. . as a result,
The mechanical strength is increased, good connectivity can be expected, and poor conduction does not occur.
【００１４】好ましくは、回路基板上の同一信号線路上
に、寸法の異なる２種類以上のバンプ電極が接続されて
いるとよい。[0014] Preferably, two or more types of bump electrodes having different dimensions are connected to the same signal line on the circuit board.
【００１５】具体的には、たとえば、回路基板の反り、
うねりの傾向が大きい場所に対接する部分の半導体チッ
プの電極上、もしくは回路基板の表層配線上に、寸法の
異なる２種類以上のバンプ電極を形成するとよい。More specifically, for example, warpage of a circuit board,
It is preferable to form two or more types of bump electrodes having different dimensions on the electrode of the semiconductor chip in contact with the place where the tendency of undulation is large, or on the surface wiring of the circuit board.
【００１６】回路基板の反り、うねりの影響が大きい傾
向がある部分では、接続部が未接着、傾き等のために不
安定となる。そのため、本願発明によれば、該部分に寸
法が大きいバンプ電極を設けることにより、回路基板の
反り等が大きい端子部でも、回路基板と半導体チップと
の接続部は寸法が大きいバンプ電極により接続されるた
め、十分な接続面積が確保される。その結果、機械的強
度が増し、良好な接続性が可能になる。In a portion where the influence of the warpage and undulation of the circuit board tends to be large, the connection portion becomes unstable due to non-adhesion, inclination and the like. Therefore, according to the invention of the present application, by providing a bump electrode having a large dimension in this portion, even in a terminal portion having a large warp or the like of the circuit board, a connection portion between the circuit board and the semiconductor chip is connected by the bump electrode having a large dimension. Therefore, a sufficient connection area is secured. As a result, the mechanical strength increases, and good connectivity is made possible.
【００１７】また、バンプ電極を、寸法の異なる２種類
以上のバンプ電極により構成する例として、たとえば、
他端子部分のバンプと同じ寸法のバンプ電極を配置し、
さらに寸法が大きいバンプ電極を設けることができる。
このような構成により、寸法が大きいバンプ電極の接続
強度分を増すことができ、安定した接続が可能になる。Further, as an example in which the bump electrode is composed of two or more types of bump electrodes having different dimensions, for example,
Place a bump electrode of the same size as the bump of the other terminal part,
Further, a bump electrode having a larger size can be provided.
With such a configuration, the connection strength of the bump electrode having a large dimension can be increased, and stable connection can be achieved.
【００１８】また、この発明によれば、同じ寸法のバン
プ電極を設ける場合と比較して、寸法が異なるバンプ電
極を同一端子上に設けることにより、バンプ電極を設け
る半導体チップや回路基板のパターンの自由度が阻害さ
れることがない。Further, according to the present invention, by providing bump electrodes having different dimensions on the same terminal as compared with the case where bump electrodes having the same dimensions are provided, the pattern of the semiconductor chip or circuit board provided with the bump electrodes can be formed. The degree of freedom is not hindered.
【００１９】このように、本願発明によれば、回路基板
の反り、うねりが大きい部分、すなわち機械的応力が集
中する回路基板の表層配線上の接続面積を、大きくする
ことが可能になる。そのため、接続部の機械的強度が増
大し、高い接続信頼性を確保することができる。As described above, according to the present invention, it is possible to increase the area of the circuit board where warpage and undulation is large, that is, the connection area on the surface wiring of the circuit board where mechanical stress is concentrated. Therefore, the mechanical strength of the connection portion increases, and high connection reliability can be secured.
【００２０】好ましくは、バンプ電極は、Ａｕを主成分
とする材質から構成されているとよい。Preferably, the bump electrode is made of a material containing Au as a main component.
【００２１】[0021]
【発明の実施の形態】以下、本発明の実施の形態を、図
１〜図３に基づいて詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to FIGS.
【００２２】なお、図１〜図３において、同一の機能を
有するものは同一の符号をつけ、その繰返しの説明を省
略する。In FIGS. 1 to 3, components having the same functions are denoted by the same reference numerals, and the description thereof will not be repeated.
【００２３】（実施の形態１）図１は、本発明の実施の
形態１に係るフリップチップ接続構造体を示す断面図で
ある。この図１は、本発明の実施の形態１における半導
体チップ電極上に形成したＡｕバンプを介して、回路基
板上に接続した接続構造体の断面図であり、後述する図
２のＩ−Ｉ線で示す断面図である。(Embodiment 1) FIG. 1 is a sectional view showing a flip chip connection structure according to Embodiment 1 of the present invention. FIG. 1 is a cross-sectional view of a connection structure connected to a circuit board via an Au bump formed on a semiconductor chip electrode according to the first embodiment of the present invention. FIG.
【００２４】また、図２は、図１に示すフリップチップ
接続構造体を得るために、Ａｕバンプを半導体チップ上
に形成した半導体チップを示す斜視図である。FIG. 2 is a perspective view showing a semiconductor chip in which Au bumps are formed on the semiconductor chip in order to obtain the flip chip connection structure shown in FIG.
【００２５】図１および図２を参照して、このフリップ
チップ接続構造体は、複数のＡｕバンプ１４、１５を介
して半導体チップ１１が回路基板２１上の表層配線２２
にフェースダウンボンディングされている。複数のＡｕ
バンプ１４、１５は、相互間の距離が等間隔で形成され
ている。また、Ａｕバンプは、通常のＡｕバンプ１４
と、半導体チップ１１と回路基板２１との接続面積を大
きくするＡｕバンプ１５とのように、寸法の異なる２種
類のものが用いられている。Referring to FIG. 1 and FIG. 2, this flip-chip connection structure has a structure in which semiconductor chip 11 is connected to surface wiring 22 on circuit board 21 via a plurality of Au bumps 14 and 15.
Face down bonding. Multiple Au
The bumps 14 and 15 are formed at equal intervals. The Au bump is a normal Au bump 14.
Two types having different dimensions are used, such as an Au bump 15 for increasing the connection area between the semiconductor chip 11 and the circuit board 21.
【００２６】半導体チップ１１は、たとえばＧａＡｓ等
の化合物半導体であり、半導体チップ１１上の電極であ
るＡｕ配線（図示せず）上にＡｕバンプ１４が形成され
ている。回路基板２１は、たとえば窒化アルミニウム、
アルミナ、ガラスセラミック等のセラミック基板からな
り、その表面には表層配線２２が形成されている。The semiconductor chip 11 is a compound semiconductor such as GaAs, for example, and Au bumps 14 are formed on Au wires (not shown) which are electrodes on the semiconductor chip 11. The circuit board 21 is made of, for example, aluminum nitride,
It is made of a ceramic substrate such as alumina or glass ceramic, and a surface wiring 22 is formed on the surface thereof.
【００２７】表層配線２２は、Ｗ（タングステン）等の
高融点厚膜ペースト上に、Ｎｉ、Ａｕのめっきが順に施
されている。The surface wiring 22 is formed by plating Ni and Au on a high melting point thick film paste such as W (tungsten) in that order.
【００２８】本発明によるフリップチップ接続構造体を
得るため、寸法が異なるＡｕバンプを形成するために
は、通常用いられているめっき法やボールボンド法を使
用することができる。In order to obtain the flip chip connection structure according to the present invention, and to form Au bumps having different dimensions, a commonly used plating method or ball bonding method can be used.
【００２９】たとえば、寸法が異なるＡｕバンプを電解
めっき法により形成する場合は、半導体チップ上に形成
しためっき用レジストの開口部の寸法を、半導体チップ
内で所望の異なる開口径とし、通常の電解めっきプロセ
スにより、２０μｍ高さのＡｕバンプを形成することが
できる。For example, when Au bumps having different dimensions are formed by electrolytic plating, the dimensions of the openings of the plating resist formed on the semiconductor chip are set to different desired aperture diameters within the semiconductor chip, and the normal electrolytic plating is performed. Au bumps having a height of 20 μm can be formed by the plating process.
【００３０】また、ボールボンド法により寸法が異なる
Ａｕバンプを形成する場合は、用いるＡｕ線の径、ボー
ル形成条件、ボールボンド条件等を変更することによ
り、容易に形成することができる。When Au bumps having different dimensions are formed by the ball bonding method, the bumps can be easily formed by changing the diameter of the used Au wire, ball forming conditions, ball bonding conditions, and the like.
【００３１】回路基板の反り、うねりは、表層配線パタ
ーン（図示せず）や裏面配線パターンの有無（図示せ
ず）により反り方向や形状が変わるが、一般的に基板に
裏面配線パターンがある場合であって、チップ搭載部を
上にした場合、凹状の反りを有することが多い。また、
表層配線パターンが密であったり、グラウンド面積が広
い場所ほど、チップ搭載部を上にした場合、凹状部の反
りを有しやすい傾向がある。The warpage and undulation of a circuit board vary depending on the presence or absence of a surface wiring pattern (not shown) or a back wiring pattern (not shown). However, when the chip mounting portion is set upward, the chip mounting portion often has a concave warpage. Also,
In a place where the surface wiring pattern is denser or the ground area is larger, when the chip mounting portion is placed above, the concave portion tends to have a warp.
【００３２】たとえば、図１に示すように、回路基板２
１上の半導体チップ搭載部２３が凹状の反りを有してい
る場合、上記のバンプ形成法により、回路基板２１の凹
部に位置する電極２２と接続すべき半導体チップ１１の
電極（図示せず）上に、後述する他端子より接続面積が
大きいＡｕバンプ１５を形成し、他の電極上には標準の
寸法のＡｕバンプ１４を形成する。For example, as shown in FIG.
In the case where the semiconductor chip mounting portion 23 on 1 has a concave warp, an electrode (not shown) of the semiconductor chip 11 to be connected to the electrode 22 located in the concave portion of the circuit board 21 by the above-described bump forming method. An Au bump 15 having a larger connection area than other terminals to be described later is formed thereon, and an Au bump 14 having a standard size is formed on other electrodes.
【００３３】なお、半導体チップ搭載部２３の反りが上
述した場合と逆の場合は、半導体チップ１１端部に接続
面積が大きいＡｕバンプ１５を形成すればよい。In the case where the warpage of the semiconductor chip mounting portion 23 is opposite to the case described above, the Au bump 15 having a large connection area may be formed at the end of the semiconductor chip 11.
【００３４】（実施の形態２）図３は、本発明の実施の
形態２に係るフリップチップ接続構造体を示す断面図で
ある。半導体チップ電極上に形成したＡｕバンプを介し
て、回路基板上に接続した接続構造体の断面図である。(Embodiment 2) FIG. 3 is a sectional view showing a flip-chip connection structure according to Embodiment 2 of the present invention. It is sectional drawing of the connection structure connected on the circuit board via the Au bump formed on the semiconductor chip electrode.
【００３５】この実施の形態におけるフリップチップ接
続構造体を得るためのＡｕバンプの形成方法は、実施の
形態１と同様であるため、その説明は省略する。The method for forming the Au bumps for obtaining the flip-chip connection structure in this embodiment is the same as that in the first embodiment, and a description thereof will be omitted.
【００３６】回路基板の反り、うねりは、表層配線パタ
ーン（図示せず）や裏面配線パターン（図示せず）の有
無により、反り方向や形状や変わるが、一般的に基板裏
面パターンがない場合は、回路基板焼成時や表層配線形
成時の応力により、チップ搭載部を上にした場合、凸状
の反りを有する傾向がある。The warpage and undulation of a circuit board vary depending on the presence or absence of a surface wiring pattern (not shown) or a back wiring pattern (not shown). In addition, when the chip mounting portion is turned upward due to the stress during the firing of the circuit board or the formation of the surface wiring, the chip mounting portion tends to have a convex warpage.
【００３７】たとえば、図３に示すように、回路基板２
１上の半導体チップ搭載部２３が凹状の反りを有してい
る場合、上記のバンプ形成法により、前記回路基板２１
の凹部に位置する電極２２と接続すべき半導体チップ１
１の電極上に、標準寸法のＡｕバンプ１４と、寸法の異
なるＡｕバンプ１６とを形成し、他の電極上には標準の
寸法のＡｕバンプ１４のみを形成する。For example, as shown in FIG.
1 has a concave warp, the circuit board 21 is formed by the bump forming method described above.
Semiconductor chip 1 to be connected to electrode 22 located in the concave portion
A standard size Au bump 14 and a standard size Au bump 16 are formed on one electrode, and only the standard size Au bump 14 is formed on the other electrode.
【００３８】なお、図３では、標準寸法のＡｕバンプ１
４を回路基板２１の反りが大きい部分に形成した状態を
図示しているが、寸法の大きいＡｕバンプ１６のみで
も、安定した接続が確保されることは言うまでもない。In FIG. 3, the Au bump 1 having the standard size is used.
Although FIG. 4 illustrates a state in which the circuit board 21 is formed on a portion of the circuit board 21 where the warpage is large, it is needless to say that a stable connection is ensured only with the large Au bump 16.
【００３９】また、上述の実施の形態１および２におい
て、Ａｕバンプ形成法は、めっき法によるバンプ形成の
場合について主に説明したが、めっき法、ボールボンド
法等に限らず、他の手法で形成したり、さらに各々のバ
ンプ電極形成を自由に組合わせても同様の接続構造体が
得られる。In the first and second embodiments, the Au bump formation method has been mainly described for the case of bump formation by plating. However, the method is not limited to plating, ball bonding, and the like, and other methods may be used. The same connection structure can be obtained by forming the bump electrodes or by freely combining the formation of the bump electrodes.
【００４０】また、上述の実施の形態１および２におい
ては、バンプ電極の接続断面形状は、円形の場合に関し
説明したが、断面形状は円形に限らず、たとえばＬ字状
のバンプ電極接続断面形状であっても差しつかえない。In the first and second embodiments, the connection cross-sectional shape of the bump electrode has been described as being circular. However, the cross-sectional shape is not limited to a circle, and may be, for example, an L-shaped bump electrode connection cross-sectional shape. Even if it does not matter.
【００４１】さらに、上述の実施の形態１および２にお
いては、半導体チップの電極上にＡｕバンプを設けた例
を採り上げて説明したが、回路基板側にＡｕバンプを設
けた場合にも、同様な構造体が得られ、同様の効果が得
られることは言うまでもない。Further, in the first and second embodiments, an example in which an Au bump is provided on an electrode of a semiconductor chip has been described. However, the same applies to a case where an Au bump is provided on a circuit board side. Needless to say, a structure can be obtained and the same effect can be obtained.
【００４２】[0042]
【実施例】（実施例１）以下のように、図１に示す実施
の形態１に係るフリップチップ接続構造体を実際に作製
した。EXAMPLES (Example 1) A flip-chip connection structure according to Embodiment 1 shown in FIG. 1 was actually manufactured as follows.
【００４３】まず、半導体チップ１１上に、接続部の面
積が３．１４×１０-4ｍｍ2 と７．０６５×１０-4ｍｍ
2 の２種類の接続面積を有するＡｕバンプ１４、１５を
形成した。次に、このＡｕバンプ１４、１５が形成され
た半導体チップ１１を、回路基板２１上の表層配線２２
に位置合わせをし、回路基板２１の表層配線２２と半導
体チップ１１の電極パッド（図示せず）とをＡｕバンプ
１４、１５を介して熱圧着することにより、半導体チッ
プ１１と回路基板２１とを電気的に接続した。なお、熱
圧着の条件は、接続温度が約３５０℃、接続荷重が１３
ｋｇｆ／ｍｍ2、接続時間が５秒であった。First, on the semiconductor chip 11, the area of the connection portion is 3.14 × 10 −4 mm 2 and 7.065 × 10 −4 mm.
To form the Au bump 14 and 15 having two connection area 2. Next, the semiconductor chip 11 on which the Au bumps 14 and 15 are formed is connected to the surface wiring 22 on the circuit board 21.
The semiconductor chip 11 and the circuit board 21 are bonded by thermocompression bonding between the surface wirings 22 of the circuit board 21 and the electrode pads (not shown) of the semiconductor chip 11 via the Au bumps 14 and 15. Connected electrically. The conditions of the thermocompression bonding are that the connection temperature is about 350 ° C. and the connection load is
kgf / mm 2 and connection time was 5 seconds.
【００４４】このようにして得られたフリップチップ接
続構造体においては、回路基板２１の反り、うねり、表
層配線２２の膜厚のばらつき等に起因する接続不良を、
事前に回避することができた。In the flip-chip connection structure obtained in this manner, the connection failure due to the warpage and undulation of the circuit board 21 and the variation in the film thickness of the surface wiring 22 is reduced.
Could be avoided in advance.
【００４５】Ａｕバンプ接続面積の違いによる接続信頼
性を比較するため、回路基板２１の反り、すなわち半導
体チップ搭載部２３の反りとして、１０μｍの反りを有
する回路基板２１に半導体チップ１１をフェースダウン
ボンディングした比較例１のテストサンプルを作製し、
−４０℃〜１２５℃の１サイクル３０分の熱衝撃試験を
行なった。その結果を表１に示す。In order to compare the connection reliability due to the difference in the Au bump connection area, the semiconductor chip 11 is face-down bonded to the circuit board 21 having a warpage of 10 μm as the warpage of the circuit board 21, that is, the warpage of the semiconductor chip mounting portion 23. A test sample of Comparative Example 1 was prepared.
A thermal shock test was performed at -40 ° C to 125 ° C for 30 minutes per cycle. Table 1 shows the results.
【００４６】[0046]
【表１】 [Table 1]
【００４７】表１より明らかなように、基板の反りの大
きい部分にバンプの接続面積が大きいＡｕバンプを接続
することにより、安定した接続を確保することができる
ことが確認できた。As is clear from Table 1, it was confirmed that a stable connection can be secured by connecting an Au bump having a large connection area to a large warp portion of the substrate.
【００４８】（実施例２）以下のように、図３に示す実
施の形態２に係るフリップチップ接続構造体を実際に作
製した。Example 2 A flip-chip connection structure according to the second embodiment shown in FIG. 3 was actually manufactured as follows.
【００４９】まず、半導体チップ電極１１上に、直径３
０μｍ、高さ２０μｍの円柱形のＡｕバンプ１６と、直
径２０μｍ、高さ２０μｍの円柱形のＡｕバンプ１４と
を、周知の技術であるめっき法にて形成した。First, the semiconductor chip electrode 11 has a diameter of 3 mm.
A cylindrical Au bump 16 having a thickness of 0 μm and a height of 20 μm and a cylindrical Au bump 14 having a diameter of 20 μm and a height of 20 μm were formed by a plating method which is a known technique.
【００５０】次に、この寸法の大きなＡｕバンプ１６と
標準の寸法のＡｕバンプ１４が形成された半導体チップ
１１を、回路基板２１の表層配線２２に位置合わせを
し、熱圧着することにより、半導体チップ１１と回路基
板２１とを電気的に接続した。なお、熱圧着の条件は、
接続温度が約３５０℃、接続荷重が１３ｋｇｆ／ｍ
ｍ2、接続時間が５秒であった。Next, the semiconductor chip 11 on which the large-sized Au bumps 16 and the standard-sized Au bumps 14 are formed is aligned with the surface wiring 22 of the circuit board 21 and is thermocompression-bonded. The chip 11 and the circuit board 21 were electrically connected. The conditions for thermocompression bonding are as follows:
Connection temperature is about 350 ° C, connection load is 13kgf / m
m 2 and connection time was 5 seconds.
【００５１】このようにして得られたフリップチップ接
続構造体においては、回路基板２１の反り、うねり、表
層配線２２の膜厚のばらつき等に起因する接続不良を、
事前に回避することができた。In the flip-chip connection structure obtained in this manner, the connection failure due to the warpage and undulation of the circuit board 21 and the variation in the film thickness of the surface wiring 22 is reduced.
Could be avoided in advance.
【００５２】寸法の異なるＡｕバンプによる接続信頼性
を比較するため、回路基板２１の反り、すなわち半導体
チップ搭載部２３の反りとして、１０μｍの反りを有す
る回路基板２１に半導体チップ１１をフェースダウンボ
ンディングした比較例２のテストサンプルを作製し、−
４０℃〜１２５℃の１サイクル３０分の熱衝撃試験を行
なった。その結果を表２に示す。In order to compare the connection reliability of Au bumps having different dimensions, the semiconductor chip 11 was face-down bonded to the circuit board 21 having a warpage of 10 μm as the warpage of the circuit board 21, that is, the warpage of the semiconductor chip mounting portion 23. A test sample of Comparative Example 2 was prepared,
A thermal shock test was performed at 40 ° C. to 125 ° C. for 30 minutes per cycle. Table 2 shows the results.
【００５３】[0053]
【表２】 [Table 2]
【００５４】表２より明らかなように、基板の反りの大
きい部分に寸法の大きなＡｕバンプ１６を形成し、接続
することにより、安定した接続が確保できることが確認
できた。As is evident from Table 2, it was confirmed that stable connection can be ensured by forming the Au bump 16 having a large size on the portion of the substrate where the warpage is large, and connecting it.
【００５５】[0055]
【発明の効果】以上説明したように、本発明によれば、
回路基板と半導体チップとの接続において、回路基板の
反り、うねり等に対応する位置に接続面積が大きいバン
プ電極を接続することにより、接続部の接続面積が増大
し、良好な信頼性を確保することができた。As described above, according to the present invention,
In the connection between the circuit board and the semiconductor chip, a bump electrode having a large connection area is connected to a position corresponding to the warpage, undulation, etc. of the circuit board, so that the connection area of the connection portion is increased and good reliability is secured. I was able to.
【００５６】また、本発明によれば、回路基板と半導体
チップとの接続において、回路基板の反り、うねり等に
対応する位置に複数のバンプ電極、寸法の大きいバンプ
電極を接続することにより、さらに接続部の強度を増大
することができる。Further, according to the present invention, in connecting a circuit board and a semiconductor chip, a plurality of bump electrodes and large-sized bump electrodes are connected to positions corresponding to warpage, undulation, and the like of the circuit board. The strength of the connecting portion can be increased.
【図１】本発明の実施の形態１に係るフリップチップ接
続構造体を示す断面図である。FIG. 1 is a cross-sectional view showing a flip-chip connection structure according to a first embodiment of the present invention.
【図２】図１に示すフリップチップ接続構造体を得るた
めにＡｕバンプを半導体チップ上に形成した半導体チッ
プを示す斜視図である。FIG. 2 is a perspective view showing a semiconductor chip in which Au bumps are formed on the semiconductor chip in order to obtain the flip chip connection structure shown in FIG.
【図３】本発明の実施の形態２に係るフリップチップ接
続構造体を示す断面図である。FIG. 3 is a cross-sectional view showing a flip-chip connection structure according to a second embodiment of the present invention.
【図４】従来のフリップチップ接続構造体の一例を模式
的に示す断面図である。FIG. 4 is a cross-sectional view schematically showing one example of a conventional flip chip connection structure.
１１ 半導体チップ １２ 電極 １３ 金属バンプ １４ Ａｕバンプ １５ 接続面積が通常のＡｕバンプより大きいＡｕバン
プ １６ 寸法が通常のＡｕバンプより大きいＡｕバンプ ２１ 回路基板 ２２ 表層配線 ２３ 半導体チップ搭載部 ３１ 樹脂DESCRIPTION OF SYMBOLS 11 Semiconductor chip 12 Electrode 13 Metal bump 14 Au bump 15 Au bump whose connection area is larger than normal Au bump 16 Au bump whose size is larger than normal Au bump 21 Circuit board 22 Surface wiring 23 Semiconductor chip mounting part 31 Resin
Claims (3)
プを回路基板上の電極にフェースダウンボンディングす
る接続構造体であって、 前記複数のバンプ電極は、相互間の距離が等間隔で形成
され、 前記バンプ電極と前記回路基板上の前記電極との接続に
より生じる接続面積の異なる部分が、前記回路基板上で
存在することを特徴とする、フリップチップ接続構造
体。1. A connection structure for face-down bonding a semiconductor chip to an electrode on a circuit board via a plurality of bump electrodes, wherein the plurality of bump electrodes are formed at equal intervals. A flip-chip connection structure, wherein a portion having a different connection area caused by connection between the bump electrode and the electrode on the circuit board exists on the circuit board.
法の異なる２種類以上の前記バンプ電極が接続されてい
ることを特徴とする、請求項１記載のフリップチップ接
続構造体。2. The flip-chip connection structure according to claim 1, wherein two or more types of the bump electrodes having different dimensions are connected on the same signal line on the circuit board.
材質から構成されていることを特徴とする、請求項１ま
たは請求項２に記載のフリップチップ接続構造体。3. The flip-chip connection structure according to claim 1, wherein the bump electrode is made of a material containing Au as a main component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11173847A JP2001007155A (en) | 1999-06-21 | 1999-06-21 | Flip chip connection structure body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11173847A JP2001007155A (en) | 1999-06-21 | 1999-06-21 | Flip chip connection structure body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001007155A true JP2001007155A (en) | 2001-01-12 |
Family
ID=15968271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11173847A Pending JP2001007155A (en) | 1999-06-21 | 1999-06-21 | Flip chip connection structure body |
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| Country | Link |
|---|---|
| JP (1) | JP2001007155A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006173345A (en) * | 2004-12-15 | 2006-06-29 | Fujikura Ltd | Semiconductor component |
| US8703600B2 (en) | 2009-06-02 | 2014-04-22 | Kabushiki Kaisha Toshiba | Electronic component and method of connecting with multi-profile bumps |
| JP2014168005A (en) * | 2013-02-28 | 2014-09-11 | Kyocer Slc Technologies Corp | Wiring board |
| US9277657B2 (en) | 2013-03-28 | 2016-03-01 | Kyocera Slc Technologies Corporation | Wiring board |
| JP2018107371A (en) * | 2016-12-28 | 2018-07-05 | 日亜化学工業株式会社 | Light-emitting device and manufacturing method thereof |
| CN110007117A (en) * | 2018-01-05 | 2019-07-12 | 旺矽科技股份有限公司 | Probe card |
-
1999
- 1999-06-21 JP JP11173847A patent/JP2001007155A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006173345A (en) * | 2004-12-15 | 2006-06-29 | Fujikura Ltd | Semiconductor component |
| US8703600B2 (en) | 2009-06-02 | 2014-04-22 | Kabushiki Kaisha Toshiba | Electronic component and method of connecting with multi-profile bumps |
| JP2014168005A (en) * | 2013-02-28 | 2014-09-11 | Kyocer Slc Technologies Corp | Wiring board |
| US9277657B2 (en) | 2013-03-28 | 2016-03-01 | Kyocera Slc Technologies Corporation | Wiring board |
| JP2018107371A (en) * | 2016-12-28 | 2018-07-05 | 日亜化学工業株式会社 | Light-emitting device and manufacturing method thereof |
| CN110007117A (en) * | 2018-01-05 | 2019-07-12 | 旺矽科技股份有限公司 | Probe card |
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