JPH09162230A - Electronic circuit device and its manufacturing method - Google Patents

Electronic circuit device and its manufacturing method

Info

Publication number
JPH09162230A
JPH09162230A JP7345137A JP34513795A JPH09162230A JP H09162230 A JPH09162230 A JP H09162230A JP 7345137 A JP7345137 A JP 7345137A JP 34513795 A JP34513795 A JP 34513795A JP H09162230 A JPH09162230 A JP H09162230A
Authority
JP
Japan
Prior art keywords
conductor layer
bump electrode
anisotropic conductive
electrode
flip chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7345137A
Other languages
Japanese (ja)
Inventor
Takashi Kimura
崇 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP7345137A priority Critical patent/JPH09162230A/en
Publication of JPH09162230A publication Critical patent/JPH09162230A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114Guiding structures outside the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134Bonding interfaces of the bump connector
    • H01L2224/81345Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

Abstract

PROBLEM TO BE SOLVED: To lower the resistance value of electronic connection using an anisotropic conductive film. SOLUTION: Recessions 10 are provided in the connecting conductor layers 6 on a circuit substrate 5 for fitting a flip chip 4. At this time, these recessions 10 are similarly formed on the front end face of the bump electrodes 3 of the flip chip 4. Finally, the bump electrodes 3 and the connecting conductor layers 6 with an anisotroical conductive film 7 interposed between them are connected to one another by pressurizing and heating steps.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、フリップチップを回路
基板にフェ−スダウンボンディングした構造の混成集積
回路等の電子回路装置及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit device such as a hybrid integrated circuit having a structure in which a flip chip is face-down bonded to a circuit board and a method for manufacturing the same.

【0002】[0002]

【従来の技術】半導体チップを回路基板に装着する方法
としてフェ−スダウンボンディング方法が知られてい
る。フェ−スダウンボンディングの代表的な方法では、
半導体チップに半田突起電極(バンプ電極)を予め設
け、半導体チップの半田突起電極を有する面を回路基板
に対向させて半田突起電極を回路基板の導体層に半田付
けする。しかし、半田付けによるフェ−スダウンボンデ
ィングによって高密度化に対処することは困難である。
高密度化を可能にする方法として半田の代りに異方性導
電接着剤を使用してフリップチップをフェ−スダウンボ
ンディングする方法がある。異方性導電性接着剤は、熱
可塑性樹脂に導電粒子(金属粒子)を均一に分散させた
ものであって、フィルム状のものとペ−スト状のものと
2種類がある。例えば異方性導電フィルムを使用してフ
リップチップをフェ−スダウンボディングする時には、
図1に示すように半導体基板1に金属端子導体層2を設
け、この金属端子導体層2にメッキによってバンプ電極
(突起電極)3を設けたフリップチップ4を用意すると
共に、セラミック等の絶縁性回路基板5に接続導体層6
を設けたものを用意する。次にバンプ電極3と接続導体
層6との間に異方性導電フィルム7を配置し、フリップ
チップ4の上面を回路基板5に向って加圧すると共に加
熱する。異方性導電フィルム7は熱可塑性樹脂8とNi
等の導電粒子9とから成るので、これがバンプ電極3と
接続導体層6との間で加圧および加熱されると、樹脂8
の流動が生じ、導電粒子9がバンプ電極3と接続導体層
6との間に残存し、両者間が電気的に接続される。バン
プ電極3と接続導体層6の間以外の部分では導電粒子9
の相互間が樹脂8で絶縁された状態にあるので、この部
分で電気的接続は成立しない。これによりバンプ電極3
のみの接続が達成される。
2. Description of the Related Art A face-down bonding method is known as a method of mounting a semiconductor chip on a circuit board. In the typical method of face-down bonding,
Solder bump electrodes (bump electrodes) are provided in advance on the semiconductor chip, and the solder bump electrodes are soldered to the conductor layer of the circuit board with the surface of the semiconductor chip having the solder bump electrodes facing the circuit board. However, it is difficult to cope with high density by face-down bonding by soldering.
As a method of enabling high density, there is a method of face-down bonding a flip chip using an anisotropic conductive adhesive instead of solder. The anisotropic conductive adhesive is one in which conductive particles (metal particles) are uniformly dispersed in a thermoplastic resin, and there are two types, a film type and a paste type. For example, when face-down boarding a flip chip using an anisotropic conductive film,
As shown in FIG. 1, a flip chip 4 having a metal terminal conductor layer 2 provided on a semiconductor substrate 1 and bump electrodes (projection electrodes) 3 provided by plating on the metal terminal conductor layer 2 is prepared, and an insulating property such as ceramics is provided. Connection conductor layer 6 to the circuit board 5
Prepare the one with. Next, the anisotropic conductive film 7 is arranged between the bump electrode 3 and the connection conductor layer 6, and the upper surface of the flip chip 4 is pressed toward the circuit board 5 and heated. The anisotropic conductive film 7 is made of a thermoplastic resin 8 and Ni.
Since the conductive particles 9 and the like are applied to the bump electrode 3 and the connection conductor layer 6 under pressure and heating, the resin 8
Flows, the conductive particles 9 remain between the bump electrode 3 and the connection conductor layer 6, and the two are electrically connected. The conductive particles 9 are provided in a portion other than between the bump electrode 3 and the connection conductor layer 6.
Since they are insulated from each other by the resin 8, no electrical connection is established at this portion. As a result, the bump electrode 3
Only connection is achieved.

【0003】[0003]

【発明が解決しようとする課題】ところで、量産性を考
慮して金(Au)メッキでバンプ電極3を形成した場合
にはバンプ電極3の先端面即ち頂面が球面又はこれに近
い状態となる。この結果、異方性導電フィルムがバンプ
電極3で加圧及び加熱された時に導電粒子9がバンプ電
極3の下から逃げる現象が生じ、バンプ電極3と接続導
体層6との間に十分な数の導電粒子9が残存しないこと
がある。このような場合にはバンプ電極3と接続導体層
6とを低抵抗接続することが不可能になる。今、異方性
導電フィルムを使用した場合について述べたが異方性導
電ペ−ストを使用する場合にも同様な問題がある。ま
た、フリップチップ4の回路基板5に対する実装に限ら
ず、一方の回路基板のバンプ電極と他方の回路基板の接
続導体層とを電気的に接続する場合にも同様な問題があ
る。
When the bump electrode 3 is formed by gold (Au) plating in consideration of mass productivity, the tip surface, that is, the top surface of the bump electrode 3 becomes a spherical surface or a state close to the spherical surface. . As a result, when the anisotropic conductive film is pressed and heated by the bump electrode 3, the conductive particles 9 escape from the bottom of the bump electrode 3, and a sufficient number of particles are provided between the bump electrode 3 and the connection conductor layer 6. The conductive particles 9 may not remain. In such a case, it becomes impossible to connect the bump electrode 3 and the connection conductor layer 6 with low resistance. Although the case where the anisotropic conductive film is used has been described above, the same problem occurs when using the anisotropic conductive paste. Further, not only the mounting of the flip chip 4 on the circuit board 5, but also the case where the bump electrodes of one circuit board and the connection conductor layers of the other circuit board are electrically connected, there is a similar problem.

【0004】そこで、本発明の目的は第1の回路構成部
材の突起電極と第2の回路構成部材の導体層とが低抵抗
接続された電子回路装置及びその製造方法を提供するこ
とにある。
Therefore, an object of the present invention is to provide an electronic circuit device in which the protruding electrode of the first circuit component member and the conductor layer of the second circuit component member are connected with low resistance, and a manufacturing method thereof.

【0005】上記目的を達成するための装置の発明は、
第1の回路構成部材の突起電極が第2の回路構成部材の
導体層に接続された構成の電子回路装置において、前記
導体層に前記突起電極の先端面の形状にほぼ相似の凹部
が形成され、前記突起電極の先端面が前記凹部に対向配
置され、前記突起電極と前記導体層が異方性導電物体に
よって接続されていることを特徴とする電子回路装置に
係わるものである。上記目的を達成するための方法の発
明は、突起電極を有する第1の回路構成部材を用意する
工程と、前記突起電極を接続するための導体層を有し、
この導体層に前記突起電極の先端面にほぼ相似の凹部が
形成されている第2の回路構成部材を用意する工程と、
前記突起電極と前記導体層とを異方性導電物体によって
接続する工程とを有することを特徴とする電子回路装置
の製造方法に係わるものである。
The invention of a device for achieving the above object is
In an electronic circuit device having a configuration in which the protruding electrode of the first circuit component member is connected to the conductor layer of the second circuit component member, a recess having a shape substantially similar to the shape of the tip surface of the protrusion electrode is formed in the conductor layer. The present invention relates to an electronic circuit device, wherein the tip end surface of the protruding electrode is arranged to face the recess, and the protruding electrode and the conductor layer are connected by an anisotropic conductive object. The invention of a method for achieving the above object, a step of preparing a first circuit component having a protruding electrode, and a conductor layer for connecting the protruding electrode,
A step of preparing a second circuit component member in which a substantially similar recess is formed on the tip surface of the protruding electrode in the conductor layer;
And a step of connecting the protruding electrode and the conductor layer with an anisotropic conductive body, which is related to a method for manufacturing an electronic circuit device.

【0006】[0006]

【発明の作用及び効果】各請求項の発明によれば、突起
電極がこれと相似の凹部を有する導体層に異方性導電物
体によって結合される。これにより、突起電極が導体層
に正確且つ安定的に位置決めされるのみでなく、両者間
の広い面積にわたって均一な間隙が生じ、この間隙に異
方性導電物体の導電粒子が安定的に配置される。この結
果、突起電極と導体層との間を低抵抗接続することがで
きる。
According to the inventions of the respective claims, the protruding electrode is bonded to the conductor layer having the concave portion similar thereto by the anisotropic conductive body. As a result, not only is the protruding electrode accurately and stably positioned on the conductor layer, but also a uniform gap is created over a large area between the two, and the conductive particles of the anisotropic conductive body are stably arranged in this gap. It As a result, a low resistance connection can be made between the protruding electrode and the conductor layer.

【0007】[0007]

【実施例】次に、図2〜図4を参照して本発明の実施例
に係わるフリチップを含む電子回路装置(混成集積回路
装置)及びその製造方法を説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an electronic circuit device (hybrid integrated circuit device) including a flip chip and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to FIGS.

【0008】まず、図2に示す第1の回路部材としての
フリップチップ4を用意する。フリップチップは、図1
と同様に半導体基板1と端子導体層2とバンプ電極(突
起電極)3とから成る。半導体基板1はトランジスタ又
はIC等を形成するための周知の半導体領域及び絶縁膜
等を含むが、説明を簡単にするためにこれ等の図示が省
略されている。端子導体層2は100μm×100μm
の平面形状が正方向のパタ−ンを有し、金(Au)で形
成されている。バンプ電極3を設ける前の半導体基板1
と端子導体層2とから成るものは一般に半導体ベアチッ
プと呼ばれているものである。バンプ電極3は金メッキ
によって形成されている。金メッキでバンプ電極3を形
成すると、バンプ電極3の先端面が球面状又は突出曲面
状に成る。バンプ電極3の寸法を例示すると、平面形状
は100μm×100μmの正方形であり、中央の高さ
は約10μmである。端子導体層2の厚さが20μmで
あるので、端子導体層2とバンプ電極3とを合せた突出
電極の中央の高さは30μmである。
First, the flip chip 4 as the first circuit member shown in FIG. 2 is prepared. Flip chip, Figure 1
Similarly, the semiconductor substrate 1, the terminal conductor layer 2, and the bump electrodes (projection electrodes) 3 are formed. The semiconductor substrate 1 includes a well-known semiconductor region for forming a transistor, an IC, etc., an insulating film, etc., but these are not shown for simplicity of description. The terminal conductor layer 2 is 100 μm × 100 μm
Has a pattern in the positive direction and is made of gold (Au). Semiconductor substrate 1 before providing bump electrodes 3
What is made up of and the terminal conductor layer 2 is generally called a semiconductor bare chip. The bump electrode 3 is formed by gold plating. When the bump electrode 3 is formed by gold plating, the tip end surface of the bump electrode 3 has a spherical shape or a protruding curved surface shape. As an example of the size of the bump electrode 3, the planar shape is a square of 100 μm × 100 μm, and the height of the center is about 10 μm. Since the thickness of the terminal conductor layer 2 is 20 μm, the height of the center of the protruding electrode, which is the combination of the terminal conductor layer 2 and the bump electrode 3, is 30 μm.

【0009】セラミックから成る絶縁性回路基板5上の
導体層6は金から成り、この厚さ約20μmである。こ
の導体層6の上面には120μm×120μmの凹部1
0が形成されている。凹部10はバンプ電極3の先端面
にほぼ相似の表面を有する。なお、ワイヤ−ボンダ−の
キャピラリの代りにバンプ電極3に相似の先端面を有す
るヘッドを取り付け、このヘッドをワイヤ−ボンダ−で
接続導体層6を押し当てることによって凹部10を形成
した。
The conductor layer 6 on the insulating circuit board 5 made of ceramic is made of gold and has a thickness of about 20 μm. The upper surface of the conductor layer 6 has a recess 1 of 120 μm × 120 μm.
0 is formed. The recess 10 has a surface that is substantially similar to the tip surface of the bump electrode 3. A head having a similar tip surface to the bump electrode 3 was attached instead of the capillary of the wire bonder, and the recess 10 was formed by pressing the connecting conductor layer 6 against the head with the wire bonder.

【0010】次に、回路基板5の接続導体層6とフリッ
プチップ4のバンプ電極3との間に異方性導電物体とし
ての異方性導電フィイルム7を配置し、フリップチップ
4の上面を回路基板5に向かって加圧すると共に約16
0℃で10秒間加熱しバンプ電極3を接続導体層6に導
電粒子9によって電気的に接続した。この時、接続導体
層6には凹部10が形成されているためにバンプ電極3
と凹10との間の導電粒子9が凹部10から逃げ難くな
り、多くの導電粒子9によって両者が低抵抗接続されて
いる。なお、異方性導電フィルム7の熱可塑性樹脂8は
接着剤として機能し、回路基板5にフリップチップ4を
機械的に固着する。
Next, an anisotropic conductive film 7 as an anisotropic conductive object is arranged between the connecting conductor layer 6 of the circuit board 5 and the bump electrode 3 of the flip chip 4, and the upper surface of the flip chip 4 is connected to the circuit. Pressurize toward the substrate 5 and about 16
The bump electrode 3 was electrically connected to the connection conductor layer 6 by the conductive particles 9 by heating at 0 ° C. for 10 seconds. At this time, since the concave portion 10 is formed in the connection conductor layer 6, the bump electrode 3
It becomes difficult for the conductive particles 9 between the recess 10 and the recess 10 to escape from the recess 10, and many conductive particles 9 are connected to each other with low resistance. The thermoplastic resin 8 of the anisotropic conductive film 7 functions as an adhesive and mechanically fixes the flip chip 4 to the circuit board 5.

【0011】上述から明らかなように凹部10の働きに
よってバンプ電極3と接続導体層6の間に多くの導電粒
子9を配置することが可能になり、従来よりも約30%
低い抵抗値で両者を接続することができる。また、バン
プ電極3の先端面を平坦面に形成することが不要である
ので、ホトエッチング法等の複雑な工程でバンプ電極3
を形成しないで、メッキ法によって容易に形成すること
が可能になる。また接続導体層6の凹部10はバンプ電
極3を位置決めし且つ安定的に保持する働きも有する。
As is apparent from the above, the function of the recess 10 makes it possible to arrange a large number of conductive particles 9 between the bump electrode 3 and the connection conductor layer 6, which is about 30% that of the conventional case.
Both can be connected with a low resistance value. Moreover, since it is not necessary to form the tip end surface of the bump electrode 3 into a flat surface, the bump electrode 3 can be formed by a complicated process such as a photoetching method.
It is possible to easily form by a plating method without forming. The recess 10 of the connection conductor layer 6 also has a function of positioning the bump electrode 3 and stably holding it.

【0012】[0012]

【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 (1) 第1の回路構成部材が回路基板5であり、第2
の回路構成部材が半導体チップであってもよい。この場
合には、例えば回路基板5の接続導体層6の上にバンプ
電極を設け半導体チップの端子導体層に凹部10に相当
するものを設ける。また、第1及び第2の回路構成部材
の両方が回路基板の場合にも本発明を適用することがで
きる。 (2) 異方性導電物体として異方性導電ペ−ストを接
続導体層6の凹部10とバンプ電極3との間に介在させ
て両者を接続することもできる。 (3) バンプ電極3を半球状にすることができるる。
[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The first circuit component is the circuit board 5, and the second
The circuit constituent member may be a semiconductor chip. In this case, for example, a bump electrode is provided on the connection conductor layer 6 of the circuit board 5 and a terminal conductor layer of the semiconductor chip corresponding to the recess 10 is provided. The present invention can also be applied when both the first and second circuit components are circuit boards. (2) An anisotropic conductive paste may be interposed as an anisotropic conductive object between the concave portion 10 of the connection conductor layer 6 and the bump electrode 3 to connect them. (3) The bump electrode 3 can have a hemispherical shape.

【図面の簡単な説明】[Brief description of the drawings]

【図1】従来の異方性導電フィルムを使用したフリップ
チップの回路基板に対する装着を原理的に示す断面図で
ある。
FIG. 1 is a sectional view showing in principle how a flip chip using a conventional anisotropic conductive film is mounted on a circuit board.

【図2】本発明の実施例に係わるフリップチップを示す
断面図である。
FIG. 2 is a cross-sectional view showing a flip chip according to an embodiment of the present invention.

【図3】本発明の実施例の接続導体層を有する回路基板
を示す断面図である。
FIG. 3 is a cross-sectional view showing a circuit board having a connection conductor layer according to an example of the present invention.

【図4】図3の回路基板に図2のフリップチップを異方
性導電フィルムで実装した状態を示す断面図である。
4 is a cross-sectional view showing a state in which the flip chip of FIG. 2 is mounted on the circuit board of FIG. 3 with an anisotropic conductive film.

【符号の説明】[Explanation of symbols]

3 バンプ電極 4 フリップチップ 5 回路基板 6 接続導体層 7 異方性導電フィルム 9 導電粒子 10 凹部 3 Bump Electrodes 4 Flip Chip 5 Circuit Board 6 Connection Conductor Layer 7 Anisotropic Conductive Film 9 Conductive Particles 10 Recess

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 第1の回路構成部材の突起電極が第2の
回路構成部材の導体層に接続された構成の電子回路装置
において、 前記導体層に前記突起電極の先端面の形状にほぼ相似の
凹部が形成され、前記突起電極の先端面が前記凹部に対
向配置され、前記突起電極と前記導体層が異方性導電物
体によって接続されていることを特徴とする電子回路装
置。
1. An electronic circuit device having a structure in which a protruding electrode of a first circuit component member is connected to a conductor layer of a second circuit component member, wherein the conductor layer is substantially similar to the shape of the tip surface of the protruding electrode. Is formed, the tip end surface of the protruding electrode is arranged so as to face the recess, and the protruding electrode and the conductor layer are connected by an anisotropic conductive object.
【請求項2】 突起電極を有する第1の回路構成部材を
用意する工程と、 前記突起電極を接続するための導体層を有し、この導体
層に前記突起電極の先端面にほぼ相似の凹部が形成され
ている第2の回路構成部材を用意する工程と、 前記突起電極と前記導体層とを異方性導電物体によって
接続する工程とを有することを特徴とする電子回路装置
の製造方法。
2. A step of preparing a first circuit component having a bump electrode, and a conductor layer for connecting the bump electrode, wherein the conductor layer has a recess substantially similar to the tip surface of the bump electrode. 2. A method for manufacturing an electronic circuit device, comprising: a step of preparing a second circuit component having the structure formed therein; and a step of connecting the protruding electrode and the conductor layer with an anisotropic conductive body.
JP7345137A 1995-12-06 1995-12-06 Electronic circuit device and its manufacturing method Pending JPH09162230A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7345137A JPH09162230A (en) 1995-12-06 1995-12-06 Electronic circuit device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7345137A JPH09162230A (en) 1995-12-06 1995-12-06 Electronic circuit device and its manufacturing method

Publications (1)

Publication Number Publication Date
JPH09162230A true JPH09162230A (en) 1997-06-20

Family

ID=18374537

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7345137A Pending JPH09162230A (en) 1995-12-06 1995-12-06 Electronic circuit device and its manufacturing method

Country Status (1)

Country Link
JP (1) JPH09162230A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388321B1 (en) 1999-06-29 2002-05-14 Kabushiki Kaisha Toshiba Anisotropic conductive film and resin filling gap between a flip-chip and circuit board
US6791185B1 (en) * 1999-09-02 2004-09-14 Micron Technology, Inc. Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer
EP0890989A4 (en) * 1997-01-24 2006-11-02 Rohm Co Ltd Semiconductor device and method for manufacturing thereof
CN100345292C (en) * 2005-11-02 2007-10-24 友达光电股份有限公司 Chip pressing structure and its shaping method and electronic installation
US7307349B2 (en) 1999-02-24 2007-12-11 Rohm Co., Ltd. Semiconductor device of chip-on-chip structure, assembling process therefor, and semiconductor chip to be bonded to solid surface
EP1247432B1 (en) * 1999-12-27 2008-03-05 TridonicAtco GmbH & Co. KG Electronic ballast and electronic transformer
JP2012049398A (en) * 2010-08-27 2012-03-08 Fujifilm Corp Conductive joint structure, mounting structure, and conductive joining method
CN111864038A (en) * 2019-04-28 2020-10-30 陕西坤同半导体科技有限公司 Display panel, display device and preparation method of display panel
US11373945B2 (en) * 2019-07-08 2022-06-28 Innolux Corporation Electronic device
US20230126990A1 (en) * 2020-03-31 2023-04-27 Kyocera Corporation Thermal head and thermal printer

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0890989A4 (en) * 1997-01-24 2006-11-02 Rohm Co Ltd Semiconductor device and method for manufacturing thereof
US7307349B2 (en) 1999-02-24 2007-12-11 Rohm Co., Ltd. Semiconductor device of chip-on-chip structure, assembling process therefor, and semiconductor chip to be bonded to solid surface
US6388321B1 (en) 1999-06-29 2002-05-14 Kabushiki Kaisha Toshiba Anisotropic conductive film and resin filling gap between a flip-chip and circuit board
US6791185B1 (en) * 1999-09-02 2004-09-14 Micron Technology, Inc. Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer
US6876089B2 (en) 1999-09-02 2005-04-05 Micron Technology, Inc. Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer
US7214962B2 (en) 1999-09-02 2007-05-08 Micron Technology, Inc. Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer
EP1247432B1 (en) * 1999-12-27 2008-03-05 TridonicAtco GmbH & Co. KG Electronic ballast and electronic transformer
CN100345292C (en) * 2005-11-02 2007-10-24 友达光电股份有限公司 Chip pressing structure and its shaping method and electronic installation
JP2012049398A (en) * 2010-08-27 2012-03-08 Fujifilm Corp Conductive joint structure, mounting structure, and conductive joining method
CN111864038A (en) * 2019-04-28 2020-10-30 陕西坤同半导体科技有限公司 Display panel, display device and preparation method of display panel
US11373945B2 (en) * 2019-07-08 2022-06-28 Innolux Corporation Electronic device
US20230126990A1 (en) * 2020-03-31 2023-04-27 Kyocera Corporation Thermal head and thermal printer

Similar Documents

Publication Publication Date Title
JP3420917B2 (en) Semiconductor device
JP2001267359A (en) Method for manufacturing semiconductor device and semiconductor device
JPH09162230A (en) Electronic circuit device and its manufacturing method
JP2000277649A (en) Semiconductor and manufacture of the same
JPH0750726B2 (en) Semiconductor chip mounting body
JPS63122133A (en) Electrically connecting method for semiconductor chip
JP2000252320A (en) Semiconductor device and manufacture thereof
JPH11163054A (en) Structure of semiconductor device and its manufacture
US6291893B1 (en) Power semiconductor device for “flip-chip” connections
JPS63168028A (en) Fine connection structure
JPH10189655A (en) Wiring board, semiconductor device and mounting of electronic component
JP3446608B2 (en) Semiconductor unit
JPH06151440A (en) Semiconductor device, its manufacture, and its packaging body
JP2652222B2 (en) Substrate for mounting electronic components
JPH08186117A (en) Method for capillary and bump forming of wire bonding apparatus
JPS63122135A (en) Electrically connecting method for semiconductor chip
JP2000232118A (en) Bare ic chip and semiconductor device manufacture
JP2000228457A (en) Semiconductor device, its manufacture, and tape carrier
JPH04356935A (en) Bump-electrode formation and mounting structure of semiconductor device
JPH01145826A (en) Electrical connection contact
JP2004288814A (en) Semiconductor device and its manufacturing method, circuit board and electronic apparatus
JPH10125730A (en) Mounted structure and manufacturing method thereof
JPH10340906A (en) Surface-mount electronic part, manufacture and mounting thereof
JP3598058B2 (en) Circuit board
JPH11224888A (en) Semiconductor device and its manufacturing

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20020320