JPS63168028A - Fine connection structure - Google Patents
Fine connection structureInfo
- Publication number
- JPS63168028A JPS63168028A JP61311049A JP31104986A JPS63168028A JP S63168028 A JPS63168028 A JP S63168028A JP 61311049 A JP61311049 A JP 61311049A JP 31104986 A JP31104986 A JP 31104986A JP S63168028 A JPS63168028 A JP S63168028A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor chip
- electrodes
- alloy
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000004020 conductor Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 14
- 229910001128 Sn alloy Inorganic materials 0.000 abstract description 6
- 229910045601 alloy Inorganic materials 0.000 abstract description 6
- 239000000956 alloy Substances 0.000 abstract description 6
- 238000002844 melting Methods 0.000 abstract description 6
- 230000008018 melting Effects 0.000 abstract description 6
- 229910020220 Pb—Sn Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 229920001971 elastomer Polymers 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 241000587161 Gomphocarpus Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
- Details Of Resistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体チップに代表されるチップ状の電子部
品を基板上の端子電極群に接続する際の微細接続構造に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a fine connection structure for connecting a chip-shaped electronic component, typified by a semiconductor chip, to a group of terminal electrodes on a substrate.
従来の技術
従来、電子部品の接続端子と基板上の回路パターン端子
との接続には半田付け（Ｐｂ−Ｓｎ半田）がよく利用さ
れていたが、近年、例えばＩＣフラットパッケージ等の
小型化と、接続端子の増加により端子間、いわゆるピッ
チ間隔が次第に狭くなり、従来の半田付は技術で対処す
ることが次第に困難になって来た。また、最近では入出
力デバイスの高精細度化が進む中で映像用の液晶ディス
プレイやサーマルヘッド等に見られる様に、微細パター
ンの形成が容易でかつ導体抵抗の低い／ｌ電極を採用す
る例が目立って増加している。加えて、これらの入出力
デバイスにあっては、半導体ＩＣを多数個構成するため
裸の半導体チップを基板上のＡｌ電極に直付けして実装
面積の効率的使用と配線の合理化を図ろうとする動きが
あり、半田付けに代る有効かつ微細な電気的接続手段が
強く望まれている。裸の半導体チップを基板の電極に直
付けして電気的に接続する方法としては、メッキ技術に
より半導体チップの電極パッド上にハンダ（Ｐｂ−Ｓｎ
）からなる突起電極（バンブ）を用いたフリップチップ
実装法が知られている。既知のフリップチップ実装法は
、半導体チップの電極バッド上に設けたＰｂ−Ｓｎバン
ブと基板上に設けたＣｕｓ Ｎｉ、Ａｕ等の接続金属層
とを加熱溶融して接続をはかるというものである。また
、特開昭６０−１３３６０３号公報に示されているよう
に、シリコンゴム中にカーボンを含めて導電ゴムを得、
これを基板の電極部とＩＣチップのバンプとの間に介し
て加圧して、電気的な接続を行う方法が提案されている
。Conventional technology In the past, soldering (Pb-Sn solder) was often used to connect the connection terminals of electronic components and the circuit pattern terminals on the board, but in recent years, with the miniaturization of IC flat packages, for example, With the increase in the number of connection terminals, the distance between the terminals, the so-called pitch interval, has gradually become narrower, and conventional soldering techniques have become increasingly difficult to handle. In recent years, as input/output devices have become increasingly high-definition, there are examples of using /l electrodes, which are easy to form fine patterns and have low conductor resistance, as seen in liquid crystal displays for video, thermal heads, etc. is increasing noticeably. In addition, for these input/output devices, in order to configure a large number of semiconductor ICs, bare semiconductor chips are directly attached to Al electrodes on the substrate in an attempt to use the mounting area efficiently and rationalize wiring. There is a strong need for an effective and fine electrical connection means that has movement and is an alternative to soldering. A method for electrically connecting a bare semiconductor chip by directly attaching it to the electrodes of a substrate is to apply solder (Pb-Sn) onto the electrode pads of the semiconductor chip using plating technology.
) is known as a flip-chip mounting method using protruding electrodes (bumps). A known flip-chip mounting method involves heating and melting a Pb-Sn bump provided on an electrode pad of a semiconductor chip and a connecting metal layer such as Cu, Ni or Au provided on a substrate to establish a connection. Furthermore, as shown in Japanese Patent Application Laid-Open No. 60-133603, conductive rubber is obtained by including carbon in silicone rubber.
A method has been proposed in which electrical connection is established by applying pressure between the electrode portion of the substrate and the bump of the IC chip.
発明が解決しようとする問題点
しかしながら第一の従来方法においては、半導体チップ
のＰｂ−Ｓｎバンブと基板上のＡ１電極とをダイレクト
に接続することは極めて困難であり、さらに半導体チッ
プと基板との接続に際して、２００℃以上といった高温
の処理工程が必要であった。また、第二の従来方法にお
いては、導電ゴムを用いているため、接続抵抗が大きく
、微小な電流しか流すことができず、用途が限定される
ものであった。さらに、電極が微細になり、また、電極
密度が高くなればなる程、電極間に介在させる導電ゴム
の微細化が困難となるといった欠点を有していた。Problems to be Solved by the Invention However, in the first conventional method, it is extremely difficult to directly connect the Pb-Sn bump of the semiconductor chip and the A1 electrode on the substrate, and furthermore, it is difficult to directly connect the Pb-Sn bump of the semiconductor chip and the A1 electrode on the substrate. Connection requires a high-temperature process of 200° C. or higher. In addition, in the second conventional method, since conductive rubber is used, the connection resistance is large and only a small current can flow, which limits the application. Furthermore, as the electrodes become finer and the electrode density becomes higher, it becomes difficult to make the conductive rubber interposed between the electrodes finer.
本発明は上記の問題点に鑑みてなされたものであり、そ
の目的とする所は微細かつ密に形成された半導体の電極
パッドと基板上のＡ１電極群とを低温で、かつ信頼性良
く電気的接続を行うことにある。The present invention has been made in view of the above-mentioned problems, and its purpose is to connect fine and densely formed semiconductor electrode pads and the A1 electrode group on a substrate at low temperature and with high reliability. The goal is to make physical connections.
問題点を解決するための手段
上記の問題点を解決するために本発明の微細接続構造は
、実装基板の導電端子部に形成されたＡｌ電極と半導体
チップの入出力端子に形成された突起電極とをＩｎ−Ｓ
ｎ接続層を介して電気的に接合されていることを特徴と
するものである。Means for Solving the Problems In order to solve the above problems, the fine connection structure of the present invention uses Al electrodes formed on the conductive terminals of the mounting board and protruding electrodes formed on the input/output terminals of the semiconductor chip. and In-S
It is characterized in that it is electrically connected via an n-connection layer.
作用
しかして本発明の上記した方法によれば、Ｉｎ−Ｓｎ合
金は低融点金属であると同時にＡ１電極との合金接合性
を備えているので半導体チップと基板上のＡｌ電極パッ
ドとを容易に、かつ低温で接続可能となる。またこの接
続構造は金属材料による合金接合であり、さらにＩｎ−
Ｓｎ合金は比較的軟かく熱疲労に強いため、有機材料を
用いた接合に比べ接触抵抗も低く、信頼性の高い電気的
接続が可能となる。According to the above-described method of the present invention, the In-Sn alloy is a low melting point metal and at the same time has alloy bonding properties with the A1 electrode, so it is possible to easily connect the semiconductor chip and the Al electrode pad on the substrate. , and can be connected at low temperatures. In addition, this connection structure is an alloy bond using metal materials, and furthermore, In-
Since the Sn alloy is relatively soft and resistant to thermal fatigue, the contact resistance is lower than that of a bond using an organic material, and a highly reliable electrical connection is possible.
実施例
以下、本発明の一実施例の微細接続構造について図面を
参照しながら説明する。EXAMPLE Hereinafter, a fine connection structure according to an example of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例を示す半導体チップの断
面図、第２図は半導体チップを実装基板の導体端子部に
実装した時の断面図である。FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention, and FIG. 2 is a sectional view of the semiconductor chip mounted on a conductor terminal portion of a mounting board.
図において１は半導体チップ、２は半導体チップの電極
パッド、３は突起電極、４はＩｎ−Ｓｎ接続層、５は実
装基板、６は導体端子部、７はＡｌ電極である。In the figure, 1 is a semiconductor chip, 2 is an electrode pad of the semiconductor chip, 3 is a protruding electrode, 4 is an In-Sn connection layer, 5 is a mounting board, 6 is a conductor terminal portion, and 7 is an Al electrode.
本発明の実施例では、まず第１図に示すように半導体チ
ップ１の電極パッド２にメッキ技術、またはネイルヘッ
ドボンディングの技術を用いて３０μ〜１００μの高さ
のＡｕからなる突起電極を形成する。この時電極パッド
２には必要に応じてＣｒ、Ｔｉ等のバリア金属層やＣｕ
、Ａｕ等の密着強化層を形成する。次いで、半導体チッ
プ１の突起電極３には２０〜３０μの厚さに５２ｉｎ−
４８５ｎ合金からなる接続層４を設ける。この接続層４
の形成は還元雰囲気中で１５０℃に加熱溶融したＩｎ−
Ｓｎ合金に突起電極３を当接させて選択的に転写したも
ので、１５０℃以下の低融点を有するものであればその
組成は必要に応じて選択が可能である。第２図に示す実
装基板５は公知の蒸着、メッキやフォトリソ技術を用い
て導体端子部６を形成しその上主面にＡ２電極７を形成
したものである。なお、形成方法については既知である
ため、ここではその説明を省略する。この後、Ｉｎ−Ｓ
ｎ接続層４を形成した半導体チップ１と実装基板５は、
第２図に示すようにＩｎ−Ｓｎ接合Ｎ４を実装基板５の
導体端子部６に形成した。ｌ電極７と対向させて位置合
せした後ダイスボンダー等を用いて加熱溶融法、あるい
は加熱音波法によりＩｎ−Ｓｎ接合層４とＡ１電極７の
間を合金接続する。In the embodiment of the present invention, first, as shown in FIG. 1, protruding electrodes made of Au with a height of 30 μm to 100 μm are formed on the electrode pads 2 of the semiconductor chip 1 using plating technology or nail head bonding technology. . At this time, the electrode pad 2 may be coated with a barrier metal layer such as Cr, Ti or Cu.
, form an adhesion reinforcing layer of Au or the like. Next, the protruding electrode 3 of the semiconductor chip 1 has a thickness of 20 to 30 μm with a thickness of 52 in-
A connection layer 4 made of 485n alloy is provided. This connection layer 4
The formation of In-
It is selectively transferred by bringing the protruding electrode 3 into contact with the Sn alloy, and the composition can be selected as necessary as long as it has a low melting point of 150° C. or less. The mounting board 5 shown in FIG. 2 has a conductor terminal portion 6 formed thereon using known vapor deposition, plating, or photolithography techniques, and an A2 electrode 7 formed on the main surface thereof. Note that since the formation method is already known, its explanation will be omitted here. After this, In-S
The semiconductor chip 1 and the mounting board 5 on which the n-connection layer 4 is formed are as follows:
As shown in FIG. 2, an In-Sn junction N4 was formed on the conductor terminal portion 6 of the mounting board 5. After alignment so as to face the A1 electrode 7, the In--Sn bonding layer 4 and the A1 electrode 7 are alloy-bonded by a heat melting method or a heating sonic method using a die bonder or the like.
以上のようにしてＩｎ−５ｎ接合Ｎ４とＡ１電極７とを
接合することにより、半導体チップ１と実装基板５とが
電気的に接続出来る。尚、実施例ではＩｎ−Ｓｎ接合Ｎ
４の形成部位を半導体チップ１の突起電極３の上主面と
したがその形成部位は突起電極上に限定されるものでは
なく、実装基板のＡＡ電極上に設けても一向に差し支え
ないものである。また、実装基板についても例えばガラ
ス、セラミックス、ガラスエポキシ等の基板であっても
良いことはいうまでもない。By joining the In-5n junction N4 and the A1 electrode 7 as described above, the semiconductor chip 1 and the mounting board 5 can be electrically connected. In the example, In-Sn junction N
4 is formed on the upper main surface of the protruding electrode 3 of the semiconductor chip 1, but the forming part is not limited to the protruding electrode, and there is no problem in providing it on the AA electrode of the mounting board. . Furthermore, it goes without saying that the mounting board may be made of glass, ceramics, glass epoxy, or the like.
発明の詳細
な説明したように、本発明の半導体チップの微細接続構
造によれば、Ｉｎ−Ｓｎ合金は低融点金属であると同時
にＡｆ電極との合金接合性を備えているので、半導体チ
ップと基板上のＡＩｌ電極とを容易にかつ低温で接続が
可能となる。またこの接続構造は金属材料による合金接
続であり、加えてＩｎ−Ｓｎ合金は比較的柔らかく熱疲
労に強いため、有機材料を用いた接続法に比べて接触抵
抗も低く、信顛性の高い電気的接続が可能となり、実用
上極めて価値が高い。As described in detail, according to the fine connection structure of the semiconductor chip of the present invention, the In-Sn alloy is a low melting point metal and at the same time has alloy bondability with the Af electrode. Connection with the Al electrode on the substrate can be made easily and at low temperature. In addition, this connection structure is an alloy connection made of metal materials. In addition, the In-Sn alloy is relatively soft and resistant to thermal fatigue, so the contact resistance is lower than that of connection methods using organic materials, making it a highly reliable electrical connection. It is extremely valuable in practical terms.
第１図は本発明の一実施例を示す半導体チップの断面図
、第２図は半導体チップを実装基板の導体端子部に実装
した時の断面図である。
１・・・・・・半導体チップ、２・・・・・・半導体チ
ップの電極パッド、３・・・・・・突起電極、４・・・
・・・Ｉｎ−Ｓｎ接合層、５・・・・・・実装基板、６
・・・・・・導体端子部、７・・・・・・ＡＪ電極。FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention, and FIG. 2 is a sectional view of the semiconductor chip mounted on a conductor terminal portion of a mounting board. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Electrode pad of semiconductor chip, 3... Projection electrode, 4...
... In-Sn bonding layer, 5 ... Mounting board, 6
......Conductor terminal part, 7...AJ electrode.
Claims (1)
、入出力端子を突起電極で形成した半導体チップと、前
記突起電極に形成したＩｎ−Ｓｎ接合層とで構成され、
前記Ｉｎ−Ｓｎ接合層を介して前記Ａｌ電極と前記突起
電極が電気的に接続されていることを特徴とする微細接
続構造。Consisting of a substrate on which an Al electrode is formed on the upper main surface of a conductor terminal portion, a semiconductor chip whose input/output terminals are formed by protruding electrodes, and an In-Sn bonding layer formed on the protruding electrodes,
A fine connection structure characterized in that the Al electrode and the protruding electrode are electrically connected via the In-Sn bonding layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61311049A JPS63168028A (en) | 1986-12-29 | 1986-12-29 | Fine connection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61311049A JPS63168028A (en) | 1986-12-29 | 1986-12-29 | Fine connection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63168028A true JPS63168028A (en) | 1988-07-12 |
Family
ID=18012492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61311049A Pending JPS63168028A (en) | 1986-12-29 | 1986-12-29 | Fine connection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63168028A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02303043A (en) * | 1989-04-26 | 1990-12-17 | Commiss Energ Atom | Method and machine for connecting electric parts by welding member |
| JPH03108734A (en) * | 1989-03-14 | 1991-05-08 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPH0661368A (en) * | 1992-08-05 | 1994-03-04 | Nec Corp | Flip chip type semiconductor device |
| JP2004289113A (en) * | 2003-03-05 | 2004-10-14 | Mitsubishi Electric Corp | Metal electrode and bonding method using same |
| WO2020149401A1 (en) * | 2019-01-18 | 2020-07-23 | 株式会社オートネットワーク技術研究所 | Metallic material and connecting terminal |
-
1986
- 1986-12-29 JP JP61311049A patent/JPS63168028A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03108734A (en) * | 1989-03-14 | 1991-05-08 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPH02303043A (en) * | 1989-04-26 | 1990-12-17 | Commiss Energ Atom | Method and machine for connecting electric parts by welding member |
| JPH0661368A (en) * | 1992-08-05 | 1994-03-04 | Nec Corp | Flip chip type semiconductor device |
| JP2004289113A (en) * | 2003-03-05 | 2004-10-14 | Mitsubishi Electric Corp | Metal electrode and bonding method using same |
| WO2020149401A1 (en) * | 2019-01-18 | 2020-07-23 | 株式会社オートネットワーク技術研究所 | Metallic material and connecting terminal |
| JP2020117742A (en) * | 2019-01-18 | 2020-08-06 | 株式会社オートネットワーク技術研究所 | Metal material and connection terminal |
| CN113286918A (en) * | 2019-01-18 | 2021-08-20 | 株式会社自动网络技术研究所 | Metal material and connection terminal |
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