JPH08186117A - Method for capillary and bump forming of wire bonding apparatus - Google Patents

Method for capillary and bump forming of wire bonding apparatus

Info

Publication number
JPH08186117A
JPH08186117A JP6327955A JP32795594A JPH08186117A JP H08186117 A JPH08186117 A JP H08186117A JP 6327955 A JP6327955 A JP 6327955A JP 32795594 A JP32795594 A JP 32795594A JP H08186117 A JPH08186117 A JP H08186117A
Authority
JP
Japan
Prior art keywords
bump
semiconductor device
curved surface
electrode pad
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6327955A
Other languages
Japanese (ja)
Inventor
Masahiro Ono
正浩 小野
Yoshihiro Bessho
芳宏 別所
Yoshihiro Tomura
善広 戸村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6327955A priority Critical patent/JPH08186117A/en
Publication of JPH08186117A publication Critical patent/JPH08186117A/en
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To electrically connect the end of the bump of a semiconductor device to the terminal electrode of a circuit board with high reliability when the device is face-down-mounted on the terminal electrode of the board formed by screen printing, plating, etc., via a junction layer. CONSTITUTION: A curvature 24 is formed at the end of the bump of a semiconductor device 6, and face-down-mounted at the input and output terminal electrode 28 of a circuit board 29 via a junction layer. Thus, the thickness of the junction layer can be formed thinnest and uniform, and the electric connection and adherence of the low connecting resistance of the connecting part and high reliability can be realized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、ワイヤボンディング装
置用のキャピラリ、それを用いることによる、回路基板
の端子電極と半導体チップの電極パッドとを電気的に接
続するための湾曲面を有するバンプおよびバンプの形成
方法およびそのバンプを用いた半導体ユニットに関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capillary for a wire bonding apparatus, and a bump having a curved surface for electrically connecting a terminal electrode of a circuit board and an electrode pad of a semiconductor chip by using the capillary. The present invention relates to a bump forming method and a semiconductor unit using the bump.

【０００２】[0002]

【従来の技術】従来のワイヤボンディング装置用のキャ
ピラリ−は、マイクロスイス社のボンディングハンドブ
ックやキャピラリ−カタログなどに記載されている。2. Description of the Related Art A conventional capillary for a wire bonding apparatus is described in Micro Swiss Co., Ltd., such as a bonding handbook and a capillary catalog.

【０００３】図１０（ａ）はワイヤボンディング装置用
のキャピラリ−の先端部を示し、図１０（ｂ）はキャピ
ラリ−の先端部の形状をより詳細に示している。FIG. 10 (a) shows the tip of a capillary for a wire bonding apparatus, and FIG. 10 (b) shows the shape of the tip of the capillary in more detail.

【０００４】図１０（ａ）に示されるように、円筒形の
キャピラリ−８１は、内部にボンディング用の金属ワイ
ヤを挿入するためのワイヤ導出孔８２を有している。ワ
イヤ導出孔８２の大きさは、２５μｍφ〜５０μｍφ程
度である。キャピラリ−８１の先端部の外側には、ボン
ディングする間隔とボンディング後の金属ワイヤの形状
および大きさとを考慮し、３０゜程度の角度αがつけら
れている。As shown in FIG. 10 (a), the cylindrical capillary 81 has a wire lead-out hole 82 into which a metal wire for bonding is inserted. The size of the wire lead-out hole 82 is about 25 μmφ to 50 μmφ. An angle α of about 30 ° is provided on the outer side of the tip of the capillary 81 in consideration of the bonding interval and the shape and size of the metal wire after bonding.

【０００５】２５μｍφ程度の金属ワイヤを用いる場合
のキャピラリ−８１の先端部の形状が図１０（ｂ）に示
されている。この場合、ホ−ル径：３８μｍ、チップ
径：２０３μｍ、およびチャンファ−径：７４μｍであ
る。このようなキャピラリ−８１を用いることによって
半導体装置の電極パッド上にバンプを形成したり、他の
回路基板の端子電極への電気的な接続を行うことができ
る。The shape of the tip of the capillary 81 when a metal wire of about 25 μmφ is used is shown in FIG. 10 (b). In this case, the hole diameter is 38 μm, the tip diameter is 203 μm, and the chamfer diameter is 74 μm. By using such a capillary 81, bumps can be formed on the electrode pads of the semiconductor device or electrically connected to the terminal electrodes of another circuit board.

【０００６】次に、ワイヤボンディング用のキャピラリ
−を用いて、ボ−ルボンディング法によって半導体装置
のバンプを形成する従来の方法を説明する。特開平２−
３４９４９号公報には、２段突出形状の電気的接続バン
プ（以下２段バンプという）と、従来のキャピラリ−を
用いた２段バンプの形成方法が示されている。Next, a conventional method of forming bumps of a semiconductor device by a ball bonding method using a wire bonding capillary will be described. JP-A-2-
Japanese Laid-Open Patent Publication No. 34949 discloses a method of forming a two-step bump using a two-step protruding electrical connection bump (hereinafter referred to as a two-step bump) and a conventional capillary.

【０００７】図１１（ａ）〜（ｄ）は、従来のボ−ルボ
ンディング法によって、２段バンプを形成する方法を示
している。11A to 11D show a method of forming a two-step bump by a conventional ball bonding method.

【０００８】図１１（ａ）に示すように、キャピラリ−
８１のワイヤ導出孔８２に２５μｍφの金属ワイヤ８４
を通す。そして、金属ワイヤ８４の先端に、熱エネルギ
−を与えることにより、金属ワイヤ８４の径の約２〜３
倍の径を有するボ−ル８５を形成する。As shown in FIG. 11 (a), the capillary is
A metal wire 84 of 25 μmφ in the wire lead-out hole 82 of 81
Pass through. Then, by applying heat energy to the tip of the metal wire 84, the diameter of the metal wire 84 is reduced to about 2 to 3
A ball 85 having a doubled diameter is formed.

【０００９】次に、図１１（ｂ）に示すように、キャピ
ラリ−８１を降下させることにより、金属ワイヤ８４の
先端に形成されたボ−ル８５を、ＩＣチップ８６の電極
パッド１８３に当接させる。熱圧着の方法や超音波振動
を与えることによってボ−ル８５を電極パッド１８３に
固着させ、２段バンプの底部８９を形成する。Next, as shown in FIG. 11B, the ball 81 formed at the tip of the metal wire 84 is brought into contact with the electrode pad 183 of the IC chip 86 by lowering the capillary 81. Let The ball 85 is fixed to the electrode pad 183 by a thermocompression method or by applying ultrasonic vibration to form a bottom 89 of the two-step bump.

【００１０】そして、図１１（ｃ）に示すように、２段
バンプの底部８９と、キャピラリ−８１のワイヤ導出孔
８２に通された金属ワイヤ８４とがつながった状態のま
ま、キャピラリ−８１をＩＣチップ８６に対してル−プ
状に移動させる。キャピラリ−８１は、まず、２段バン
プの底部８９上方に垂直に上昇してからル−プ状軌道を
描くように移動し、その後、垂直に降下しながら、金属
ワイヤ８４を切断する。Then, as shown in FIG. 11C, the capillary 81 is held while the bottom portion 89 of the two-step bump and the metal wire 84 passed through the wire lead-out hole 82 of the capillary 81 are connected. The IC chip 86 is moved like a loop. The capillary 81 first rises vertically above the bottom portion 89 of the two-stage bump and then moves so as to draw a loop-shaped orbit, and then vertically descends to cut the metal wire 84.

【００１１】図１１（ｄ）に示されるように、キャピラ
リ−８１のル−プ状の運動により、底部８９の上には金
属ワイヤ８４がリング状または逆Ｕ字状に形成される。
この部分が２段バンプの頂部８８を形成する。キャピラ
リ−８１のエッジ部分１８２によって金属ワイヤ８４が
切断されることにより、２段バンプが形成される。As shown in FIG. 11D, the loop-shaped movement of the capillary 81 forms a metal wire 84 on the bottom 89 in a ring shape or an inverted U shape.
This portion forms the top 88 of the two-step bump. The metal wire 84 is cut by the edge portion 182 of the capillary 81 to form a two-step bump.

【００１２】この２段バンプをレベリングした（高さを
揃えた）ものの概略断面図を図１２に示す。FIG. 12 shows a schematic cross-sectional view of the two-level bump leveled (having the same height).

【００１３】それから、実装方法の従来例について以下
に述べる。従来、回路基板の入出力端子電極に半導体装
置を実装する際には、半田付けを用いたワイヤボンディ
ング方法がよく利用されてきた。しかし、近年、半導体
装置のパッケ−ジの小型化と接続端子数の増加により、
接続端子の間隔が狭くなり、従来の半田付け技術で対処
することが次第に困難になってきた。Then, a conventional example of the mounting method will be described below. Conventionally, a wire bonding method using soldering has been often used when mounting a semiconductor device on an input / output terminal electrode of a circuit board. However, in recent years, due to the miniaturization of semiconductor device packages and the increase in the number of connection terminals,
The space between the connection terminals has become narrower, and it has become increasingly difficult to cope with the problem with conventional soldering technology.

【００１４】そこで、最近では集積回路チップ等の半導
体装置を回路基板の入出力端子電極上に直接実装するこ
とにより、実装面積を小型化して効率的使用を図ろうと
する方法が提案されてきた。Therefore, recently, a method has been proposed in which a semiconductor device such as an integrated circuit chip is directly mounted on the input / output terminal electrodes of a circuit board to reduce the mounting area and achieve efficient use.

【００１５】なかでも、半導体装置を回路基板にフェイ
スダウン状態でフリップチップ実装する方法は、半導体
装置と回路基板との電気的接続が一括してできること、
および接続後の機械的強度が強いことから有用な方法で
あるとされている。In particular, in the method of flip-chip mounting the semiconductor device on the circuit board in a face-down state, the semiconductor device and the circuit board can be electrically connected at once.
It is considered to be a useful method because of its high mechanical strength after connection.

【００１６】例えば、工業調査会、１９８０年１月１５
日発行、日本マイクロエレクトロニクス協会編、「ＩＣ
化実装技術」には、半田めっき法を用いた実装方法が記
載されている。この実装方法を以下に説明する。[0016] For example, Industrial Research Committee, January 15, 1980
Published by Japan Microelectronics Association, "IC
The "mounting technology" describes a mounting method using a solder plating method. This mounting method will be described below.

【００１７】図１３は従来の半導体装置の半田バンプの
概略断面図（ａ）および半導体ユニットの概略断面図
（ｂ）を示す。図１３に示されるように、半導体装置
（ＩＣ基板）１１６の電極パッド１１３を図（ｂ）に示
す回路基板１１９の入出力端子電極１１８に接続する場
合に、まず半導体装置（ＩＣ基板）１１６の電極パッド
１１３上に密着金属膜１１２および拡散防止金属膜１１
１を蒸着法によって形成し、さらに、この上に半田から
なる電気的接続接点（以下、半田バンプという）１１０
をメッキ法により形成する。次に、このようにして形成
されたＩＣチップを、図１３（ｂ）に示されるようにフ
ェイスダウン状態で、半田バンプ１１０が入出力端子電
極１１８上に当接するように位置合わせを行い、回路基
板１１９上に載置する。その後、この半導体装置の実装
体（半導体ユニット）を高温に加熱することにより、半
田バンプ１１０を回路基板１１９の入出力端子電極１１
８に融着する。FIG. 13 shows a schematic sectional view (a) of a solder bump of a conventional semiconductor device and a schematic sectional view (b) of a semiconductor unit. As shown in FIG. 13, when connecting the electrode pads 113 of the semiconductor device (IC substrate) 116 to the input / output terminal electrodes 118 of the circuit board 119 shown in FIG. The adhesion metal film 112 and the diffusion prevention metal film 11 are formed on the electrode pad 113.
1 is formed by a vapor deposition method, and an electrical connection contact (hereinafter, referred to as a solder bump) 110 made of solder is further formed thereon.
Are formed by a plating method. Next, the IC chip thus formed is aligned face down as shown in FIG. 13B so that the solder bumps 110 abut on the input / output terminal electrodes 118, and a circuit is formed. It is placed on the substrate 119. Thereafter, by heating the mounted body (semiconductor unit) of this semiconductor device to a high temperature, the solder bumps 110 are connected to the input / output terminal electrodes 11 of the circuit board 119.
Fuse 8.

【００１８】また、最近では図１４の導電性接着剤を用
いた半導体ユニットの概略断面図に示されるように、半
導体装置（ＩＣ基板）１２６の電極パッド１２３上にワ
イヤボンディング法またはメッキ法により電気的接続接
点（Ａｕバンプ）１２０を形成し、このＡｕバンプ１２
０を導電性接着剤（接合層）１２５を介して回路基板１
２９の入出力端子電極１２８に接続するような半導体ユ
ニットも提案されている。このような半導体ユニットに
おいては、半導体装置１２６のＡｕバンプ１２０に導電
性接着剤１２５を転写してから、回路基板１２９の入出
力端子電極１２８にＡｕバンプ１２０が当接するように
位置合わせをし、導電性接着剤１２５を硬化して電気的
接続を得ている。Recently, as shown in the schematic cross-sectional view of a semiconductor unit using a conductive adhesive of FIG. 14, electrical bonding is performed on the electrode pad 123 of the semiconductor device (IC substrate) 126 by a wire bonding method or a plating method. Forming the contact point (Au bump) 120, and the Au bump 12
0 through the conductive adhesive (bonding layer) 125
A semiconductor unit that is connected to 29 input / output terminal electrodes 128 has also been proposed. In such a semiconductor unit, after the conductive adhesive 125 is transferred to the Au bumps 120 of the semiconductor device 126, the Au bumps 120 are aligned so that the Au bumps 120 contact the input / output terminal electrodes 128 of the circuit board 129. The conductive adhesive 125 is cured to obtain an electrical connection.

【００１９】[0019]

【発明が解決しようとする課題】上記のような従来のキ
ャピラリ−および従来のバンプおよびバンプ形成方法
は、半導体装置にバンプを形成する工程と、形成したバ
ンプをさらに整形するためのレベリング工程とを要する
ためにコストがかかる。また、レベリングを行うための
装置も別途必要である。しかし、レベリング工程を省く
ことは好ましくない。それは、ボ−ルボンディング法に
よって形成されたバンプの頂部８８は、リング状や逆Ｕ
字型の形状をしているので、頂部８８の端部の面積が小
さいため、回路基板の端子電極との接触面積が小さい。
また、バンプの高さのバラツキも大きいので、そのまま
実装したのでは信頼性の高い接続を行うことはできな
い。さらに、導電性接着剤を接合層に用いる場合には、
レベリング前のバンプの上記のような形状では、バンプ
先端部への導電性接着剤の転写量が少なく、転写量のバ
ラツキも大きいことから、導電性接着剤硬化した後の接
着強度が小さいので接着の信頼性が低く接続抵抗値も大
きくなってしまう。The conventional capillaries and the conventional bumps and bump forming methods as described above include a step of forming bumps on a semiconductor device and a leveling step for further shaping the formed bumps. It costs money because it takes. In addition, a device for performing leveling is required separately. However, it is not preferable to omit the leveling step. It is because the top portion 88 of the bump formed by the ball bonding method has a ring shape or an inverted U shape.
Since it has a V shape, the area of the end of the top portion 88 is small, and thus the contact area with the terminal electrode of the circuit board is small.
Further, since the bumps have a large variation in height, it is not possible to make a highly reliable connection if they are mounted as they are. Furthermore, when a conductive adhesive is used for the bonding layer,
With the above bump shape before leveling, the amount of transfer of the conductive adhesive to the tip of the bump is small and the transfer amount varies greatly. The reliability is low and the connection resistance value becomes large.

【００２０】回路基板上の端子電極はスクリ−ン印刷や
メッキ法によって形成されているため、端子電極の断面
形状が凸状に湾曲している。そのため、半導体装置の凸
状または平坦な先端面を設けたバンプを端子電極に接合
層を介して接続すると、端子電極の湾曲面の頂点とバン
プの先端部との間のみが電気的接続抵抗が一番小さくな
る。よって、位置合わせ時にずれが生じた場合には、バ
ンプと端子電極の距離が離れてしまい、接続抵抗値が増
大する。また、接続部も不安定になる。Since the terminal electrodes on the circuit board are formed by screen printing or plating, the terminal electrodes have a convex cross section. Therefore, when a bump provided with a convex or flat tip surface of a semiconductor device is connected to a terminal electrode through a bonding layer, electrical connection resistance is provided only between the apex of the curved surface of the terminal electrode and the tip portion of the bump. The smallest. Therefore, if a displacement occurs during alignment, the distance between the bump and the terminal electrode increases, and the connection resistance value increases. Also, the connection becomes unstable.

【００２１】本発明は、上記課題を解決するためになさ
れたものであり、その目的とするところは、半導体装置
と回路基板とを、容易に、信頼性よく、電気的に安定に
接続することを可能とするワイヤボンディング装置用の
キャピラリ、それを用いた回路基板の端子電極と半導体
チップの電極パッドとを電気的に接続するための湾曲面
を有するバンプおよびバンプの形成方法およびそのバン
プを有する半導体ユニット（実装体）を提供することに
ある。The present invention has been made to solve the above problems, and an object of the present invention is to connect a semiconductor device and a circuit board easily, reliably and electrically. For a wire bonding apparatus that enables the above, a bump having a curved surface for electrically connecting a terminal electrode of a circuit board using the same to an electrode pad of a semiconductor chip, a method for forming the bump, and the bump It is to provide a semiconductor unit (mounting body).

【００２２】[0022]

【課題を解決するための手段】本発明によるバンプの形
成方法は、回路基板の表面の端子電極と、前記回路基板
の表面上にフェイスダウン状態で実装される半導体装置
の電極パッドとを電気的に接続するためのバンプを形成
する方法であって、前記バンプを前記半導体装置の電極
パッド上に形成する工程ａと、前記バンプの先端部に湾
曲面を形成する工程ｂとを含むことを特徴とする。A bump forming method according to the present invention electrically connects a terminal electrode on a surface of a circuit board and an electrode pad of a semiconductor device mounted on the surface of the circuit board in a face-down state. A method for forming a bump for connecting to a semiconductor device, the method comprising: a step of forming the bump on an electrode pad of the semiconductor device; and a step b of forming a curved surface at a tip portion of the bump. And

【００２３】本発明による半導体ユニットは、表面に端
子電極を有する回路基板と、前記回路基板の表面上にフ
ェイスダウン状態で実装された半導体装置とを有する半
導体ユニットであって、前記半導体装置は、電極パッド
と、前記電極パッドと前記端子電極とを電気的に接続す
るためのバンプとを有し、前記バンプの先端部に湾曲面
が形成され、前記バンプの先端部と前記端子電極との間
に接合層が形成されていることを特徴とする。A semiconductor unit according to the present invention is a semiconductor unit having a circuit board having a terminal electrode on its surface and a semiconductor device mounted on the surface of the circuit board in a face-down state, wherein the semiconductor device comprises: An electrode pad and a bump for electrically connecting the electrode pad and the terminal electrode are formed, and a curved surface is formed at a tip end portion of the bump, and between the tip end portion of the bump and the terminal electrode. Is characterized in that a bonding layer is formed.

【００２４】[0024]

【作用】本発明は、バンプの先端部に凹型状の湾曲面を
形成することによって、バンプの湾曲面が端子電極の曲
面に面で接続するため、バンプと端子電極との接続距離
が短縮されることになり、電気的導通が向上する。ま
た、バルクが安定に形成されるため、接着強度が増強さ
れ、信頼性が極めて向上する。According to the present invention, since the curved surface of the bump is connected to the curved surface of the terminal electrode by forming the concave curved surface at the tip of the bump, the connection distance between the bump and the terminal electrode is shortened. As a result, electrical continuity is improved. Further, since the bulk is stably formed, the adhesive strength is enhanced and the reliability is extremely improved.

【００２５】[0025]

【実施例】以下に、本発明の各実施例を図面に基づき説
明する。Embodiments of the present invention will be described below with reference to the drawings.

【００２６】（実施例１）図１（ａ）は本発明の第１の
実施例におけるワイヤボンディング用のキャピラリ−の
先端部の概略断面図である。図１（ｂ）は、キャピラリ
−の先端部の形状をより詳細に示している。(Embodiment 1) FIG. 1A is a schematic cross-sectional view of a tip portion of a wire bonding capillary according to a first embodiment of the present invention. FIG. 1 (b) shows the shape of the tip of the capillary in more detail.

【００２７】図１（ａ）に示されるように、円筒形のキ
ャピラリ−１は、その先端部の外周部に設けられた、レ
ベリング部材である突出部３を有している。キャピラリ
−１は、セラミックあるいは人工ルビ−により作られて
いる。突出部３の下端面（レベリング面）１５は、凸型
状の湾曲面を持っており、キャピラリ−１の先端のフェ
イス１１からの高さが所定の値ｄであるように設けられ
ている。下端面１５の大きさは、ボンディングピッチお
よび成形すべきバンプの先端径の大きさに応じて設定す
ることができる。また、キャピラリ−１の先端部の外側
は、ボンディングする間隔とボンディング後の金属ワイ
ヤ（あるいはバンプ）の形状および大きさとを考慮し、
１０〜３０°程度の角度αがつけられている。As shown in FIG. 1 (a), the cylindrical capillary-1 has a protruding portion 3 which is a leveling member and is provided on the outer peripheral portion of the distal end portion thereof. Capillary-1 is made of ceramic or artificial ruby. The lower end surface (leveling surface) 15 of the protruding portion 3 has a convex curved surface, and is provided so that the height of the tip of the capillary -1 from the face 11 is a predetermined value d. The size of the lower end surface 15 can be set according to the bonding pitch and the size of the tip diameter of the bump to be formed. In addition, the outside of the tip of the capillary-1 has a bonding interval and the shape and size of the metal wire (or bump) after bonding,
The angle α is about 10 to 30 °.

【００２８】図１（ｂ）に示されるように、２５μｍφ
程度の金属ワイヤを用いる場合、キャピラリ−の先端部
の形状は、ホ−ル径：３８μｍ、チップ径：２０３μ
ｍ、およびチャンファ−径：７４μｍである。As shown in FIG. 1B, 25 μmφ
When using a metal wire of a certain size, the shape of the tip of the capillary is as follows: hole diameter: 38 μm, tip diameter: 203 μm
m and chamfer diameter: 74 μm.

【００２９】図２は本発明の第１の実施例における半導
体装置のバンプの正面図であり、これは半導体装置の一
部分における複数の電気的接続点のうちの１つを示して
いる。図２に示すように、半導体装置（以下、ＩＣ基板
という）６の上に突起電極（以下、バンプという）２７
が形成されている。このバンプ２７の先端部には凹型状
の湾曲面２４が設けられている。本実施例において、バ
ンプ２７は、図２に示されるように第１のバンプ２７の
上にそれより小さい第２のバンプ２７′を有しており、
２段になった突起状の形状をしている（以下、単にバン
プ２７という）。FIG. 2 is a front view of the bump of the semiconductor device according to the first embodiment of the present invention, which shows one of a plurality of electrical connection points in a part of the semiconductor device. As shown in FIG. 2, protruding electrodes (hereinafter referred to as bumps) 27 are provided on the semiconductor device (hereinafter referred to as IC substrate) 6.
Are formed. A concave curved surface 24 is provided at the tip of the bump 27. In this embodiment, the bump 27 has a smaller second bump 27 'on the first bump 27 as shown in FIG.
It has a projecting shape with two steps (hereinafter simply referred to as bump 27).

【００３０】図３（ａ）〜（ｆ）は本発明の第１の実施
例におけるボ−ルボンディング法によって、ＩＣチップ
６の上に形成された電極パッド１３の上に、キャピラリ
−１を用いて２段バンプを形成する方法の概略を示して
いる。3 (a) to 3 (f) use the capillary-1 on the electrode pad 13 formed on the IC chip 6 by the ball bonding method in the first embodiment of the present invention. 2 shows an outline of a method for forming a two-stage bump.

【００３１】図３（ａ）に示すように、キャピラリ−１
のワイヤ導出孔２に２５μｍφの金属ワイヤ４を通す。
そして、金属ワイヤ４の先端に、熱エネルギ−を与える
ことにより、金属ワイヤ４の径の約２〜３倍の径を有す
るボ−ル５を形成する。As shown in FIG. 3 (a), the capillary-1
The metal wire 4 having a diameter of 25 μm is passed through the wire lead-out hole 2 in FIG.
Then, by applying heat energy to the tip of the metal wire 4, the ball 5 having a diameter of about 2 to 3 times the diameter of the metal wire 4 is formed.

【００３２】次に、図３（ｂ）に示すように、キャピラ
リ−１を降下させることにより、金属ワイヤ４の先端に
形成されたボ−ル５を、ＩＣチップ６の電極パッド１３
に当接させる。熱圧着の方法や超音波振動を与えること
によってボ−ル５を電極パッド１３に固着させ、２段バ
ンプの底部９を形成する。Next, as shown in FIG. 3B, the capillary 1 is lowered to move the ball 5 formed at the tip of the metal wire 4 to the electrode pad 13 of the IC chip 6.
Contact. The ball 5 is fixed to the electrode pad 13 by thermocompression bonding or by applying ultrasonic vibration to form the bottom 9 of the two-step bump.

【００３３】そして、図３（ｃ）に示すように、２段バ
ンプの底部９と、キャピラリ−１のワイヤ導出孔２に通
された金属ワイヤ４とがつながった状態のまま、キャピ
ラリ−１をＩＣチップ６に対してル−プ状に移動させ
る。キャピラリ−１は、まず、２段バンプの底部９上方
に垂直に上昇してからル−プ状軌道を描くように移動す
る。Then, as shown in FIG. 3 (c), the capillary-1 is held with the bottom 9 of the two-stage bump and the metal wire 4 passed through the wire lead-out hole 2 of the capillary-1 being connected. The IC chip 6 is moved in a loop. The capillary-1 first rises vertically above the bottom 9 of the two-stage bump and then moves so as to draw a loop-shaped orbit.

【００３４】図３（ｄ）に示されるように、キャピラリ
−１がＩＣチップ６に対してル−プ状に運動することに
より、底部９の上には金属ワイヤ４がリング状または逆
Ｕ字状に形成される。As shown in FIG. 3D, the capillary-1 moves in a loop shape with respect to the IC chip 6, so that the metal wire 4 is ring-shaped or inverted U-shaped on the bottom portion 9. Formed into a shape.

【００３５】その後、キャピラリ−１のエッジ部分１２
が２段バンプの底部９の外周に位置するようにキャピラ
リ−１を移動させ、垂直に下降しながらエッジ部分１２
によって金属ワイヤ４を切断する。キャピラリ−１はそ
のまま降下を続け、キャピラリ−１の外周部に設けられ
た突出部分３の下端面１５によって２段バンプを押圧整
形する。このとき、キャピラリ−１は、そのフェイス１
１が電極パッド１３に当接するまで下降する（図３
（ｅ）参照）。After that, the edge portion 12 of the capillary-1
Is moved to the outer periphery of the bottom 9 of the two-step bump, and the edge portion 12 is moved vertically downward.
The metal wire 4 is cut by. The capillary -1 continues descending as it is, and the lower bump 15 of the projecting portion 3 provided on the outer peripheral portion of the capillary -1 presses and shapes the two-step bump. At this time, the capillary-1 is the face 1
1 descends until it contacts the electrode pad 13 (see FIG. 3).
(E)).

【００３６】また、図３（ｆ）に示されるように、正面
から見たときにも湾曲面が形成されているようにキャピ
ラリの下端面１５が作られていてもよく、湾曲面の形成
される方向は問わない。Further, as shown in FIG. 3 (f), the lower end surface 15 of the capillary may be formed so that the curved surface is formed even when viewed from the front, and the curved surface is formed. It does not matter which way you go.

【００３７】次に図４は本発明の第１の実施例における
半導体装置を回路基板上に実装した半導体ユニットの一
部断面図である。図４に示すように、上記の工程で得ら
れた半導体装置（ＩＣ基板）６のバンプの先端部の湾曲
面２４に、接合層としての導電性接着剤２５を転写法や
印刷法によって塗布する。本実施例において、２段突起
状のバンプを用いることにより、必要量以上の導電性接
着剤２５がバンプ先端部に付着するのを防ぎ、適量の導
電性接着剤２５を塗布することができる。しかし、バン
プは、先端部に湾曲面２４を有していれば、その形状は
特に制限されるものではない。Next, FIG. 4 is a partial sectional view of a semiconductor unit in which the semiconductor device according to the first embodiment of the present invention is mounted on a circuit board. As shown in FIG. 4, a conductive adhesive 25 as a bonding layer is applied to the curved surface 24 at the tip of the bump of the semiconductor device (IC substrate) 6 obtained in the above process by a transfer method or a printing method. . In the present embodiment, by using the bumps having the two-step projection shape, it is possible to prevent an excessive amount of the conductive adhesive 25 from adhering to the tip of the bump and to apply an appropriate amount of the conductive adhesive 25. However, the shape of the bump is not particularly limited as long as it has the curved surface 24 at the tip.

【００３８】このことによって、接合層の厚みを最も薄
く均一なものとでき、接続部の接続抵抗が低く、信頼性
の高い電気的接続と接着を実現できる。As a result, the thickness of the bonding layer can be made the thinnest and uniform, the connection resistance of the connection portion is low, and highly reliable electrical connection and adhesion can be realized.

【００３９】（実施例２）図５（ａ）〜（ｃ）は本発明
の第２の実施例における、ＩＣチップ６の上の電極パッ
ド１３の上に形成されたバンプの先端部に、先端部に凸
型状の湾曲面４１をもった冶具を用いて凹型状の湾曲面
２４を形成する方法の概略を示している。(Embodiment 2) FIGS. 5A to 5C show tips of bumps formed on the electrode pads 13 on the IC chip 6 in the second embodiment of the present invention. The outline of the method of forming the concave curved surface 24 by using a jig having a convex curved surface 41 in the portion is shown.

【００４０】図５（ａ）はＩＣチップ６の上の電極パッ
ド１３の上に形成された２段バンプである。このバンプ
の先端部を凸型状の湾曲面４１をもった冶具を用いて押
圧することによって、バンプの先端部に凹型状の湾曲面
２４を形成する。このとき、図５（ｂ）、（ｃ）に示す
ように、湾曲面の形成される方向は問わない。FIG. 5A shows a two-step bump formed on the electrode pad 13 on the IC chip 6. A concave curved surface 24 is formed at the tip of the bump by pressing the tip of the bump with a jig having a convex curved surface 41. At this time, as shown in FIGS. 5B and 5C, the direction in which the curved surface is formed does not matter.

【００４１】この形成方法を用いても、図４に示す半導
体ユニットが得られる。 （実施例３）図６は半田メッキバンプを用いた場合にお
ける本発明の第３の実施例におけるバンプの先端部に凹
型状の湾曲面をもつ半導体装置の断面図（ａ）と、半導
体装置を回路基板上に実装した半導体ユニットの一部断
面図（ｂ）である。The semiconductor unit shown in FIG. 4 can also be obtained by using this forming method. (Embodiment 3) FIG. 6 is a sectional view (a) of a semiconductor device having a concave curved surface at the tip of the bump in the third embodiment of the present invention in the case of using a solder plating bump, and FIG. It is a partial cross section figure (b) of the semiconductor unit mounted on the circuit board.

【００４２】（実施例４）図７は１段突起状のバンプを
用いた場合における本発明の第４の実施例におけるバン
プの先端部に凹型状の湾曲面をもつ半導体装置の断面図
（ａ）と、半導体装置を回路基板上に実装した半導体ユ
ニットの一部断面図（ｂ）である。(Embodiment 4) FIG. 7 is a sectional view (a) of a semiconductor device having a concave curved surface at the tip of the bump in the fourth embodiment of the present invention when a bump having a one-step protrusion is used. ) And a partial sectional view (b) of a semiconductor unit in which a semiconductor device is mounted on a circuit board.

【００４３】（実施例５）図８は実施例１，２で得られ
た半導体装置を異方性導電材を界して回路基板上に実装
した半導体ユニットの一部断面図である。(Embodiment 5) FIG. 8 is a partial cross-sectional view of a semiconductor unit in which the semiconductor devices obtained in Embodiments 1 and 2 are mounted on a circuit board with an anisotropic conductive material in between.

【００４４】（実施例６）図９は実施例１，２で得られ
た半導体装置を、半導体装置と回路基板の間隙以上の厚
みをもった異方性導電材を界して回路基板上に実装した
半導体ユニットの一部断面図である。(Embodiment 6) FIG. 9 shows the semiconductor device obtained in Embodiments 1 and 2 on the circuit board with an anisotropic conductive material having a thickness larger than the gap between the semiconductor device and the circuit board. It is a partial cross section figure of the mounted semiconductor unit.

【００４５】[0045]

【発明の効果】以上説明したように、本発明によれば、
特殊なバンプの構造や製造方法に限られることなく、通
常のボ−ルボンディング法やメッキ法等を用いて形成さ
れたバンプの先端部に、容易に湾曲面を形成することが
できるため、実用上において極めて汎用性が高い。As described above, according to the present invention,
Not limited to a special bump structure or manufacturing method, a curved surface can be easily formed at the tip of the bump formed by using an ordinary ball bonding method or a plating method. Very versatile above.

【００４６】さらに、本発明により、半導体装置のバン
プの先端部に湾曲面を形成することにより、バンプと回
路基板上の端子電極との境界面間の接合距離を短縮し、
電気的導通性を向上させることができる。これによって
接着強度を増し、さらに、より確実で信頼性の高い電気
的接続を得ることができる。Furthermore, according to the present invention, by forming a curved surface at the tip of the bump of the semiconductor device, the bonding distance between the boundary surface between the bump and the terminal electrode on the circuit board is shortened,
The electrical conductivity can be improved. As a result, the adhesive strength is increased, and more reliable and reliable electrical connection can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図１】（ａ）は本発明の第１の実施例におけるワイヤ
ボンディング装置用のキャピラリ−の先端部の概略断面
図 （ｂ）はキャピラリ−の先端部の形状の詳細図1A is a schematic cross-sectional view of the tip of a capillary for a wire bonding apparatus in a first embodiment of the present invention, FIG. 1B is a detailed view of the shape of the tip of the capillary.

【図２】本発明の第１の実施例における半導体装置の２
段突起状のバンプの正面図FIG. 2 shows a semiconductor device 2 according to the first embodiment of the present invention.
Front view of stepped bump

【図３】本発明によるキャピラリ−を用いて２段バンプ
を形成する方法の概略を示す工程図FIG. 3 is a process diagram showing an outline of a method for forming a two-step bump using a capillary according to the present invention.

【図４】本発明によって形成された２段バンプを有する
半導体装置を、回路基板上に導電性接着剤によって実装
された半導体ユニットを示す断側面図FIG. 4 is a sectional side view showing a semiconductor unit in which a semiconductor device having two-stage bumps formed according to the present invention is mounted on a circuit board with a conductive adhesive.

【図５】本発明の第２の実施例における、凸型状の治具
を用いてバンプの先端部に凹型状の湾曲面を形成する方
法の概略図FIG. 5 is a schematic view of a method of forming a concave curved surface at the tip of a bump using a convex jig in the second embodiment of the present invention.

【図６】（ａ）および（ｂ）は、本発明の第３の実施例
におけるメッキバンプを有する半導体装置を、回路基板
上に導電性接着剤によって接着する前の状態および実装
された半導体ユニットを示す断側面図6 (a) and 6 (b) are a state before a semiconductor device having a plating bump according to a third embodiment of the present invention is attached to a circuit board with a conductive adhesive and a mounted semiconductor unit. Side view showing

【図７】（ａ）および（ｂ）は、本発明の第４の実施例
における１段バンプを有する半導体装置を、回路基板上
に導電性接着剤によって接着する前の状態および実装さ
れた半導体ユニットを示す断側面図7 (a) and 7 (b) are a state before a semiconductor device having a one-step bump according to a fourth embodiment of the present invention is attached to a circuit board by a conductive adhesive and a mounted semiconductor. Side view showing unit

【図８】本発明の第１，２の実施例における２段バンプ
を有する半導体装置を、回路基板上に異方性導電材によ
って実装した半導体ユニットを示す断側面図FIG. 8 is a sectional side view showing a semiconductor unit in which a semiconductor device having two-stage bumps according to the first and second embodiments of the present invention is mounted on a circuit board with an anisotropic conductive material.

【図９】本発明の第１，２の実施例における２段バンプ
を有する半導体装置を、回路基板上に異方性導電材によ
って実装した図８と異なる半導体ユニットを示す断側面
図9 is a sectional side view showing a semiconductor unit different from that of FIG. 8 in which a semiconductor device having two-stage bumps according to the first and second embodiments of the present invention is mounted on a circuit board by an anisotropic conductive material.

【図１０】（ａ）は従来のワイヤボンディング装置用の
キャピラリ−の先端部の概略断面図 （ｂ）は従来のキャピラリ−の先端部の形状の詳細図FIG. 10A is a schematic cross-sectional view of the tip portion of a capillary for a conventional wire bonding apparatus, and FIG. 10B is a detailed view of the shape of the tip portion of a conventional capillary.

【図１１】従来のキャピラリ−を用いたボ−ルボンディ
ング法によって２段バンプを形成する方法の概略を示す
工程図FIG. 11 is a process diagram showing an outline of a method of forming a two-stage bump by a ball bonding method using a conventional capillary.

【図１２】従来のボ−ルボンディング法によってレベリ
ングされたバンプの典型的な形状を示す概略断面図FIG. 12 is a schematic cross-sectional view showing a typical shape of bumps leveled by a conventional ball bonding method.

【図１３】（ａ）は従来の半導体装置の半田バンプの概
略断面図 （ｂ）は従来の半導体ユニットの概略断面図13A is a schematic cross-sectional view of a solder bump of a conventional semiconductor device, and FIG. 13B is a schematic cross-sectional view of a conventional semiconductor unit.

【図１４】従来の導電性接着剤を用いた半導体ユニット
の概略断面図FIG. 14 is a schematic sectional view of a semiconductor unit using a conventional conductive adhesive.

【符号の説明】[Explanation of symbols]

１ キャピラリ− ２ ワイヤ導出孔 ３ 突出部 ４ 金属ワイヤ ５ ボ−ル ６ ＩＣチップ（半導体装置） ７ バンプ ８ バンプの頂部 ９ バンプの底部 １１ キャピラリ−のフェイス １２ キャピラリ−のエッジ １３ 電極パッド １５ 突出部の下端面 ２４ バンプの先端部 ２５ 導電性接着剤 ２７，２７′ 突起電極（バンプ） ２８ 入出力端子電極 ２９ 回路基板 ４１ 凸型治具 ４２ 凸型治具の突出部の下端面 ６０ 電気的接続接点（半田バンプ） ６１ 金属膜 ６３ 電極パッド ６６ ＩＣチップ（半導体装置） ６８ 入出力端子電極 ６９ 回路基板 ７０ 突起電極（バンプ） ７３ 電極パッド ７６ ＩＣチップ（半導体装置） ７８ 入出力端子電極 ７９ 回路基板 1 Capillary 2 Wire Derivation Hole 3 Protrusion 4 Metal Wire 5 Ball 6 IC Chip (Semiconductor Device) 7 Bump 8 Top of Bump 9 Bottom of Bump 11 Capillary Face 12 Capillary Edge 13 Electrode Pad 15 Protrusion Bottom surface 24 of bump 24 Tip of conductive adhesive 27, 27 'Projection electrode (bump) 28 Input / output terminal electrode 29 Circuit board 41 Convex jig 42 Lower end surface of projection of convex jig 60 Electrical connection Contact (solder bump) 61 Metal film 63 Electrode pad 66 IC chip (semiconductor device) 68 Input / output terminal electrode 69 Circuit board 70 Projection electrode (bump) 73 Electrode pad 76 IC chip (semiconductor device) 78 Input / output terminal electrode 79 Circuit board

Claims (12)

【特許請求の範囲】[Claims] 【請求項１】半導体装置の電極パッド上にバンプを形成
するためのボ−ルボンディング用のキャピラリ−であっ
て、前記キャピラリ−は、金属ワイヤのボ−ル状の先端
部を電極パッドに対して押圧し、前記ボ−ル状先端部を
前記電極パッドに圧着させる押圧部材と、前記押圧部材
に設けられた、前記金属ワイヤを供給する導出孔と、前
記電極パッド上に形成されたバンプの先端部に凹型状に
湾曲した面を設けるためのレベリング部材とを備えたワ
イヤボンディング装置用のキャピラリ−。1. A ball bonding capillary for forming a bump on an electrode pad of a semiconductor device, wherein the capillary has a ball-shaped tip portion of a metal wire with respect to the electrode pad. Of the bumps formed on the electrode pad, a pressing member that presses the ball-shaped tip portion against the electrode pad to press it, and a lead-out hole that is provided in the pressing member for supplying the metal wire. A capillary for a wire bonding apparatus, comprising a leveling member for providing a concavely curved surface at a tip portion. 【請求項２】押圧部材は、キャピラリ−の下端面（第１
の下端面）を含んでおり、レベリング部材は、バンプを
押圧する第２の下端面を有し、前記第２の下端面が凸状
の湾曲面を有している請求項１に記載のワイヤボンディ
ング装置用のキャピラリ−。2. The pressing member is a lower end surface of the capillary (first
The wire according to claim 1, wherein the leveling member has a second lower end surface that presses the bump, and the second lower end surface has a convex curved surface. Capillary for bonding equipment. 【請求項３】回路基板の表面の端子電極と、前記回路基
板の表面上にフェイスダウン状態で実装される半導体装
置の電極パッドとを電気的に接続するためのバンプであ
って、前記半導体装置の電極パッド上に形成された、先
端部に凹型状に湾曲した面を有するバンプ。3. A bump for electrically connecting a terminal electrode on the surface of a circuit board and an electrode pad of a semiconductor device mounted face down on the surface of the circuit board, the bump comprising the semiconductor device. A bump having a concavely curved surface at the tip formed on the electrode pad of. 【請求項４】ワイヤボンディング装置を用いて、回路基
板の表面の端子電極と、前記回路基板の表面上にフェイ
スダウン状態で実装される半導体装置の電極パッドとを
電気的に接続するためのバンプを形成する方法であっ
て、前記バンプを前記半導体装置の電極パッド上に形成
する工程ａと、金属ワイヤを切除すると同時に、前記バ
ンプの先端部に凹型状に湾曲面を形成する工程ｂとを含
むことを特徴とする湾曲面を有するバンプの形成方法。4. A bump for electrically connecting a terminal electrode on the surface of a circuit board and an electrode pad of a semiconductor device mounted face down on the surface of the circuit board by using a wire bonding device. A step of forming the bump on the electrode pad of the semiconductor device, and a step b of cutting the metal wire and simultaneously forming a concave curved surface at the tip of the bump. A method of forming a bump having a curved surface, comprising: 【請求項５】工程ｂは、バンプの先端部形状を揃えるた
めに前記バンプをレベリングする工程を含むことを特徴
とする請求項４記載の湾曲面を有するバンプの形成方
法。5. The method of forming a bump having a curved surface according to claim 4, wherein the step b includes a step of leveling the bump so as to make the shape of the tip of the bump uniform. 【請求項６】バンプは、Ａｕ，Ｃｕ，Ａｌ，半田または
これらのいずれかを含む合金から形成されていることを
特徴とする請求項４記載の湾曲面を有するバンプの形成
方法。6. The method of forming a bump having a curved surface according to claim 4, wherein the bump is formed of Au, Cu, Al, solder or an alloy containing any of these. 【請求項７】工程ａは、ボ−ルボンディング法によって
バンプを電極パッド上に形成することを特徴とする請求
項４記載の湾曲面を有するバンプの形成方法。7. The method of forming a bump having a curved surface according to claim 4, wherein in step a, the bump is formed on the electrode pad by a ball bonding method. 【請求項８】回路基板の表面の端子電極と、前記回路基
板の表面上にフェイスダウン状態で実装される半導体装
置の電極パッドとを電気的に接続するためのバンプを形
成する方法であって、前記バンプを前記半導体装置の電
極パッド上に形成する工程と、前記バンプの先端部に凹
型状の湾曲面を凸型状の湾曲面をもつ冶具を用いて形成
する工程からなることを特徴とする湾曲面を有するバン
プの形成方法。8. A method of forming a bump for electrically connecting a terminal electrode on a surface of a circuit board and an electrode pad of a semiconductor device mounted face down on the surface of the circuit board. And a step of forming the bump on an electrode pad of the semiconductor device, and a step of forming a concave curved surface at a tip end portion of the bump using a jig having a convex curved surface. For forming a bump having a curved surface to be formed. 【請求項９】バンプは、メッキ法、ワイヤボンディング
法などによって電極パッド上に形成されることを特徴と
する請求項８記載の湾曲面を有するバンプの形成方法。9. The method of forming a bump having a curved surface according to claim 8, wherein the bump is formed on the electrode pad by a plating method, a wire bonding method, or the like. 【請求項１０】表面に端子電極を有する回路基板と、前
記回路基板の表面上にフェイスダウン状態で実装された
半導体装置とを有する半導体ユニットであって、前記半
導体装置は、電極パッドと、前記電極パッドと前記端子
電極とを電気的に接続するためのバンプとを有し、前記
バンプの先端部に湾曲面が形成され、前記バンプの先端
部と前記端子電極との間に接合層が形成されていること
を特徴とする半導体ユニット。10. A semiconductor unit comprising a circuit board having a terminal electrode on a surface thereof, and a semiconductor device mounted on the surface of the circuit board in a face-down state, wherein the semiconductor device comprises an electrode pad and the semiconductor device. A bump for electrically connecting the electrode pad and the terminal electrode is formed, a curved surface is formed at the tip of the bump, and a bonding layer is formed between the tip of the bump and the terminal electrode. The semiconductor unit is characterized by being. 【請求項１１】接合層は、導電性接着剤から形成される
ことを特徴とする請求項１０記載の半導体ユニット。11. The semiconductor unit according to claim 10, wherein the bonding layer is formed of a conductive adhesive. 【請求項１２】接合層は、異方性導電材から形成される
ことを特徴とする請求項１０記載の半導体ユニット。12. The semiconductor unit according to claim 10, wherein the bonding layer is made of an anisotropic conductive material.
JP6327955A 1994-12-28 1994-12-28 Method for capillary and bump forming of wire bonding apparatus Pending JPH08186117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6327955A JPH08186117A (en) 1994-12-28 1994-12-28 Method for capillary and bump forming of wire bonding apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6327955A JPH08186117A (en) 1994-12-28 1994-12-28 Method for capillary and bump forming of wire bonding apparatus

Publications (1)

Publication Number Publication Date
JPH08186117A true JPH08186117A (en) 1996-07-16

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP6327955A Pending JPH08186117A (en) 1994-12-28 1994-12-28 Method for capillary and bump forming of wire bonding apparatus

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6774494B2 (en) * 2001-03-22 2004-08-10 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
WO2008048262A1 (en) * 2006-10-18 2008-04-24 Kulicke And Soffa Industries, Inc. Improved conductive bumps, wire loops including the improved conductive bumps, and methods of forming the same
JP2014093318A (en) * 2012-10-31 2014-05-19 Dowa Electronics Materials Co Ltd Semiconductor element and manufacturing method of the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6774494B2 (en) * 2001-03-22 2004-08-10 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
WO2008048262A1 (en) * 2006-10-18 2008-04-24 Kulicke And Soffa Industries, Inc. Improved conductive bumps, wire loops including the improved conductive bumps, and methods of forming the same
JP2014093318A (en) * 2012-10-31 2014-05-19 Dowa Electronics Materials Co Ltd Semiconductor element and manufacturing method of the same

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