JP3446608B2 - Semiconductor unit - Google Patents
Semiconductor unitInfo
- Publication number
- JP3446608B2 JP3446608B2 JP14899198A JP14899198A JP3446608B2 JP 3446608 B2 JP3446608 B2 JP 3446608B2 JP 14899198 A JP14899198 A JP 14899198A JP 14899198 A JP14899198 A JP 14899198A JP 3446608 B2 JP3446608 B2 JP 3446608B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- semiconductor device
- electrode
- circuit board
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置と回路
基板とが電気的および機械的に接続された半導体ユニッ
トに関するものであり、特に、半導体装置と回路基板と
をフェースダウンで接続したフリップチップ実装の半導
体ユニットに適用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor unit in which a semiconductor device and a circuit board are electrically and mechanically connected, and more particularly to a flip chip in which the semiconductor device and the circuit board are connected face down. The present invention relates to a technique effectively applied to a mounted semiconductor unit.
【０００２】[0002]
【従来の技術】半導体装置と回路基板とを直接フェース
ダウンで電気的および機械的に接続するフリップチップ
実装は、樹脂等で保護成形した従来のパッケージに比較
して実装面積を大幅に縮小することができるという利点
を持ち、注目を集めている技術である。2. Description of the Related Art Flip-chip mounting, in which a semiconductor device and a circuit board are directly face-down electrically and mechanically connected, requires a large reduction in mounting area as compared with a conventional package formed by protection molding with resin or the like. This technology has the advantage of being able to perform and is attracting attention.
【０００３】以下に、従来の半導体装置の実装技術につ
いて説明する。ここで、図８は従来の第１の技術におけ
る半導体装置と回路基板の接合状態の要部を示す断面
図、図９は従来の第２の技術における半導体装置と回路
基板の接合状態の要部を示す断面図、図１０は従来の技
術における半導体装置と回路基板の接合状態の要部を示
す断面図である。A conventional mounting technique for a semiconductor device will be described below. Here, FIG. 8 is a cross-sectional view showing a main part of a state where the semiconductor device and the circuit board are joined in the first conventional technique, and FIG. 9 is a main part of a state where the semiconductor device and the circuit board are joined in the second conventional technique. FIG. 10 is a cross-sectional view showing a main part of a bonded state of a semiconductor device and a circuit board in a conventional technique.
【０００４】図８に示すように、従来から、アルミ電極
１１上に突起電極１０が形成された半導体装置９を回路
基板２９に電気的および機械的に接続する第１の技術と
して、両者を絶縁性接着樹脂２７によって固定し、半導
体装置１の突起電極１０と回路基板２９上の入出力電極
２８との機械的な接触のみで接続する半導体ユニットが
知られている。As shown in FIG. 8 , conventionally, as a first technique for electrically and mechanically connecting a semiconductor device 9 having a protruding electrode 10 formed on an aluminum electrode 11 to a circuit board 29, the two are insulated from each other. There is known a semiconductor unit that is fixed by a conductive adhesive resin 27 and is connected only by mechanical contact between the protruding electrode 10 of the semiconductor device 1 and the input / output electrode 28 on the circuit board 29.
【０００５】この接続技術は、図８に示すように、まず
入出力電極２８を有する回路基板２９上に絶縁性接着樹
脂２７を貼り付ける。次いで、ボンディング装置（図示
せず）あるいはめっき装置（図示せず）によってアルミ
電極１１上に突起電極１０が形成された半導体装置９を
回路基板２９上に位置決めして重ね合わせる。そして、
加熱と加圧とを同時に行い、突起電極１０と入出力電極
２８との間に絶縁性接着樹脂２７が存在しないように十
分に荷重を印加して絶縁性接着樹脂２７を硬化させる。
このようにすることで、突起電極１０と入出力電極２８
とが直接接触して両者が電気的に接続されることにな
る。In this connection technique, as shown in FIG. 8 , an insulating adhesive resin 27 is first attached onto a circuit board 29 having input / output electrodes 28. Next, the semiconductor device 9 in which the bump electrode 10 is formed on the aluminum electrode 11 is positioned and superposed on the circuit board 29 by a bonding device (not shown) or a plating device (not shown). And
Heating and pressurization are simultaneously performed, and a sufficient load is applied so that the insulating adhesive resin 27 does not exist between the protruding electrode 10 and the input / output electrode 28, and the insulating adhesive resin 27 is cured.
By doing so, the protruding electrode 10 and the input / output electrode 28
And will be in direct contact with each other and will be electrically connected.
【０００６】また、アルミ電極１１上に突起電極１０が
形成された半導体装置９を回路基板２９に電気的および
機械的に接続する第２の技術として、異方導電性フィル
ムを使用するものが知られている。Further, as a second technique for electrically and mechanically connecting the semiconductor device 9 in which the protruding electrode 10 is formed on the aluminum electrode 11 to the circuit board 29, there is known one using an anisotropic conductive film. Has been.
【０００７】この接続技術は、図９に示すように、まず
絶縁性接着樹脂５に対して絶縁性を損なわない程度に導
電性粒子６が分散されたものからなる異方導電性フィル
ム７を用意し、これを入出力電極２８を有する回路基板
２９の上に貼り付ける。In this connection technique, as shown in FIG. 9 , first, an anisotropic conductive film 7 made of conductive particles 6 dispersed to an insulating adhesive resin 5 to the extent that the insulating property is not impaired is prepared. Then, this is attached onto the circuit board 29 having the input / output electrodes 28.
【０００８】ここで、導電性粒子６はＮｉ粒子やＡｇ粒
子、あるいは樹脂ボールに金属薄膜と絶縁膜をコートし
た粒子等が用いられ、その直径は５μｍ程度であり、１
００μｍ3に２５個程度が混入されている。Here, as the conductive particles 6, Ni particles, Ag particles, particles obtained by coating a resin ball with a metal thin film and an insulating film, or the like are used, and the diameter thereof is about 5 μm.
About 25 are mixed in 00 μm 3 .
【０００９】次いで、ボンディング装置（図示せず）あ
るいはめっき装置（図示せず）によって半導体装置９の
アルミ電極１１上に突起電極１０を形成し、突起電極１
０の形成された半導体装置９を回路基板２９上に位置決
めして重ね合わせる。そして、加熱と加圧とを同時に行
い、突起電極１０と入出力電極２８との間の距離を導電
性粒子６の直径以下に維持した状態で絶縁性接着剤５を
硬化させる。このようにすると、突起電極１０と入出力
電極２８との間は、突起電極１０と入出力電極１０との
間の直接接触か、あるいは両者間で押し潰された導電性
粒子６を介しての接触によって電気的に接続されること
になる。Next, a bump electrode 10 is formed on the aluminum electrode 11 of the semiconductor device 9 by a bonding device (not shown) or a plating device (not shown).
The semiconductor device 9 in which the number 0 is formed is positioned and superposed on the circuit board 29. Then, heating and pressurization are performed at the same time, and the insulating adhesive 5 is cured in a state where the distance between the protruding electrode 10 and the input / output electrode 28 is maintained at the diameter of the conductive particles 6 or less. By doing so, the protrusion electrode 10 and the input / output electrode 28 are directly contacted with each other via the protrusion electrode 10 and the input / output electrode 10, or via the conductive particles 6 crushed between the protrusion electrode 10 and the input / output electrode 10. It will be electrically connected by contact.
【００１０】ここで、第１の技術による突起電極１０と
入出力電極２８との間の直接接触は絶縁性接着剤２７に
よる機械的接着保持力で維持されるものであり、突起電
極１０には弾力性がないので、電気的接続を維持するた
めの能動的な加圧力が存在しない。したがって、ヒート
サイクルを加えた場合の電気的接続の信頼性が低くな
る。Here, the direct contact between the protruding electrode 10 and the input / output electrode 28 according to the first technique is maintained by the mechanical adhesive holding force of the insulating adhesive 27. Since it is not elastic, there is no active force to maintain the electrical connection. Therefore, the reliability of electrical connection is reduced when a heat cycle is applied.
【００１１】これに対して、第２の技術による突起電極
１０と入出力電極２４との間で押し潰された導電性粒子
６を介する異方導電性フィルム７による電気的接触に
は、押し潰された導電性粒子６の弾力性による能動的な
加圧力が存在するので、ヒートサイクルを加えた場合の
電気的接続の信頼性を第１の技術よりも高く維持するこ
とができるとされている。On the other hand, the electrical contact by the anisotropic conductive film 7 through the conductive particles 6 crushed between the protruding electrode 10 and the input / output electrode 24 according to the second technique is crushed. Since there is an active pressing force due to the elasticity of the conductive particles 6 that have been generated, it is said that the reliability of the electrical connection when a heat cycle is applied can be maintained higher than that of the first technique. .
【００１２】[0012]
【発明が解決しようとする課題】しかしながら、上記の
実装構造において、半導体装置９に形成された突起電極
１０の高さおよび回路基板２９側の入出力電極２８の高
さはある許容範囲でそれぞれ微妙に異なる。また、機器
への更なる小型化が要求され、半導体装置９の電極間の
ピッチが小さくなると、回路基板２９の入出力電極間の
ピッチも小さくなり、電極幅も小さくなってくる。それ
に伴い、回路基板２９の入出力電極２８のピール強度も
弱くなってくる。However, in the above mounting structure, the height of the bump electrode 10 formed on the semiconductor device 9 and the height of the input / output electrode 28 on the side of the circuit board 29 are delicate within a certain allowable range. Different to Further, when further downsizing of the device is required and the pitch between the electrodes of the semiconductor device 9 becomes smaller, the pitch between the input and output electrodes of the circuit board 29 also becomes smaller and the electrode width also becomes smaller. Along with that, the peel strength of the input / output electrode 28 of the circuit board 29 also becomes weak.
【００１３】この状態で半導体装置９を回路基板２９上
に加熱と加圧をしながら固定すると、図８に示すよう
に、高さの高い突起電極１０に対応した回路基板２９上
の入出力電極２８と、高さの低い突起電極１０に対応し
た回路基板２９上の入出力電極２８とでは、それぞれに
印加される荷重に差が生じる。In this state, when the semiconductor device 9 is fixed on the circuit board 29 while being heated and pressed, as shown in FIG. 8 , the input / output electrodes on the circuit board 29 corresponding to the protruding electrodes 10 having a high height are provided. 28 and the input / output electrode 28 on the circuit board 29 corresponding to the protruding electrode 10 having a low height, a difference occurs in the load applied to each.
【００１４】また、図１０に示すように、高さの高い入
出力電極２８に対応した突起電極１０と、高さの低い入
出力電極２８に対応した突起電極１０とでも、それぞれ
に印加される荷重に差が生じる。Further, as shown in FIG. 10 , the projection electrode 10 corresponding to the high input / output electrode 28 and the projection electrode 10 corresponding to the low input / output electrode 28 are applied to each. There is a difference in load.
【００１５】一般には、高さの低い突起電極１０も十分
に回路基板２９上の入出力電極２８に接触するように、
さらには高さの低い入出力電極２８も十分に突起電極１
０に接触するように荷重を印加して固定するため、高さ
が高い突起電極１０に対応した回路基板２９上の入出力
電極２８部、および高さの高い入出力電極２８部におい
てはかなりの荷重が印加されることになる。すると、入
出力電極２８の先端が回路基板２９からの剥がれたり、
さらには剥がれた入出力電極２８が半導体装置９に接触
する場合が発生する。Generally, the protruding electrode 10 having a low height is sufficiently contacted with the input / output electrode 28 on the circuit board 29.
Further, the input / output electrode 28 having a low height is also sufficiently protruded
Since a load is applied and fixed so as to come into contact with 0, the input / output electrodes 28 on the circuit board 29 corresponding to the protruding electrodes 10 having a high height and the input / output electrodes 28 having a high height are considerably A load will be applied. Then, the tip of the input / output electrode 28 is peeled off from the circuit board 29,
Further, the peeled input / output electrode 28 may come into contact with the semiconductor device 9.
【００１６】そこで、本発明は、半導体装置に形成され
た突起電極と回路基板に形成された入出力電極との電気
的接続不良の発生を抑制することのできる半導体ユニッ
トを提供することを目的とする。Therefore, an object of the present invention is to provide a semiconductor unit capable of suppressing the occurrence of a defective electrical connection between a protruding electrode formed on a semiconductor device and an input / output electrode formed on a circuit board. To do.
【００１７】[0017]
【課題を解決するための手段】この課題を解決するため
に、本発明の半導体ユニットは、複数の突起電極が形成
された半導体装置と、絶縁性および接着性を有する接合
部材と、基幹部の幅よりも先端部の幅の方が広くなった
複数の入出力電極が形成され、入出力電極に対応した突
起電極がこの入出力電極の基幹部を押圧するように半導
体装置が実装される回路基板とからなることを特徴とす
る。In order to solve this problem, a semiconductor unit of the present invention comprises a semiconductor device having a plurality of protruding electrodes, a bonding member having an insulating property and an adhesive property, and a core part. A circuit in which a plurality of input / output electrodes are formed with the width of the tip portion wider than the width, and the semiconductor device is mounted so that the protruding electrode corresponding to the input / output electrode presses the basic portion of the input / output electrode. And a substrate.
【００１８】これにより、半導体装置に形成された突起
電極と回路基板に形成された入出力電極との電気的接続
不良の発生を抑制することができる。As a result, it is possible to suppress the occurrence of a defective electrical connection between the protruding electrode formed on the semiconductor device and the input / output electrode formed on the circuit board.
【００１９】また、本発明の半導体ユニットは、複数の
突起電極が形成された半導体装置と、絶縁性および接着
性を有する接合部材と、基幹部の幅よりも幅の狭いくび
れ部が設けられた複数の入出力電極が形成され、入出力
電極に対応した突起電極がくびれ部の方を先端側にして
この入出力電極の基幹部を押圧するように半導体装置が
実装される回路基板とからなることを特徴とする。Further, the semiconductor unit of the present invention is provided with a semiconductor device in which a plurality of protruding electrodes are formed, a joining member having an insulating property and an adhesive property, and a constricted portion having a width narrower than the width of the base portion. A circuit board on which a plurality of input / output electrodes are formed and a semiconductor device is mounted so that a protruding electrode corresponding to the input / output electrodes presses the basic part of the input / output electrodes with the constricted part on the tip side. It is characterized by
【００２０】これにより、半導体装置に形成された突起
電極と回路基板に形成された入出力電極との電気的接続
不良の発生を抑制することができる。As a result, it is possible to suppress the occurrence of a poor electrical connection between the protruding electrode formed on the semiconductor device and the input / output electrode formed on the circuit board.
【００２１】本発明の半導体ユニットは、複数の突起電
極が形成された半導体装置と、絶縁性および接着性を有
する接合部材と、陥没して内層電極と接続されたホール
部が設けられた複数の入出力電極が形成され、入出力電
極に対応した突起電極がホール部の方を先端側にしてこ
の入出力電極を押圧するように半導体装置が実装される
回路基板とからなることを特徴とする。The semiconductor unit of the present invention is provided with a semiconductor device having a plurality of protruding electrodes, a bonding member having an insulating property and an adhesive property, and a plurality of hole portions which are depressed and connected to the inner layer electrodes. An input / output electrode is formed, and a projecting electrode corresponding to the input / output electrode is composed of a circuit board on which a semiconductor device is mounted so as to press the input / output electrode with the hole portion toward the tip side. .
【００２２】これにより、半導体装置に形成された突起
電極と回路基板に形成された入出力電極との電気的接続
不良の発生を抑制することができる。As a result, it is possible to suppress the occurrence of a defective electrical connection between the protruding electrode formed on the semiconductor device and the input / output electrode formed on the circuit board.
【００２３】本発明の半導体ユニットは、複数の突起電
極が形成された半導体装置と、絶縁性および接着性を有
する接合部材と、平面方向に向かって所定の角度に屈曲
された屈曲部が設けられた複数の入出力電極が形成さ
れ、入出力電極に対応した突起電極が屈曲部の方を先端
側にしてこの入出力電極を押圧するように半導体装置が
実装される回路基板とからなることを特徴とする。The semiconductor unit of the present invention is provided with a semiconductor device having a plurality of protruding electrodes, a joining member having an insulating property and an adhesive property, and a bent portion bent at a predetermined angle in the plane direction. A plurality of input / output electrodes are formed, and the projecting electrodes corresponding to the input / output electrodes are composed of a circuit board on which the semiconductor device is mounted so as to press the input / output electrodes with the bent portion toward the tip side. Characterize.
【００２４】これにより、半導体装置に形成された突起
電極と回路基板に形成された入出力電極との電気的接続
不良の発生を抑制することができる。As a result, it is possible to suppress the occurrence of a defective electrical connection between the protruding electrode formed on the semiconductor device and the input / output electrode formed on the circuit board.
【００２５】[0025]
【００２６】[0026]
【００２７】[0027]
【００２８】[0028]
【００２９】[0029]
【発明の実施の形態】本発明の請求項１に記載の発明
は、複数の突起電極が形成された半導体装置と、絶縁性
および接着性を有する接合部材と、基幹部の幅よりも先
端部の幅の方が広くなった複数の入出力電極が形成さ
れ、入出力電極に対応した突起電極がこの入出力電極の
基幹部を押圧するように半導体装置が実装される回路基
板とからなることを特徴とする半導体ユニットであり、
実装時に入出力電極に印加される荷重が分散されるの
で、半導体装置に形成された突起電極と回路基板に形成
された入出力電極との電気的接続不良の発生を抑制する
ことが可能になるという作用を有する。BEST MODE FOR CARRYING OUT THE INVENTION The invention according to claim 1 of the present invention is a semiconductor device in which a plurality of protruding electrodes are formed, a bonding member having an insulating property and an adhesive property, and a tip end portion rather than a width of a base portion. A plurality of input / output electrodes having a wider width are formed, and the projecting electrodes corresponding to the input / output electrodes are composed of a circuit board on which the semiconductor device is mounted so as to press the basic part of the input / output electrodes. Is a semiconductor unit characterized by
Since the load applied to the input / output electrodes during mounting is dispersed, it is possible to suppress the occurrence of a poor electrical connection between the protruding electrodes formed on the semiconductor device and the input / output electrodes formed on the circuit board. Has the effect of.
【００３０】本発明の請求項２に記載の発明は、複数の
突起電極が形成された半導体装置と、絶縁性および接着
性を有する接合部材と、基幹部の幅よりも幅の狭いくび
れ部が設けられた複数の入出力電極が形成され、入出力
電極に対応した突起電極がくびれ部の方を先端側にして
この入出力電極の基幹部を押圧するように半導体装置が
実装される回路基板とからなることを特徴とする半導体
ユニットであり、実装時に入出力電極に印加される荷重
が分散されるので、半導体装置に形成された突起電極と
回路基板に形成された入出力電極との電気的接続不良の
発生を抑制することが可能になるという作用を有する。According to a second aspect of the present invention, a semiconductor device having a plurality of protruding electrodes formed thereon, a joining member having an insulating property and an adhesive property, and a constricted portion having a width narrower than the width of the base portion are provided. A circuit board on which a plurality of input / output electrodes are provided, and the semiconductor device is mounted so that the protruding electrode corresponding to the input / output electrode presses the basic part of the input / output electrode with the constricted part facing toward the tip side. Since the load applied to the input / output electrodes during mounting is dispersed, the electrical conductivity between the protruding electrodes formed on the semiconductor device and the input / output electrodes formed on the circuit board is improved. This has the effect of making it possible to suppress the occurrence of defective connection.
【００３１】本発明の請求項３に記載の発明は、複数の
突起電極が形成された半導体装置と、絶縁性および接着
性を有する接合部材と、陥没して内層電極と接続された
ホール部が設けられた複数の入出力電極が形成され、入
出力電極に対応した突起電極がホール部の方を先端側に
してこの入出力電極を押圧するように半導体装置が実装
される回路基板とからなることを特徴とする半導体ユニ
ットであり、実装時に入出力電極に印加される荷重が分
散されるので、半導体装置に形成された突起電極と回路
基板に形成された入出力電極との電気的接続不良の発生
を抑制することが可能になるという作用を有する。According to a third aspect of the present invention, a semiconductor device having a plurality of protruding electrodes, a bonding member having an insulating property and an adhesive property, and a hole portion which is depressed and connected to the inner layer electrode are provided. A plurality of input / output electrodes provided are formed, and a projecting electrode corresponding to the input / output electrodes is formed of a circuit board on which a semiconductor device is mounted so as to press the input / output electrodes with the hole portion toward the tip side. This is a semiconductor unit characterized by the fact that the load applied to the input / output electrodes during mounting is dispersed, so that there is a poor electrical connection between the protruding electrodes formed on the semiconductor device and the input / output electrodes formed on the circuit board. It is possible to suppress the occurrence of
【００３２】本発明の請求項４に記載の発明は、複数の
突起電極が形成された半導体装置と、絶縁性および接着
性を有する接合部材と、平面方向に向かって所定の角度
に屈曲された屈曲部が設けられた複数の入出力電極が形
成され、入出力電極に対応した突起電極が屈曲部の方を
先端側にしてこの入出力電極を押圧するように半導体装
置が実装される回路基板とからなることを特徴とする半
導体ユニットであり、実装時に入出力電極に印加される
荷重が分散されるので、半導体装置に形成された突起電
極と回路基板に形成された入出力電極との電気的接続不
良の発生を抑制することが可能になるという作用を有す
る。According to a fourth aspect of the present invention, a semiconductor device having a plurality of protruding electrodes formed thereon, a joining member having an insulating property and an adhesive property, and bent at a predetermined angle in a plane direction are provided. A circuit board on which a plurality of input / output electrodes each having a bent portion are formed, and a semiconductor device is mounted so that a protruding electrode corresponding to the input / output electrode presses the input / output electrode with the bent portion toward the tip side. Since the load applied to the input / output electrodes during mounting is dispersed, the electrical conductivity between the protruding electrodes formed on the semiconductor device and the input / output electrodes formed on the circuit board is improved. This has the effect of making it possible to suppress the occurrence of defective connection.
【００３３】[0033]
【００３４】[0034]
【００３５】以下、本発明の実施の形態について、図１
から図１３を用いて説明する。なお、これらの図面にお
いて同一の部材には同一の符号を付しており、また、重
複した説明は省略されている。FIG. 1 shows an embodiment of the present invention.
From now on, it will be described with reference to FIG. In addition, in these drawings, the same members are denoted by the same reference numerals, and duplicate description is omitted.
【００３６】（実施の形態１）図１は本発明の実施の形
態１における入出力電極の形状の一例を示す平面図、図
２は本発明の実施の形態１における異方導電性フィルム
を回路基板に貼った状態を示す断面図、図３は本発明の
実施の形態１におけるスタッドバンプの形成工程の一部
を示す説明図、図４は本発明の実施の形態１における半
導体装置と回路基板の異方導電性フィルムを使用した接
合工程および接合状態を連続して示す断面図、図５は本
発明の実施の形態１における入出力電極の形状の他の一
例を示す平面図、図６は本発明の実施の形態１における
入出力電極の形状のさらに他の一例を示す断面図、図７
は本発明の実施の形態１における入出力電極の形状のさ
らに他の一例を示す平面図である。(Embodiment 1) FIG. 1 is a plan view showing an example of the shape of an input / output electrode according to Embodiment 1 of the present invention, and FIG. 2 is a circuit diagram of an anisotropic conductive film according to Embodiment 1 of the present invention. FIG. 3 is a cross-sectional view showing a state of being stuck on a substrate, FIG. 3 is an explanatory view showing a part of a stud bump forming process in the first embodiment of the present invention, and FIG. 4 is a semiconductor device and a circuit board in the first embodiment of the present invention. FIG. 5 is a cross-sectional view continuously showing a joining process and a joining state using the anisotropic conductive film of FIG. 5, FIG. 5 is a plan view showing another example of the shape of the input / output electrode in the first embodiment of the present invention, and FIG. FIG. 7 is a sectional view showing still another example of the shape of the input / output electrodes according to the first embodiment of the present invention.
FIG. 6 is a plan view showing still another example of the shape of the input / output electrode according to the first embodiment of the present invention.
【００３７】本実施の形態の半導体ユニットにおいて
は、回路形成部分にエッチングレジストを設けエッチン
グにより回路部を形成するサブトラクティブ法にて回路
基板を形成する際に、半導体装置の実装部分である入出
力電極１の形状を、図１に示すように、二点鎖線で示す
突起電極が実装される基幹部の幅ａより先端部の幅ｂの
方を広くする。In the semiconductor unit of the present embodiment, when a circuit board is formed by a subtractive method in which an etching resist is provided in a circuit forming portion to form a circuit portion by etching, an input / output which is a mounting portion of a semiconductor device is used. As shown in FIG. 1, the shape of the electrode 1 is such that the width b of the tip portion is wider than the width a of the basic portion on which the protruding electrode shown by the chain double-dashed line is mounted.
【００３８】次に、図２に示すように、このような入出
力電極１が形成された回路基板４の上に、絶縁性接着樹
脂５に絶縁性を損なわない程度に少量の導電性粒子６が
分散されたものからなる異方導電性フィルム（接合部
材）７を貼り付ける。なお、本発明において、回路基板
４と半導体装置９との接続には必ずしも異方導電性フィ
ルム７を用いる必要はなく、絶縁性および接着性を有す
る種々の接合部材を用いることが可能である。Next, as shown in FIG. 2, on the circuit board 4 on which the input / output electrodes 1 are formed, a small amount of the conductive particles 6 is provided so that the insulating adhesive resin 5 does not impair the insulating property. An anisotropic conductive film (bonding member) 7 made of a dispersed material is attached. In the present invention, the anisotropic conductive film 7 does not necessarily have to be used for connecting the circuit board 4 and the semiconductor device 9, and various bonding members having insulating properties and adhesive properties can be used.
【００３９】一方、図３に示すように、１５０℃〜３０
０℃に加熱されたステージ８上に真空吸着により半導体
装置９を固定し、公知のワイヤボンディング技術による
最初のボンディング工程と同様の方法で、突起電極（以
下、「スタッドバンプ」という。）１０を半導体装置９
上のアルミ電極１１上に形成する。On the other hand, as shown in FIG.
The semiconductor device 9 is fixed on the stage 8 heated to 0 ° C. by vacuum suction, and the protruding electrodes (hereinafter referred to as “stud bumps”) 10 are formed by the same method as the first bonding step by the known wire bonding technique. Semiconductor device 9
It is formed on the upper aluminum electrode 11.
【００４０】ここで、半導体装置９のアルミ電極１１上
に形成された数多くのスタッドバンプ１０はこのままで
はその高さがそれぞれ微妙に異なる。この状態では、半
導体装置９を回路基板４に機械的に接続した際に、回路
基板４上の入出力電極１に接触することのできるスタッ
ドバンプ１０と、回路基板４上の入出力電極１に届かな
いスタッドバンプ１０とが存在してしまい、電気的な接
続を信頼性良く行うことができない。そこで、これらの
高さの異なるスタッドバンプ１０の高さを一定の許容範
囲内に揃えるために、図３に示すように、レベリングス
テージ１２を使用して１つの半導体装置９内全てのスタ
ッドバンプ１０を同時に押さえ付け、全てのスタッドバ
ンプ１０の高さを揃える。Here, the many stud bumps 10 formed on the aluminum electrodes 11 of the semiconductor device 9 have slightly different heights as they are. In this state, when the semiconductor device 9 is mechanically connected to the circuit board 4, the stud bump 10 that can come into contact with the input / output electrode 1 on the circuit board 4 and the input / output electrode 1 on the circuit board 4 are connected. Since there is the stud bump 10 that does not reach, electrical connection cannot be made reliably. Therefore, in order to make the heights of the stud bumps 10 having different heights within a certain allowable range, as shown in FIG. 3, all the stud bumps 10 in one semiconductor device 9 are used by using the leveling stage 12. Are pressed simultaneously, and the heights of all the stud bumps 10 are made uniform.
【００４１】次に、図４（ａ）に示すように、レベリン
グを行った半導体装置９を、先に処理済みの異方導電性
フィルム７を貼り付けた回路基板４上に位置決めして重
ね合わせる。Next, as shown in FIG. 4A, the leveled semiconductor device 9 is positioned and superposed on the circuit board 4 to which the anisotropically conductive film 7 which has been previously processed is attached. .
【００４２】最後に、加熱と加圧を同時に行って、図４
（ｂ）に示すように、スタッドバンプ１０の先端部と回
路基板４上の入出力電極１との間の距離を導電性粒子６
の直径以下に維持した状態で絶縁性接着樹脂５を硬化さ
せる。Finally, heating and pressurization are performed at the same time, and FIG.
As shown in (b), the distance between the tip portion of the stud bump 10 and the input / output electrode 1 on the circuit board 4 is set to the conductive particles 6.
The insulating adhesive resin 5 is cured in a state where the diameter is maintained to be equal to or less than the diameter.
【００４３】このようにすることで、入出力電極１の基
幹部の幅ａよりも先端部の幅ｂの方が広くなっており、
スタッドバンプ１０は基幹部に実装されているので、実
装時に入出力電極１に印加される荷重は分散されるよう
になる。これにより、半導体装置９に形成されたスタッ
ドバンプ１０の高さおよび回路基板４の入出力電極１の
高さがある許容範囲でそれぞれ微妙に異なっていたり、
ピール強度の弱い入出力電極１を有する回路基板４に半
導体装置９を実装しても、入出力電極１の先端が回路基
板４から剥がれたり、剥がれた入出力電極１が半導体装
置９に接触することがなくなる。By doing so, the width b of the tip end portion is wider than the width a of the base portion of the input / output electrode 1,
Since the stud bumps 10 are mounted on the basic part, the load applied to the input / output electrodes 1 during mounting is dispersed. As a result, the height of the stud bumps 10 formed on the semiconductor device 9 and the height of the input / output electrodes 1 of the circuit board 4 are slightly different within a certain allowable range.
Even if the semiconductor device 9 is mounted on the circuit board 4 having the input / output electrode 1 having a weak peel strength, the tip of the input / output electrode 1 is peeled from the circuit board 4, or the peeled input / output electrode 1 contacts the semiconductor device 9. Will disappear.
【００４４】したがって、半導体装置９に形成されたス
タッドバンプ１０と回路基板４に形成された入出力電極
１との電気的接続不良の発生を抑えることができる。Therefore, it is possible to suppress the occurrence of a defective electrical connection between the stud bump 10 formed on the semiconductor device 9 and the input / output electrode 1 formed on the circuit board 4.
【００４５】なお、入出力電極１は、図５に示すよう
に、二点鎖線で示す突起電極１０が実装される位置より
先端側に、入出力電極１の基幹部の幅ａよりも幅ｃの狭
いくびれ部１３を形成するようにしてもよい。As shown in FIG. 5, the input / output electrode 1 has a width c larger than the width a of the main portion of the input / output electrode 1 on the tip side from the position where the protruding electrode 10 shown by the chain double-dashed line is mounted. The constricted portion 13 having a narrow width may be formed.
【００４６】また、図６に示すように、突起電極が実装
される位置より先端側に、入出力電極１が陥没して内層
電極１４と接続されたホール部１５を形成するようにし
てもよい。Further, as shown in FIG. 6, the input / output electrode 1 may be depressed to form a hole portion 15 connected to the inner layer electrode 14 at the tip side from the position where the protruding electrode is mounted. .
【００４７】さらに、図７に示すように、回路基板４の
平面方向に対して所定の角度に屈曲された屈曲部１ａを
入出力電極１に形成し、この屈曲部１ａを先端側にして
突起電極１０を実装してもよい。Further, as shown in FIG. 7, a bent portion 1a bent at a predetermined angle with respect to the plane direction of the circuit board 4 is formed in the input / output electrode 1, and the bent portion 1a is projected toward the tip side. The electrode 10 may be mounted.
【００４８】なお、回路基板４は、サブトラクティブ法
でなく、めっきレジストを用いてめっきにより回路部分
を形成するアディティブ法やセミアディティブ法でも形
成してもよい。The circuit board 4 may be formed not by the subtractive method but by the additive method or the semi-additive method of forming a circuit portion by plating using a plating resist.
【００４９】また、半導体装置９に形成された突起電極
１０は、ワイヤボンディングでなく公知のめっき装置
（図示せず）にて形成しためっきバンプであってもよ
い。The protruding electrodes 10 formed on the semiconductor device 9 may be plating bumps formed by a known plating device (not shown) instead of wire bonding.
【００５０】さらに、導電性微粒子６の混入された異方
導電性フィルム７を用いず、絶縁性接着樹脂５のみで固
定するようにしてもよい。Further, the anisotropic conductive film 7 having the conductive fine particles 6 mixed therein may not be used, and the insulating adhesive resin 5 alone may be used for fixing.
【００５１】[0051]
【００５２】[0052]
【００５３】[0053]
【００５４】[0054]
【００５５】[0055]
【００５６】[0056]
【００５７】[0057]
【００５８】[0058]
【００５９】[0059]
【００６０】[0060]
【００６１】[0061]
【００６２】[0062]
【００６３】[0063]
【００６４】[0064]
【００６５】[0065]
【００６６】[0066]
【００６７】[0067]
【００６８】[0068]
【００６９】[0069]
【００７０】[0070]
【００７１】[0071]
【００７２】[0072]
【００７３】[0073]
【００７４】[0074]
【発明の効果】以上のように、本発明によれば、半導体
装置に形成された突起電極の高さおよび回路基板の入出
力電極の高さが異なっていたり、ピール強度の弱い入出
力電極を有する回路基板に半導体装置を実装しても、入
出力電極の先端が回路基板から剥がれたり、剥がれた入
出力電極が半導体装置に接触することがなくなるという
有効な効果が得られる。As described above, according to the present invention, the height of the protruding electrode formed on the semiconductor device and the height of the input / output electrode of the circuit board are different, or the input / output electrode having a weak peel strength is used. Even if the semiconductor device is mounted on the circuit board that it has, it is possible to obtain an effective effect that the tips of the input / output electrodes are not peeled off from the circuit board and the peeled input / output electrodes are not in contact with the semiconductor device.
【００７５】これにより、半導体装置に形成された突起
電極と回路基板に形成された入出力電極との電気的接続
不良の発生を抑制することが可能になるというという有
効な効果が得られる。As a result, it is possible to obtain an effective effect that it is possible to suppress the occurrence of a defective electrical connection between the protruding electrode formed on the semiconductor device and the input / output electrode formed on the circuit board.
【図１】本発明の実施の形態１における入出力電極の形
状の一例を示す平面図FIG. 1 is a plan view showing an example of shapes of input / output electrodes according to a first embodiment of the present invention.
【図２】本発明の実施の形態１における異方導電性フィ
ルムを回路基板に貼った状態を示す断面図FIG. 2 is a cross-sectional view showing a state in which the anisotropic conductive film according to Embodiment 1 of the present invention is attached to a circuit board.
【図３】本発明の実施の形態１におけるスタッドバンプ
の形成工程の一部を示す説明図FIG. 3 is an explanatory view showing a part of a process of forming a stud bump according to the first embodiment of the present invention.
【図４】本発明の実施の形態１における半導体装置と回
路基板の異方導電性フィルムを使用した接合工程および
接合状態を連続して示す断面図FIG. 4 is a cross-sectional view continuously showing a joining process and a joining state using the anisotropic conductive film of the semiconductor device and the circuit board according to the first embodiment of the present invention.
【図５】本発明の実施の形態１における入出力電極の形
状の他の一例を示す平面図FIG. 5 is a plan view showing another example of the shape of the input / output electrode according to the first embodiment of the present invention.
【図６】本発明の実施の形態１における入出力電極の形
状のさらに他の一例を示す断面図FIG. 6 is a sectional view showing still another example of the shape of the input / output electrodes according to the first embodiment of the present invention.
【図７】本発明の実施の形態１における入出力電極の形
状のさらに他の一例を示す平面図FIG. 7 is a plan view showing still another example of the shape of the input / output electrodes according to the first embodiment of the present invention.
【図８】従来の第１の技術における半導体装置と回路基
板の接合状態の要部を示す断面図FIG. 8 is a cross-sectional view showing a main part of a bonded state of a semiconductor device and a circuit board according to a conventional first technique.
【図９】従来の第２の技術における半導体装置と回路基
板の接合状態の要部を示す断面図FIG. 9 is a cross-sectional view showing a main part of a bonded state of a semiconductor device and a circuit board in a second conventional technique.
【図１０】従来の技術における半導体装置と回路基板の
接合状態の要部を示す断面図FIG. 10 is a cross-sectional view showing a main part of a bonded state of a semiconductor device and a circuit board in a conventional technique.
１ 入出力電極 １ａ 屈曲部 ４ 回路基板 ５ 絶縁性接着樹脂（接合部材） ７ 異方導電性フィルム（接合部材） ９ 半導体装置 １０ 突起電極（スタッドバンプ） １３ くびれ部 １４ 内層電極 １５ ホール部 1 I / O electrode 1a Bent part 4 circuit board 5 Insulating adhesive resin (joint member) 7 Anisotropic conductive film (joint member) 9 Semiconductor devices 10 Projection electrode (stud bump) 13 Constriction 14 Inner layer electrode 15 holes
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平６−232205（ＪＰ，Ａ) 特開 平３−16147（ＪＰ，Ａ) 特開 昭53−8566（ＪＰ，Ａ) 特開 平１−152637（ＪＰ，Ａ) 特開 平４−82241（ＪＰ，Ａ) 特開 平９−82755（ＪＰ，Ａ) 国際公開98／18161（ＷＯ，Ａ１) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 21/92 H01L 23/12 H05K 1/18 ─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-6-232205 (JP, A) JP-A-3-16147 (JP, A) JP-A-53-8566 (JP, A) JP-A-1- 152637 (JP, A) JP-A-4-82241 (JP, A) JP-A-9-82755 (JP, A) International Publication 98/18161 (WO, A1) (58) Fields investigated (Int. Cl. 7) , DB name) H01L 21/60 H01L 21/92 H01L 23/12 H05K 1/18
Claims (4)
と、 絶縁性および接着性を有する接合部材と、 基幹部の幅よりも先端部の幅の方が広くなった複数の入
出力電極が形成され、前記入出力電極に対応した前記突
起電極がこの入出力電極の基幹部を押圧するように前記
半導体装置が実装される回路基板とからなることを特徴
とする半導体ユニット。1. A semiconductor device having a plurality of protruding electrodes, a joining member having an insulating property and an adhesive property, and a plurality of input / output electrodes having a width of a tip portion wider than a width of a trunk portion. A semiconductor unit, which is formed and comprises a circuit board on which the semiconductor device is mounted so that the protruding electrode corresponding to the input / output electrode presses a basic portion of the input / output electrode.
と、 絶縁性および接着性を有する接合部材と、 基幹部の幅よりも幅の狭いくびれ部が設けられた複数の
入出力電極が形成され、前記入出力電極に対応した前記
突起電極が前記くびれ部の方を先端側にしてこの入出力
電極の基幹部を押圧するように前記半導体装置が実装さ
れる回路基板とからなることを特徴とする半導体ユニッ
ト。2. A semiconductor device having a plurality of protruding electrodes, a joining member having an insulating property and an adhesive property, and a plurality of input / output electrodes provided with a constricted portion having a width narrower than a width of a main portion. And a circuit board on which the semiconductor device is mounted so that the protruding electrode corresponding to the input / output electrode presses the basic part of the input / output electrode with the constricted part facing toward the tip side. And semiconductor unit.
と、 絶縁性および接着性を有する接合部材と、 陥没して内層電極と接続されたホール部が設けられた複
数の入出力電極が形成され、前記入出力電極に対応した
前記突起電極が前記ホール部の方を先端側にしてこの入
出力電極を押圧するように前記半導体装置が実装される
回路基板とからなることを特徴とする半導体ユニット。3. A semiconductor device having a plurality of protruding electrodes, a bonding member having an insulating property and an adhesive property, and a plurality of input / output electrodes provided with a hole portion which is depressed and connected to an inner layer electrode. And a circuit board on which the semiconductor device is mounted so that the protruding electrode corresponding to the input / output electrode presses the input / output electrode with the hole portion facing toward the tip side. unit.
と、 絶縁性および接着性を有する接合部材と、 平面方向に向かって所定の角度に屈曲された屈曲部が設
けられた複数の入出力電極が形成され、前記入出力電極
に対応した前記突起電極が前記屈曲部の方を先端側にし
てこの入出力電極を押圧するように前記半導体装置が実
装される回路基板とからなることを特徴とする半導体ユ
ニット。4. A semiconductor device having a plurality of protruding electrodes, a bonding member having an insulating property and an adhesive property, and a plurality of input / outputs each having a bent portion bent at a predetermined angle in a plane direction. An electrode is formed, and the projecting electrode corresponding to the input / output electrode comprises a circuit board on which the semiconductor device is mounted so as to press the input / output electrode with the bent portion facing toward the tip side. And semiconductor unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14899198A JP3446608B2 (en) | 1998-05-29 | 1998-05-29 | Semiconductor unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14899198A JP3446608B2 (en) | 1998-05-29 | 1998-05-29 | Semiconductor unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11340282A JPH11340282A (en) | 1999-12-10 |
| JP3446608B2 true JP3446608B2 (en) | 2003-09-16 |
Family
ID=15465265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14899198A Expired - Fee Related JP3446608B2 (en) | 1998-05-29 | 1998-05-29 | Semiconductor unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3446608B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007039959A1 (en) * | 2005-10-05 | 2007-04-12 | Sharp Kabushiki Kaisha | Wiring board and display device provided with same |
| WO2007039960A1 (en) * | 2005-10-05 | 2007-04-12 | Sharp Kabushiki Kaisha | Wiring board and display device provided with same |
-
1998
- 1998-05-29 JP JP14899198A patent/JP3446608B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11340282A (en) | 1999-12-10 |
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