JP3446608B2 - Semiconductor unit - Google Patents

Semiconductor unit

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Publication number
JP3446608B2
JP3446608B2 JP14899198A JP14899198A JP3446608B2 JP 3446608 B2 JP3446608 B2 JP 3446608B2 JP 14899198 A JP14899198 A JP 14899198A JP 14899198 A JP14899198 A JP 14899198A JP 3446608 B2 JP3446608 B2 JP 3446608B2
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JP14899198A
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Japanese (ja)
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JPH11340282A (en )
Inventor
泰行 ▲高▼野
崇好 村端
雅俊 竹田
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松下電器産業株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401Structure
    • H01L2224/1403Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114Guiding structures outside the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は、半導体装置と回路基板とが電気的および機械的に接続された半導体ユニットに関するものであり、特に、半導体装置と回路基板とをフェースダウンで接続したフリップチップ実装の半導体ユニットに適用して有効な技術に関するものである。 BACKGROUND OF THE INVENTION [0001] [Technical Field of the Invention The present invention includes a semiconductor device and the circuit board are to a semiconductor units electrically and mechanically connected, in particular, the semiconductor device and the circuit a substrate applied to a semiconductor unit of the flip-chip mounting which is connected in a face-down to a technique effectively. 【0002】 【従来の技術】半導体装置と回路基板とを直接フェースダウンで電気的および機械的に接続するフリップチップ実装は、樹脂等で保護成形した従来のパッケージに比較して実装面積を大幅に縮小することができるという利点を持ち、注目を集めている技術である。 [0002] The electrical and mechanical flip-chip mounting of connecting BACKGROUND OF THE INVENTION Direct facedown the semiconductor device and the circuit board, the mounting area significantly as compared with the conventional package protected molded with resin or the like has the advantage that it is possible to reduce a technique has attracted attention. 【0003】以下に、従来の半導体装置の実装技術について説明する。 [0003] The following describes the implementation technique of the conventional semiconductor device. ここで、図は従来の第1の技術における半導体装置と回路基板の接合状態の要部を示す断面図、図は従来の第2の技術における半導体装置と回路基板の接合状態の要部を示す断面図、図10は従来の技術における半導体装置と回路基板の接合状態の要部を示す断面図である。 Here, FIG. 8 is a sectional view showing an essential part of the bonded state of the semiconductor device and the circuit board in a conventional first technique, FIG. 9 is a main portion of the bonding state of the semiconductor device and the circuit board in a conventional second technique the cross-sectional view illustrating, FIG. 10 is a sectional view showing an essential part of the bonded state of the semiconductor device and the circuit board in the prior art. 【0004】図に示すように、従来から、アルミ電極11上に突起電極10が形成された半導体装置9を回路基板29に電気的および機械的に接続する第1の技術として、両者を絶縁性接着樹脂27によって固定し、半導体装置1の突起電極10と回路基板29上の入出力電極28との機械的な接触のみで接続する半導体ユニットが知られている。 [0004] As shown in FIG. 8, conventionally, as a first technique for connecting the semiconductor device 9 protruding electrode 10 is formed on the aluminum electrode 11 on the circuit board 29 electrically and mechanically, both insulating fixed by gender adhesive resin 27, the semiconductor unit is known to be connected only by a mechanical contact between the projection electrodes 10 and the circuit input and output electrodes 28 on the substrate 29 of the semiconductor device 1. 【0005】この接続技術は、図に示すように、まず入出力電極28を有する回路基板29上に絶縁性接着樹脂27を貼り付ける。 [0005] The connection technique, as shown in FIG. 8, first paste insulating adhesive resin 27 on the circuit board 29 having an input-output electrode 28. 次いで、ボンディング装置(図示せず)あるいはめっき装置(図示せず)によってアルミ電極11上に突起電極10が形成された半導体装置9を回路基板29上に位置決めして重ね合わせる。 Then, a bonding device (not shown) or plating device superimposed by positioning the semiconductor device 9 protruding electrode 10 on the aluminum electrode 11 (not shown) is formed on the circuit board 29. そして、 And,
加熱と加圧とを同時に行い、突起電極10と入出力電極28との間に絶縁性接着樹脂27が存在しないように十分に荷重を印加して絶縁性接着樹脂27を硬化させる。 It performs a heating and pressurizing at the same time, curing the insulating adhesive resin 27 by applying a sufficiently load as insulating adhesive resin 27 does not exist between the projection electrodes 10 and the output electrode 28.
このようにすることで、突起電極10と入出力電極28 In this way, the bump electrode 10 output electrodes 28
とが直接接触して両者が電気的に接続されることになる。 Doo is that both in direct contact are electrically connected. 【0006】また、アルミ電極11上に突起電極10が形成された半導体装置9を回路基板29に電気的および機械的に接続する第2の技術として、異方導電性フィルムを使用するものが知られている。 Further, those as a second technique for connecting the semiconductor device 9 protruding electrode 10 is formed on the aluminum electrode 11 on the circuit board 29 electrically and mechanically, using the anisotropic conductive film is known It is. 【0007】この接続技術は、図に示すように、まず絶縁性接着樹脂5に対して絶縁性を損なわない程度に導電性粒子6が分散されたものからなる異方導電性フィルム7を用意し、これを入出力電極28を有する回路基板29の上に貼り付ける。 [0007] The connection technique, as shown in FIG. 9, first, prepared anisotropic conductive film 7 consisting of those conductive particles 6 are dispersed to such an extent of not impairing the insulating property to the insulating adhesive resin 5 and, pasting on a circuit board 29 having an input and output electrodes 28 this. 【0008】ここで、導電性粒子6はNi粒子やAg粒子、あるいは樹脂ボールに金属薄膜と絶縁膜をコートした粒子等が用いられ、その直径は5μm程度であり、1 [0008] Here, the conductive particles 6 Ni particles and Ag particles, or particles coated with the resin ball a metal thin film and the insulating film or the like is used, its diameter is about 5 [mu] m, 1
00μm 3に25個程度が混入されている。 About 25 to 00Myuemu 3 are mixed. 【0009】次いで、ボンディング装置(図示せず)あるいはめっき装置(図示せず)によって半導体装置9のアルミ電極11上に突起電極10を形成し、突起電極1 [0009] Then, the protruding electrodes 10 formed on the aluminum electrode 11 of the semiconductor device 9 by a bonding device (not shown) or a plating apparatus (not shown), protruding electrodes 1
0の形成された半導体装置9を回路基板29上に位置決めして重ね合わせる。 The semiconductor device 9 formed of 0 superimposed and positioned on the circuit board 29. そして、加熱と加圧とを同時に行い、突起電極10と入出力電極28との間の距離を導電性粒子6の直径以下に維持した状態で絶縁性接着剤5を硬化させる。 Then, a heating and pressurizing at the same time, curing the insulating adhesive 5 while maintaining a distance below the diameter of the conductive particles 6 between the projection electrodes 10 and the output electrode 28. このようにすると、突起電極10と入出力電極28との間は、突起電極10と入出力電極10との間の直接接触か、あるいは両者間で押し潰された導電性粒子6を介しての接触によって電気的に接続されることになる。 In this way, between the projection electrodes 10 and the output electrode 28, the via direct contact or conductive particles 6 or which is squeezed between them, between the input and output electrodes 10 and the bump electrode 10 It will be electrically connected by contact. 【0010】ここで、第1の技術による突起電極10と入出力電極28との間の直接接触は絶縁性接着剤27による機械的接着保持力で維持されるものであり、突起電極10には弾力性がないので、電気的接続を維持するための能動的な加圧力が存在しない。 [0010] Here, direct contact between the first technology and the bump electrode 10 by the input and output electrodes 28 are intended to be maintained by the mechanical bond retention by insulating adhesive 27, the projection electrodes 10 is since there is no elasticity, active pressure is not present for maintaining the electrical connection. したがって、ヒートサイクルを加えた場合の電気的接続の信頼性が低くなる。 Therefore, the reliability of the electrical connection when the addition of heat cycle falls. 【0011】これに対して、第2の技術による突起電極10と入出力電極24との間で押し潰された導電性粒子6を介する異方導電性フィルム7による電気的接触には、押し潰された導電性粒子6の弾力性による能動的な加圧力が存在するので、ヒートサイクルを加えた場合の電気的接続の信頼性を第1の技術よりも高く維持することができるとされている。 [0011] In contrast, the electrical contact according to the anisotropic conductive film 7 through the conductive particles 6 was crushed between the output electrode 24 and the bump electrode 10 by the second technique, press ulcer because active pressure is present due to the elasticity of the conductive particles 6 is, there is a can be maintained higher than the reliability of the first technical electrical connection when added heat cycle . 【0012】 【発明が解決しようとする課題】しかしながら、上記の実装構造において、半導体装置9に形成された突起電極10の高さおよび回路基板29側の入出力電極28の高さはある許容範囲でそれぞれ微妙に異なる。 [0012] SUMMARY OF THE INVENTION However, in the above mounting structure, tolerance height and the height of the circuit board 29 side of the input and output electrodes 28 of the bump electrode 10 formed on the semiconductor device 9 is in a slightly different each. また、機器への更なる小型化が要求され、半導体装置9の電極間のピッチが小さくなると、回路基板29の入出力電極間のピッチも小さくなり、電極幅も小さくなってくる。 Further, the required further miniaturization of the device, the pitch between electrodes of the semiconductor device 9 is reduced, the pitch between the input and output electrodes of the circuit board 29 becomes small, it becomes smaller electrode width. それに伴い、回路基板29の入出力電極28のピール強度も弱くなってくる。 Along with this, the peel strength of the input and output electrodes 28 of the circuit board 29 also becomes weaker. 【0013】この状態で半導体装置9を回路基板29上に加熱と加圧をしながら固定すると、図に示すように、高さの高い突起電極10に対応した回路基板29上の入出力電極28と、高さの低い突起電極10に対応した回路基板29上の入出力電極28とでは、それぞれに印加される荷重に差が生じる。 [0013] Fixing while heating and pressurizing the semiconductor device 9 in this state on the circuit board 29, as shown in FIG. 8, the input and output electrodes on the circuit board 29 corresponding to the high projecting electrodes 10 heights 28, the input and output electrodes 28 on the circuit board 29 corresponding to the lower projection electrode 10 heights, a difference in load applied to the respective results. 【0014】また、図10に示すように、高さの高い入出力電極28に対応した突起電極10と、高さの低い入出力電極28に対応した突起電極10とでも、それぞれに印加される荷重に差が生じる。 Further, as shown in FIG. 10, even the bump electrode 10 corresponding to the high input and output electrodes 28 in height, the bump electrode 10 corresponding to the lower output electrode 28 in height, applied to each difference in load occurs. 【0015】一般には、高さの低い突起電極10も十分に回路基板29上の入出力電極28に接触するように、 [0015] Generally, as is the projection electrodes 10 low profile contacts the input and output electrodes 28 on the well circuit board 29,
さらには高さの低い入出力電極28も十分に突起電極1 Furthermore low profile input and output electrodes 28 also sufficiently protruding electrodes 1
0に接触するように荷重を印加して固定するため、高さが高い突起電極10に対応した回路基板29上の入出力電極28部、および高さの高い入出力電極28部においてはかなりの荷重が印加されることになる。 For fixing by applying a load to contact the 0 input and output electrodes 28 parts on the circuit board 29 corresponding to the high projecting electrodes 10 height, and considerable at high input and output electrodes 28 parts of heights so that the load is applied. すると、入出力電極28の先端が回路基板29からの剥がれたり、 Then, peeled off from the front end circuit board 29 of the input and output electrodes 28,
さらには剥がれた入出力電極28が半導体装置9に接触する場合が発生する。 Furthermore if the input and output electrodes 28 detached contact with the semiconductor device 9 occurs. 【0016】そこで、本発明は、半導体装置に形成された突起電極と回路基板に形成された入出力電極との電気的接続不良の発生を抑制することのできる半導体ユニットを提供することを目的とする。 [0016] Therefore, the present invention is, intended to provide a semiconductor unit which can suppress the electrical connection defective of input and output electrodes formed on the projecting electrodes and the circuit board formed on a semiconductor device to. 【0017】 【課題を解決するための手段】この課題を解決するために、本発明の半導体ユニットは、複数の突起電極が形成された半導体装置と、絶縁性および接着性を有する接合部材と、基幹部の幅よりも先端部の幅の方が広くなった複数の入出力電極が形成され、入出力電極に対応した突起電極がこの入出力電極の基幹部を押圧するように半導体装置が実装される回路基板とからなることを特徴とする。 [0017] [Means for Solving the Problems] To solve this problem, the semiconductor unit of the present invention, a semiconductor device having a plurality of protruding electrodes formed thereon, and a joint member having an insulating property and adhesion, it is formed with a plurality of input and output electrodes it is widened in the width of the tip portion than the width of the trunk portion, the semiconductor device so as to press the mounting protrusion electrodes corresponding to the input and output electrodes of the backbone portion of the input and output electrodes characterized in that comprising a circuit board. 【0018】これにより、半導体装置に形成された突起電極と回路基板に形成された入出力電極との電気的接続不良の発生を抑制することができる。 [0018] Thus, it is possible to suppress the occurrences of poor electrical connection between the input and output electrodes formed on the projecting electrodes and the circuit board formed on the semiconductor device. 【0019】また、本発明の半導体ユニットは、複数の突起電極が形成された半導体装置と、絶縁性および接着性を有する接合部材と、基幹部の幅よりも幅の狭いくびれ部が設けられた複数の入出力電極が形成され、入出力電極に対応した突起電極がくびれ部の方を先端側にしてこの入出力電極の基幹部を押圧するように半導体装置が実装される回路基板とからなることを特徴とする。 Further, the semiconductor unit of the present invention, a semiconductor device having a plurality of protruding electrodes formed thereon, and a joint member having an insulating property and adhesiveness, a narrow neck portion having a width greater than the width of the trunk portion is provided a plurality of input and output electrodes are formed, consists towards the constricted portion protruding electrodes corresponding to the input and output electrodes in the distal end side and the circuit board on which the semiconductor device is mounted so as to press the core portion of the input and output electrodes it is characterized in. 【0020】これにより、半導体装置に形成された突起電極と回路基板に形成された入出力電極との電気的接続不良の発生を抑制することができる。 [0020] Thus, it is possible to suppress the occurrences of poor electrical connection between the input and output electrodes formed on the projecting electrodes and the circuit board formed on the semiconductor device. 【0021】本発明の半導体ユニットは、複数の突起電極が形成された半導体装置と、絶縁性および接着性を有する接合部材と、陥没して内層電極と接続されたホール部が設けられた複数の入出力電極が形成され、入出力電極に対応した突起電極がホール部の方を先端側にしてこの入出力電極を押圧するように半導体装置が実装される回路基板とからなることを特徴とする。 The semiconductor unit of the present invention includes a semiconductor device having a plurality of protruding electrodes formed thereon, and a joint member having an insulating property and adhesion, hole portion which is connected to the internal electrodes and depression plurality of provided input and output electrodes are formed, projecting electrodes corresponding to the input and output electrodes is characterized in that it consists of a circuit board on which the semiconductor device is mounted so as to press the input and output electrodes in the distal end side towards the hole portion . 【0022】これにより、半導体装置に形成された突起電極と回路基板に形成された入出力電極との電気的接続不良の発生を抑制することができる。 [0022] Thus, it is possible to suppress the occurrences of poor electrical connection between the input and output electrodes formed on the projecting electrodes and the circuit board formed on the semiconductor device. 【0023】本発明の半導体ユニットは、複数の突起電極が形成された半導体装置と、絶縁性および接着性を有する接合部材と、平面方向に向かって所定の角度に屈曲された屈曲部が設けられた複数の入出力電極が形成され、入出力電極に対応した突起電極が屈曲部の方を先端側にしてこの入出力電極を押圧するように半導体装置が実装される回路基板とからなることを特徴とする。 The semiconductor unit of the present invention includes a semiconductor device having a plurality of protruding electrodes formed thereon, and a joint member having an insulating property and adhesion, the bent portion is provided which is bent at a predetermined angle toward the plane direction a plurality of input and output electrodes are formed with, that comprising a circuit board on which the semiconductor device is mounted as projecting electrodes corresponding to the input and output electrodes for pressing the input and output electrodes in the distal end side toward the bent portion and features. 【0024】これにより、半導体装置に形成された突起電極と回路基板に形成された入出力電極との電気的接続不良の発生を抑制することができる。 [0024] Thus, it is possible to suppress the occurrences of poor electrical connection between the input and output electrodes formed on the projecting electrodes and the circuit board formed on the semiconductor device. 【0025】 【0026】 【0027】 【0028】 【0029】 【発明の実施の形態】本発明の請求項1に記載の発明は、複数の突起電極が形成された半導体装置と、絶縁性および接着性を有する接合部材と、基幹部の幅よりも先端部の幅の方が広くなった複数の入出力電極が形成され、入出力電極に対応した突起電極がこの入出力電極の基幹部を押圧するように半導体装置が実装される回路基板とからなることを特徴とする半導体ユニットであり、 [0025] [0026] [0027] [0028] [0029] The invention according to claim 1 of the embodiment of the present invention includes a semiconductor device having a plurality of protruding electrodes are formed, insulating and adhesive pressing the bonding member, it is formed with a plurality of input and output electrodes it is widened in the width of the tip portion than the width of the trunk portion, protruding electrodes corresponding to the input and output electrodes of the backbone portion of the input and output electrodes with sex the semiconductor device to become a circuit board which is mounted a semiconductor unit according to claim,
実装時に入出力電極に印加される荷重が分散されるので、半導体装置に形成された突起電極と回路基板に形成された入出力電極との電気的接続不良の発生を抑制することが可能になるという作用を有する。 Since the load applied to the input and output electrodes during mounting is dispersed, it is possible to suppress the occurrences of poor electrical connection between the input and output electrodes formed on the projecting electrodes and the circuit board formed on a semiconductor device It has the effect of. 【0030】本発明の請求項2に記載の発明は、複数の突起電極が形成された半導体装置と、絶縁性および接着性を有する接合部材と、基幹部の幅よりも幅の狭いくびれ部が設けられた複数の入出力電極が形成され、入出力電極に対応した突起電極がくびれ部の方を先端側にしてこの入出力電極の基幹部を押圧するように半導体装置が実装される回路基板とからなることを特徴とする半導体ユニットであり、実装時に入出力電極に印加される荷重が分散されるので、半導体装置に形成された突起電極と回路基板に形成された入出力電極との電気的接続不良の発生を抑制することが可能になるという作用を有する。 The invention described in claim 2 of the present invention includes a semiconductor device having a plurality of protruding electrodes formed thereon, and a joint member having an insulating property and adhesiveness, a narrow neck portion having a width greater than the width of the core portion a plurality of input and output electrodes provided are formed, the circuit board on which the semiconductor device is mounted so as to press the core portion of the input and output electrodes toward the constricted portion protruding electrodes corresponding to the input and output electrodes in the distal end characterized in that it consists of a a semiconductor unit, the load applied to the input and output electrodes during mounting is dispersed, electrical input and output electrodes formed on the projecting electrodes and the circuit board formed on a semiconductor device It has the effect that it is possible to suppress connection failure occurrence. 【0031】本発明の請求項3に記載の発明は、複数の突起電極が形成された半導体装置と、絶縁性および接着性を有する接合部材と、陥没して内層電極と接続されたホール部が設けられた複数の入出力電極が形成され、入出力電極に対応した突起電極がホール部の方を先端側にしてこの入出力電極を押圧するように半導体装置が実装される回路基板とからなることを特徴とする半導体ユニットであり、実装時に入出力電極に印加される荷重が分散されるので、半導体装置に形成された突起電極と回路基板に形成された入出力電極との電気的接続不良の発生を抑制することが可能になるという作用を有する。 The invention described in claim 3 of the present invention includes a semiconductor device having a plurality of protruding electrodes formed thereon, and a joint member having an insulating property and adhesion, hole portion which is connected to the internal electrodes and depression is a plurality of input and output electrodes provided is formed, and a circuit board on which the semiconductor device is mounted as projecting electrodes corresponding to the input and output electrodes for pressing the input and output electrodes in the distal end side towards the hole portion it is a semiconductor unit, wherein, since the load applied to the input and output electrodes during mounting is dispersed, electrical connection failure between the input and output electrodes formed on the projecting electrodes and the circuit board formed on a semiconductor device It has the effect that it is possible to suppress the occurrence of. 【0032】本発明の請求項4に記載の発明は、複数の突起電極が形成された半導体装置と、絶縁性および接着性を有する接合部材と、平面方向に向かって所定の角度に屈曲された屈曲部が設けられた複数の入出力電極が形成され、入出力電極に対応した突起電極が屈曲部の方を先端側にしてこの入出力電極を押圧するように半導体装置が実装される回路基板とからなることを特徴とする半導体ユニットであり、実装時に入出力電極に印加される荷重が分散されるので、半導体装置に形成された突起電極と回路基板に形成された入出力電極との電気的接続不良の発生を抑制することが可能になるという作用を有する。 The invention described in claim 4 of the present invention includes a semiconductor device having a plurality of protruding electrodes formed thereon, and a joint member having an insulating property and adhesion, which is bent at a predetermined angle toward the plane direction the bent portion is formed with a plurality of input and output electrodes provided, the circuit board on which the semiconductor device is mounted as projecting electrodes corresponding to the input and output electrodes for pressing the input and output electrodes in the distal end side toward the bent portion characterized in that it consists of a a semiconductor unit, the load applied to the input and output electrodes during mounting is dispersed, electrical input and output electrodes formed on the projecting electrodes and the circuit board formed on a semiconductor device It has the effect that it is possible to suppress connection failure occurrence. 【0033】 【0034】 【0035】以下、本発明の実施の形態について、図1 [0033] [0034] [0035] Hereinafter, embodiments of the present invention, FIG. 1
から図13を用いて説明する。 It will be described with reference to FIG. 13. なお、これらの図面において同一の部材には同一の符号を付しており、また、重複した説明は省略されている。 Incidentally, the same members in these drawings are assigned the same reference numerals, also duplicate description is omitted. 【0036】(実施の形態1)図1は本発明の実施の形態1における入出力電極の形状の一例を示す平面図、図2は本発明の実施の形態1における異方導電性フィルムを回路基板に貼った状態を示す断面図、図3は本発明の実施の形態1におけるスタッドバンプの形成工程の一部を示す説明図、図4は本発明の実施の形態1における半導体装置と回路基板の異方導電性フィルムを使用した接合工程および接合状態を連続して示す断面図、図5は本発明の実施の形態1における入出力電極の形状の他の一例を示す平面図、図6は本発明の実施の形態1における入出力電極の形状のさらに他の一例を示す断面図、図7 [0036] (Embodiment 1) FIG. 1 is a plan view showing an example of the shape of the input and output electrodes in the first embodiment of the present invention, FIG. 2 circuit the anisotropic conductive film in the first embodiment of the present invention sectional view showing a state in which affixed to the substrate, Fig. 3 is an explanatory view showing a part of a stud bump formation process according to the first embodiment of the present invention, a semiconductor device and a circuit board in the first embodiment of FIG. 4 is the invention cross-sectional view illustrating a bonding step and the bonding state by continuously using the anisotropic conductive film of FIG. 5 is a plan view showing another example of the shape of the input and output electrodes in the first embodiment of the present invention, FIG. 6 sectional view showing still another example of the shape of the input and output electrodes in the first embodiment of the present invention, FIG. 7
は本発明の実施の形態1における入出力電極の形状のさらに他の一例を示す平面図である。 Is a plan view showing still another example of the shape of the input and output electrodes in the first embodiment of the present invention. 【0037】本実施の形態の半導体ユニットにおいては、回路形成部分にエッチングレジストを設けエッチングにより回路部を形成するサブトラクティブ法にて回路基板を形成する際に、半導体装置の実装部分である入出力電極1の形状を、図1に示すように、二点鎖線で示す突起電極が実装される基幹部の幅aより先端部の幅bの方を広くする。 [0037] In the semiconductor device of the embodiment, when forming the circuit board by the subtractive method to form a circuit section by etching is provided an etching resist on the circuit forming portion, a mounting portion of the semiconductor device output the shape of the electrode 1, as shown in FIG. 1, wider towards the width b of the tip portion than the width a of the core portion protruding electrode shown by a two-dot chain line is mounted. 【0038】次に、図2に示すように、このような入出力電極1が形成された回路基板4の上に、絶縁性接着樹脂5に絶縁性を損なわない程度に少量の導電性粒子6が分散されたものからなる異方導電性フィルム(接合部材)7を貼り付ける。 Next, as shown in FIG. 2, on a circuit board 4 such input and output electrodes 1 are formed, a small amount of conductive particles to an extent of not impairing the insulating property to the insulating adhesive resin 5 6 There pasting an anisotropic conductive film (bonding member) 7 consisting of those that are distributed. なお、本発明において、回路基板4と半導体装置9との接続には必ずしも異方導電性フィルム7を用いる必要はなく、絶縁性および接着性を有する種々の接合部材を用いることが可能である。 In the present invention, the connection between the circuit board 4 and the semiconductor device 9 is not always necessary to use an anisotropic conductive film 7, it is possible to use various joining members having insulating properties and adhesion. 【0039】一方、図3に示すように、150℃〜30 On the other hand, as shown in FIG. 3, 0.99 ° C. to 30
0℃に加熱されたステージ8上に真空吸着により半導体装置9を固定し、公知のワイヤボンディング技術による最初のボンディング工程と同様の方法で、突起電極(以下、「スタッドバンプ」という。)10を半導体装置9 0 a semiconductor device 9 is fixed by vacuum suction on the stage 8 which is heated in ° C., in the first bonding step the same way by known wire bonding technique, protruding electrodes (hereinafter, referred to as. "Stud bump") 10 semiconductor device 9
上のアルミ電極11上に形成する。 Formed on the aluminum electrode 11 above. 【0040】ここで、半導体装置9のアルミ電極11上に形成された数多くのスタッドバンプ10はこのままではその高さがそれぞれ微妙に異なる。 [0040] Here, the height a number of stud bump 10 formed on the aluminum electrode 11 of the semiconductor device 9 remains this is slightly different, respectively. この状態では、半導体装置9を回路基板4に機械的に接続した際に、回路基板4上の入出力電極1に接触することのできるスタッドバンプ10と、回路基板4上の入出力電極1に届かないスタッドバンプ10とが存在してしまい、電気的な接続を信頼性良く行うことができない。 In this state, the semiconductor device 9 upon mechanically connected to the circuit board 4, the stud bump 10 which can be brought into contact with the input and output electrodes 1 on the circuit board 4, the input and output electrodes 1 on the circuit board 4 unreachable will and the stud bump 10 is present, it is impossible to carry out electrical connection reliably. そこで、これらの高さの異なるスタッドバンプ10の高さを一定の許容範囲内に揃えるために、図3に示すように、レベリングステージ12を使用して1つの半導体装置9内全てのスタッドバンプ10を同時に押さえ付け、全てのスタッドバンプ10の高さを揃える。 Therefore, in order to align the heights of different stud bump 10 of these heights within a certain tolerance, as shown in FIG. 3, by using the leveling stage 12 all within a single semiconductor device 9 stud bump 10 simultaneously pressed, aligning the height of all of the stud bumps 10. 【0041】次に、図4(a)に示すように、レベリングを行った半導体装置9を、先に処理済みの異方導電性フィルム7を貼り付けた回路基板4上に位置決めして重ね合わせる。 Next, as shown in FIG. 4 (a), the semiconductor device 9 subjected to leveling, superimposed and positioned on the circuit board 4 was attached an anisotropic conductive film 7 treated previously . 【0042】最後に、加熱と加圧を同時に行って、図4 [0042] Finally, subjected to heat and pressure at the same time, as shown in FIG. 4
(b)に示すように、スタッドバンプ10の先端部と回路基板4上の入出力電極1との間の距離を導電性粒子6 (B), the conductive distance between the input and output electrodes 1 on the front end portion and the circuit board 4 of the stud bump 10 particles 6
の直径以下に維持した状態で絶縁性接着樹脂5を硬化させる。 While maintaining the diameter of less than curing the insulating adhesive resin 5. 【0043】このようにすることで、入出力電極1の基幹部の幅aよりも先端部の幅bの方が広くなっており、 [0043] In this manner, it has become wider towards the width b of the tip portion than the width a of the core portion of the input and output electrodes 1,
スタッドバンプ10は基幹部に実装されているので、実装時に入出力電極1に印加される荷重は分散されるようになる。 Since the stud bump 10 is mounted to the backbone portion, the load applied to the input and output electrodes 1 at the time of mounting will be distributed. これにより、半導体装置9に形成されたスタッドバンプ10の高さおよび回路基板4の入出力電極1の高さがある許容範囲でそれぞれ微妙に異なっていたり、 Accordingly, or they are subtly different from each with a tolerance of height and the height of the input and output electrodes 1 of the circuit board 4 of the stud bump 10 formed on the semiconductor device 9 is,
ピール強度の弱い入出力電極1を有する回路基板4に半導体装置9を実装しても、入出力電極1の先端が回路基板4から剥がれたり、剥がれた入出力電極1が半導体装置9に接触することがなくなる。 Even when mounting the semiconductor device 9 to the circuit board 4 with a weak output electrodes 1 of peel strength, peeled off the tip of the input and output electrodes 1 from the circuit board 4, the input-output electrode 1 peeling contacts the semiconductor device 9 it is eliminated. 【0044】したがって、半導体装置9に形成されたスタッドバンプ10と回路基板4に形成された入出力電極1との電気的接続不良の発生を抑えることができる。 [0044] Thus, it is possible to suppress the occurrences of poor electrical connection between the input and output electrodes 1 formed on the stud bump 10 and the circuit board 4 formed on the semiconductor device 9. 【0045】なお、入出力電極1は、図5に示すように、二点鎖線で示す突起電極10が実装される位置より先端側に、入出力電極1の基幹部の幅aよりも幅cの狭いくびれ部13を形成するようにしてもよい。 [0045] Incidentally, the input and output electrodes 1, as shown in FIG. 5, the distal end side than the position where the projection electrode 10 indicated by the two-dot chain line is mounted, the width c than the width a of the core portion of the input and output electrodes 1 it may be formed a narrow neck portion 13 of. 【0046】また、図6に示すように、突起電極が実装される位置より先端側に、入出力電極1が陥没して内層電極14と接続されたホール部15を形成するようにしてもよい。 Further, as shown in FIG. 6, the distal end side than the position at which the protruding electrodes are mounted, input and output electrodes 1 may be formed a hole portion 15 which is connected to the internal electrodes 14 and depressed . 【0047】さらに、図7に示すように、回路基板4の平面方向に対して所定の角度に屈曲された屈曲部1aを入出力電極1に形成し、この屈曲部1aを先端側にして突起電極10を実装してもよい。 [0047] Further, as shown in FIG. 7, to form a bent portion 1a which is bent at a predetermined angle with respect to the planar direction of the circuit board 4 to the input and output electrodes 1, and the bent portion 1a distally projecting it may be mounted electrode 10. 【0048】なお、回路基板4は、サブトラクティブ法でなく、めっきレジストを用いてめっきにより回路部分を形成するアディティブ法やセミアディティブ法でも形成してもよい。 [0048] The circuit board 4 is not a subtractive process, may be also formed by an additive method or semi-additive method to form a circuit section by plating using a plating resist. 【0049】また、半導体装置9に形成された突起電極10は、ワイヤボンディングでなく公知のめっき装置(図示せず)にて形成しためっきバンプであってもよい。 [0049] Further, protruding electrodes 10 formed on the semiconductor device 9 may be a plated bump formed by a known plating apparatus (not shown) instead of wire bonding. 【0050】さらに、導電性微粒子6の混入された異方導電性フィルム7を用いず、絶縁性接着樹脂5のみで固定するようにしてもよい。 [0050] Further, without using the anisotropic conductive film 7 that is mixed conductive particles 6, it may be fixed only by the insulating adhesive resin 5. 【0051】 【0052】 【0053】 【0054】 【0055】 【0056】 【0057】 【0058】 【0059】 【0060】 【0061】 【0062】 【0063】 【0064】 【0065】 【0066】 【0067】 【0068】 【0069】 【0070】 【0071】 【0072】 【0073】 【0074】 【発明の効果】以上のように、本発明によれば、半導体装置に形成された突起電極の高さおよび回路基板の入出力電極の高さが異なっていたり、ピール強度の弱い入出力電極を有する回路基板に半導体装置を実装しても、入出力電極の先端が回路基板から剥がれたり、剥がれた入出力電極が半導体装置に接触することがなくなるという有効な効果が得られる。 [0051] [0052] [0053] [0054] [0055] [0056] [0057] [0058] [0059] [0060] [0061] [0062] [0063] [0064] [0065] [0066] [0067 ] [0068] [0069] [0070] [0071] [0072] [0073] [0074] [as in the effects described above, according to the present invention, the height of the projecting electrodes formed on the semiconductor device and or have different heights of the input and output electrodes of the circuit board, even when mounting the semiconductor device on a circuit board having a weak input and output electrodes of peel strength, peeled off the tip of the input and output electrodes from the circuit board, peeling input and output electrode active effect is obtained that there is no possible contact with the semiconductor device. 【0075】これにより、半導体装置に形成された突起電極と回路基板に形成された入出力電極との電気的接続不良の発生を抑制することが可能になるというという有効な効果が得られる。 [0075] Thus, an effective effect is obtained that that it is possible to suppress the electrical connection defective of input and output electrodes formed on the projecting electrodes and the circuit board formed on the semiconductor device.

【図面の簡単な説明】 【図1】本発明の実施の形態1における入出力電極の形状の一例を示す平面図【図2】本発明の実施の形態1における異方導電性フィルムを回路基板に貼った状態を示す断面図【図3】本発明の実施の形態1におけるスタッドバンプの形成工程の一部を示す説明図【図4】本発明の実施の形態1における半導体装置と回路基板の異方導電性フィルムを使用した接合工程および接合状態を連続して示す断面図【図5】本発明の実施の形態1における入出力電極の形状の他の一例を示す平面図【図6】本発明の実施の形態1における入出力電極の形状のさらに他の一例を示す断面図【図7】本発明の実施の形態1における入出力電極の形状のさらに他の一例を示す平面図【図8】従来の第1の技術における半導体装置と回路 BRIEF DESCRIPTION OF THE DRAWINGS [Figure 1] The anisotropic conductive film of the circuit board in the first embodiment of the plan view Figure 2 the present invention showing an example of the shape of the input and output electrodes in the first embodiment of the present invention to put a cross-sectional view illustrating a state [3] of the semiconductor device and the circuit board in the first embodiment of the present explanatory view showing a part of a stud bump formation process in the first embodiment of the invention the present invention; FIG sectional view plan view showing another example of the shape of the input and output electrodes in the first embodiment of the present invention; FIG 6 is a book showing a bonding step and the bonding state using anisotropic conductive film continuously plan view showing still another example of the shape of the input and output electrodes in the first embodiment of the cross section 7 the invention showing a still another example of the shape of the input and output electrodes in the first embodiment of the invention Figure 8 the semiconductor device and the circuit in a conventional first technique 基板の接合状態の要部を示す断面図【図9】従来の第2の技術における半導体装置と回路基板の接合状態の要部を示す断面図【図10】従来の技術における半導体装置と回路基板の接合状態の要部を示す断面図【符号の説明】 1 入出力電極1a 屈曲部4 回路基板5 絶縁性接着樹脂(接合部材) 7 異方導電性フィルム(接合部材) 9 半導体装置10 突起電極(スタッドバンプ) 13 くびれ部14 内層電極15 ホール部 Cross-sectional view showing the main portion of the bonding state of the substrate 9 conventional second cross-sectional view showing the main portion of the bonding state of the semiconductor device and the circuit board in the art [10] The semiconductor device and the circuit board of the prior art sectional view [Reference numerals] 1 output electrode 1a bent portion 4 the circuit board 5 insulating adhesive resin (bonding member) 7 anisotropic conductive film (bonding member) 9 semiconductor device 10 protruding electrodes showing an essential part of the bonding state of (bump) 13 constricted portion 14 inner electrode 15 hole portion

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平6−232205(JP,A) 特開 平3−16147(JP,A) 特開 昭53−8566(JP,A) 特開 平1−152637(JP,A) 特開 平4−82241(JP,A) 特開 平9−82755(JP,A) 国際公開98/18161(WO,A1) (58)調査した分野(Int.Cl. 7 ,DB名) H01L 21/60 H01L 21/92 H01L 23/12 H05K 1/18 ────────────────────────────────────────────────── ─── continued (56) references of the front page Patent flat 6-232205 (JP, a) JP flat 3-16147 (JP, a) JP Akira 53-8566 (JP, a) JP flat 1- 152637 (JP, a) JP flat 4-82241 (JP, a) JP flat 9-82755 (JP, a) WO 98/18161 (WO, A1) (58 ) investigated the field (Int.Cl. 7 , DB name) H01L 21/60 H01L 21/92 H01L 23/12 H05K 1/18

Claims (1)

  1. (57)【特許請求の範囲】 【請求項1】複数の突起電極が形成された半導体装置と、 絶縁性および接着性を有する接合部材と、 基幹部の幅よりも先端部の幅の方が広くなった複数の入出力電極が形成され、前記入出力電極に対応した前記突起電極がこの入出力電極の基幹部を押圧するように前記半導体装置が実装される回路基板とからなることを特徴とする半導体ユニット。 (57) and the semiconductor device Claims 1. A plurality of projection electrodes are formed, and the bonding member having an insulating property and adhesiveness, the direction of width of the tip portion than the width of the core portion a plurality of input and output electrodes becomes wider is formed, characterized in that said protruding electrode corresponding to the input and output electrodes are composed of a circuit board on which the semiconductor device is mounted so as to press the core portion of the input and output electrodes semiconductor unit to be. 【請求項2】複数の突起電極が形成された半導体装置と、 絶縁性および接着性を有する接合部材と、 基幹部の幅よりも幅の狭いくびれ部が設けられた複数の入出力電極が形成され、前記入出力電極に対応した前記突起電極が前記くびれ部の方を先端側にしてこの入出力電極の基幹部を押圧するように前記半導体装置が実装される回路基板とからなることを特徴とする半導体ユニット。 A semiconductor device wherein a plurality of protruding electrodes formed thereon, and a joint member having an insulating property and adhesiveness, a plurality of input and output electrodes narrow constriction in width than the width provided in the trunk portion formed It is, characterized in that the said projecting electrodes corresponding to the input and output electrodes are composed of a circuit board on which the semiconductor device is mounted so as to press the core portion of the input and output electrodes in the distal end side toward the constricted portion semiconductor unit to be. 【請求項3】複数の突起電極が形成された半導体装置と、 絶縁性および接着性を有する接合部材と、 陥没して内層電極と接続されたホール部が設けられた複数の入出力電極が形成され、前記入出力電極に対応した前記突起電極が前記ホール部の方を先端側にしてこの入出力電極を押圧するように前記半導体装置が実装される回路基板とからなることを特徴とする半導体ユニット。 A semiconductor device wherein a plurality of protruding electrodes formed thereon, and a joint member having an insulating property and adhesion, a plurality of input and output electrodes hole portion which is connected to the internal electrodes are provided with depressions are formed It is a semiconductor in which the input and output electrodes the protruding electrode corresponding to is characterized in that it consists of a circuit board on which the semiconductor device is mounted so as to press the input and output electrodes in the distal end side towards the said hole portion unit. 【請求項4】複数の突起電極が形成された半導体装置と、 絶縁性および接着性を有する接合部材と、 平面方向に向かって所定の角度に屈曲された屈曲部が設けられた複数の入出力電極が形成され、前記入出力電極に対応した前記突起電極が前記屈曲部の方を先端側にしてこの入出力電極を押圧するように前記半導体装置が実装される回路基板とからなることを特徴とする半導体ユニット。 A semiconductor device wherein a plurality of protruding electrodes formed thereon, and a joint member having an insulating property and adhesion, a plurality of input and output the bent portion which is bent at a predetermined angle is provided the plane direction electrodes are formed, characterized in that the said projecting electrodes corresponding to the input and output electrodes are composed of a circuit board on which the semiconductor device is mounted so as to press the input and output electrodes in the distal end side toward the bent portion semiconductor unit to be.
JP14899198A 1998-05-29 1998-05-29 Semiconductor unit Expired - Fee Related JP3446608B2 (en)

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