JP2002134558A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

Info

Publication number
JP2002134558A
JP2002134558A JP2000326106A JP2000326106A JP2002134558A JP 2002134558 A JP2002134558 A JP 2002134558A JP 2000326106 A JP2000326106 A JP 2000326106A JP 2000326106 A JP2000326106 A JP 2000326106A JP 2002134558 A JP2002134558 A JP 2002134558A
Authority
JP
Japan
Prior art keywords
semiconductor device
conductive film
anisotropic conductive
semiconductor chip
reinforcing member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000326106A
Other languages
Japanese (ja)
Inventor
Tomohisa Motomura
知久 本村
Hiroyuki Hirai
浩之 平井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000326106A priority Critical patent/JP2002134558A/en
Publication of JP2002134558A publication Critical patent/JP2002134558A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • H01L2224/29018Shape in side view comprising protrusions or indentations
    • H01L2224/29019Shape in side view comprising protrusions or indentations at the bonding interface of the layer connector, i.e. on the surface of the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • H01L2224/32058Shape in side view being non uniform along the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that does not cause peeling or an electrical connection failure between a chip and a board even if the semiconductor chip size is large, and to provide a method for manufacturing the semiconductor device. SOLUTION: After the semiconductor chip 4 is bonded to a wiring board 11 through an anisotropic conductive film (ACF) 3, a reinforcing material 7 is arranged in the proximity of the top surface of the anisotropic conductive film (ACF) 3 and the corners of a chip 4 housing 41 arranged on the top surface of this film 3. Since this reinforcing material 7 is arranged so as to have a stress dispersion shape typified by a fillet shape, even if a flexural stress is acted on the semiconductor device, this stress is dispersed by the reinforcing material, and stress concentration to the corners of the semiconductor chip 4 can be prevented, whereby connection failures between the semiconductor chip 4 and the wiring board 11 can be prevented in advance.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置に係り、
更に詳細にはフリップチップ実装工法で製造されるフリ
ップチップ型半導体装置とその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
More specifically, the present invention relates to a flip-chip type semiconductor device manufactured by a flip-chip mounting method and a method of manufacturing the same.

【0002】[0002]

【従来の技術】従来より、半導体装置の一つとして異方
性導電フィルム(以下、「ACF」と略すことがあ
る。)を介して半導体チップを基板上に直接接続して配
設したフリップチップ型半導体装置が広く製造されてい
る。
2. Description of the Related Art Conventionally, as one of the semiconductor devices, a flip chip in which a semiconductor chip is directly connected to a substrate via an anisotropic conductive film (hereinafter sometimes abbreviated as “ACF”) is provided. Semiconductor devices are widely manufactured.

【0003】図12は代表的なフリップチップ型半導体
装置の製造工程を表わした図である。この製造工程で
は、まず、図12(a)のように半導体ベアチップ10
1の電極上に金ボールバンプ102を形成する。その一
方で回路基板104の電極105を含む一面に直径3〜
5μmの導電粒子、即ちプラスチック製粒子表面にニッ
ケルや金などの金属をメッキしたものを含有する樹脂フ
ィルム103を仮圧着して固定し、上記金ボールバンプ
102と回路基板104の電極105の位置合わせを行
なう。
FIG. 12 is a diagram showing a manufacturing process of a typical flip-chip type semiconductor device. In this manufacturing process, first, as shown in FIG.
The gold ball bump 102 is formed on one electrode. On the other hand, one surface of the circuit board 104 including the electrode 105 has a diameter of 3 to
A resin film 103 containing 5 μm conductive particles, that is, a plastic particle surface plated with a metal such as nickel or gold, is temporarily compressed and fixed, and the gold ball bump 102 and the electrode 105 of the circuit board 104 are aligned. Perform

【0004】次いで半導体ベアチップ101を回路基板
104側に加圧加熱して前記ACF103を硬化させる
ことにより金ボールバンプ102を介して回路基板10
4と電極105との間が電気的に接続された半導体装置
が得られる。
Next, the semiconductor bare chip 101 is pressed and heated toward the circuit board 104 to harden the ACF 103, so that the circuit board 10
Thus, a semiconductor device in which the electrode 4 and the electrode 105 are electrically connected is obtained.

【0005】[0005]

【発明が解決しようとする課題】しかし、このACF1
03は高温高湿の環境下で吸湿させても樹脂の密着強度
や硬化後の硬度が大きく劣化することはないが、例え
ば、マイナス55℃、と125℃との間を300サイク
ル行き来させる温度サイクルテストを行なうと、各部材
の線熱膨張係数の差により反りが生じ、図12(d)の
ように半導体ベアチップ101とACF103との間で
剥離が生じ、金ボールバンプ102と回路基板104の
電極105との接続が破壊されるという問題が生じた。
However, this ACF1
03 is a temperature cycle in which 300 cycles between −55 ° C. and 125 ° C. are performed, although the adhesion strength of the resin and the hardness after curing are not significantly deteriorated even when moisture is absorbed in a high temperature and high humidity environment. When the test is performed, warping occurs due to the difference in linear thermal expansion coefficient of each member, and peeling occurs between the semiconductor bare chip 101 and the ACF 103 as shown in FIG. There is a problem that the connection with the terminal 105 is broken.

【0006】また縦×横寸法が8mm×8mmの比較的
小型の半導体ベアチップ試験片を用いた温度サイクルテ
ストでは不具合は生じないが、大型の試験片、例えば1
6mm×16mmの半導体ベアチップ試験片を用いた場
合には図12(d)に示すように半導体ベアチップ10
1とACF103との間で剥離が生じ、金ボールバンプ
102と回路基板104の電極105との間の接続が破
壊される現象が100%の確率で発生するという問題が
ある。
Although a temperature cycle test using a relatively small semiconductor bare chip test piece measuring 8 mm × 8 mm in length and width does not cause any problem, a large test piece such as 1
When a 6 mm × 16 mm semiconductor bare chip test piece is used, as shown in FIG.
There is a problem that the peeling occurs between the ACF 103 and the ACF 103 and the connection between the gold ball bump 102 and the electrode 105 of the circuit board 104 is broken with a 100% probability.

【0007】この接続破壊は反りによる変形が最大とな
る半導体チップのコーナー部で生じることが分かってい
る。そこでこの現象を防止するために半導体ベアチップ
に形成する金ボールバンプをコーナー部の端から2mm
以上内側の位置に形成する提案も成されているが、この
ように金ボールバンプの形成位置を制限すると使用でき
る半導体が制約されたり、集積度の向上が妨げられると
いう問題があった。
It is known that this connection destruction occurs at the corner of the semiconductor chip where the deformation due to the warp is maximum. Therefore, in order to prevent this phenomenon, the gold ball bump formed on the semiconductor bare chip is placed 2 mm from the end of the corner.
Although proposals have been made to form the gold ball bumps on the inner side as described above, there is a problem in that when the formation positions of the gold ball bumps are limited, usable semiconductors are restricted and improvement in the degree of integration is hindered.

【0008】本発明は上記従来の問題を解決するために
なされた発明である。即ち、本発明は、半導体チップの
サイズを大きくしてもチップと基板との間で剥離した
り、チップと基板との間での電気的な接続不良が生じる
ことのない半導体装置やそのような半導体装置の製造方
法を提供することを目的とする。
The present invention has been made to solve the above-mentioned conventional problems. That is, the present invention provides a semiconductor device or a semiconductor device in which peeling between the chip and the substrate does not occur even when the size of the semiconductor chip is increased, and in which electrical connection failure between the chip and the substrate does not occur. It is an object to provide a method for manufacturing a semiconductor device.

【0009】[0009]

【課題を解決するための手段】本発明の半導体装置は、
絶縁性基板と、前記絶縁性基板上に配設された配線層
と、前記配線層上に配設された異方性導電フィルム層
と、前記異方性導電フィルム層上に配設された半導体チ
ップと、前記半導体チップ上に配設された電極板と、前
記異方性導電フィルム層内において前記配線層と前記電
極板とを導通させる金ボールバンプと、前記異方性導電
フィルム層と前記半導体チップのコーナー部との間に配
設され、応力分散型形状を備えた補強部材とを具備す
る。
According to the present invention, there is provided a semiconductor device comprising:
An insulating substrate, a wiring layer provided on the insulating substrate, an anisotropic conductive film layer provided on the wiring layer, and a semiconductor provided on the anisotropic conductive film layer A chip, an electrode plate disposed on the semiconductor chip, a gold ball bump for conducting the wiring layer and the electrode plate in the anisotropic conductive film layer, the anisotropic conductive film layer, A reinforcing member provided between the corner portion of the semiconductor chip and the stress-dispersing shape.

【0010】また本発明の半導体装置製造方法は、絶縁
性基板上に配線層を形成する工程と、前記配線層上に異
方性導電性フィルム層を形成する工程と、半導体チップ
上に電極板を形成する工程と、前記電極板上に金ボール
バンプを形成する工程と、前記絶縁性基板上の配線層と
半導体チップ上の前記電極板とを位置合わせする工程
と、前記絶縁性基板と前記半導体チップとを加圧下に加
熱して前記金ボールバンプを前記異方性導電フィルムを
貫通させ、前記配線層と前記電極板とを接続する工程
と、前記半導体チップのコーナー部と前記異方性導電フ
ィルムとの間に補強部材を塗布する工程と、前記補強部
材を硬化させる工程とを具備する。
[0010] The method of manufacturing a semiconductor device according to the present invention further comprises a step of forming a wiring layer on an insulating substrate, a step of forming an anisotropic conductive film layer on the wiring layer, and a step of forming an electrode plate on the semiconductor chip. Forming a gold ball bump on the electrode plate; aligning a wiring layer on the insulating substrate with the electrode plate on a semiconductor chip; and Heating the semiconductor chip under pressure to penetrate the gold ball bumps through the anisotropic conductive film and connecting the wiring layer and the electrode plate; and A step of applying a reinforcing member between the conductive member and the conductive film; and a step of curing the reinforcing member.

【0011】上記発明において、前記応力分散型形状と
は、前記異方性導電フィルムと前記半導体チップとの間
に作用する応力を分散することができる形状をいい、具
体的にはフィレット型の垂直断面を示す形状が挙げられ
る。
In the above invention, the stress-dispersed shape refers to a shape capable of dispersing a stress acting between the anisotropic conductive film and the semiconductor chip, and specifically, a fillet-shaped vertical shape. A shape showing a cross section is exemplified.

【0012】ここで「フィレット型」とは直交する二本
の直線を滑らかに結ぶ凹型に窪んだ曲線、例えば弧や放
物線状に窪んだ形状をいう。
Here, the "fillet type" refers to a concavely concave curve that smoothly connects two orthogonal straight lines, for example, an arc or a parabolic concave shape.

【0013】上記発明において、前記応力分散型形状の
例として、真上から見たときの平面形状が、前記異方性
導電フィルム層のコーナー部を中心とする中心角270
度の扇型形状が挙げられる。
In the above invention, as an example of the stress dispersion type shape, when viewed from directly above, the planar shape has a center angle of 270 around a corner of the anisotropic conductive film layer.
The fan shape of the degree is mentioned.

【0014】上記発明において、前記補強部材は、前記
異方性導電フィルムと同じ物性値を有する材料で形成さ
れていることが好ましい。
In the above invention, it is preferable that the reinforcing member is formed of a material having the same physical properties as the anisotropic conductive film.

【0015】上記発明において、前記補強部材が、前記
異方性導電フィルムと一体化されていてもよい。
In the above invention, the reinforcing member may be integrated with the anisotropic conductive film.

【0016】上記発明において、前記補強部材が、前記
異方性導電フィルムの上部に形成された枠状の凹部によ
り構成されていてもよい。
In the above invention, the reinforcing member may be constituted by a frame-shaped concave portion formed on an upper part of the anisotropic conductive film.

【0017】上記発明において、前記補強部材が、前記
異方性導電フィルム上面と前記半導体チップ側面との間
にわたって配設された部材であってもよい。
In the above invention, the reinforcing member may be a member disposed between an upper surface of the anisotropic conductive film and a side surface of the semiconductor chip.

【0018】上記発明において、前記補強部材が、前記
異方性導電フィルムと一体的に成形されていてもよい。
In the above invention, the reinforcing member may be formed integrally with the anisotropic conductive film.

【0019】上記発明において、前記異方性導電部材
が、前記半導体チップと嵌合する凹部を備えており、前
記補強部材が、前記異方性導電フィルムと前記半導体チ
ップとの隙間に配設されていてもよい。
In the above invention, the anisotropic conductive member has a concave portion to be fitted to the semiconductor chip, and the reinforcing member is disposed in a gap between the anisotropic conductive film and the semiconductor chip. May be.

【0020】本発明では、前記異方性導電フィルムと前
記半導体チップのコーナー部との間に応力分散型形状を
備えた補強部材を配設したので、半導体チップや異方性
導電フィルムに曲げ応力が作用した場合にも応力がセラ
ミックのコーナー部に集中するのが防止され、曳いては
配線層と電極板との間の電気的接続が破壊するのが防止
される。
In the present invention, since a reinforcing member having a stress-dispersive shape is provided between the anisotropic conductive film and the corner of the semiconductor chip, bending stress is applied to the semiconductor chip and the anisotropic conductive film. Prevents the stress from concentrating on the corners of the ceramics, thereby preventing the electrical connection between the wiring layer and the electrode plate from being broken.

【0021】前記補強部材が、フィレット型の垂直断面
を示す形状や、前記半導体チップのコーナー部を中心と
する中心角270度の扇型平面形状を備える場合には、
半導体チップのコーナー部に集中し易い応力を分散させ
ることができるので、半導体チップのコーナー部への応
力の集中を効果的に防止することができ、曳いては配線
層と電極板との間の電気的接続が破壊するのが防止され
る。
In the case where the reinforcing member has a fillet-shaped vertical cross section or a fan-shaped planar shape having a center angle of 270 degrees centering on a corner of the semiconductor chip,
Since the stress that tends to concentrate on the corner of the semiconductor chip can be dispersed, the concentration of stress on the corner of the semiconductor chip can be effectively prevented, and the gap between the wiring layer and the electrode plate can be effectively pulled. Electrical connections are prevented from breaking.

【0022】前記補強部材が、前記異方性導電フィルム
と同じ物性値を有する材料で形成したり、前記異方性導
電フィルムと一体化されている場合には、前記異方性導
電フィルムと補強部材との間に応力が作用しにくいの
で、より効果的に半導体チップのコーナー部に集中し易
い応力を分散させることができる。
When the reinforcing member is formed of a material having the same physical property value as the anisotropic conductive film, or when the reinforcing member is integrated with the anisotropic conductive film, the reinforcing member and the anisotropic conductive film are reinforced. Since stress does not easily act between members, stress that tends to concentrate on corners of the semiconductor chip can be more effectively dispersed.

【0023】前記補強部材が、前記異方性導電フィルム
の上部に形成された枠状の凹部により構成されている場
合には補強部材を形成する手間を省くことができる。
When the reinforcing member is constituted by a frame-shaped concave portion formed on the upper part of the anisotropic conductive film, the labor for forming the reinforcing member can be omitted.

【0024】前記補強部材が、前記異方性導電フィルム
と一体的に成形されている場合には補強部材を形成する
手間を省くことができる。
When the reinforcing member is formed integrally with the anisotropic conductive film, the labor for forming the reinforcing member can be omitted.

【0025】前記異方性導電部材が前記半導体チップと
嵌合する枠状の凹部を備えており、前記補強部材が、前
記異方性導電フィルムと前記半導体チップとの隙間に配
設されている場合には、容易に加工することができる。
The anisotropic conductive member has a frame-shaped concave portion to be fitted to the semiconductor chip, and the reinforcing member is disposed in a gap between the anisotropic conductive film and the semiconductor chip. In that case, it can be easily processed.

【0026】[0026]

【発明の実施の形態】(第1の実施形態)以下、本発明
の第1の実施形態に係る半導体装置について説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A semiconductor device according to a first embodiment of the present invention will be described below.

【0027】図1は本実施形態に係る半導体装置の製造
工程を示したフローチャートであり、図2〜図4は製造
途中の本実施形態に係る半導体装置の垂直断面図であ
る。
FIG. 1 is a flowchart showing the manufacturing process of the semiconductor device according to the present embodiment, and FIGS. 2 to 4 are vertical sectional views of the semiconductor device according to the present embodiment in the course of manufacturing.

【0028】本実施形態に係る半導体装置を製造するに
は、まず図2(a)に示すように絶縁性基板1の上に銅
箔2が積層された銅張基板10を用意し、この銅張基板
10の銅箔2上に図示しないマスキングを施した後、エ
ッチング処理などによりパターンニングを行ない(ステ
ップ1)、絶縁性基板1の上に配線層21が形成された
配線基板11を形成する。
In order to manufacture the semiconductor device according to the present embodiment, first, as shown in FIG. 2A, a copper-clad board 10 having a copper foil 2 laminated on an insulating board 1 is prepared. After masking (not shown) is performed on the copper foil 2 of the stretched substrate 10, patterning is performed by an etching process or the like (Step 1) to form the wiring substrate 11 having the wiring layer 21 formed on the insulating substrate 1. .

【0029】次にこの配線基板11の配線層21を形成
した面の上に異方性導電フィルム(ACF)3を仮圧着
して(ステップ2)、積層体12を得る。この異方性導
電フィルム(ACF)3は、例えばエポキシ樹脂などの
熱硬化性の絶縁性樹脂中に導電性微粒子を分散させたも
のである。
Next, an anisotropic conductive film (ACF) 3 is temporarily pressed on the surface of the wiring board 11 on which the wiring layer 21 is formed (Step 2), and a laminate 12 is obtained. The anisotropic conductive film (ACF) 3 is obtained by dispersing conductive fine particles in a thermosetting insulating resin such as an epoxy resin.

【0030】この異方性導電フィルムの例としては、例
えばソニーケミカル株式会社製のTJ107−50(商
品名)や日立化成株式会社製のFC−262B(商品
名)やFC−212B(商品名)等のようなものが挙げ
られる。
Examples of the anisotropic conductive film include TJ107-50 (trade name) manufactured by Sony Chemical Co., Ltd., FC-262B (trade name) and FC-212B (trade name) manufactured by Hitachi Chemical Co., Ltd. And the like.

【0031】次いでこの積層体12に対して半導体チッ
プ4を位置合わせする(ステップ3)。
Next, the semiconductor chip 4 is positioned with respect to the laminated body 12 (step 3).

【0032】この半導体チップ4はセラミック製のハウ
ジング41内に集積回路(図示省略)が組み込まれてお
り、ハウジング41の下面側に配設された電極板5,
5,…と集積回路とが内部で結線されている。また、こ
の半導体チップ4の電極板5,5,…上にはそれぞれ金
ボールバンプ6,6,…が形成去れている。
The semiconductor chip 4 has an integrated circuit (not shown) built in a housing 41 made of ceramic, and has an electrode plate 5 provided on the lower surface side of the housing 41.
, And the integrated circuit are internally connected. Also, gold ball bumps 6, 6,... Are formed on the electrode plates 5, 5,.

【0033】半導体チップ4の電極板5,5,…が配線
層21の配線パターンと対向するように位置合わせが完
了したら、加熱したプレスにて加圧して加熱と加圧とを
同時に行なう(ステップ4)。
When the positioning is completed so that the electrode plates 5, 5,... Of the semiconductor chip 4 face the wiring pattern of the wiring layer 21, pressure is applied by a heated press to perform heating and pressing simultaneously (step). 4).

【0034】このプレス時の熱により、ACF3が軟化
する。この状態で金ボールバンプ6,6,…が加圧され
るので、この金ボールバンプ6,6,…がACF3を貫
通する。ACF3を貫通した金ボールバンプ6,6,…
の幾つかは直接配線層21に当接し、金ボールバンプ
6,6,…の他の幾つかはACF3導電性粒子31,3
1,…を介して間接的に配線層21に当接する。このよ
うにして得られた積層体13では金ボールバンプ6,
6,…や更に導電性粒子31,31,…を介して電極板
5,5,…と配線層21,21,…との間を電気的に接
続させる。更にプレス時の熱によりACF3は硬化し、
硬化した積層体13が得られる。
The heat generated during the pressing softens the ACF 3. In this state, the gold ball bumps 6, 6,... Penetrate the ACF 3 because the gold ball bumps 6, 6,. Gold ball bumps penetrating ACF3 6, 6, ...
Some directly contact the wiring layer 21, and some of the gold ball bumps 6, 6,...
Indirectly contact with the wiring layer 21 via 1,. In the laminate 13 thus obtained, the gold ball bumps 6,
, And the conductive layers 31, 31, and further, the electrode plates 5, 5, ... and the wiring layers 21, 21, ... are electrically connected. In addition, ACF3 is cured by heat during pressing,
A cured laminate 13 is obtained.

【0035】次いで、この積層体13のうち、半導体チ
ップ4のコーナー部とACF3の上面との間にわたって
補強部材7を塗布する(ステップ5)。このとき塗布す
る補強部材7は最終的に硬化後のACF3を構成する樹
脂と同じ物性値を有するものであることが好ましい。最
終的な物性値が補強部材7とACF3とで異なると、補
強部材7とACF3との界面で応力が作用するからであ
る。
Next, the reinforcing member 7 is applied between the corners of the semiconductor chip 4 and the upper surface of the ACF 3 in the laminate 13 (Step 5). The reinforcing member 7 applied at this time preferably has the same physical property value as the resin constituting the ACF 3 finally cured. If the final physical property values are different between the reinforcing member 7 and the ACF 3, stress acts on the interface between the reinforcing member 7 and the ACF 3.

【0036】補強部材7は応力分散型形状になるように
形成する。ここで「応力分散型形状」とは、前記異方性
導電フィルムと前記半導体チップとの間に作用する応力
を分散することができる形状をいう。具体的には図3に
示したようなフィレット型の垂直断面を示す形状が挙げ
られる。ここで「フィレット型」とは直交する二本の直
線を滑らかに結ぶ凹型に窪んだ曲線、例えば弧や放物線
状に窪んだ形状をいう。
The reinforcing member 7 is formed so as to have a stress distribution type shape. Here, the “stress-dispersed shape” refers to a shape capable of dispersing stress acting between the anisotropic conductive film and the semiconductor chip. Specifically, a shape showing a vertical cross section of a fillet type as shown in FIG. 3 can be given. Here, the “fillet type” refers to a concavely concave curve that smoothly connects two orthogonal straight lines, for example, an arc or a parabolic concave shape.

【0037】補強部材7をこのフィレット型形状に形成
するには、例えば、液状タイプの未硬化の樹脂ペースト
を補強部材7として、積層体13のチップコーナー部分
(図4に示したような位置)にディスペンサーを用い
て、手作業で塗布し、しかる後、125℃のオーブン中
で樹脂ペースト内のエポキシ主材を硬化剤が反応して硬
化する方法が挙げられる。この方法では、フィレット形
状は樹脂の粘性流動により自然に形成される。
In order to form the reinforcing member 7 into this fillet type shape, for example, a liquid corner type uncured resin paste is used as the reinforcing member 7 and the chip corner portion of the laminate 13 (position as shown in FIG. 4). A method of applying the resin manually by using a dispenser, and then curing the epoxy main material in the resin paste by reacting with a curing agent in a 125 ° C. oven. In this method, the fillet shape is formed naturally by viscous flow of the resin.

【0038】また、この補強部材7を形成するには、例
えば、東芝ケミカル株式会社製の異方性導電ペースト
(型番:TAP−0211C)を使用するのが好まし
い。この補強部材7を形成する材料としては、線膨張
率、ヤング率、ガラス転移温度(Tg)など、その物性
値ができるだけACF3と近いものが望ましい。
In order to form the reinforcing member 7, for example, it is preferable to use an anisotropic conductive paste (model number: TAP-0211C) manufactured by Toshiba Chemical Corporation. As a material for forming the reinforcing member 7, a material having physical properties as close as possible to ACF3, such as a coefficient of linear expansion, a Young's modulus, and a glass transition temperature (Tg), is desirable.

【0039】以上説明したように、本実施形態に係る半
導体装置では、半導体チップのセラミックハウジング4
1のコーナー部とACF3上面との間にフィレット型の
断面形状を有する補強部材7を配設したので、半導体装
置に曲げ応力が作用したときでも応力がセラミックハウ
ジング41のコーナー部とこれに隣接するACF3上面
との間に集中するのが防止される。そしてその結果、半
導体チップ4とACF3との剥離が防止され、電極板
5,5,…と配線層21,21,…との接続信頼性が保
たれる。
As described above, in the semiconductor device according to the present embodiment, the ceramic housing 4 of the semiconductor chip is used.
Since the reinforcing member 7 having a fillet-shaped cross-sectional shape is disposed between the corner portion of the ceramic housing 41 and the upper surface of the ACF 3, even when a bending stress is applied to the semiconductor device, the stress is adjacent to the corner portion of the ceramic housing 41 and the adjacent portion. Concentration with the upper surface of the ACF 3 is prevented. As a result, separation of the semiconductor chip 4 from the ACF 3 is prevented, and the connection reliability between the electrode plates 5, 5,... And the wiring layers 21, 21,.

【0040】フィレット形状を備えた補強部材7が半導
体チップ4のコーナー部分の導電粒子を含んだ異方性導
電フィルム(ACF)3に集中する応力を分散させて半
導体チップ4と異方性導電フィルム(ACF)3との界
面の剥離を防止できた。
The reinforcing member 7 having a fillet shape disperses the stress concentrated on the anisotropic conductive film (ACF) 3 containing the conductive particles at the corners of the semiconductor chip 4 to disperse the stress on the semiconductor chip 4 and the anisotropic conductive film. The separation of the interface with (ACF) 3 was prevented.

【0041】また、半導体チップのサイズが縦×横=1
6mm×16mm以上の大きさであり、かつ、半導体チ
ップのコーナー部分に配置されている電極板が半導体チ
ップのコーナー部から2mm以内の距離に配設されてい
る半導体チップを用いたフリップチップ実装のバンプ接
続の信頼性が向上し、実用可能にすることができる。
The size of the semiconductor chip is length × width = 1.
Flip-chip mounting using a semiconductor chip having a size of 6 mm × 16 mm or more and an electrode plate disposed at a corner portion of the semiconductor chip within a distance of 2 mm or less from the corner portion of the semiconductor chip. The reliability of the bump connection is improved, and the bump connection can be made practical.

【0042】(実施例)図2のように、縦×横=16m
m×16mm、厚さ625μmの半導体ベアチップ4の
電極板5上に直径65μm、高さ80μmの金ボールバ
ンプ6を形成した。
(Embodiment) As shown in FIG. 2, length × width = 16 m
A gold ball bump 6 having a diameter of 65 μm and a height of 80 μm was formed on the electrode plate 5 of the semiconductor bare chip 4 having a size of m × 16 mm and a thickness of 625 μm.

【0043】その一方、BTレジン材(Tg=180
℃、線膨張係数=1.5×10−5/℃、ヤング率=
2.4×10MPa)からなる絶縁性基板1のニッケ
ル金メッキされた銅からなる配線層21を含む一面に導
電粒子を含有した異方性導電フィルム(ACF)3(型
番:TJ107、ソニーケミカル製、Tg=144℃、
線膨張係数=2.8×10−5/℃、ヤング率=4×1
MPa)を仮圧着して固定し、上記金ボールバンプ
6と絶縁性基板1の配線層21との位置合わせを行な
い、次に半導体ベアチップ4を絶縁性基板1側に加熱し
ながら加圧して導電粒子を含有した異方性導電フィルム
(ACF)3を硬化させることにより図2(e)に示す
ような金ボールバンプ6によるフリップチップ接続を形
成した。
On the other hand, a BT resin material (Tg = 180
° C, coefficient of linear expansion = 1.5 × 10 −5 / ° C, Young's modulus =
Anisotropic conductive film (ACF) 3 (model number: TJ107, Sony Chemical Inc.) containing conductive particles on one surface including wiring layer 21 made of nickel-gold plated copper on insulating substrate 1 made of 2.4 × 10 4 MPa) Manufactured, Tg = 144 ° C,
Linear expansion coefficient = 2.8 × 10 −5 / ° C., Young's modulus = 4 × 1
0 3 MPa) is fixed by temporary compression bonding, the above-mentioned gold ball bumps 6 are aligned with the wiring layer 21 of the insulating substrate 1, and then the semiconductor bare chip 4 is pressed against the insulating substrate 1 while heating. By curing the anisotropic conductive film (ACF) 3 containing conductive particles by the above method, a flip-chip connection by the gold ball bumps 6 as shown in FIG. 2E was formed.

【0044】図2(e)のACF3を用いたフリップチ
ップ接続を行なった後に図3及び図4のように半導体チ
ップ4のコーナー部分に液状の樹脂(型番:TAP−0
211C、東芝ケミカル社製、Tg=145℃、線膨張
係数3.7×10−5/℃、ヤング率=8.5×10
MPa、粘度=80Pas)を塗布し、125℃で15
時間加熱して樹脂を硬化させてフィレット状の補強部材
7を形成した。図4は半導体装置を上から見た図であ
る。この補強部材7を形成した後に試験片を温度サイク
ル試験に投入したところ、接続が維持できることが判明
した。初期での接続抵抗の平均値(N=64)は1バン
プ当り2.5mΩであったが、試験後は7.9mΩであ
り、良好な結果が得られた。
After the flip-chip connection using the ACF 3 shown in FIG. 2E is performed, a liquid resin (model number: TAP-0) is applied to the corners of the semiconductor chip 4 as shown in FIGS.
211C, manufactured by Toshiba Chemical Co., Ltd., Tg = 145 ° C., coefficient of linear expansion 3.7 × 10 −5 / ° C., Young's modulus = 8.5 × 10 3
MPa, viscosity = 80 Pas) and apply at 125 ° C. for 15
The resin was cured by heating for a time to form a fillet-shaped reinforcing member 7. FIG. 4 is a view of the semiconductor device as viewed from above. When the test piece was put into a temperature cycle test after forming the reinforcing member 7, it was found that the connection could be maintained. The average value of the connection resistance at the initial stage (N = 64) was 2.5 mΩ per bump, but after the test was 7.9 mΩ, and a good result was obtained.

【0045】(比較例)一方、前述のように条件が12
5℃/−55℃/300サイクルの温度サイクル試験に
投入すると図12(d)のように反りが生じ、縦×横=
16mm×16mmの半導体ベアチップに対しては試験
終了後に接続不良が生じた。また、接続不良は反りによ
る形状変化の最も大きい半導体チップのコーナー部分で
生じていた。このため、半導体ベアチップのコーナー部
分に金ボールバンプを形成しない制限領域を設けること
が必要となり、その長さLは2mm以上必要であり、使
用できる半導体の種類や大きさが大幅に制限されること
が判明した。
(Comparative Example) On the other hand, as described above,
When it is put into a temperature cycle test of 5 ° C./−55° C./300 cycles, warpage occurs as shown in FIG.
A connection failure occurred on a 16 mm × 16 mm semiconductor bare chip after the test was completed. In addition, the connection failure occurred at the corner of the semiconductor chip where the change in shape due to warpage was the largest. For this reason, it is necessary to provide a restricted area where no gold ball bump is formed at the corner of the semiconductor bare chip, and its length L is required to be 2 mm or more, and the type and size of the semiconductor that can be used are greatly restricted. There was found.

【0046】なお、本発明は上記実施形態に制限される
ものではない。例えば、上記実施形態では、補強部材7
はACF3の上に半導体チップ4を固着した後に形成す
る構成としたが、この補強部材7は、ACF3上面の半
導体チップ4コーナー部に相当する位置に予め形成して
おいても良い。その形成のし方はACF3の上面に補強
部材7を後から取り付ける方法でもよく、また、ACF
3の一部として一体的に形成しておいても良い。
The present invention is not limited to the above embodiment. For example, in the above embodiment, the reinforcing member 7
Is formed after the semiconductor chip 4 is fixed on the ACF 3. However, the reinforcing member 7 may be formed in advance at a position corresponding to the corner of the semiconductor chip 4 on the upper surface of the ACF 3. The reinforcing member 7 may be attached to the upper surface of the ACF 3 later.
3 may be integrally formed.

【0047】(第2の実施形態)以下、本発明の第2の
実施形態に係る半導体装置について説明する。なお、本
実施形態に係る半導体装置のうち、上記第1の実施形態
と重複する内容については説明を省略する。
(Second Embodiment) Hereinafter, a semiconductor device according to a second embodiment of the present invention will be described. Note that, in the semiconductor device according to the present embodiment, the description of the same contents as those in the first embodiment will be omitted.

【0048】図5は本実施形態に係る半導体装置の垂直
断面図であり、図6は本実施形態に係る半導体装置の平
面図である。
FIG. 5 is a vertical sectional view of the semiconductor device according to the present embodiment, and FIG. 6 is a plan view of the semiconductor device according to the present embodiment.

【0049】本実施形態に係る半導体装置では、補強部
材71として、平面図で表わしたときに中心角270度
の扇型を示す形状に形成した。この扇型の中心は半導体
チップ4のコーナー部に一致させる。またこの補強部材
71の垂直断面は図5に示すようにフィレット形状を示
す。
In the semiconductor device according to the present embodiment, the reinforcing member 71 is formed in a fan-shaped shape having a central angle of 270 degrees when represented in a plan view. The center of the sector is aligned with the corner of the semiconductor chip 4. A vertical cross section of the reinforcing member 71 has a fillet shape as shown in FIG.

【0050】本実施形態に係る半導体装置では、図5及
び図6に示した形状の補強部材71を備えているので、
半導体装置に曲げ応力が作用したときにも、応力が半導
体チップ4のコーナー部に集中するのが防止される。そ
のため、半導体チップとACF3、曳いては電極板5と
配線層21との間の電気的接続が維持され、信頼性の高
い半導体装置が得られる。
The semiconductor device according to the present embodiment has the reinforcing member 71 having the shape shown in FIGS.
Even when a bending stress acts on the semiconductor device, the stress is prevented from being concentrated on the corner of the semiconductor chip 4. Therefore, the electrical connection between the semiconductor chip and the ACF 3 and between the electrode plate 5 and the wiring layer 21 is maintained, and a highly reliable semiconductor device can be obtained.

【0051】(第3の実施形態)本実施形態に係る半導
体装置では、補強部材をACF3の上面に後から形成す
るのではなく、ACF3の一部を利用して補強部材を形
成する構成とした。
(Third Embodiment) In a semiconductor device according to this embodiment, a reinforcing member is formed by using a part of the ACF 3 instead of forming the reinforcing member on the upper surface of the ACF 3 later. .

【0052】図7は本実施形態に係る半導体装置の製造
工程を示すフローチャートであり、図8は製造途中の半
導体装置を示す垂直断面図である。
FIG. 7 is a flow chart showing the manufacturing process of the semiconductor device according to the present embodiment, and FIG. 8 is a vertical sectional view showing the semiconductor device being manufactured.

【0053】本実施形態に係る半導体装置を製造するに
は、銅張基板10をパターニングして(ステップ1a)
配線基板11を形成し、この配線基板11の配線層21
を形成した面の上に異方性導電フィルム(ACF)3を
仮圧着して(ステップ2a)積層体12を得る。
To manufacture the semiconductor device according to the present embodiment, the copper-clad substrate 10 is patterned (step 1a).
The wiring board 11 is formed, and the wiring layer 21 of the wiring board 11 is formed.
The anisotropic conductive film (ACF) 3 is temporarily pressure-bonded on the surface on which is formed (Step 2a) to obtain the laminate 12.

【0054】次に積層体12のACF3の上面を切削な
どを施して加工し、半導体チップ4のハウジング41の
外形に嵌合する形状の凹部31を形成する(ステップ3
a)次いで凹部31を形成したACF3の上部で、金ボ
ールバンプ6,6,…を電極5,5,…上に形成した半
導体チップ4を位置合わせし(ステップ4a)、加熱下
に加圧する(ステップ5a)。
Next, the upper surface of the ACF 3 of the laminated body 12 is machined by cutting or the like to form a concave portion 31 having a shape fitting into the outer shape of the housing 41 of the semiconductor chip 4 (step 3).
a) Next, the semiconductor chip 4 in which the gold ball bumps 6, 6,... are formed on the electrodes 5, 5,... is positioned above the ACF 3 in which the concave portion 31 is formed (step 4a), and pressurized under heating (step 4a). Step 5a).

【0055】この加圧により金ボールバンプ6,6,…
がACF3を貫通して電極5,5,…と配線層21,2
1,…との間を電気的に接続する。また、この加圧によ
り半導体チップ4のハウジング41がACF3上部に形
成した凹部31に嵌合してハウジング41の側面がAC
F3の凹部31と接触し、図8(f)に示すようにハウ
ジング41の下部がACF3内に埋没した状態となる。
この状態で熱が作用してACF3を構成する樹脂が硬化
することにより、ハウジング41のコーナー部を含む下
部がACF3と固着される。そのため、ハウジング41
のコーナー部に上記第1及び第2の実施形態で説明した
補強部材7を配設したのと同様の状態となる。
The gold ball bumps 6, 6,...
Are penetrating the ACF 3 and the electrodes 5, 5,.
Are electrically connected. Further, the housing 41 of the semiconductor chip 4 is fitted into the concave portion 31 formed above the ACF 3 by this pressure, and the side surface of the housing 41 is
As shown in FIG. 8F, the lower portion of the housing 41 is buried in the ACF 3 as it contacts the concave portion 31 of F3.
In this state, heat acts to cure the resin constituting the ACF 3, whereby the lower portion including the corner of the housing 41 is fixed to the ACF 3. Therefore, the housing 41
This is the same state as the case where the reinforcing member 7 described in the first and second embodiments is arranged at the corner portion of FIG.

【0056】その結果、半導体装置に曲げ応力が作用し
ても、応力が半導体チップ4のコーナー部に集中するこ
とが防止され、ハウジング41とACF3との剥離が防
がれ、曳いては電極板5,5,…と配線層21,21,
…との間の接続信頼性が向上する。
As a result, even if a bending stress acts on the semiconductor device, the stress is prevented from being concentrated on the corners of the semiconductor chip 4, the separation between the housing 41 and the ACF 3 is prevented, and the electrode plate is pulled. 5, 5,... And the wiring layers 21, 21, 21
The connection reliability between... Is improved.

【0057】本実施形態によれば、補強部材7を形成し
たり、硬化したりする工程が不要となるので、工数の削
減が図られるという特有の効果が得られる。
According to the present embodiment, since the step of forming or hardening the reinforcing member 7 is not required, a unique effect that the number of steps can be reduced is obtained.

【0058】(第4の実施形態)本実施形態に係る半導
体装置では、ACF3を配線基板11上に圧着した後に
凹部31を形成するのではなく、ACF3の仮圧着と同
時に凹部を形成する構成とした。
(Fourth Embodiment) In the semiconductor device according to the present embodiment, the concave portion 31 is not formed after the ACF 3 is press-bonded on the wiring board 11, but the concave portion is formed simultaneously with the temporary press-bonding of the ACF 3. did.

【0059】図9は本実施形態に係る半導体装置の製造
工程を示すフローチャートであり、図10は製造途中の
半導体装置を示す垂直断面図である。
FIG. 9 is a flowchart showing the manufacturing process of the semiconductor device according to the present embodiment, and FIG. 10 is a vertical sectional view showing the semiconductor device in the course of manufacturing.

【0060】本実施形態に係る半導体装置を製造するに
は、銅張基板10をパターニングして(ステップ1b)
配線基板11を形成した後、図10(a)に示すよう
に、配線基板11の上にACF3と更にその上に断面凸
型の押し型8を配設する。
To manufacture the semiconductor device according to the present embodiment, the copper-clad substrate 10 is patterned (step 1b).
After the wiring substrate 11 is formed, as shown in FIG. 10A, the ACF 3 is disposed on the wiring substrate 11, and the pressing die 8 having a convex cross section is disposed thereon.

【0061】ここで用いる押し型8は垂直断面が凸型に
形成されており、この突出した部分81の大きさ及び形
状は半導体チップ4のハウジング41と同じ大きさ及び
形状に形成されている。
The pressing die 8 used here has a vertical cross section formed in a convex shape, and the size and shape of the projecting portion 81 are formed to be the same size and shape as the housing 41 of the semiconductor chip 4.

【0062】次に、一番下に配線基板11を配置し、そ
の上にACF3、更にその上に押し型8を配置した状態
で押し型8でACF3を押圧する(ステップ2b)。こ
の押圧によりACF3の下面側が配線基板11上に仮圧
着される。それと同時に押し型8の突出部81はACF
3の上面から内部にめり込み、図10(b)に示した状
態となる。
Next, the wiring board 11 is disposed at the bottom, the ACF 3 is placed thereon, and the ACF 3 is pressed with the pressing die 8 while the pressing die 8 is further placed thereon (step 2b). By this pressing, the lower surface side of the ACF 3 is temporarily pressed on the wiring board 11. At the same time, the protrusion 81 of the pressing die 8 is ACF
3 is sunk into the inside from the upper surface, resulting in the state shown in FIG.

【0063】次いで押し型8を取り除くと、図10
(c)に示したように、半導体チップ4のハウジング4
1の外形に嵌合する形状の凹部31がACF3の上部に
形成される。
Next, when the pressing die 8 is removed, FIG.
As shown in (c), the housing 4 of the semiconductor chip 4
A concave portion 31 having a shape that fits into the outer shape of the ACF 3 is formed on the ACF 3.

【0064】次いで凹部31を形成したACF3の上部
で、金ボールバンプ6,6,…を電極5,5,…上に形
成した半導体チップ4を位置合わせし(ステップ3
b)、加熱下に加圧する(ステップ4b)。
Then, the semiconductor chip 4 having the gold ball bumps 6, 6,... Formed on the electrodes 5, 5,.
b) Pressurizing under heating (step 4b).

【0065】この加圧により金ボールバンプ6,6,…
がACF3を貫通して電極5,5,…と配線層21,2
1,…との間を電気的に接続する。また、この加圧によ
り半導体チップ4のハウジング41がACF3上部に形
成した凹部31に嵌合してハウジング41の側面がAC
F3の凹部31と接触し、図8(f)に示すようにハウ
ジング41の下部がACF3内に埋没した状態となる。
この状態で熱が作用してACF3を構成する樹脂が硬化
することにより、ハウジング41のコーナー部を含む下
部がACF3と固着される。
By the pressing, the gold ball bumps 6, 6,...
Are penetrating the ACF 3 and the electrodes 5, 5,.
Are electrically connected. Further, the housing 41 of the semiconductor chip 4 is fitted into the concave portion 31 formed above the ACF 3 by this pressure, and the side surface of the housing 41 is
As shown in FIG. 8F, the lower portion of the housing 41 is buried in the ACF 3 as it contacts the concave portion 31 of F3.
In this state, heat acts to cure the resin constituting the ACF 3, whereby the lower portion including the corner of the housing 41 is fixed to the ACF 3.

【0066】そのため、ハウジング41のコーナー部に
上記第1及び第2の実施形態で説明した補強部材7を配
設したのと同様の状態となる。
Therefore, the state is the same as when the reinforcing member 7 described in the first and second embodiments is disposed at the corner of the housing 41.

【0067】その結果、半導体装置に曲げ応力が作用し
ても、応力が半導体チップ4のコーナー部に集中するこ
とが防止され、ハウジング41とACF3との剥離が防
がれ、曳いては電極板5,5,…と配線層21,21,
…との間の接続信頼性が向上する。
As a result, even if a bending stress acts on the semiconductor device, the stress is prevented from concentrating on the corner of the semiconductor chip 4, the separation between the housing 41 and the ACF 3 is prevented, and the electrode plate is pulled. 5, 5,... And the wiring layers 21, 21, 21
The connection reliability between... Is improved.

【0068】本実施形態によれば、押し型8を用いてA
CF3を仮圧着すると同時に凹部31を形成する。その
ため、仮圧着後に凹部31を形成する工程が不用となる
ので、工数の削減が図られるという特有の効果が得られ
る。
According to the present embodiment, A
Concave portions 31 are formed at the same time as CF3 is temporarily pressed. For this reason, the step of forming the concave portion 31 after the temporary press-bonding becomes unnecessary, so that a unique effect of reducing the number of steps can be obtained.

【0069】(第5の実施形態)本実施形態では、AC
F3の上面に形成する凹部を二段型の形状に構成した。
図11は実施形態に係る半導体装置の製造途中のものの
垂直断面図を示した図である。
(Fifth Embodiment) In this embodiment, AC
The recess formed on the upper surface of F3 was formed in a two-stage shape.
FIG. 11 is a vertical cross-sectional view of the semiconductor device according to the embodiment in the process of being manufactured.

【0070】図11(a)に示すように、本実施形態に
係る半導体装置では、ACF3の上部に二段構造の凹部
32が形成されている。即ち、凹部の下部33の開口部
の寸法w1は上部34の開口部の寸法w2より一段狭く
なっている。この下部33の寸法w1は半導体チップ4
のハウジング41の外形寸法に対応している。そのた
め、このACF3の凹部32に半導体チップ4を位置合
わせした後にプレスして圧入すると、図11(c)に示
したように半導体チップ4は凹部32の底部でACF3
と嵌合し、凹部32の上部34との間には幅dの隙間が
形成される。
As shown in FIG. 11A, in the semiconductor device according to the present embodiment, a recess 32 having a two-stage structure is formed above the ACF 3. That is, the dimension w1 of the opening of the lower part 33 of the recess is one step smaller than the dimension w2 of the opening of the upper part. The dimension w1 of the lower part 33 is the semiconductor chip 4
Of the housing 41. Therefore, when the semiconductor chip 4 is press-fitted after the semiconductor chip 4 is positioned in the concave portion 32 of the ACF 3, the semiconductor chip 4 is positioned at the bottom of the concave portion 32 as shown in FIG.
And a gap having a width d is formed between the concave portion 32 and the upper portion 34 of the concave portion 32.

【0071】図11(d)に示すように、この隙間に補
強材9を充填することにより半導体チップ4とACF3
とが密着し、半導体チップ4が固定される。
As shown in FIG. 11D, by filling the gap with a reinforcing material 9, the semiconductor chip 4 and the ACF 3 are filled.
And the semiconductor chip 4 is fixed.

【0072】本実施形態では、半導体チップより寸法の
大きい凹部をACFに設けてここに半導体チップを圧入
するので、凹部を形成したり、半導体チップを圧入する
作業を容易に行なうことができるという特有の効果が得
られる。
In the present embodiment, a recess larger in size than the semiconductor chip is provided in the ACF, and the semiconductor chip is press-fitted into the ACF. Therefore, the operation of forming the recess and press-fitting the semiconductor chip can be easily performed. The effect of is obtained.

【0073】[0073]

【発明の効果】本発明によれば、前記異方性導電フィル
ムと前記半導体チップのコーナー部との間に応力分散型
形状を備えた補強部材を配設したので、半導体チップや
異方性導電フィルムに曲げ応力が作用した場合にも応力
がセラミックのコーナー部に集中するのが防止され、曳
いては配線層と電極板との間の電気的接続が破壊するの
が防止される。
According to the present invention, a reinforcing member having a stress-dispersive shape is disposed between the anisotropic conductive film and the corner of the semiconductor chip. Even when a bending stress is applied to the film, the stress is prevented from being concentrated on the corners of the ceramic, and the electrical connection between the wiring layer and the electrode plate is prevented from being broken.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1の実施形態に係る半導体装置の製造工程の
フローチャートである。
FIG. 1 is a flowchart of a manufacturing process of a semiconductor device according to a first embodiment.

【図2】製造途中の第1の実施形態に係る半導体装置の
垂直断面図である。
FIG. 2 is a vertical sectional view of the semiconductor device according to the first embodiment which is being manufactured.

【図3】製造途中の第1の実施形態に係る半導体装置の
垂直断面図である。
FIG. 3 is a vertical sectional view of the semiconductor device according to the first embodiment which is being manufactured.

【図4】製造途中の第1の実施形態に係る半導体装置の
垂直断面図である。
FIG. 4 is a vertical sectional view of the semiconductor device according to the first embodiment in the course of manufacture.

【図5】第2の実施形態に係る半導体装置の垂直断面図
である。
FIG. 5 is a vertical sectional view of a semiconductor device according to a second embodiment.

【図6】第2の実施形態に係る半導体装置の平面図であ
る。
FIG. 6 is a plan view of a semiconductor device according to a second embodiment.

【図7】第3の実施形態に係る半導体装置の製造工程を
示すフローチャートである。
FIG. 7 is a flowchart illustrating a manufacturing process of a semiconductor device according to a third embodiment.

【図8】製造途中の第3の実施形態に係る半導体装置を
示す垂直断面図である。
FIG. 8 is a vertical sectional view showing a semiconductor device according to a third embodiment in the course of manufacture.

【図9】第4の実施形態に係る半導体装置の製造工程を
示すフローチャートである。
FIG. 9 is a flowchart illustrating a manufacturing process of a semiconductor device according to a fourth embodiment.

【図10】製造途中の第4の実施形態に係る半導体装置
を示す垂直断面図である。
FIG. 10 is a vertical sectional view showing a semiconductor device according to a fourth embodiment in the course of manufacture.

【図11】製造途中の第5の実施形態に係る半導体装置
を示す垂直断面図である。
FIG. 11 is a vertical sectional view showing a semiconductor device according to a fifth embodiment in the course of manufacture.

【図12】従来の半導体装置の製造工程を示す図であ
る。
FIG. 12 is a diagram showing a manufacturing process of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1…絶縁性基板、21…配線層、3…異方性導電フィル
ム(ACF)、4…半導体チップ、5…電極板(電極
板)、6…金ボールバンプ、7…補強部材、8…押し
型、9…隙間。
DESCRIPTION OF SYMBOLS 1 ... Insulating board, 21 ... Wiring layer, 3 ... Anisotropic conductive film (ACF), 4 ... Semiconductor chip, 5 ... Electrode plate (electrode plate), 6 ... Gold ball bump, 7 ... Reinforcement member, 8 ... Push Mold, 9 ... clearance.

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板と、 前記絶縁性基板上に配設された配線層と、 前記配線層上に配設された異方性導電フィルム層と、 前記異方性導電フィルム層上に配設された半導体チップ
と、 前記半導体チップ上に配設された電極板と、 前記異方性導電フィルム層内において前記配線層と前記
電極板とを導通させる金ボールバンプと、 前記異方性導電フィルム層と前記半導体チップのコーナ
ー部との間に配設され、応力分散型形状を備えた補強部
材とを具備する半導体装置。
An insulating substrate; a wiring layer provided on the insulating substrate; an anisotropic conductive film layer provided on the wiring layer; and an anisotropic conductive film layer provided on the anisotropic conductive film layer. A semiconductor chip provided; an electrode plate provided on the semiconductor chip; a gold ball bump for electrically connecting the wiring layer and the electrode plate in the anisotropic conductive film layer; A semiconductor device, comprising: a reinforcing member provided between a conductive film layer and a corner portion of the semiconductor chip, the reinforcing member having a stress distribution type shape.
【請求項2】 請求項1に記載の半導体装置であって、
前記応力分散型形状が、フィレット型の垂直断面を示す
形状であることを特徴とする半導体装置。
2. The semiconductor device according to claim 1, wherein:
A semiconductor device, wherein the stress dispersion type shape is a shape showing a fillet-type vertical cross section.
【請求項3】 請求項1又は2に記載の半導体装置であ
って、前記応力分散型形状が、前記半導体チップのコー
ナー部を中心とする中心角270度の扇型平面形状であ
ることを特徴とする半導体装置。
3. The semiconductor device according to claim 1, wherein the stress-dispersed shape is a fan-shaped planar shape having a central angle of 270 degrees around a corner of the semiconductor chip. Semiconductor device.
【請求項4】 請求項1〜3の何れか1項に記載の半導
体装置であって、前記補強部材が、前記異方性導電フィ
ルムと同じ物性値を有する材料で形成されていることを
特徴とする半導体装置。
4. The semiconductor device according to claim 1, wherein the reinforcing member is made of a material having the same physical property value as the anisotropic conductive film. Semiconductor device.
【請求項5】 請求項1〜4の何れか1項に記載の半導
体装置であって、前記補強部材が、前記異方性導電フィ
ルムと一体化されていることを特徴とする半導体装置。
5. The semiconductor device according to claim 1, wherein the reinforcing member is integrated with the anisotropic conductive film.
【請求項6】 請求項3〜5の何れか1項に記載の半導
体装置であって、前記補強部材が、前記異方性導電フィ
ルムの上部に形成された枠状の凹部により構成されてい
ることを特徴とする半導体装置。
6. The semiconductor device according to claim 3, wherein the reinforcing member is formed by a frame-shaped recess formed on an upper part of the anisotropic conductive film. A semiconductor device, comprising:
【請求項7】 請求項1〜6の何れか1項に記載の半導
体装置であって、前記補強部材が、前記異方性導電フィ
ルム上面と前記半導体チップ側面との間にわたって配設
された部材であることを特徴とする半導体装置。
7. The semiconductor device according to claim 1, wherein the reinforcing member is disposed between an upper surface of the anisotropic conductive film and a side surface of the semiconductor chip. A semiconductor device, characterized in that:
【請求項8】 請求項1〜7の何れか1項に記載の半導
体装置であって、前記補強部材が、前記異方性導電フィ
ルムと一体的に成形されていることを特徴とする半導体
装置。
8. The semiconductor device according to claim 1, wherein the reinforcing member is formed integrally with the anisotropic conductive film. .
【請求項9】 請求項8に記載の半導体装置であって、
前記異方性導電部材が前記半導体チップと嵌合する枠状
の凹部を備えており、前記補強部材が、前記異方性導電
フィルムと前記半導体チップとの隙間に配設されている
ことを特徴とする半導体装置。
9. The semiconductor device according to claim 8, wherein
The anisotropic conductive member includes a frame-shaped concave portion that fits with the semiconductor chip, and the reinforcing member is disposed in a gap between the anisotropic conductive film and the semiconductor chip. Semiconductor device.
【請求項10】 絶縁性基板上に配線層を形成する工程
と、 前記配線層上に異方性導電性フィルム層を形成する工程
と、 半導体チップ上に電極板を形成する工程と、 前記電極板上に金ボールバンプを形成する工程と、 前記絶縁性基板上の配線層と半導体チップ上の前記電極
板とを位置合わせする工程と、 前記絶縁性基板と前記半導体チップとを加圧下に加熱し
て前記金ボールバンプを前記異方性導電フィルムを貫通
させ、前記配線層と前記電極板とを接続する工程と、 前記半導体チップのコーナー部と前記異方性導電フィル
ムとの間に補強部材を塗布する工程と、 前記補強部材を硬化させる工程と、 を具備する半導体装置の製造方法。
10. A step of forming a wiring layer on an insulating substrate; a step of forming an anisotropic conductive film layer on the wiring layer; a step of forming an electrode plate on a semiconductor chip; Forming a gold ball bump on a plate; aligning a wiring layer on the insulating substrate with the electrode plate on a semiconductor chip; heating the insulating substrate and the semiconductor chip under pressure Making the gold ball bumps penetrate the anisotropic conductive film and connecting the wiring layer and the electrode plate; and a reinforcing member between a corner of the semiconductor chip and the anisotropic conductive film. And a step of curing the reinforcing member.
JP2000326106A 2000-10-25 2000-10-25 Semiconductor device and its manufacturing method Pending JP2002134558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000326106A JP2002134558A (en) 2000-10-25 2000-10-25 Semiconductor device and its manufacturing method

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004146655A (en) * 2002-10-25 2004-05-20 Taiyo Yuden Co Ltd Coil component and circuit device using the same
KR100641564B1 (en) 2004-12-30 2006-10-31 동부일렉트로닉스 주식회사 Method for fabricating chip size package using anisotropic conductive film
WO2010134230A1 (en) * 2009-05-20 2010-11-25 パナソニック株式会社 Semiconductor device and method for manufacturing same
US8110933B2 (en) 2006-12-26 2012-02-07 Panasonic Corporation Semiconductor device mounted structure and semiconductor device mounted method
JP2012204570A (en) * 2011-03-25 2012-10-22 Hitachi Plant Technologies Ltd Manufacturing device and manufacturing method of printed board
WO2020182361A1 (en) * 2019-03-13 2020-09-17 Danfoss Silicon Power Gmbh Method for making a cohesive connection by fluxless chip- or element soldering, gluing or sintering using a material preform

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004146655A (en) * 2002-10-25 2004-05-20 Taiyo Yuden Co Ltd Coil component and circuit device using the same
KR100641564B1 (en) 2004-12-30 2006-10-31 동부일렉트로닉스 주식회사 Method for fabricating chip size package using anisotropic conductive film
US8110933B2 (en) 2006-12-26 2012-02-07 Panasonic Corporation Semiconductor device mounted structure and semiconductor device mounted method
WO2010134230A1 (en) * 2009-05-20 2010-11-25 パナソニック株式会社 Semiconductor device and method for manufacturing same
JP2012204570A (en) * 2011-03-25 2012-10-22 Hitachi Plant Technologies Ltd Manufacturing device and manufacturing method of printed board
WO2020182361A1 (en) * 2019-03-13 2020-09-17 Danfoss Silicon Power Gmbh Method for making a cohesive connection by fluxless chip- or element soldering, gluing or sintering using a material preform
DE102019106394B4 (en) 2019-03-13 2023-06-01 Danfoss Silicon Power Gmbh Method of making a cohesive bond and bonding material preform therefor

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