JP2002170848A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JP2002170848A JP2002170848A JP2000364014A JP2000364014A JP2002170848A JP 2002170848 A JP2002170848 A JP 2002170848A JP 2000364014 A JP2000364014 A JP 2000364014A JP 2000364014 A JP2000364014 A JP 2000364014A JP 2002170848 A JP2002170848 A JP 2002170848A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- semiconductor element
- bumps
- bump
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、回路基板に関し、
特に、配線基板の実装面上にフェースダウン方式で半導
体素子を実装する回路基板に有効な技術に関するもので
ある。TECHNICAL FIELD The present invention relates to a circuit board,
In particular, the present invention relates to a technology effective for a circuit board on which a semiconductor element is mounted on a mounting surface of a wiring board by a face-down method.
【０００２】[0002]
【従来の技術】近年の半導体素子の配線基板への実装技
術の動向は、電子機器の超小型化、高密度化に伴い、微
細化、薄型化の傾向にある。半導体素子と配線基板との
間の接合方法として、従来からのワイヤボンディング、
半田付けよりも微細化、薄型化が可能である、超音波熱
接合が大いに注目されている。以下、超音波熱接合につ
いて説明する。図５はバンプ２付き半導体素子１を配線
基板５に接合した状態を示す断面図である。図におい
て、５０は回路基板、１は半導体素子、２はバンプ、４
は絶縁性樹脂、５は配線基板、６はパッド部である。ま
た、パッド部６は、配線基板５上の表面配線導体の一部
を構成している。2. Description of the Related Art In recent years, the trend of mounting technology of a semiconductor element on a wiring board has been toward miniaturization and thinning as electronic devices have become ultra-small and high-density. As a bonding method between a semiconductor element and a wiring board, conventional wire bonding,
Ultrasonic thermal bonding, which can be made finer and thinner than soldering, has attracted much attention. Hereinafter, the ultrasonic thermal bonding will be described. FIG. 5 is a cross-sectional view showing a state where the semiconductor element 1 with the bumps 2 is joined to the wiring board 5. In the figure, 50 is a circuit board, 1 is a semiconductor element, 2 is a bump,
Is an insulating resin, 5 is a wiring board, and 6 is a pad portion. The pad portion 6 forms a part of a surface wiring conductor on the wiring board 5.
【０００３】超音波熱接合は、まず、複数のバンプ２が
配置された半導体素子１を準備する。次に、複数のパッ
ド部６が配置された配線基板５の実装面のチップ塔載領
域に、例えばエポキシ系の熱硬化型絶縁性樹脂４を塗布
する。次に、配線基板５の実装面に半導体素子１の実装
面を向かい合わせた状態で、配線基板５の実装面の素子
塔載領域上に絶縁性樹脂４を介して半導体素子１を載置
する。次に、半導体素子１を加圧した状態で、超音波振
動を印加し、配線基板５のパッド部に半導体素子１のバ
ンプ２を圧接する。このことにより、半導体素子１のバ
ンプ２は、配線基板５のパッド部６に電気的にかつ機械
的に接続される。一方、絶縁性樹脂４は、加熱すること
により、一旦ゲル化しその後に硬化する。すなわち、半
導体素子１は、絶縁性樹脂４の硬化によって配線基板５
に接着固定される。また、このことにより、配線基板５
の実装面上に半導体素子１が実装される。In ultrasonic thermal bonding, first, a semiconductor element 1 on which a plurality of bumps 2 are arranged is prepared. Next, for example, an epoxy-based thermosetting insulating resin 4 is applied to the chip mounting area on the mounting surface of the wiring board 5 on which the plurality of pad portions 6 are arranged. Next, the semiconductor element 1 is mounted on the element mounting area of the mounting surface of the wiring board 5 via the insulating resin 4 with the mounting surface of the semiconductor element 1 facing the mounting surface of the wiring board 5. . Next, while the semiconductor element 1 is pressurized, ultrasonic vibration is applied, and the bump 2 of the semiconductor element 1 is pressed against the pad portion of the wiring board 5. As a result, the bumps 2 of the semiconductor element 1 are electrically and mechanically connected to the pad portions 6 of the wiring board 5. On the other hand, the insulating resin 4 gels once by heating, and then hardens. That is, the semiconductor element 1 is cured by the hardening of the insulating resin 4.
Adhesively fixed. This also allows the wiring substrate 5
The semiconductor element 1 is mounted on the mounting surface.
【０００４】このように、超音波熱接合は、配線基板に
半導体素子を実装した後、配線基板と半導体素子との間
に絶縁性樹脂を充填する方法に比較し、再度絶縁性樹脂
を充填する必要がないので、工程の短縮がなされ、低コ
スト化を図ることができる。また、バンプ３とパッド部
６は金属接合を行うため、半導体素子１と配線基板５の
間で確実な電気接合と高い実装強度を満足できる。従っ
て、この実装技術は、配線基板の実装面上にフェースダ
ウン方式で半導体素子を実装するパッケージ構造の回路
基板の製造や、配線基板の実装面上にフェースダウン方
式で複数の半導体素子を実装するモジュール構造の回路
基板の製造に有効である。As described above, in the ultrasonic thermal bonding, as compared with a method of mounting a semiconductor element on a wiring board and then filling an insulating resin between the wiring board and the semiconductor element, the insulating resin is filled again. Since there is no need, the process can be shortened and the cost can be reduced. Further, since the bumps 3 and the pad portions 6 are metal-bonded, reliable electrical bonding and high mounting strength between the semiconductor element 1 and the wiring board 5 can be satisfied. Therefore, this mounting technique manufactures a circuit board having a package structure in which semiconductor elements are mounted on a mounting surface of a wiring board in a face-down manner, and mounts a plurality of semiconductor elements in a face-down manner on a mounting surface of a wiring board. It is effective for manufacturing a circuit board having a module structure.
【０００５】ところで、上記回路基板において、機械的
圧力や応力歪み等により、バンプによって支持されてい
ない部分において、配線基板及び半導体素子の変形が生
じ、その結果、配線基板及び半導体素子の特性が劣化す
るといった問題があった。In the circuit board, the wiring board and the semiconductor element are deformed in portions not supported by the bumps due to mechanical pressure, stress distortion, and the like. As a result, the characteristics of the wiring board and the semiconductor element deteriorate. There was a problem of doing.
【０００６】そこで、配線基板と半導体素子との間の接
続信頼性を向上させるために、電気接続のための接合の
バンプを形成していない部分に、電気接続に寄与しない
第２のバンプを形成した回路基板が、特開２０００−１
９５９００号公報、特開２０００−２３２２００号公報
に開示されている。Therefore, in order to improve the connection reliability between the wiring board and the semiconductor element, a second bump which does not contribute to the electrical connection is formed in a portion where the bonding bump for the electrical connection is not formed. Circuit board is disclosed in JP-A-2000-1
95900 and JP-A-2000-232200.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、図５に
示す回路基板５０では、半導体素子１の熱膨張係数が配
線基板５の熱膨張係数より小さいため、例えば、温度サ
イクル試験等を行った場合、この熱膨張係数の差により
発生する応力で、異方性導電樹脂層４が疲労劣化してし
まう。However, in the circuit board 50 shown in FIG. 5, since the coefficient of thermal expansion of the semiconductor element 1 is smaller than the coefficient of thermal expansion of the wiring board 5, for example, when a temperature cycle test or the like is performed, The stress generated due to the difference in the thermal expansion coefficient causes the anisotropic conductive resin layer 4 to be fatigued and deteriorated.
【０００８】この結果、異方性導電樹脂層４の硬化温
度、例えば２００℃で半導体素子１と配線基板５が接合
した後、常温付近での温度における応力の発生状況を図
６に示す。種々の実験によれば、配線基板５の中央付近
に向かって応力（図では矢印）が発生し、その結果、図
の点線で示すように、配線基板５の中央付近が、半導体
素子１に対して離れる方向に変形する傾向がある。As a result, FIG. 6 shows a state of occurrence of stress at a temperature near normal temperature after the semiconductor element 1 and the wiring board 5 are joined at the curing temperature of the anisotropic conductive resin layer 4, for example, 200 ° C. According to various experiments, a stress (arrow in the figure) is generated near the center of the wiring board 5, and as a result, as shown by a dotted line in the figure, the vicinity of the center of the wiring board 5 Tend to deform away.
【０００９】ここで、特開２０００−１９５９００号公
報に開示された回路基板によれば、半導体素子と配線基
板を超音波熱接合で接合しているのではなく、絶縁性樹
脂の収縮力でバンプと配線基板を接触させている。ま
た、特開２０００−２３２２００号公報に開示された回
路基板によれば、絶縁性樹脂を塗布後に、配線基板のパ
ッド部に半導体素子のバンプを接合するのではなく、半
導体素子と配線基板を接合した後に、これらを樹脂封止
している。このため、図６に示す問題点の解決方法とは
なっていない。Here, according to the circuit board disclosed in Japanese Patent Application Laid-Open No. 2000-195900, the semiconductor element and the wiring board are not bonded by ultrasonic thermal bonding, but the bumps are formed by the contraction force of the insulating resin. And the wiring board are in contact. Further, according to the circuit board disclosed in Japanese Patent Application Laid-Open No. 2000-232200, after applying the insulating resin, the semiconductor element and the wiring board are joined together instead of joining the bumps of the semiconductor element to the pad portions of the wiring board. After that, they are sealed with resin. For this reason, it does not solve the problem shown in FIG.
【００１０】本発明は、上述の問題点に鑑みて案出され
たものであり、その目的は、温度サイクル試験等におい
て、半導体素子と配線基板との熱膨張係数の違いによ
り、繰り返し発生する応力で絶縁性樹脂が疲労した場合
も、半導体素子と配線基板が確実に安定して電気的に接
続した高品質の回路基板を、簡単且つ安価な工程で提供
することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to provide a semiconductor device and a wiring board which are subjected to repeated stresses in a temperature cycle test or the like due to a difference in thermal expansion coefficient between a semiconductor element and a wiring board. Therefore, even when the insulating resin is fatigued, a high-quality circuit board in which the semiconductor element and the wiring board are reliably and stably electrically connected is provided in a simple and inexpensive process.
【００１１】[0011]
【課題を解決するための手段】上記の問題点を解決する
ため、本発明は、実装面の周縁部に沿って第１及び第２
のバンプを形成させた半導体素子を、前記第１及び第２
のバンプと対応する位置に第１及び第２のパッド部を含
む表面配線導体を形成した配線基板に接合させた回路基
板であって、前記半導体素子の角部付近には、信号の入
出力及び電源供給等が行われる前記第１のバンプを配置
し、前記半導体素子の各辺の中央部付近には、接合のみ
を行う前記第２のバンプを配置し、前記第１及び第２の
バンプが、それぞれ前記第１及び第２のパッドに超音波
熱接合により接合されるとともに、前記半導体素子と配
線基板との間隔に絶縁性樹脂を介在させたことを特徴と
する。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method of forming a first and a second along a peripheral portion of a mounting surface.
The semiconductor element having the bumps formed thereon is replaced with the first and second semiconductor elements.
A circuit board joined to a wiring board on which surface wiring conductors including first and second pad portions are formed at positions corresponding to the bumps, wherein signal input / output and signal input / output The first bumps to be supplied with power are arranged, and the second bumps that only perform bonding are arranged near the center of each side of the semiconductor element, and the first and second bumps are arranged. The semiconductor device is bonded to the first and second pads by ultrasonic thermal bonding, and an insulating resin is interposed between the semiconductor element and the wiring board.
【００１２】[0012]
【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１３】図１は、本発明の回路基板の一実施例の断
面図である。図２は、図１の回路基板の半導体素子のバ
ンプ配置を示す実装面の平面図である。FIG. 1 is a sectional view of an embodiment of a circuit board according to the present invention. FIG. 2 is a plan view of a mounting surface showing a bump arrangement of a semiconductor element of the circuit board of FIG.
【００１４】図において、１０は回路基板、１は半導体
素子、２は第１のバンプ、３は第２のバンプ、４は絶縁
性樹脂層、５は配線基板、６は第１のパッド部、７は第
２のパッド部である。また、第１のパッド部６、第２の
パッド部７は、表面配線導体の一部を構成し、表面配線
としては、パッド部の他、電子部品を半田により搭載す
るための導体、これらの導体間を電気的に結合する導体
等が挙げられる。In the drawing, 10 is a circuit board, 1 is a semiconductor element, 2 is a first bump, 3 is a second bump, 4 is an insulating resin layer, 5 is a wiring board, 6 is a first pad section, Reference numeral 7 denotes a second pad section. The first pad portion 6 and the second pad portion 7 constitute a part of a surface wiring conductor. As the surface wiring, in addition to the pad portion, a conductor for mounting an electronic component by soldering, Conductors for electrically coupling between conductors may be used.
【００１５】半導体素子１は、例えばシリコンにトラン
ジスタ等を能動素子を形成するため、ドーパンド材を拡
散したり、また、保護層を形成するため、部分的に酸化
または窒化したり、さらに、第１、第２のバンプ２、３
の形成領域に電極部材を被着したりして構成されてい
る。The semiconductor element 1 is formed by, for example, diffusing a dopant material to form an active element such as a transistor in silicon, or partially oxidizing or nitriding to form a protective layer. , The second bumps 2, 3
Is formed by attaching an electrode member to the formation region of.
【００１６】配線基板５は、例えば、アルミナ、サファ
イア、窒化アルミニウム、ガラスセラミックス、石英等
の耐熱性を有する絶縁基板である。The wiring substrate 5 is an insulating substrate having heat resistance, such as alumina, sapphire, aluminum nitride, glass ceramic, and quartz.
【００１７】半導体素子１は、実装面を配線基板５の実
装面に対向させた、いわゆるフェースダウン方式で配線
基板５に接合されている。具体的に説明すると、半導体
素子１の実装面には、複数の第１及び第２のバンプ２、
３が形成されている。また、配線基板５の実装面には、
第１、第２のパッド部６、７が形成されている。そし
て、半導体素子１は、複数の第１のバンプ２、第２のバ
ンプ３がそれぞれ対応する第１のパッド部６、第２のパ
ッド部７に接続されることになる。第１及び第２のバン
プ２、３は、Ａｕ等よりなり、突起量は２０〜５０μｍ
程度である。第１及び第２のバンプ２、３は、例えばＡ
ｕ線によるワイヤボンディング方法のファーストボンデ
ィングを利用して形成し、半導体素子１の実装面の周辺
において、その角部付近には第１のバンプ２が形成さ
れ、各辺の中央付近には第２のバンプ３が形成されてい
る。第２のバンプ３は各辺中央近傍に少なくとも１個設
け、半導体素子１サイズにより適宜第２のバンプ３の数
を設定すればよい。ここで、第２のバンプ３を設ける領
域は、半導体素子１の各辺の中央部を含んで長さの３０
〜４０％の範囲にあることが望ましい。The semiconductor element 1 is joined to the wiring board 5 by a so-called face-down method in which the mounting surface faces the mounting surface of the wiring board 5. More specifically, a plurality of first and second bumps 2 are provided on the mounting surface of the semiconductor element 1.
3 are formed. Also, on the mounting surface of the wiring board 5,
First and second pad portions 6 and 7 are formed. Then, in the semiconductor element 1, the plurality of first bumps 2 and second bumps 3 are connected to the corresponding first pad portion 6 and second pad portion 7, respectively. The first and second bumps 2 and 3 are made of Au or the like, and have a projection amount of 20 to 50 μm.
It is about. The first and second bumps 2 and 3 are, for example, A
The first bump 2 is formed near the corner of the mounting surface of the semiconductor element 1 around the mounting surface of the semiconductor element 1, and the second bump 2 is formed near the center of each side. Are formed. At least one second bump 3 may be provided near the center of each side, and the number of the second bumps 3 may be appropriately set according to the size of the semiconductor element 1. Here, the area where the second bump 3 is provided has a length of 30 including the center of each side of the semiconductor element 1.
It is desirable that it be in the range of ４０40%.
【００１８】第１のパッド部６、第２のパッド部７の厚
みは７〜１５μｍ程度であり、材質はＡｕ、Ａｇ、Ｃ
ｕ、あるいはこれらの合金よりなる。The first pad portion 6 and the second pad portion 7 have a thickness of about 7 to 15 μm, and are made of Au, Ag, C
u or an alloy thereof.
【００１９】また、第１のバンプ２と第２のバンプ３と
は同じ材料で構成されるとしたが、第１のバンプ２と第
２のバンプ３とを異なる材料で構成してもよい。あるい
は、第１のバンプ２と第２のバンプ３とを異なる形状に
してもよい。例えば、第２のバンプ３として、電気的特
性が低下するが接合強度の大きい材料、あるいは形状を
用いてもよい。また、第１のバンプ２は信号の入出力及
び電源供給等を行い、第２のバンプ３は半導体素子１と
配線基板５との接合のみを行う。さらに、第１及び第２
のバンプ２、３は、それぞれ第１及び第２のパッド６、
７に超音波熱接合により接合され、半導体素子１と配線
基板５との間隔に絶縁性樹脂４を介在させている。Although the first bumps 2 and the second bumps 3 are made of the same material, the first bumps 2 and the second bumps 3 may be made of different materials. Alternatively, the first bump 2 and the second bump 3 may have different shapes. For example, the second bump 3 may be formed of a material or a material having a low electrical property but high bonding strength. The first bumps 2 perform input / output of signals and power supply, and the like, and the second bumps 3 perform only bonding between the semiconductor element 1 and the wiring board 5. In addition, the first and second
Of the first and second pads 6 and 3, respectively.
7 is bonded by ultrasonic thermal bonding, and an insulating resin 4 is interposed between the semiconductor element 1 and the wiring board 5.
【００２０】次に本発明の回路基板の製造方法について
説明する。Next, a method of manufacturing a circuit board according to the present invention will be described.
【００２１】まず、セラミック等よりなる配線基板５の
第１のパッド６、第２のパッド７を有する面に絶縁性樹
脂４を塗布する。絶縁性樹脂４は光硬化と熱硬化併用
型、あるいは熱硬化型等を用いる。主成分は、アクリ
ル，エポキシ等である。この時の硬化時に発生する収縮
力が所望する高温での絶縁性樹脂４の熱応力よりも大き
くなるような絶縁性樹脂４を用いる。次に、半導体素子
１の第１のバンプ２と配線基板５の第１のパッド６、半
導体素子１の第２のバンプ３と配線基板５の第２のパッ
ド７とをそれぞれ一致させ、半導体素子１を配線基板５
に加圧ツールにより加圧する。この時、パッド部上にあ
った絶縁性樹脂４は周囲に押し出され、第１のバンプ２
と第１のパッド６、第２のバンプ３と第２のパッド７が
それぞれ接触する。次に、半導体素子１を加圧した状態
で、超音波振動を印加し接合する。基板の加熱は１５０
〜２００℃で、基板の特性により選択する。このように
して、絶縁性樹脂４を硬化する。絶縁性樹脂４の硬化
は、光硬化と熱硬化併用タイプの場合は、半導体素子１
の周囲にはみ出した絶縁性樹脂４を光硬化し、他の部分
は加圧を取り除いた後に、オーブン等で加熱硬化する。
また加熱硬化の場合は、加圧ツールに加熱機構を設け、
加圧ツールにて加熱硬化する。次に、加圧ツールを取り
除く。この時半導体素子１は絶縁性樹脂４により固着さ
れるとともに、硬化時の収縮力により、第１のバンプ２
と第１のパッド６は、互いに押し合う力が作用し、接触
による電気的な接続が得られる。First, the insulating resin 4 is applied to the surface of the wiring board 5 made of ceramic or the like having the first pads 6 and the second pads 7. As the insulating resin 4, a combination of light curing and thermosetting, or a thermosetting type is used. The main component is acrylic, epoxy, or the like. The insulating resin 4 is used such that the contraction force generated at the time of curing at this time becomes larger than the thermal stress of the insulating resin 4 at a desired high temperature. Next, the first bumps 2 of the semiconductor element 1 and the first pads 6 of the wiring board 5 are matched, and the second bumps 3 of the semiconductor element 1 and the second pads 7 of the wiring board 5 are matched with each other. 1 for wiring board 5
Pressure by a pressure tool. At this time, the insulating resin 4 on the pad portion is extruded to the periphery, and the first bump 2
And the first pad 6 and the second bump 3 and the second pad 7 are in contact with each other. Next, while the semiconductor element 1 is pressurized, ultrasonic vibration is applied to perform bonding. Substrate heating 150
At ~ 200 ° C, it is selected according to the characteristics of the substrate. Thus, the insulating resin 4 is cured. In the case where the insulating resin 4 is cured by a combination of light curing and heat curing, the semiconductor element 1
The insulating resin 4 protruding to the periphery is light-cured, and the other parts are heat-cured in an oven or the like after removing the pressure.
In the case of heat curing, a heating mechanism is provided on the pressing tool,
Heat and cure with a pressure tool. Next, the pressure tool is removed. At this time, the semiconductor element 1 is fixed by the insulating resin 4 and the first bump 2
The first pad 6 and the first pad 6 are pressed against each other, and an electrical connection by contact is obtained.
【００２２】このようにして、図１のような回路基板１
０が得られる。Thus, the circuit board 1 as shown in FIG.
0 is obtained.
【００２３】かくして本発明の回路基板１０によれば、
半導体素子１の各辺の中央部付近に、電気接続に寄与し
ない第２のバンプ３を形成し、その他の部分に、電気接
続のための接合のバンプ２を形成したため、温度サイク
ル試験等において、半導体素子１と配線基板５との熱膨
張係数の違いにより、繰り返し発生する応力で絶縁性樹
脂４が疲労した場合も、半導体素子１と配線基板５の接
合不良を防ぐことができる。Thus, according to the circuit board 10 of the present invention,
Since the second bump 3 not contributing to the electrical connection was formed near the center of each side of the semiconductor element 1 and the bonding bump 2 for the electrical connection was formed in other portions, Even when the insulating resin 4 is fatigued due to the repeatedly generated stress due to the difference in the coefficient of thermal expansion between the semiconductor element 1 and the wiring board 5, it is possible to prevent the bonding failure between the semiconductor element 1 and the wiring board 5.
【００２４】また、絶縁性樹脂４を塗布後に、配線基板
５のパッド部６，７に半導体素子１のバンプ２，３を超
音波熱接合で圧接する方法を採用でき、従来のラインを
大きく変更する必要がないため、回路基板１０を簡単且
つ安価な工程で製造することができる。Further, after applying the insulating resin 4, a method of pressing the bumps 2, 3 of the semiconductor element 1 to the pad portions 6, 7 of the wiring board 5 by ultrasonic thermal bonding can be adopted, which greatly changes the conventional line. Therefore, the circuit board 10 can be manufactured by a simple and inexpensive process.
【００２５】なお、本発明は上記の実施の形態例に限定
されるものではなく、本発明の要旨を逸脱しない範囲内
での種々の変更や改良等は何ら差し支えない。It should be noted that the present invention is not limited to the above embodiment, and various changes and improvements may be made without departing from the scope of the present invention.
【００２６】例えば、図３に示すように、半導体素子１
と配線基板５の接合強度を向上させるために、第２のバ
ンプ３（第２のパッド７）の径を第１のバンプ２（第１
のパッド６）の径（先端部分が約４０〜６０μｍ、チャ
ンファー部分が約８０〜１００μｍ）より大きくしても
よい。また、このことにより、半導体素子１で発生した
熱を効率よく放散することができるという効果もある。For example, as shown in FIG.
In order to improve the bonding strength between the first bump 2 (the first pad 7) and the wiring board 5, the diameter of the second bump 3 (the second pad 7) is increased.
Of the pad 6) (the tip portion is approximately 40 to 60 μm, and the chamfer portion is approximately 80 to 100 μm). This also has the effect that heat generated in the semiconductor element 1 can be efficiently dissipated.
【００２７】あるいは、図４に示すように、第２のバン
プ３（第２のパッド７）間の間隔を、第１のバンプ２
（第１のパッド６）間の間隔（約１００〜１５０μｍ）
より小さくしてもよい。このことにより、単位面積当た
りの第２のバンプ３（第２のパッド７）の数が増大する
ため、接合強度を向上させることができる。なお、第２
のバンプ３（第２のパッド７）は、電気接続に寄与しな
いため、第２のバンプ３（第２のパッド７）間の間隔を
小さくすることにより、第２のバンプ３（第２のパッド
７）間で導通が生じたとしても、問題とはならない。た
だし、第２のバンプ３（第２のパッド７）を形成する際
の精度から、第２のバンプ３（第２のパッド７）間の間
隔は約５０μｍ以上にすることが望ましい。Alternatively, as shown in FIG. 4, the distance between the second bumps 3 (the second pads 7) is
(Interval between the first pads 6) (about 100 to 150 μm)
It may be smaller. This increases the number of the second bumps 3 (second pads 7) per unit area, so that the bonding strength can be improved. The second
Since the bumps 3 (the second pads 7) do not contribute to the electrical connection, by reducing the distance between the second bumps 3 (the second pads 7), the second bumps 3 (the second pads 7) Even if conduction occurs between 7), no problem occurs. However, from the precision in forming the second bumps 3 (the second pads 7), it is desirable that the interval between the second bumps 3 (the second pads 7) is about 50 μm or more.
【００２８】また、半導体素子１と配線基板５の接合強
度を向上させるために、第２のバンプ３及び第２のパッ
ド７を半導体素子１の中央部に設けてもよい。Further, in order to improve the bonding strength between the semiconductor element 1 and the wiring board 5, the second bump 3 and the second pad 7 may be provided at the center of the semiconductor element 1.
【００２９】また、本実施の形態では、配線基板の実装
面上に１つの半導体素子を接合させたが、複数の半導体
素子を接合させてもよい。Further, in the present embodiment, one semiconductor element is bonded on the mounting surface of the wiring board, but a plurality of semiconductor elements may be bonded.
【００３０】本実施例では、半導体素子１のサイズ２ｍ
ｍ角で、各辺１個、４ｍｍ角で各辺２個の第２のバンプ
３を設けた。配線基板５はガラスセラミックからなり電
極はＡｕメッキが施され、第２のバンプ３は電気的機能
を有していない。配線基板５の半導体実装位置に一定量
の絶縁性樹脂４を塗布する第１の工程と、半導体素子１
の第１のバンプ２、第２のバンプ３と１５０℃に加熱し
た配線基板５の第１のパッド６、第２のパッド７を位置
合わせし、超音波熱接合接合する第２の工程と、接合し
た半導体素子１に荷重及び１５０℃の熱を加え、絶縁性
樹脂４を硬化収縮させる第３の工程により作成される。In this embodiment, the size of the semiconductor device 1 is 2 m.
The second bumps 3 each having one m side and two sides each having 4 mm square were provided. The wiring board 5 is made of glass ceramic, the electrodes are plated with Au, and the second bumps 3 have no electrical function. A first step of applying a fixed amount of insulating resin 4 to a semiconductor mounting position of a wiring board 5;
A second step of aligning the first bumps 2 and the second bumps 3 with the first pads 6 and the second pads 7 of the wiring board 5 heated to 150 ° C. and performing ultrasonic thermal bonding; It is formed by a third step of applying a load and heat of 150 ° C. to the bonded semiconductor element 1 to cure and shrink the insulating resin 4.
【００３１】第１の工程で使用した絶縁性樹脂４はガラ
ス転移点＝１４０℃、線膨張係数＝２５×１０-6ｍｍ／
℃、曲げ弾性率＝１０００ｋｇｆ／ｍｍ2の絶縁性樹脂
を使用した。配線基板５は、線膨張係数＝６．３×１０
-6ｍｍ／℃、曲げ弾性率＝１２９５０ｋｇｆ／ｍｍ2よ
りなるガラスセラミックを使用した。ガラスセラミック
配線基板５の所定の位置に、ディスペンサーにて絶縁性
樹脂４を塗布し、第２の工程である接合するステージに
配線基板５を搬送した。The insulating resin 4 used in the first step had a glass transition point of 140 ° C. and a coefficient of linear expansion of 25 × 10 −6 mm /
An insulating resin having a flexural modulus of 1000 ° C. and a flexural modulus of 1000 kgf / mm 2 was used. The wiring board 5 has a linear expansion coefficient of 6.3 × 10
A glass ceramic having -6 mm / ° C. and a flexural modulus of 12950 kgf / mm 2 was used. The insulating resin 4 was applied to a predetermined position of the glass ceramic wiring substrate 5 with a dispenser, and the wiring substrate 5 was transported to a joining stage which is a second step.
【００３２】接合ステージで配線基板５と半導体素子１
を位置合わせを行うと同時に、配線基板５を１５０℃に
加熱すると共に、４０ｇｆ／バンプの荷重と超音波印加
し接合を行った。その後配線基板５及び接合された半導
体素子１に４０ｇｆ／バンプの荷重と１５０℃を加えて
絶縁性樹脂４を本硬化する第３の工程にて接合を完了し
た。At the joining stage, the wiring board 5 and the semiconductor element 1
At the same time, the wiring substrate 5 was heated to 150 ° C., and a bonding was performed by applying a load of 40 gf / bump and ultrasonic waves. Thereafter, the bonding was completed in a third step of applying a load of 40 gf / bump and 150 ° C. to the wiring substrate 5 and the bonded semiconductor element 1 to fully cure the insulating resin 4.
【００３３】以上の工程で作成した回路基板１０と従来
の回路基板５０を、温度サイクル試験（条件：−４０℃
〜１２５℃、１サイクル／３０分）を行い、接続の信頼
性を確認した。従来の回路基板５０が３００サイクルか
ら接合不良が発生し、７７０サイクルでｎ＝１０個のサ
ンプルがすべて不良となった。これに対し、本発明の回
路基板１０は、１２００サイクル経過後も、ｎ＝１０個
のサンプルに接合不良が発生しなかった。The circuit board 10 prepared in the above steps and the conventional circuit board 50 are subjected to a temperature cycle test (condition: -40 ° C.).
１２５125 ° C., 1 cycle / 30 minutes) to confirm the connection reliability. In the conventional circuit board 50, bonding failure occurred from 300 cycles, and all of n = 10 samples failed in 770 cycles. In contrast, in the circuit board 10 of the present invention, no bonding failure occurred in n = 10 samples even after 1200 cycles.
【００３４】[0034]
【発明の効果】以上に述べたように、本発明によれば、
応力の小さい半導体素子の頂点付近に、電気接続のため
の接合のバンプを形成しているため、温度サイクル試験
等において、半導体素子と配線基板との熱膨張係数の違
いにより、繰り返し発生する応力で絶縁性樹脂が疲労し
た場合も、半導体素子と配線基板の接合不良を防ぐこと
ができる。As described above, according to the present invention,
Since bumps for electrical connection are formed near the apex of the semiconductor element with small stress, in a temperature cycle test etc., due to the difference in the coefficient of thermal expansion between the semiconductor element and the wiring board, the stress generated repeatedly Even when the insulating resin is fatigued, it is possible to prevent poor bonding between the semiconductor element and the wiring board.
【００３５】また、絶縁性樹脂を塗布後に、配線基板の
パッド部に半導体素子のバンプを超音波熱接合で圧接す
る方法を採用でき、従来のラインを大きく変更する必要
がないため、回路基板を簡単且つ安価な工程で製造する
ことができる。In addition, after applying the insulating resin, it is possible to employ a method in which the bump of the semiconductor element is pressed against the pad portion of the wiring board by ultrasonic thermal bonding, and it is not necessary to largely change the conventional line. It can be manufactured by a simple and inexpensive process.
【図１】本発明の回路基板の一実施例の断面図である。FIG. 1 is a sectional view of one embodiment of a circuit board of the present invention.
【図２】図１の回路基板の半導体素子のバンプ配置を示
す実装面の平面図である。FIG. 2 is a plan view of a mounting surface showing a bump arrangement of a semiconductor element of the circuit board of FIG. 1;
【図３】本発明の他の実施例の半導体素子のバンプ配置
を示す実装面の平面図である。FIG. 3 is a plan view of a mounting surface showing a bump arrangement of a semiconductor device according to another embodiment of the present invention.
【図４】本発明の他の実施例の半導体素子のバンプ配置
を示す実装面の平面図である。FIG. 4 is a plan view of a mounting surface showing a bump arrangement of a semiconductor device according to another embodiment of the present invention.
【図５】従来の回路基板の断面図である。FIG. 5 is a cross-sectional view of a conventional circuit board.
【図６】回路基板の内部応力を説明する断面図である。FIG. 6 is a cross-sectional view illustrating an internal stress of the circuit board.
１０、５０ 回路基板 １ 半導体素子 ２ 第１のバンプ ３ 第２のバンプ ４ 絶縁性樹脂 ５ 配線基板 ６ 第１のパッド ７ 第２のパッド 10, 50 Circuit board 1 Semiconductor element 2 First bump 3 Second bump 4 Insulating resin 5 Wiring board 6 First pad 7 Second pad
Claims (1)
バンプを形成させた四角形状の半導体素子を、前記第１
及び第２のバンプと対応する位置に第１及び第２のパッ
ド部を含む表面配線導体を形成した配線基板に接合させ
た回路基板であって、前記半導体素子の実装面の角部付
近に、信号の入出力及び電源供給等を行う前記第１のバ
ンプを配置し、前記半導体素子の各辺の中央部付近に
は、前記半導体素子と前記配線基板との接合のみを行う
前記第２のバンプを配置し、 前記第１及び第２のバンプが、それぞれ前記第１及び第
２のパッドに超音波熱接合により接合されるとともに、
前記半導体素子と前記配線基板との間隔に絶縁性樹脂を
介在させたことを特徴とする回路基板。1. A semiconductor device having a rectangular shape having first and second bumps formed along a peripheral portion of a mounting surface, the first semiconductor device comprising:
And a circuit board joined to a wiring board having surface wiring conductors including first and second pad portions formed at positions corresponding to the second bumps, and near a corner of a mounting surface of the semiconductor element, The first bump for performing signal input / output, power supply, and the like is disposed, and the second bump for performing only bonding between the semiconductor element and the wiring board is provided near a center of each side of the semiconductor element. And the first and second bumps are respectively bonded to the first and second pads by ultrasonic thermal bonding,
A circuit board, wherein an insulating resin is interposed between the semiconductor element and the wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000364014A JP3572254B2 (en) | 2000-11-30 | 2000-11-30 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000364014A JP3572254B2 (en) | 2000-11-30 | 2000-11-30 | Circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002170848A true JP2002170848A (en) | 2002-06-14 |
| JP3572254B2 JP3572254B2 (en) | 2004-09-29 |
Family
ID=18835030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000364014A Expired - Fee Related JP3572254B2 (en) | 2000-11-30 | 2000-11-30 | Circuit board |
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| Country | Link |
|---|---|
| JP (1) | JP3572254B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7071576B2 (en) * | 2003-06-30 | 2006-07-04 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| JP2007214291A (en) * | 2006-02-08 | 2007-08-23 | Fujitsu Ltd | Flip-chip mounting method |
| JP2010278318A (en) * | 2009-05-29 | 2010-12-09 | Renesas Electronics Corp | Semiconductor device |
| JP2013038270A (en) * | 2011-08-09 | 2013-02-21 | Fujitsu Ltd | Electronic device and method for manufacturing the same |
| JP2019129258A (en) * | 2018-01-25 | 2019-08-01 | 浜松ホトニクス株式会社 | Semiconductor device and method for manufacturing semiconductor device |
-
2000
- 2000-11-30 JP JP2000364014A patent/JP3572254B2/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7071576B2 (en) * | 2003-06-30 | 2006-07-04 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| JP4659634B2 (en) * | 2006-02-08 | 2011-03-30 | 富士通株式会社 | Flip chip mounting method |
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| US8975120B2 (en) | 2009-05-29 | 2015-03-10 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
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| JP2013038270A (en) * | 2011-08-09 | 2013-02-21 | Fujitsu Ltd | Electronic device and method for manufacturing the same |
| JP2019129258A (en) * | 2018-01-25 | 2019-08-01 | 浜松ホトニクス株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| WO2019146244A1 (en) * | 2018-01-25 | 2019-08-01 | 浜松ホトニクス株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN111630645A (en) * | 2018-01-25 | 2020-09-04 | 浜松光子学株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| KR20200108889A (en) * | 2018-01-25 | 2020-09-21 | 하마마츠 포토닉스 가부시키가이샤 | Semiconductor device and method of manufacturing semiconductor device |
| US11482555B2 (en) | 2018-01-25 | 2022-10-25 | Hamamatsu Photonics K.K. | Semiconductor device and method for manufacturing semiconductor device |
| JP7236807B2 (en) | 2018-01-25 | 2023-03-10 | 浜松ホトニクス株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN111630645B (en) * | 2018-01-25 | 2023-10-17 | 浜松光子学株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| KR102641911B1 (en) * | 2018-01-25 | 2024-02-29 | 하마마츠 포토닉스 가부시키가이샤 | Semiconductor device, and method of manufacturing the semiconductor device |
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