JP2001127194A - Flip chip semiconductor device and its manufacturing method - Google Patents
Flip chip semiconductor device and its manufacturing methodInfo
- Publication number
- JP2001127194A JP2001127194A JP30649799A JP30649799A JP2001127194A JP 2001127194 A JP2001127194 A JP 2001127194A JP 30649799 A JP30649799 A JP 30649799A JP 30649799 A JP30649799 A JP 30649799A JP 2001127194 A JP2001127194 A JP 2001127194A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- circuit board
- flip
- semiconductor chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29005—Structure
- H01L2224/29007—Layer connector smaller than the underlying bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップを回
路基板にフリップチップ方式にて電気的に接続するフリ
ップチップ型半導体装置及びその製造方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip type semiconductor device for electrically connecting a semiconductor chip to a circuit board by a flip-chip method, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来より電子部品や半導体装置を液状又
はフィルム状の接着樹脂を介して、回路基板上にフリッ
プチップ接続することが一般的に実施されている。接着
樹脂は、熱可塑性或いは熱硬化性の樹脂中に導電性粒子
を分散させ、フィルム状に整形した異方導電性フィルム
（以下、「ＡＦＣ」とする：Ａｎｉｓｏｔｒｏｐｉｃ ｃ
ｏｎｄｕｃｔｉｖｅ ｆｉｌｍ）やペースト状の異方導
電性ペースト（以下、「ＡＦＰ」とする：Ａｎｉｓｏｔｒ
ｏｐｉｃ ｃｏｎｄｕｃｔｉｖｅ ｐａｓｔ）や導電性
の粒子を含まない接着樹脂フィルムやペーストなどが知
られている。2. Description of the Related Art Conventionally, flip-chip connection of an electronic component or a semiconductor device onto a circuit board via a liquid or film-like adhesive resin has been generally practiced. The adhesive resin is an anisotropic conductive film (hereinafter referred to as “AFC”: Anisotropic c) in which conductive particles are dispersed in a thermoplastic or thermosetting resin and shaped into a film.
conductive film) or paste-like anisotropic conductive paste (hereinafter referred to as “AFP”: Anisotr)
There are known an adhesive conductive paste and an adhesive resin film or paste containing no conductive particles.
【０００３】以下、ＡＣＦを用いたフリップチップ接続
工程を図１１を用いて説明する。図１１は従来のフリッ
プチップ型半導体装置の製造工程図である。[0003] A flip chip connection process using an ACF will be described below with reference to FIG. FIG. 11 is a manufacturing process diagram of a conventional flip-chip type semiconductor device.
【０００４】半導体チップ２６のＡｌ電極上には突起電
極２７が形成されている。突起電極２７は金が用いられ
る場合が多いが、これに限定されるものではない。ま
た、突起電極の形成方法として、電解メッキや無電解メ
ッキ、あるいはワイヤーボンドを利用したワイヤーバン
プなどが知られている。A protruding electrode 27 is formed on the Al electrode of the semiconductor chip 26. The protruding electrode 27 is often made of gold, but is not limited thereto. Further, as a method for forming the protruding electrode, electrolytic plating, electroless plating, a wire bump using wire bonding, and the like are known.
【０００５】回路基板２１上には配線パターンが形成さ
れている。半導体チップ２６の電極と対応する位置に、
回路基板２１の電極２２が形成されている。ＡＣＦ接続
の場合、回路基板２１の電極２２を覆うようにＡＣＦ２
４が貼り付けられる。液状熱硬化接着剤を用いた接続で
あれば、ディスペンスなどの手法により、回路基板２１
上に供給される（図１１）。[0005] A wiring pattern is formed on the circuit board 21. At a position corresponding to the electrode of the semiconductor chip 26,
The electrodes 22 of the circuit board 21 are formed. In the case of the ACF connection, the ACF 2 is formed so as to cover the electrode 22 of the circuit board 21.
4 is pasted. In the case of connection using a liquid thermosetting adhesive, the circuit board 21 may be dispensed or the like.
Supplied above (FIG. 11).
【０００６】フリップチップボンダーなどの半導体チッ
プ搭載装置により、半導体チップ２６の電極２７と回路
基板２１の電極２２が位置合わせされ、回路基板２１上
に半導体チップ２６が搭載される。図中符号２５はボン
ディングツールを示す。この時、加圧、加熱などの所定
の条件で、樹脂を押し広げるとともに、硬化させること
で、半導体チップ２６は回路基板２１上に固定され、半
導体チップ２６の突起電極２７と回路基板２１の電極２
２が接触し、導通が得られる。The electrodes 27 of the semiconductor chip 26 and the electrodes 22 of the circuit board 21 are aligned by a semiconductor chip mounting device such as a flip chip bonder, and the semiconductor chip 26 is mounted on the circuit board 21. Reference numeral 25 in the drawing indicates a bonding tool. At this time, the semiconductor chip 26 is fixed on the circuit board 21 by spreading and curing the resin under predetermined conditions such as pressurization and heating, and the protruding electrodes 27 of the semiconductor chip 26 and the electrodes of the circuit board 21 are fixed. 2
2 come into contact, and conduction is obtained.
【０００７】[0007]
【発明が解決しようとする課題】ＡＣＦやＡＣＰなどの
接着樹脂を介して、半導体チップ２６を回路基板２１に
フリップチップ接続する場合には次のような問題があ
る。When the semiconductor chip 26 is flip-chip connected to the circuit board 21 via an adhesive resin such as ACF or ACP, there are the following problems.
【０００８】即ち、半導体チップ２６を回路基板２１に
搭載する際、加熱、加圧により、接着樹脂が流動し、接
着樹脂をチップ下部に押し広げ、チップ外に排出し、樹
脂はみ出し部を形成する。このとき、接着剤中や接着剤
とチップとの間或いは接着剤と回路基板との間に気泡が
生じる。That is, when the semiconductor chip 26 is mounted on the circuit board 21, the adhesive resin flows by heating and pressing, the adhesive resin is spread under the chip, and is discharged out of the chip to form a resin protrusion. . At this time, air bubbles are generated in the adhesive, between the adhesive and the chip, or between the adhesive and the circuit board.
【０００９】この気泡の発生原因は、ＡＦＣの張り付け
時やＡＦＰ等の接着樹脂を回路基板に塗布したときに巻
き込む気泡２８や、加熱により樹脂或いは回路基板より
発生するガス或いは樹脂がチップ下部より外に排出され
る過程で巻き込まれる気泡２８などがある。[0009] The causes of the generation of the bubbles are bubbles 28 which are entrained when the AFC is adhered to the circuit board or when an adhesive resin such as AFP is applied to the circuit board, or when the resin or gas or resin generated from the circuit board is heated from below the chip. There are bubbles 28 and the like that are entrained in the process of being discharged to the air.
【００１０】このように樹脂２４内部に気泡２８を含ん
でいる場合、この部分に空気中の湿気を吸湿し、半田付
けリフロー時にポップコーン現象といわれる、膨れや剥
離などを生じ、場合によってはフリップチップ接続部の
導通不良などの問題が生じる。When the resin 24 contains bubbles 28 as described above, moisture in the air is absorbed in this portion, and swelling or peeling, which is called a popcorn phenomenon at the time of reflow soldering, occurs. Problems such as poor conduction of the connection portion occur.
【００１１】従来技術の課題の説明に供する図である図
１２（ａ）、（ｂ）に示すように、特に半導体チップを
フリップチップ接続後に樹脂封止されたパッケージの場
合、気泡内に吸湿した水分の逃げる経路が無く、チップ
と回路基板との間などで剥離３１をより生じ易くなる。
また、樹脂封止型の半導体装置の場合、図１２（ｂ）に
示すように、半導体チップ２６と回路基板２１との間な
どで剥離３１が生じる他、封止樹脂３０にクラック３２
が生じる。As shown in FIGS. 12 (a) and 12 (b), which are diagrams for explaining the problems of the prior art, in the case of a package in which a semiconductor chip is resin-sealed after flip-chip connection, moisture is absorbed in bubbles. There is no path for moisture to escape, and peeling 31 is more likely to occur between the chip and the circuit board.
In the case of a resin-sealed semiconductor device, as shown in FIG. 12B, peeling 31 occurs between the semiconductor chip 26 and the circuit board 21 or the like, and cracks 32 occur in the sealing resin 30.
Occurs.
【００１２】この気泡は、チップ下部より外部に排出さ
れた樹脂中により多く含まれているため、チップエッジ
部付近やはみ出し部に多く見られる。また、多くの半導
体チップの電極はチップの周辺部に形成されているた
め、フリップチップ接続部の導通不良につながりやす
い。[0012] Since these bubbles are more contained in the resin discharged to the outside from the lower part of the chip, they are often seen near the chip edge and in the protruding part. Further, since the electrodes of many semiconductor chips are formed in the peripheral portion of the chip, it is likely to lead to poor conduction at the flip chip connection portion.
【００１３】このポップコーン現象を防止する手段は、
フリップチップ接続法ではないが、ワイヤーボンディン
グ法による実装体においては、特開平４−１７１９６９
号公報や、特開平１１−２６６２７号公報に開示されて
いる。The means for preventing the popcorn phenomenon is as follows.
Although the flip-chip connection method is not used, in the case of a mounting body by a wire bonding method, Japanese Patent Application Laid-Open No. 4-171969
And Japanese Patent Application Laid-Open No. 11-26627.
【００１４】特開平４−１７１９６９号公報では、チッ
プとワイヤーボンディングの接続パッドとの間に貫通孔
を形成することで、液状の封止樹脂をポッティングする
際に発生する気泡を防止する構成となっている。Japanese Patent Application Laid-Open No. 4-171969 discloses a configuration in which a through hole is formed between a chip and a connection pad for wire bonding to prevent bubbles generated when potting a liquid sealing resin. ing.
【００１５】また、特開平１１−２６６２７号公報で
は、半導体チップを搭載する領域に貫通孔を形成し、貫
通孔を塞がないように接着剤を供給し、貫通孔を塞がな
いように、半導体チップを接着する構成となっている。In Japanese Patent Application Laid-Open No. H11-26627, a through hole is formed in a region where a semiconductor chip is mounted, an adhesive is supplied so as not to block the through hole, and a through hole is formed so as not to block the through hole. The semiconductor chip is bonded.
【００１６】上述の従来技術は、いずれもワイヤーボン
ディング法によるものであり、フリップチップ接続に適
用できるものではない。即ち、特開平４−１７１９６９
号公報では、液状のポッティング樹脂を塗布する際に生
ずる気泡を貫通孔から抜く構成であるため、ＡＣＦやＡ
ＣＰなどのチップと基板との界面から押し上げられた接
着剤中の気泡を抜くことはできない。（なぜ気泡を抜く
ことができないかの理由について、補充願います。）ま
た、特開平１１−２６６２７号公報では、半導体チップ
の搭載部に貫通孔を形成しているが、回路基板の配線レ
イアウトの自由度が小さくなり、また、接着樹脂が押し
つぶされるので、接着樹脂は横方向に強くはみ出す。フ
リップチップの接続は加圧が大きいので、貫通孔を通過
して裏面へはみ出すとステージとチップとが接着し、取
り外せなくなる。また、フリップチップ接続時の特有の
チップエッジ付近に発生する気泡対策にはならない。The above-mentioned prior arts are all based on a wire bonding method and cannot be applied to flip chip connection. That is, JP-A-4-171969
In Japanese Patent Application Laid-Open Publication No. H11-146, since air bubbles generated when applying a liquid potting resin are removed from the through holes, the ACF or ACF is used.
Air bubbles in the adhesive pushed up from the interface between the chip such as CP and the substrate cannot be removed. (Please explain why air bubbles cannot be removed.) Also, in Japanese Patent Application Laid-Open No. 11-26627, a through hole is formed in a mounting portion of a semiconductor chip. Since the degree of freedom is reduced and the adhesive resin is crushed, the adhesive resin protrudes strongly in the lateral direction. Since connection of the flip chip requires a large amount of pressure, if it passes through the through hole and protrudes to the back surface, the stage and the chip adhere to each other and cannot be removed. Also, this is not a countermeasure for bubbles generated near the specific chip edge at the time of flip chip connection.
【００１７】[0017]
【課題を解決するための手段】本発明のフリップチップ
型半導体装置は、第１の電極を有する半導体チップと該
半導体チップと対向する面に前記第１の電極と対向する
位置に第２の電極を有する回路基板とを接続用樹脂を介
してフリップチップ方式にて、電気的に接続するフリッ
プチップ構造半導体装置において、前記半導体チップ外
周端より外側であり、且つ、前記接続用樹脂が前記回路
基板を覆う領域内に少なくとも一部が位置する貫通孔が
前記回路基板に設けられたことを特徴とするものであ
る。A flip chip type semiconductor device according to the present invention comprises a semiconductor chip having a first electrode and a second electrode provided on a surface facing the semiconductor chip at a position facing the first electrode. In a flip-chip structure semiconductor device for electrically connecting a circuit board having a flip-chip method via a connection resin with a circuit board, the connection resin is outside the semiconductor chip outer peripheral end, and the connection resin is formed on the circuit board. Wherein a through-hole at least partially located in a region covering the circuit board is provided in the circuit board.
【００１８】また、本発明のフリップチップ型半導体装
置は、２つの前記貫通孔の間隔が、半導体チップ辺にお
いて、端部よりも中央部において、狭くなっていること
が望ましい。In the flip-chip type semiconductor device according to the present invention, it is preferable that the distance between the two through holes is smaller at the center of the side of the semiconductor chip than at the end.
【００１９】また、本発明のフリップチップ型半導体装
置は、前記貫通孔の半径が、半導体チップの角部よりも
該半導体チップ辺の中央部において、大きくなっている
ことが望ましい。In the flip-chip type semiconductor device according to the present invention, it is preferable that the radius of the through hole is larger in the center of the side of the semiconductor chip than in the corner of the semiconductor chip.
【００２０】また、本発明のフリップチップ型半導体装
置は、前記半導体チップを樹脂封止してもよい。In the flip chip type semiconductor device according to the present invention, the semiconductor chip may be sealed with a resin.
【００２１】更に、本発明のフリップチップ型半導体装
置についての製造方法において、体チップを回路基板に
フリップチップ方式にて電気的に接続した後、半導体チ
ップ搭載面と反対面から前記回路基板の前記半導体チッ
プエッジと接続用樹脂塗布面端との間の領域に、少なく
とも一部が位置する貫通孔を形成することが望ましい。Further, in the method for manufacturing a flip-chip type semiconductor device according to the present invention, after the body chip is electrically connected to the circuit board by the flip-chip method, the circuit board is mounted on the circuit board from the surface opposite to the semiconductor chip mounting surface. It is desirable to form a through-hole at least partially located in a region between the semiconductor chip edge and the end of the connection resin coating surface.
【００２２】[0022]
【発明の実施の形態】以下、実施の形態に基づいて、本
発明のフリップチップ型半導体装置及びその製造方法を
詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a flip-chip type semiconductor device according to the present invention and a method for manufacturing the same will be described in detail based on embodiments.
【００２３】図1は本発明の第1の実施例のフリップチッ
プ型半導体装置の製造工程図、図2は本発明の第１の実
施例に用いる回路基板の裏面図、図3は本発明の作用の
説明に供する図、図４は本発明の第2の実施例のフリッ
プチップ型半導体装置の構造断面図、図5は本発明の第3
の実施例に用いる回路基板の裏面図、図６は本発明の第
３の実施例のフリップチップ型半導体装置の製造工程
図、図７は本発明の第４の実施例のフリップチップ型半
導体装置の製造工程図、図８は本発明の第４の実施例に
用いる回路基板の裏面図、図９は本発明の第５の実施例
のフリップチップ型半導体装置の製造工程図、図１０は
本発明の第６の実施例に用いる回路基板の裏面図であ
る。図１乃至図１０において、１は回路基板、２は回路
基板上に形成された電極、３は水分排出用の貫通孔、４
はＡＣＦ、５はボンディングツール、５ａは加熱ツー
ル、６は半導体チップ、７は半導体チップに設けられた
電極、８は気泡、９は外部接続電極用貫通孔、１０は封
止樹脂、１１は外部接続電極、１２はＡＣＰ（液状の熱
硬化性接着剤）、１３はソルダーレジスト、１４はディ
スペンサー、１５はマスクを示す。FIG. 1 is a manufacturing process diagram of a flip-chip type semiconductor device according to a first embodiment of the present invention, FIG. 2 is a rear view of a circuit board used in the first embodiment of the present invention, and FIG. FIG. 4 is a cross-sectional view illustrating the structure of a flip-chip type semiconductor device according to a second embodiment of the present invention, and FIG.
FIG. 6 is a back view of a circuit board used in the third embodiment, FIG. 6 is a manufacturing process diagram of the flip-chip type semiconductor device of the third embodiment of the present invention, and FIG. 7 is a flip-chip type semiconductor device of the fourth embodiment of the present invention. FIG. 8 is a rear view of a circuit board used in the fourth embodiment of the present invention, FIG. 9 is a manufacturing process diagram of the flip-chip type semiconductor device of the fifth embodiment of the present invention, and FIG. It is a rear view of the circuit board used for the 6th example of the invention. 1 to 10, 1 is a circuit board, 2 is an electrode formed on the circuit board, 3 is a through hole for discharging moisture, 4
Is an ACF, 5 is a bonding tool, 5a is a heating tool, 6 is a semiconductor chip, 7 is an electrode provided on the semiconductor chip, 8 is a bubble, 9 is a through hole for an external connection electrode, 10 is a sealing resin, and 11 is an outside. Reference numeral 12 denotes an ACP (liquid thermosetting adhesive), 13 denotes a solder resist, 14 denotes a dispenser, and 15 denotes a mask.
【００２４】本発明では、チップエッジ部付近に多くの
気泡を含んでいても、膨れや剥離を防止するために、以
下のような構成とする。In the present invention, the following configuration is adopted to prevent swelling and peeling even if many bubbles are contained near the chip edge.
【００２５】チップエッジ部に相当する回路基板に貫通
孔を形成する。貫通孔を形成する位置は、接着樹脂がチ
ップ外に排出された部分が望ましい。樹脂の種類や量、
回路基板の構成により樹脂の排出量は異なるため、最適
な位置に形成する必要がある。A through hole is formed in a circuit board corresponding to a chip edge portion. The position where the through hole is formed is desirably a portion where the adhesive resin is discharged out of the chip. The type and amount of resin,
Since the amount of resin discharged differs depending on the configuration of the circuit board, it is necessary to form the resin at an optimum position.
【００２６】通常樹脂の排出量は、チップの側面から這
い上がった樹脂がチップ裏面に到達しない程度であるの
で、チップエッジより０．１〜１．０ｍｍ程度はみ出
す。この部分に貫通孔を形成する。Usually, the amount of resin discharged is such that the resin crawling up from the side surface of the chip does not reach the back surface of the chip, so that the resin protrudes from the chip edge by about 0.1 to 1.0 mm. A through hole is formed in this portion.
【００２７】この貫通孔により、チップエッジ部に生じ
た気泡に吸湿された水分が、外部に逃げやすくなり、水
分の気化膨張による膨れや剥離を防止することができ
る。また、接着樹脂はチップの辺の中央部付近が最もは
み出し量が多く、気泡も多く見られるため、辺の中央部
付近には貫通孔の密度を高くしたり、開口率を高くする
ことで効果を高めることができる。The through holes facilitate the escape of moisture absorbed by the bubbles generated at the chip edge to the outside, thereby preventing swelling and peeling due to vaporization and expansion of the moisture. In addition, the adhesive resin has the largest amount of protrusion near the center of the side of the chip, and many bubbles are seen.Therefore, it is effective to increase the density of through holes and increase the aperture ratio near the center of the side. Can be increased.
【００２８】貫通孔が樹脂により塞がった場合であって
も、水分が樹脂内を移動し、貫通孔を通じて外部に排出
される効果がある。これはリフロー接続の予熱や加熱時
に水分が、セラミックやガラス基材、あるいはポリイミ
ドやガラスエポキシ等の基材中よりも、接着樹脂中を透
過し、外部に排出されやすいためである。Even when the through-hole is closed by the resin, there is an effect that moisture moves in the resin and is discharged to the outside through the through-hole. This is because moisture is more likely to pass through the adhesive resin and be discharged to the outside during preheating or heating of the reflow connection than in a ceramic or glass substrate or a substrate such as polyimide or glass epoxy.
【００２９】本発明は、ＡＣＦやＡＣＰなどの接着樹脂
を用いたフリップチップ接続に特有のはみ出し部分付近
に発生する気泡の吸湿によるポップコーン現象を防止す
ることが目的であり、貫通孔の形成位置をチップエッジ
部付近にするものである。An object of the present invention is to prevent a popcorn phenomenon due to moisture absorption of bubbles generated near a protruding portion which is peculiar to flip chip connection using an adhesive resin such as ACF or ACP. It is located near the chip edge.
【００３０】つまり、半導体チップのエッジから±１ｍ
ｍ以内に貫通孔を形成することで、チップエッジ部付近
に生じた気泡が吸湿しても、リフロー時に水分が貫通孔
を通じて、外部に排出されやすくなるため、膨れや剥離
などのポップコーン現象を防ぐことが可能となる。ま
た、通常接着樹脂は、半導体チップの辺の中央部が最も
はみ出し量が大きく、同心円状に広がるため、辺の中央
部で、隣接する貫通孔３、３の間隔を狭くし、密度を高
めたり、貫通孔３の径を大きくすることで、より大きな
効果が得られるものである。That is, ± 1 m from the edge of the semiconductor chip
By forming a through hole within m, even if bubbles generated near the chip edge absorb moisture, it is easy to discharge water to the outside through the through hole during reflow, preventing popcorn phenomena such as blistering and peeling. It becomes possible. In addition, the adhesive resin usually has the largest amount of protrusion at the center of the side of the semiconductor chip and spreads concentrically. Therefore, at the center of the side, the interval between the adjacent through holes 3 is narrowed to increase the density. By increasing the diameter of the through hole 3, a greater effect can be obtained.
【００３１】図１の示すように、回路基板１には半導体
チップ６の電極７に対応した位置に配線の一部となる電
極２が形成されている。回路基板１は７５〜９０μｍの
厚みのポリイミドをベースとした基板で、接着剤（図示
せず）を介して、Ｃｕ箔が貼り付けられ、パターニング
されている。通常、回路基板１の配線はＣｕ配線にＮｉ
メッキ及び金メッキを順次施したものが多く用いられて
いる。配線の厚みは１５〜４０μｍ程度である。図２に
示すように、半導体チップ６の周辺には貫通孔３が複数
個形成されている。貫通孔３の形成位置は、チップエッ
ジの少なくとも一部が外側に位置すればよく、配線の引
き回しに合わせて形成すればよい。本発明の効果を十分
に発揮するためには、ＡＣＦなどの接着用の樹脂中に気
泡が多く含まれている部分に形成する。したがって、概
ねチップエッジの±１ｍｍ以内、好ましくは±０．５ｍ
ｍ以内に形成する。As shown in FIG. 1, the circuit board 1 has electrodes 2 which are to be a part of the wiring formed at positions corresponding to the electrodes 7 of the semiconductor chip 6. The circuit board 1 is a substrate based on polyimide having a thickness of 75 to 90 μm, and is patterned by attaching a Cu foil via an adhesive (not shown). Usually, the wiring of the circuit board 1 is Ni
Those subjected to plating and gold plating sequentially are often used. The thickness of the wiring is about 15 to 40 μm. As shown in FIG. 2, a plurality of through holes 3 are formed around the semiconductor chip 6. The through hole 3 may be formed at least partially outside the chip edge, and may be formed in accordance with the wiring layout. In order to sufficiently exhibit the effects of the present invention, the adhesive is formed at a portion where a large amount of bubbles are contained in an adhesive resin such as ACF. Therefore, generally within ± 1 mm of the chip edge, preferably ± 0.5 m
m.
【００３２】回路基板１の配線ピッチや引き回しにより
その径は決定されるが、概ね５０〜３００μｍ程度であ
る。貫通孔３の形成方法としては、ドリルやレーザーな
どが用いられるが、どのような形成方法を用いてもよ
い。貫通孔の形状は、円以外の矩形等でも問題ない。The diameter of the circuit board 1 is determined by the wiring pitch and wiring, but is generally about 50 to 300 μm. As a method for forming the through hole 3, a drill, a laser, or the like is used, but any method may be used. The shape of the through hole may be a rectangle other than a circle without any problem.
【００３３】回路基板１上には電極２部分を覆うように
異方導電性接着フィルム（以下、「ＡＣＦ」という）４が
貼り付けられている。ＡＣＦ４は図１（ａ）に示すよう
に加熱ツール５ａにより圧着されるため、配線の段差
（図1（ｂ）においては電極２、２間）で空気を挟み込
んだ状態で貼り付けられる。An anisotropic conductive adhesive film (hereinafter, referred to as “ACF”) 4 is attached on the circuit board 1 so as to cover the electrodes 2. Since the ACF 4 is pressure-bonded by the heating tool 5a as shown in FIG. 1A, the ACF 4 is attached in a state where air is sandwiched between wiring steps (in FIG. 1B, between the electrodes 2 and 2).
【００３４】次に、回路基板１の電極２と半導体チップ
６の電極７をフリップチップボンダーなどの搭載装置を
用いて位置合わせを行ない、回路基板１上に半導体チッ
プ６を搭載する。この時、所定の圧力と加熱によりＡＣ
Ｆ４は流動し、半導体チップ６と回路基板１間から余分
なＡＣＦ４が排出されるとともに硬化が進行する。半導
体チップ６中央部付近に存在した気泡８や、加熱により
発生したガスによる気泡、或いは、ＡＣＦ４中から発生
したガスによる気泡８ａ等がＡＣＦ４と共に排出される
が、チップエッジ部やはみ出し部４ａには残ってしまう
（図１（ｃ））。Next, the electrodes 2 of the circuit board 1 and the electrodes 7 of the semiconductor chip 6 are aligned using a mounting device such as a flip chip bonder, and the semiconductor chip 6 is mounted on the circuit board 1. At this time, a predetermined pressure and heating cause AC
F4 flows, and excess ACF4 is discharged from between the semiconductor chip 6 and the circuit board 1 and curing proceeds. Bubbles 8 existing near the center of the semiconductor chip 6, bubbles due to gas generated by heating, or bubbles 8 a due to gas generated from the ACF 4 are discharged together with the ACF 4. It remains (FIG. 1C).
【００３５】こうして得られたフリップチップ型半導体
装置を吸湿リフローテストの実施や室内に保存すること
で、フリップチップ型半導体装置は吸湿する。空気中の
水分は密着力の弱い界面や気泡などに多く貯えられ、リ
フロー接続時に気化、膨張し、界面はや膨れなどを生じ
る。The flip-chip type semiconductor device thus obtained absorbs moisture by conducting a moisture absorption reflow test or storing it indoors. A large amount of moisture in the air is stored in an interface or air bubble having a weak adhesive force, and vaporizes and expands at the time of reflow connection, causing the interface to swell.
【００３６】しかしながら、本発明では、気泡の発生す
る位置の回路基板に貫通孔を形成しているため、接着樹
脂中の気泡に貯えられた水分が接着樹脂４、４ａ中を移
動し、貫通孔３を通じて外部に排出されるため、界面剥
離や膨れを生ずることがない（図３）。However, in the present invention, since the through holes are formed in the circuit board at the positions where the bubbles are generated, the moisture stored in the bubbles in the adhesive resin moves through the adhesive resins 4 and 4a, and the through holes are formed. 3, there is no interface separation or swelling (FIG. 3).
【００３７】ここでは、ポリイミドをベースとした基板
を前提に説明してきたが、ガラスエポキシ基板や各種セ
ラミック基板、ガラス基板であっても同様の効果が得ら
れる。特に、セラミック基板やガラス基板などの水分を
透過しにくい基材を用いた場合は、接着樹脂中の水分が
移動し、貫通孔３から排出される効果が高い。Although the description has been made on the assumption that the substrate is based on polyimide, similar effects can be obtained with a glass epoxy substrate, various ceramic substrates, and a glass substrate. In particular, when a substrate such as a ceramic substrate or a glass substrate that does not easily transmit moisture is used, the effect is high that moisture in the adhesive resin moves and is discharged from the through holes 3.
【００３８】また、第２の実施例として、本発明は、図
４に示すように、半導体チップ６と回路基板１のチップ
搭載面が、モールド樹脂１０により樹脂封止されパッケ
ージ化されたフリップチップ実装体にも適用可能であ
る。このような封止構造体では、リフロー時に気化、膨
張した水分の逃げ道がないため、モールド樹脂１０内部
や回路基板１とモールド樹脂界面、或いは半導体チップ
６とＡＣＦ４界面などで剥離を生じ易くなるが、本発明
では、気泡の発生する位置の回路基板１に貫通孔３を形
成しているため、接着樹脂中の気泡に貯えられた水分が
接着樹脂中を移動し、貫通孔３を通じて外部に排出され
るため、界面剥離や膨れを生ずることがない。尚、図４
は第１の実施例と同様に、ＡＣＦ４を用いて半導体チッ
プ６が回路基板１に接続されている。回路基板１には貫
通孔３が形成されており、外部接続電極用貫通孔９を通
して、外部接続電極１１が回路基板１の配線と接続され
ている。As a second embodiment, the present invention relates to a flip chip in which the chip mounting surfaces of the semiconductor chip 6 and the circuit board 1 are sealed with a mold resin 10 and packaged as shown in FIG. It is also applicable to a mounted body. In such a sealing structure, since there is no escape path for the vaporized and expanded moisture at the time of reflow, separation easily occurs inside the mold resin 10, at the interface between the circuit board 1 and the mold resin, or at the interface between the semiconductor chip 6 and the ACF4. According to the present invention, since the through holes 3 are formed in the circuit board 1 at positions where bubbles are generated, moisture stored in the bubbles in the adhesive resin moves through the adhesive resin and is discharged to the outside through the through holes 3. Therefore, there is no occurrence of interface peeling or swelling. FIG.
The semiconductor chip 6 is connected to the circuit board 1 using the ACF 4 as in the first embodiment. The through hole 3 is formed in the circuit board 1, and the external connection electrode 11 is connected to the wiring of the circuit board 1 through the through hole 9 for the external connection electrode.
【００３９】次に第３の実施例について、図５乃至図７
を用いて説明する。Next, a third embodiment will be described with reference to FIGS.
This will be described with reference to FIG.
【００４０】回路基板１は第１の実施例と同様である
が、図５に示すように、チップの辺の中央部付近に貫通
孔３の密度が高くなるように形成した。本実施例におい
ては、図６（ａ）に示すように、回路基板１のチップ搭
載部にエポキシを主成分とする液状の熱硬化性接着剤１
２がディスペンサー１４等を用いて塗布されている。導
電性粒子を含むものは異方性導電性ペースト（ＡＣＰ）
と呼ばれるものが市販されているが、導電性粒子を含ま
ない接着剤でもよい。The circuit board 1 was the same as that of the first embodiment, but was formed so as to increase the density of the through holes 3 near the center of the side of the chip as shown in FIG. In this embodiment, as shown in FIG. 6A, a liquid thermosetting adhesive 1 containing epoxy as a main component is mounted on a chip mounting portion of a circuit board 1.
2 is applied using a dispenser 14 or the like. Those containing conductive particles are anisotropic conductive paste (ACP)
Is commercially available, but an adhesive containing no conductive particles may be used.
【００４１】回路基板１の電極２と半導体チップ６の電
極７をフリップチップボンダーなどの搭載装置を用いて
位置あわせを行ない、回路基板１上に半導体チップ６を
搭載する。図６（ｂ）に示すように、チップ６により液
状の接着剤１２は押し広げられ、チップ６と回路基板１
との間から余分な接着剤１２が排出される。同時に加熱
することで接着剤が硬化される。この時、チップ下部の
気泡８は接着剤１２と共に排出され、チップエッジ部付
近やはみ出し部１２ａに溜まる。The electrodes 2 of the circuit board 1 and the electrodes 7 of the semiconductor chip 6 are aligned using a mounting device such as a flip chip bonder, and the semiconductor chip 6 is mounted on the circuit board 1. As shown in FIG. 6B, the liquid adhesive 12 is spread by the chip 6, and the chip 6 and the circuit board 1 are spread.
The excess adhesive 12 is discharged from between the positions. The adhesive is cured by heating at the same time. At this time, the air bubbles 8 at the lower part of the chip are discharged together with the adhesive 12 and accumulate near the chip edge and in the protruding part 12a.
【００４２】はみ出しの形状を図５（ｂ）に示す。チッ
プ外に排出された接着剤は同心円状に広がるため、半導
体チップ６の辺の中央部が最も大きくはみ出し、角部で
のはみ出しが小さくなる。気泡が含まれるはみ出し部１
２ａの下部により多くの貫通孔３を形成しているため、
リフロー時に水分が貫通孔３から排出される。The protruding shape is shown in FIG. Since the adhesive discharged outside the chip spreads concentrically, the center of the side of the semiconductor chip 6 protrudes most, and the protrusion at the corner becomes small. Protruding part 1 containing air bubbles
Since more through holes 3 are formed in the lower part of 2a,
Water is discharged from the through holes 3 during reflow.
【００４３】液状の熱硬化性接着剤を用いた場合を説明
したが、ＡＣＦなどのフィルム状の接着剤であっても、
同様に同心円状に広がるため、半導体チップの辺の中央
でのはみ出しが大きくなり、本発明の効果がある。Although the case where a liquid thermosetting adhesive is used has been described, a film-like adhesive such as ACF may be used.
Similarly, since it spreads concentrically, the protrusion at the center of the side of the semiconductor chip becomes large, and the effect of the present invention is obtained.
【００４４】なお、貫通孔がＡＣＰなどの封止材により
塞がったとしても、本発明の効果は得られる。回路基板
の基材を通しては水分が逃げ難いが、エポキシ樹脂内は
比較的水分が移動しやすく、リフローの予熱時や昇温の
過程で貫通孔を通じて水分が排出されるためである。The effect of the present invention can be obtained even if the through hole is closed by a sealing material such as ACP. Although it is difficult for moisture to escape through the base material of the circuit board, the moisture easily moves in the epoxy resin, and the moisture is discharged through the through holes during preheating of reflow or during the process of raising the temperature.
【００４５】次に、第４の実施例について、図７及び図
８を用いて説明する。Next, a fourth embodiment will be described with reference to FIGS.
【００４６】本実施例では、第１の実施例と同様に回路
基板１上にＡＣＦ４が貼り付けられているが、図８に示
すようにチップ６の辺の中央部付近にいくほど開口径の
大きな貫通孔３が形成されている。In this embodiment, the ACF 4 is adhered on the circuit board 1 as in the first embodiment. However, as shown in FIG. A large through hole 3 is formed.
【００４７】まず、図７に示すように、回路基板１の電
極２と半導体チップ６の電極７をフリップチップボンダ
ーなどの搭載装置を用いて、位置合わせを行ない、回路
基板１上に半導体チップ６を搭載する。回路基板１の配
線上にはソルダーレジスト１３が形成されており、配線
の段差は比較的小さくなっているため、気泡の巻き込み
は低減されている。しかし、基板１のチップエッジにお
ける電極２ａ部分は配線の段差とソルダーレジスト１３
の段差が加わり、大きな段差ができるため、気泡８の巻
き込みが大きくなっている。所定の圧力と加熱によりＡ
ＣＦ４は流動し、チップ６と回路基板１との間から余分
なＡＣＦ４が排出されると共に硬化が進行する。チップ
中央部付近に存在した気泡もＡＣＦ４と共に排出される
が、電極部付近の気泡と共にチップエッジ部やフィレッ
ト部に残ってしまう。First, as shown in FIG. 7, the electrodes 2 of the circuit board 1 and the electrodes 7 of the semiconductor chip 6 are aligned using a mounting device such as a flip chip bonder. With. Since the solder resist 13 is formed on the wiring of the circuit board 1 and the step of the wiring is relatively small, the entrapment of air bubbles is reduced. However, the electrode 2a at the chip edge of the substrate 1 has a wiring step and a solder resist 13a.
Is added, and a large step is formed, so that the entrapment of the bubble 8 is increased. A at a given pressure and heating
The CF4 flows, excess ACF4 is discharged from between the chip 6 and the circuit board 1, and curing proceeds. The bubbles existing near the center of the chip are also discharged together with the ACF4, but remain at the chip edge and fillet together with the bubbles near the electrode.
【００４８】次に、図７（ｃ）に示すように、このフリ
ップチップ型半導体装置をトランスファモールドにより
樹脂封止し、回転基板裏面の外部電極取り出し部に半田
ボール１１を形成することで、ボールグリッドアレイの
ような半導体パッケージが得られる。半導体パッケージ
のチップエッジ部付近の気泡に空気中の水分を吸湿し貯
えられた水分はリフロー接続時に気化、膨張しようとす
るが、リフローの予熱部等で回路基板に形成された貫通
孔３より水分が排出されるため、ポップコーン現象の発
生はなく、高い信頼性が確保できる。Next, as shown in FIG. 7C, the flip-chip type semiconductor device is resin-sealed by transfer molding, and solder balls 11 are formed at the external electrode take-out portions on the back surface of the rotating substrate. A semiconductor package such as a grid array is obtained. Moisture in the air is absorbed by bubbles in the vicinity of the chip edge of the semiconductor package, and the stored water tends to evaporate and expand at the time of reflow connection. Is discharged, so that no popcorn phenomenon occurs and high reliability can be ensured.
【００４９】次に第5の実施例について、図９を用いて
説明する。Next, a fifth embodiment will be described with reference to FIG.
【００５０】図９は実施例４と同様の手法により作成し
たフリップチップ型半導体装置の回路基板側にマスク１
５を位置合わせし、レーザーにより貫通孔３ａを形成す
る工程を示した略図である。レーザーに限らずドリルに
よる貫通孔３ａの形成など、他の手法を用いてもよい。
また、フリップチップ型半導体装置は実施例４以外の実
施例におけるフリップチップ型半導体装置においても適
用可能である。FIG. 9 shows a mask 1 on the circuit board side of a flip-chip type semiconductor device prepared by the same method as in the fourth embodiment.
5 is a schematic view showing a process of aligning No. 5 and forming a through hole 3a by laser. Not only the laser but also another method such as formation of the through hole 3a by a drill may be used.
Further, the flip-chip type semiconductor device can be applied to the flip-chip type semiconductor devices in the embodiments other than the fourth embodiment.
【００５１】フリップチップ実装後に貫通孔３を形成す
ることで、貫通孔３が接着樹脂で塞がることなく、ま
た、一部の気泡が開口するなど、リフロー時の水分がよ
り抜けやすい構造となる。By forming the through-holes 3 after the flip chip mounting, the through-holes 3 are not closed by the adhesive resin, and a structure in which moisture is easily removed at the time of reflow, such as opening of some bubbles, is obtained.
【００５２】また、本発明において、図１１に示すよう
に回路基板のチップエッジ接触領域上に貫通孔３を設け
てもよい。In the present invention, as shown in FIG. 11, a through hole 3 may be provided on the chip edge contact area of the circuit board.
【００５３】以上、本発明は、フリップチップ方式を用
いて、回路基板に半導体チップを搭載する半導体装置に
おいて、少なくとも半導体チップ６のエッジより外側
に、少なくとも一部が位置する貫通孔３を回路基板１に
設けていればよく、上述の実施例に記載の貫通孔３の形
状、配列と回路基板１及び半導体チップの接続方法（Ａ
ＣＦを用いるか、ＡＣＰを用いるか、またはソルダーレ
ジストを用いるか否か）との組み合わせは上述の実施例
に限定されるものではない。As described above, according to the present invention, in a semiconductor device in which a semiconductor chip is mounted on a circuit board by using a flip-chip method, at least a part of the through-hole 3 located outside the edge of the semiconductor chip 6 is formed in the circuit board. 1, the shape and arrangement of the through holes 3 described in the above embodiment and the method of connecting the circuit board 1 and the semiconductor chip (A
Whether to use CF, use ACP, or use solder resist) is not limited to the above embodiment.
【００５４】[0054]
【発明の効果】以上、詳細に説明したように、本発明
の、第１の電極を有する半導体チップと該半導体チップ
と対向する面に前記第１の電極と対向する位置に第２の
電極を有する回路基板とを接続用樹脂を介してフリップ
チップ方式にて、電気的に接続するフリップチップ構造
半導体装置において、前記半導体チップ外周端より外側
であり、且つ、前記接続用樹脂が前記回路基板を覆う領
域内に少なくとも一部が位置する貫通孔が前記回路基板
に設けられたことフリップチップ構造の半導体装置を用
いることによって、また、本発明のように、２つの前記
貫通孔の間隔が、半導体チップ辺において、端部よりも
中央部において狭くなるようにすることによって、より
効率的に水分を排出することができるので、ポップコー
ン現象を抑制することができる。As described above in detail, according to the present invention, the semiconductor chip having the first electrode and the second electrode are provided on the surface facing the semiconductor chip at the position facing the first electrode. In a flip-chip structure semiconductor device that is electrically connected to a circuit board having a flip-chip method via a connection resin, the flip-chip structure semiconductor device is located outside the outer peripheral edge of the semiconductor chip, and the connection resin is connected to the circuit board. By using a semiconductor device having a flip-chip structure in which a through hole at least a part of which is located in a region to be covered is provided in the circuit board, and as in the present invention, the distance between the two By making the center of the chip narrower at the center than at the end, water can be discharged more efficiently, thus suppressing the popcorn phenomenon. Can.
【００５５】また、本発明のように、フリップチップ構
造半導体装置は、前記貫通孔の半径が、半導体チップの
角部よりも該半導体チップ辺の中央部において大きくす
ることによって、更により効率的に水分を排出すること
ができるので、ポップコーン現象を抑制することができ
る。Further, as in the present invention, in the flip-chip structure semiconductor device, the radius of the through hole is made larger at the center of the side of the semiconductor chip than at the corner of the semiconductor chip, so that the efficiency is further improved. Since water can be discharged, the popcorn phenomenon can be suppressed.
【００５６】また、本発明のように、半導体チップを樹
脂封止することによって、プリント基板等に実装し、携
帯電話等に組み込まれても、半導体チップ等を保護する
ことができる。Further, as in the present invention, the semiconductor chip can be protected by sealing the semiconductor chip with resin so that the semiconductor chip can be mounted on a printed circuit board or the like and incorporated into a mobile phone or the like.
【００５７】更に、本発明のように、フリップチップ構
造半導体装置についての製造方法において、半導体チッ
プを回路基板にフリップチップ方式にて電気的に接続し
た後、半導体チップ搭載面と反対面から前記回路基板の
前記半導体チップエッジと接続用樹脂塗布面端との間の
領域に少なくとも一部が位置するように貫通孔を形成す
ることにより、貫通孔が接着用樹脂で塞がること無く、
また、一部の気泡が開口することができ、リフロー時の
水分が選り抜けやすい構造にすることができる。Further, as in the present invention, in a method of manufacturing a semiconductor device having a flip-chip structure, a semiconductor chip is electrically connected to a circuit board by a flip-chip method, and then the circuit is mounted on a surface opposite to the semiconductor chip mounting surface. By forming a through-hole so that at least a part is located in a region between the semiconductor chip edge of the substrate and the end of the connection resin application surface, the through-hole is not closed by the adhesive resin,
In addition, a structure can be provided in which some of the bubbles can be opened, and moisture during reflow can be easily selected.
【図１】本発明の第１の実施例のフリップチップ型半導
体装置の製造工程図である。FIG. 1 is a manufacturing process diagram of a flip-chip type semiconductor device according to a first embodiment of the present invention.
【図2】本発明の第１の実施例に用いる回路基板の裏面
図である。FIG. 2 is a back view of the circuit board used in the first embodiment of the present invention.
【図3】本発明の作用の説明に供する図である。FIG. 3 is a diagram provided for describing an operation of the present invention.
【図４】本発明の第2の実施例のフリップチップ型半導
体装置の構造断面図である。FIG. 4 is a structural sectional view of a flip-chip type semiconductor device according to a second embodiment of the present invention.
【図5】（ａ）は本発明の第3の実施例に用いる、チップ
エッジの中央部において貫通孔密度が高くなっている回
路基板の裏面図であり、（ｂ）は同中央部において貫通
孔の径が大きくなっている回路基板の裏面図である。FIG. 5A is a rear view of a circuit board used in a third embodiment of the present invention, in which a through hole density is high at a central portion of a chip edge, and FIG. FIG. 4 is a rear view of the circuit board in which the diameter of the hole is large.
【図６】本発明の第３の実施例のフリップチップ型半導
体装置の製造工程図である。FIG. 6 is a manufacturing process diagram of the flip-chip type semiconductor device according to the third embodiment of the present invention.
【図７】本発明の第４の実施例のフリップチップ型半導
体装置の製造工程図である。FIG. 7 is a manufacturing process diagram of the flip-chip type semiconductor device according to the fourth embodiment of the present invention.
【図８】本発明の第４の実施例に用いる回路基板の裏面
図である。FIG. 8 is a back view of a circuit board used in a fourth embodiment of the present invention.
【図９】本発明の第５の実施例のフリップチップ型半導
体装置の製造工程図である。FIG. 9 is a manufacturing process diagram of the flip-chip type semiconductor device according to the fifth embodiment of the present invention.
【図１０】本発明の第６の実施例に用いる回路基板の裏
面図である。FIG. 10 is a back view of a circuit board used in a sixth embodiment of the present invention.
【図１１】従来のフリップチップ型半導体装置の製造工
程図である。FIG. 11 is a manufacturing process diagram of a conventional flip-chip type semiconductor device.
【図１２】従来技術の課題の説明に供する図である。FIG. 12 is a diagram provided for describing a problem of the related art.
１ 回路基板 ２ 回路基板上に形成された電極 ３ 水分排出用の貫通孔 ４ ＡＣＦ ５ ボンディングツール ５ａ 加熱ツール ６ 半導体チップ ７ 半導体チップに設けられた電極 ８ 気泡 ９ 外部接続電極用貫通孔 １０ 封止樹脂 １１ 外部接続電極 １２ ＡＣＰ（液状の熱硬化性接着剤） １３ ソルダーレジスト １４ ディスペンサー １５ マスク REFERENCE SIGNS LIST 1 circuit board 2 electrode formed on circuit board 3 through hole for discharging moisture 4 ACF 5 bonding tool 5 a heating tool 6 semiconductor chip 7 electrode provided on semiconductor chip 8 bubble 9 through hole for external connection electrode 10 sealing Resin 11 External connection electrode 12 ACP (liquid thermosetting adhesive) 13 Solder resist 14 Dispenser 15 Mask
───────────────────────────────────────────────────── フロントページの続き (72)発明者 玉置 和雄 大阪府大阪市阿倍野区長池町22番22号 シ ャープ株式会社内 Ｆターム(参考） 5F044 KK01 KK27 LL09 RR12 RR16 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Tamaki 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka F-term (reference) 5F044 KK01 KK27 LL09 RR12 RR16
Claims (5)
導体チップと対向する面に前記第１の電極と対向する位
置に第２の電極を有する回路基板とを接続用樹脂を介し
てフリップチップ方式にて、電気的に接続するフリップ
チップ型半導体装置において、 前記半導体チップ外周端より外側であり、且つ、前記接
続用樹脂が前記回路基板を覆う領域内に少なくとも一部
が位置する貫通孔が前記回路基板に設けられたことを特
徴とするフリップチップ型半導体装置。A flip chip including a semiconductor chip having a first electrode and a circuit board having a second electrode on a surface facing the semiconductor chip and a position facing the first electrode via a connection resin. In a flip-chip type semiconductor device which is electrically connected by a method, a through hole which is at least partially located in an area outside the semiconductor chip outer peripheral end and in which the connection resin covers the circuit board is provided. A flip chip type semiconductor device provided on the circuit board.
プ辺において、端部よりも中央部において、狭くなって
いることを特徴とする、請求項１に記載のフリップチッ
プ型半導体装置。2. The flip-chip type semiconductor device according to claim 1, wherein an interval between the two through holes is narrower at the center of the side of the semiconductor chip than at the end.
部よりも該半導体チップ辺の中央部において、大きくな
っていることを特徴とする、請求項１又は請求項２に記
載のフリップチップ型半導体装置。3. The flip chip according to claim 1, wherein a radius of the through hole is larger in a central portion of a side of the semiconductor chip than in a corner of the semiconductor chip. Type semiconductor device.
特徴とする、請求項１〜請求項４のいずれかに記載のフ
リップチップ型半導体装置。4. The flip chip type semiconductor device according to claim 1, wherein said semiconductor chip is sealed with a resin.
ップ型半導体装置の製造方法において、 半導体チップを回路基板にフリップチップ方式にて電気
的に接続した後、半導体チップ搭載面と反対面から前記
回路基板の前記半導体チップエッジと接続用樹脂塗布面
端との間の領域に、少なくとも一部が位置するように貫
通孔を形成することを特徴とする、フリップチップ型半
導体装置の製造方法。5. The method of manufacturing a flip-chip type semiconductor device according to claim 1, wherein the semiconductor chip is electrically connected to a circuit board by a flip-chip method, and then the surface opposite to the semiconductor chip mounting surface. Forming a through hole in a region between the semiconductor chip edge of the circuit board and the end of the connection resin coating surface so as to at least partially locate the through hole. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30649799A JP3485509B2 (en) | 1999-10-28 | 1999-10-28 | Flip chip type semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30649799A JP3485509B2 (en) | 1999-10-28 | 1999-10-28 | Flip chip type semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001127194A true JP2001127194A (en) | 2001-05-11 |
| JP3485509B2 JP3485509B2 (en) | 2004-01-13 |
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ID=17957747
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30649799A Expired - Fee Related JP3485509B2 (en) | 1999-10-28 | 1999-10-28 | Flip chip type semiconductor device and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP3485509B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005076352A1 (en) * | 2004-02-05 | 2005-08-18 | Renesas Technology Corp. | Semiconductor device and method for manufacturing semiconductor device |
| JP2006019450A (en) * | 2004-06-30 | 2006-01-19 | Sumitomo Metal Micro Devices Inc | Circuit board and substrate after packaged |
| WO2008050635A1 (en) * | 2006-10-19 | 2008-05-02 | Panasonic Corporation | Semiconductor element mounting structure and semiconductor element mounting method |
| JP2008270646A (en) * | 2007-04-24 | 2008-11-06 | Toppan Forms Co Ltd | Conductive connection structure and its manufacturing method |
| JP2010034590A (en) * | 2009-11-09 | 2010-02-12 | Panasonic Corp | Semiconductor device and method of mounting the same |
| US7687319B2 (en) | 2005-10-06 | 2010-03-30 | Fujitsu Microelectronics Limited | Semiconductor device and manufacturing method thereof |
| WO2021015008A1 (en) * | 2019-07-24 | 2021-01-28 | Tdk株式会社 | Electronic component-embedded substrate |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1126483A (en) * | 1997-06-30 | 1999-01-29 | Matsushita Electric Works Ltd | Resin sealing semiconductor device and method for resin sealing |
| JPH1126627A (en) * | 1997-07-03 | 1999-01-29 | Mitsui Chem Inc | Semiconductor mounting board |
| JP2000183237A (en) * | 1998-12-10 | 2000-06-30 | Sony Corp | Semiconductor device, printed wiring board, and manufacture thereof |
-
1999
- 1999-10-28 JP JP30649799A patent/JP3485509B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1126483A (en) * | 1997-06-30 | 1999-01-29 | Matsushita Electric Works Ltd | Resin sealing semiconductor device and method for resin sealing |
| JPH1126627A (en) * | 1997-07-03 | 1999-01-29 | Mitsui Chem Inc | Semiconductor mounting board |
| JP2000183237A (en) * | 1998-12-10 | 2000-06-30 | Sony Corp | Semiconductor device, printed wiring board, and manufacture thereof |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005076352A1 (en) * | 2004-02-05 | 2005-08-18 | Renesas Technology Corp. | Semiconductor device and method for manufacturing semiconductor device |
| JP2006019450A (en) * | 2004-06-30 | 2006-01-19 | Sumitomo Metal Micro Devices Inc | Circuit board and substrate after packaged |
| US7687319B2 (en) | 2005-10-06 | 2010-03-30 | Fujitsu Microelectronics Limited | Semiconductor device and manufacturing method thereof |
| WO2008050635A1 (en) * | 2006-10-19 | 2008-05-02 | Panasonic Corporation | Semiconductor element mounting structure and semiconductor element mounting method |
| JPWO2008050635A1 (en) * | 2006-10-19 | 2010-02-25 | パナソニック株式会社 | Semiconductor element mounting structure and semiconductor element mounting method |
| US8106521B2 (en) | 2006-10-19 | 2012-01-31 | Panasonic Corporation | Semiconductor device mounted structure with an underfill sealing-bonding resin with voids |
| JP5066529B2 (en) * | 2006-10-19 | 2012-11-07 | パナソニック株式会社 | Semiconductor element mounting structure and semiconductor element mounting method |
| JP2008270646A (en) * | 2007-04-24 | 2008-11-06 | Toppan Forms Co Ltd | Conductive connection structure and its manufacturing method |
| JP2010034590A (en) * | 2009-11-09 | 2010-02-12 | Panasonic Corp | Semiconductor device and method of mounting the same |
| WO2021015008A1 (en) * | 2019-07-24 | 2021-01-28 | Tdk株式会社 | Electronic component-embedded substrate |
| JP2021019168A (en) * | 2019-07-24 | 2021-02-15 | Tdk株式会社 | Electronic component embedded substrate |
| JP7331521B2 (en) | 2019-07-24 | 2023-08-23 | Tdk株式会社 | Substrate with built-in electronic components |
Also Published As
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|---|---|
| JP3485509B2 (en) | 2004-01-13 |
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