WO2005076352A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
WO2005076352A1
WO2005076352A1 PCT/JP2005/000905 JP2005000905W WO2005076352A1 WO 2005076352 A1 WO2005076352 A1 WO 2005076352A1 JP 2005000905 W JP2005000905 W JP 2005000905W WO 2005076352 A1 WO2005076352 A1 WO 2005076352A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
semiconductor chip
underfill resin
semiconductor
manufacturing
Prior art date
Application number
PCT/JP2005/000905
Other languages
French (fr)
Japanese (ja)
Inventor
Keiichiro Wakamiya
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to JP2005517648A priority Critical patent/JPWO2005076352A1/en
Publication of WO2005076352A1 publication Critical patent/WO2005076352A1/en

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    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.
  • it relates to a semiconductor device in which a semiconductor chip is flip-chip bonded to a substrate or the like.
  • a method of mounting a semiconductor chip on a substrate or the like is to form a bump on an electrode pad of the semiconductor chip without directly bonding a wire such as a gold wire, and directly connect the bump to a land of the substrate.
  • a coupling method using a flip chip For example, bumps (protrusions) are respectively formed on the main surfaces of a plurality of electrode pads which also have aluminum (A1) force formed on the main surface of a semiconductor chip.
  • the bumps and lands formed on the substrate or the like are directly connected.
  • the bumps are formed of gold (Au) using a wire bonding technique, so-called start bumps, or a barrier metal is formed in advance on the main surface of the electrode pad, and the barrier metal is formed using solder.
  • Au gold
  • a flip chip bonding method is a method of bonding to a semiconductor chip or a substrate in a twisted-down manner by a thermo-compression bonding method or a thermo-compression bonding method using ultrasonic waves.
  • an underfill resin is injected between the semiconductor chips or between the semiconductor chip and the substrate (gap). The underfill resin is injected so as to fill the entire gap between the semiconductor chips or the entire gap between the semiconductor chip and the substrate.
  • Japanese Patent Application Laid-Open No. 2003-234362 discloses a manufacturing method of forming a dam with a high-viscosity resin around a flip chip and then injecting the underfill in order to prevent the underfill from flowing out. Is disclosed.
  • the substrate and the flip chip are bonded by a plurality of solder bumps. It is disclosed that underfill is injected and solidified in a portion between the substrate and the flip chip where no solder bump is surrounded by the dam.
  • a substrate and a plurality of solder bumps formed on the substrate, a flip chip bonded to the substrate by these solder bumps, and a semiconductor chip injected between the substrate and the flip chip are disclosed.
  • a semiconductor device includes a resin to be solidified, and a solder dam formed on the substrate so as to surround the periphery of the flip chip and blocking outflow of the resin onto the substrate. According to this semiconductor device, it is possible to reduce the area required for forming a dam for preventing resin from flowing out, and it is possible to form a solder dam in the same step as the step of forming a solder bump. It has been disclosed that it will be possible to eliminate factors that increase costs.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2003-234362
  • the gap between one semiconductor chip and another semiconductor chip, or the gap between a semiconductor chip and a substrate has become narrower with miniaturization of the device. In other words, the gap is being narrowed. With this narrowing of the gap, the penetration of the underfill resin into the gap deteriorates. In order to improve the penetration of the underfill resin, the viscosity of the underfill resin has been reduced. However, while lowering the viscosity improves the penetration of the underfill resin into the gaps, the underfill resin flows toward the electrode pads and external lands located around the semiconductor chip or substrate. There was a problem that the electrode pads and external lands were contaminated.
  • An object of the present invention is to provide a semiconductor device and a method of manufacturing a semiconductor device in which components such as an electrode pad formed on the surface of a substrate or a semiconductor chip are prevented from being contaminated by an underfill resin. I do.
  • the first member and the second member fixed to the first member with a gap therebetween so that the surfaces are substantially parallel to each other. And an underfill resin filled in the gap.
  • a protective film for protecting the first member is formed outside a region where the second member is projected on the first member, and the protective film is formed from a surface of the first member. It is formed to protrude and become a weir.
  • the first member and the second member fixed to the first member with a gap therebetween so that the surfaces are substantially parallel to each other.
  • a member and an underfill resin filled in the gap are provided.
  • a concave portion is formed outside a region where the second member is projected on the first member.
  • the first member and the second member fixed to the first member with a gap therebetween so that the surfaces are substantially parallel to each other.
  • a member and an underfill resin filled in the gap are provided.
  • a through-hole penetrating the first member is formed outside the region where the second member is projected on the first member so as to surround the region.
  • the method for manufacturing a semiconductor device includes the first member and the second member fixed to the first member with a gap so that the surfaces are substantially parallel to each other; Forming a first pad on a surface of a second member outside a region where the first member is to be arranged, in the method of manufacturing a semiconductor device including the underfill resin disposed in the gap. Forming a second pad for connecting the first member on the surface of the second member, and forming a force-raising portion by disposing a conductive member on the surface of the first pad. After the raising portion forming step and the force and raising portion forming step, an underfill resin arranging step of arranging an underfill resin between the first member and the second member is included.
  • FIG. 1 is a schematic sectional view of a first semiconductor device according to a first embodiment.
  • FIG. 2 is a schematic plan view of a first semiconductor device according to the first embodiment.
  • FIG. 3 is a schematic sectional view of a second semiconductor device according to the first embodiment.
  • FIG. 4 is a schematic plan view of a third semiconductor device according to the first embodiment.
  • FIG. 5 is a schematic plan view of a fourth semiconductor device according to the first embodiment.
  • FIG. 6 is a schematic plan view of a fifth semiconductor device according to the first embodiment.
  • FIG. 7 is an explanatory view of a first step in the method for manufacturing a semiconductor device in the first embodiment.
  • FIG. 8 is an explanatory view of a second step in the method for manufacturing a semiconductor device in the first embodiment.
  • FIG. 9 is an explanatory view of a third step in the method for manufacturing a semiconductor device in the first embodiment.
  • FIG. 10 is an explanatory view of a fourth step in the method for manufacturing a semiconductor device in the first embodiment.
  • FIG. 11 is an explanatory view of a fifth step in the method for manufacturing a semiconductor device in the first embodiment.
  • FIG. 12 is an explanatory view of a sixth step of the method for manufacturing a semiconductor device in the first embodiment.
  • FIG. 13 is a schematic sectional view of a semiconductor device according to a second embodiment.
  • FIG. 14 is an explanatory view of a first step in the method for manufacturing a semiconductor device in the second embodiment.
  • FIG. 15 is an explanatory view of a second step in the method for manufacturing a semiconductor device in the second embodiment.
  • FIG. 16 is an explanatory view of a third step in the method for manufacturing a semiconductor device in the second embodiment.
  • FIG. 17 is an explanatory view of a fourth step in the method for manufacturing a semiconductor device in the second embodiment.
  • FIG. 18 is an explanatory view of a fifth step in the method for manufacturing a semiconductor device in the second embodiment.
  • FIG. 19 is an explanatory view of the sixth step in the method for manufacturing a semiconductor device in the second embodiment.
  • FIG. 20 is an explanatory view of the seventh step in the method for manufacturing a semiconductor device in the second embodiment.
  • FIG. 21 is a schematic sectional view of a semiconductor device according to a third embodiment.
  • FIG. 22 is a schematic sectional view of a semiconductor device according to a fourth embodiment.
  • FIG. 23 is a schematic plan perspective view of a semiconductor device according to a fourth embodiment.
  • FIG. 24 is a bottom view of the semiconductor device according to the fourth embodiment.
  • FIG. 25 is an explanatory view of a first step in the method for manufacturing a semiconductor device in the fourth embodiment.
  • FIG. 26 is an explanatory view of a second step in the method for manufacturing a semiconductor device in the fourth embodiment.
  • FIG. 27 is an explanatory view of the third step in the method for manufacturing a semiconductor device in the fourth embodiment.
  • FIG. 28 is an explanatory view of the fourth step of the method for manufacturing a semiconductor device in the fourth embodiment.
  • FIG. 29 is an explanatory view of the fifth step of the method for manufacturing a semiconductor device in the fourth embodiment.
  • FIG. 30 is an explanatory view of the sixth step in the method for manufacturing the semiconductor device in the fourth embodiment.
  • FIG. 31 is an explanatory view of the seventh step in the method for manufacturing the semiconductor device in the fourth embodiment.
  • FIG. 32 is an eighth step explanatory view of the method for manufacturing a semiconductor device in the fourth embodiment.
  • 33 is an explanatory view of the ninth step of the method for manufacturing a semiconductor device in the fourth embodiment.
  • FIG. FIG. 34 is an explanatory view of the tenth step of the method for manufacturing a semiconductor device in the fourth embodiment.
  • FIG. 35 is a schematic sectional view of a semiconductor device in a fifth embodiment.
  • FIG. 36 is an explanatory view of the first step in the method for manufacturing a semiconductor device in the fifth embodiment.
  • FIG. 37 is an explanatory view of the second step in the method for manufacturing the semiconductor device in the fifth embodiment. 38 illustrates a third step of the method for manufacturing a semiconductor device in the fifth embodiment.
  • FIG. 39 is an explanatory view of the fourth step in the method for manufacturing the semiconductor device in the fifth embodiment.
  • FIG. 40 is an explanatory view of the sixth step in the method for manufacturing the semiconductor device in the fifth embodiment.
  • FIG. 41 is an explanatory diagram of the method for manufacturing the first semiconductor device in the sixth embodiment.
  • FIG. 42 is an explanatory diagram of the method for manufacturing the second semiconductor device in the sixth embodiment.
  • FIG. 15 is a partially enlarged view of a semiconductor device in a sixth embodiment.
  • FIG. 1 is a schematic sectional view of a first semiconductor device according to the present embodiment.
  • the first semiconductor device includes a semiconductor chip 2 as a first member and a semiconductor chip 1 as a second member.
  • the semiconductor chip 1 and the semiconductor chip 2 are formed in a plate shape.
  • the semiconductor chip 1 is fixed to the semiconductor chip 2 with a gap so that the main surface is substantially parallel to the main surface of the semiconductor chip 2.
  • a plurality of electrode pads 12 made of aluminum (A1) are formed on the main surface of the semiconductor chip 1, and bumps (projections) 11 are formed on the surface of the electrode pads 12.
  • One bump 11 is formed on each electrode pad 12.
  • the bump 11 for example, a stud bump formed using a metal of gold (Au) is used.
  • electrode pads are formed so as to correspond to the positions of the electrode pads 12 of the semiconductor chip 1. ), The bumps 11 are fixedly connected to the electrode pads.
  • the semiconductor chip 1 is fixed to the semiconductor chip 2 by a flip chip.
  • a gap between the semiconductor chip 1 and the semiconductor chip 2 is filled with an underfill resin 20.
  • an epoxy resin having high fluidity and low viscosity is mainly used.
  • a recess 27 is formed outside a region where the semiconductor chip 1 is projected onto the semiconductor chip 2.
  • the recess 27 includes the through hole 5 and the lid 17 and is recessed from the main surface of the semiconductor chip 2.
  • the through hole 5 is formed so as to penetrate the semiconductor chip 2.
  • a plating film (not shown) made of copper is formed on the inner wall of the through hole 5.
  • a cover 17 is arranged on the main surface of the semiconductor chip 2 opposite to the side to which the semiconductor chip 1 is coupled so as to cover the opening of the through hole 5.
  • the lid 17 is formed in a flat plate shape and is formed along the plane shape of the through hole 5. In the present embodiment, lid 17 is made of copper.
  • the recess 27 is formed by the through hole 5 penetrating the semiconductor chip 2 and the lid 17 formed so as to seal one opening of the through hole 5.
  • the accumulating membrane arranged on the inner wall of the through hole 5 is joined to the lid 17 and is electrically connected.
  • the electrode pad 13 is formed outside the through hole 5 on the main surface of the semiconductor chip 2 on the side to which the semiconductor chip 1 is bonded. That is, the concave portion 27 is disposed between the electrode pad 13 and a region where a gap between the semiconductor chips is formed. A gold wire 15 for connection to an external electric circuit is connected and fixed to the electrode pad 13.
  • the underfill resin 20 is disposed so as to face outward from the gap between the semiconductor chip 1 and the semiconductor chip 2.
  • the underfill resin 20 is arranged along the main surface of the semiconductor chip 2, and a part is arranged inside the concave portion 27.
  • FIG. 2 shows a plan view of the first semiconductor device in the present embodiment.
  • the semiconductor chip 1 and the semiconductor chip 2 of the first semiconductor device according to the present embodiment are formed so that their planar shapes are substantially square.
  • the concave portion 27 is formed in a groove shape along one side of a planar square of the semiconductor chip 1.
  • the concave portion 27 is arranged so as to surround the area where the semiconductor chip 1 is arranged.
  • the recess 27 is formed so as to surround the area when the semiconductor chip 1 is projected onto the semiconductor chip 2.
  • the recess 27 is formed so as to be substantially rectangular in a planar shape.
  • the width of the recess 27 in the first semiconductor device is about 100 ⁇ m.
  • a plurality of electrode pads 13 are formed outside the recess 27, and a gold wire 15 is connected to each of the electrode pads 13.
  • FIG. 3 shows a schematic cross-sectional view of the second semiconductor device in the present embodiment.
  • a recess 10 is formed instead of the recess including the through hole in the first semiconductor device.
  • the recess 10 is formed by cutting out a part of the semiconductor chip 2 so as not to penetrate the semiconductor chip 2.
  • the concave portion 10 is formed in a groove shape.
  • the plating film on the inner wall of the recess 10 is not formed.
  • the recess 10 is formed around a region when the semiconductor chip 1 is projected onto the main surface of the semiconductor chip 2 so as to surround this region.
  • the underfill resin 20 is partially disposed inside the recess 10. Other configurations are the same as those of the first semiconductor device.
  • FIG. 4 shows a plan view of a third semiconductor device according to the present embodiment.
  • the underfill resin is omitted for the sake of explanation.
  • the semiconductor chip 1 and the semiconductor chip 2 are connected by a flip chip, and the gap between the two semiconductor chips 1 and 2 is filled with an underfill resin, as in the first semiconductor device.
  • the recess 6 is formed intermittently.
  • the recess 6 includes a through-hole of the semiconductor chip 2, and the main surface of the main surface of the semiconductor chip 2 opposite to the side on which the semiconductor chip 1 is arranged covers the opening of the through-hole.
  • a lid is formed on the door.
  • Each of the recesses 6 is formed in a groove shape having a rectangular planar shape, and is arranged such that a long side of the rectangular shape is substantially parallel to one side of a square which is a planar shape of the semiconductor chip 1. ing.
  • the recess 6 is formed such that one recess 6 corresponds to two electrode pads 13.
  • the recesses 6 are arranged at substantially equal intervals, and are formed so as to surround a region when the semiconductor chip 1 is projected onto the semiconductor chip 2. That is, the recess 6 in the third semiconductor device has a shape obtained by dividing the recess in the first semiconductor device into a plurality.
  • the underfill resin (not shown) is partially disposed inside the recess 6. Other configurations are the same as those of the first semiconductor device.
  • FIG. 5 shows a plan view of a fourth semiconductor device in the present embodiment.
  • the underfill resin is omitted for the sake of explanation.
  • the semiconductor chip 1 and the semiconductor chip 2 are connected by a flip chip, and a gap between the two semiconductor chips 1 and 2 is formed.
  • the fact that the underfill resin is filled is the same as in the first semiconductor device.
  • a concave portion 7 having a circular planar shape is formed.
  • the recess 7 includes a through hole penetrating the semiconductor chip 2.
  • a lid is formed on the main surface of the semiconductor chip 2 opposite to the side to which the semiconductor chip 1 is coupled so as to cover the opening of the through hole.
  • a plurality of recesses 7 are formed, and are arranged such that the direction in which the recesses 7 are arranged and one side of a square of the semiconductor chip 1 are substantially parallel to each other.
  • the recess 7 is formed between the electrode pad 13 and the semiconductor chip 1, and one recess 7 is formed so as to correspond to each one electrode pad 13.
  • the recess 7 is arranged so as to surround the area where the semiconductor chip 1 is projected onto the semiconductor chip 2.
  • the underfill resin (not shown) is partially disposed inside the recess 7. Other configurations are the same as those of the first semiconductor device.
  • FIG. 6 shows a plan view of a fifth semiconductor device in the present embodiment.
  • the underfill resin is omitted for the sake of explanation.
  • the semiconductor chip 1 and the semiconductor chip 2 are connected by a flip chip, and the gap between the two semiconductor chips 1 and 2 is filled with an underfill resin.
  • two rows of recesses 9 each having a substantially square planar shape are formed between the gap between the semiconductor chips and the electrode pads 13. That is, the plurality of recesses 9 are formed and arranged so as to have a row arranged on the side of the semiconductor chip 1 and a system IJ arranged on the side of the electrode pad 13. Each row is formed so as to be substantially parallel to one side of a square which is a planar shape of the semiconductor chip 1.
  • the row of recesses 9 formed on the side of the electrode pad 13 is arranged so as to correspond to the electrode pad 13. That is, one recess 9 is formed between each one electrode pad 13 and the semiconductor chip 1.
  • the recesses 9 formed on the side of the semiconductor chip 1 are arranged so as to correspond between the recesses 9 in the row arranged on the side of the electrode pad 13.
  • the plurality of rows in which the concave portions 9 are formed are formed so as to be shifted from each other.
  • Other configurations are the same as those of the first semiconductor device.
  • two members are connected by a flip chip.
  • the plate-shaped members are joined such that the main surfaces are parallel to each other.
  • the semiconductor chip 1 is flip-chip bonded to the semiconductor chip 2 by a thermocompression bonding method or a thermocompression bonding method using ultrasonic waves.
  • a low-viscosity underfill resin 20 is injected into the gap between the semiconductor chip 1 and the semiconductor chip 2.
  • the concave portion is formed outside the region where the second member is projected on the first member in the first member, components such as the electrode pad are contaminated with the underfill resin. It is possible to provide a semiconductor device in which the occurrence of the semiconductor device is prevented.
  • the force concave portion having the bottomed concave portion instead of the force concave portion having the bottomed concave portion, only a through hole having an opening on the front and back of the first member is formed through the first member, and The same effect is obtained even if is not formed.
  • a concave portion penetrates through the first member, and a lid formed so as to seal one opening of the through hole.
  • a plating film is formed on the inner wall of the through hole, and the plating film and the lid are both made of conductive copper.
  • the concave portion can be used as a via for connecting an electric circuit formed on the front and back main surfaces of the first member.
  • the lid 25 is formed of a conductive material, the lid 25 can be used as an electrode pad.
  • a lid on the through hole, it is possible to prevent the underfill resin from adhering to the back surface of the semiconductor chip.
  • wires connected through through holes are formed on the front and back of the semiconductor chip, wires and electrode pads are also formed on the back. ing. For this reason, even on the back surface of the substrate or the semiconductor chip, it is possible to prevent the contamination by forming a lid which is preferable to prevent the component from being contaminated by the underfill resin.
  • the concave portion is formed in a groove shape, and is formed so as to surround a region where the second member is projected on the first member. Let's do it.
  • the recess 10 is formed by a notched portion so as not to penetrate the semiconductor chip 2.
  • the underfill resin 20 flowing toward the outside of the semiconductor chip 2 can be guided to the concave portion 10, and the electrode pads 13 can be prevented from being contaminated.
  • the lid is not required to be formed on one main surface of the semiconductor chip 2, so that the configuration is simplified.
  • the second semiconductor device is useful when a single semiconductor chip is connected and fixed to a single semiconductor chip or a substrate.
  • the recess can be used as a via for connecting the semiconductor chips as in the first semiconductor device shown in FIG. It is preferable that a lid is provided for the fin.
  • Other functions and effects are the same as those of the first semiconductor device.
  • the respective through holes are arranged so as to correspond to the positions of the electrode pads. That is, in the third semiconductor device, one concave portion 6 is formed so as to correspond to two electrode pads 13, and the concave portion 6 is formed so as to prevent the underfill resin from reaching the electrode pad 13. Are arranged. In the fourth semiconductor device, one electrode pad 13 corresponds to one electrode pad 13. The concave portions 7 are formed, and the concave portions 7 are arranged so that the underfill resin facing outward does not reach the electrode pad 13. Employing any of these configurations can more effectively prevent the electrode pads from being contaminated by the underfill resin. Other functions and effects are the same as those of the first semiconductor device.
  • a plurality of recesses 9 are formed between semiconductor chip 1 and electrode pads 13 in two rows. By forming a plurality of rows of concave portions in this way, it is possible to more reliably prevent the underfill resin from reaching the electrode pads 13.
  • the bump material connecting the two semiconductor chips is made of gold (Au).
  • the present invention is not particularly limited to this mode.
  • the bump material is made of solder. It doesn't matter if bump material is used.
  • the first member and the second member are not limited to the semiconductor chip, and any parts can be used.
  • the present invention can be applied to an apparatus for performing flip chip bonding.
  • the planar shape of the formed concave portion is formed to be a quadrangle.
  • the shape is not limited, and may be a shape including a curve when viewed in a plan view.
  • the through hole included in the concave portion in the present embodiment is a force in which the direction in which it is formed is perpendicular to the main surface of semiconductor chip 2. It may be formed so as to be inclined with respect to. Further, each recess is formed to have a rectangular cross-sectional shape, but is not particularly limited to this mode, and may be formed to have a trapezoidal cross-sectional shape, for example.
  • the partial force of the underfill resin is disposed inside the concave portion.
  • the present invention is not particularly limited to this mode.
  • the underfill resin may not be disposed inside.
  • FIG. 7 to 12 are schematic cross-sectional views illustrating respective manufacturing steps.
  • an interlayer insulating film 22 having an opening is formed on the upper surface of a Si substrate 21.
  • the interlayer insulating film 22 is etched and Form part 26.
  • a SiN film 23 is formed by a CVD (Chemical Vapor D mark osition) method so as to cover the upper surface of the interlayer insulating film 22 and the inner wall of the notch 26.
  • CVD Chemical Vapor D mark osition
  • a TiN film (not shown) is formed on the surface of the SiN film 23 by a CVD method. Further, a Cu film (not shown) is formed on the upper surface of the TiN film by a CVD method. Thereafter, as shown in FIG. 9, a Cu film 24 is formed by electrolytic Cu plating using the Cu film formed by the CVD method as an electrode.
  • portions of the Cu film 24 other than the portions formed inside the cutouts 26 are removed by a CMP (chemical mechanical polishing) method.
  • portions of the SiN film 23 other than the portions formed inside the cutouts 26 are also removed by the CMP method.
  • the back surface of the Si substrate 21 is polished to expose the Cu film 24 formed at the bottom of the notch.
  • a lid 25 made of Cu is disposed on the Cu film 24 exposed on the back surface of the Si substrate 21 via a diffusion prevention film made of TiN. .
  • the concave portion can be formed before the flip chip bonding is performed.
  • the semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS.
  • the semiconductor device according to the second embodiment is a semiconductor device in which the semiconductor chip as the first member in the first embodiment is replaced with an organic substrate, and a semiconductor chip as a second member is further laminated.
  • FIG. 13 is a schematic cross-sectional view of the semiconductor device according to the present embodiment.
  • the semiconductor device according to the present embodiment includes an organic substrate 4 as a first member and a semiconductor chip 1 as a second member.
  • the organic substrate 4 and the semiconductor chip 1 are fixed with a gap so that their main surfaces are almost parallel to each other.
  • the semiconductor chip 1 is coupled to the organic substrate 4 via a bump 11 by a flip chip.
  • the electrode pads 12 formed on the semiconductor chip 1 are formed of aluminum (A1).
  • the bump 11 is, for example, a stud bump formed from a metal such as gold (Au). Is used.
  • the semiconductor chip 1 is joined to another semiconductor chip 3, and the semiconductor chips are stacked.
  • the semiconductor chip 3 is electrically connected to an external land 14 formed on the main surface of the organic substrate 4 by a gold wire 16.
  • a recess 28 is formed outside a region where the semiconductor chip 1 is projected on the organic substrate 4.
  • the recess 28 includes the through hole 8, the Cu film 30, and the lid 18 formed of Cu.
  • the through-hole 8 is formed so as to penetrate the organic substrate 4, and the opening of the through-hole 8 opposite to the side on which the semiconductor chip 1 is arranged seals (closes) this opening.
  • a lid 18 is formed.
  • the lid 18 is formed so as to conform to the shape of the opening of the through hole 8.
  • the gap between the organic substrate 4 and the semiconductor chip 1 is filled with an underfill resin 20.
  • the underfill resin 20 extends toward the outside of the organic substrate 4. Part of the underfill resin 20 is arranged inside the concave portion 28.
  • the recess 28 is recessed from the main surface of the organic substrate 4 on which the wiring layer is formed.
  • the planar shape of the concave portion 28 is formed to be rectangular.
  • the concave portion 28 is formed such that the longitudinal direction of the planar shape follows the outer shape of the semiconductor chip 1. That is, the recess 28 is formed so as to have the same planar shape as the recess of the first semiconductor device in the first embodiment. (See Figure 2).
  • the organic substrate 4 in the present embodiment is formed using a glass epoxy resin.
  • the lands (not shown) formed on the organic substrate 4 to which the bumps 11 are bonded are provided with nickel (Ni) and gold (Au) on the upper surface of a copper (Cu) foil.
  • the lands formed on the organic substrate 4 are arranged so as to correspond to the positions of the electrode pads 12 formed on the semiconductor chip 1.
  • the other configuration is the same as that of the first semiconductor device in the first embodiment.
  • the semiconductor chip 1 and the organic substrate 4 are flip-chip bonded by a thermocompression bonding method or a thermocompression bonding method using ultrasonic waves.
  • the lands formed on the organic substrate 4 and the electrode pads 12 formed on the semiconductor chip 1 are coupled and fixed via force bumps 11.
  • the concave portion is formed outside the region where the semiconductor chip 1 is projected on the organic substrate 4, it is possible to prevent the underfill resin 20 from flowing and the external land 14 from being contaminated. That is, by forming the concave portion 28 between the above-mentioned region and the external land 14, the external land 14 can be prevented from being contaminated by the underfill resin 20. As a result, it is possible to provide a semiconductor device in which the outer lands 14 are not contaminated by the underfill resin.
  • concave portion 28 has Cu film 30 formed on the inner wall of through hole 8, and lid 18 is formed of Cu, which is a conductive material.
  • a through-hole penetrating the organic substrate is formed, and the opening on the other side of the through-hole is sealed with a lid.
  • the present invention is not limited to this mode.
  • a concave part is formed, and a concave part is formed.
  • a glass epoxy resin is used for the organic substrate as the first member.
  • the present invention is not limited to this mode.
  • the organic substrate may be formed using a polyimide resin. Good.
  • 14 to 20 are schematic cross-sectional views illustrating each step.
  • an electroless Cu plating film is formed on the entire substrate. At this time, the Cu plating film 36 is formed inside the through hole.
  • the main surface of the front and back of the organic substrate 31 was An insulating film 32 is formed. At this time, the region surrounded by the Cu plating film 36 is also filled with the material of the insulating film 32.
  • a notch 37 is formed from the back side of the organic substrate 31 by laser processing.
  • the notch 37 is formed so as to follow the planar shape of the Cu plating film 36.
  • an electroless Cu plating film 33 is formed.
  • An electroless Cu plating film 33 is formed on the main surface of the insulating film 32 on the rear surface side of the organic substrate 31 and inside the notch 37.
  • a resist (not shown) is formed to form an electrolytic Cu plated portion 34.
  • the electrolytic Cu plating part 34 is formed so as to follow the shape of the notch.
  • the electroless Cu plating film 33 formed on the main surface of the insulating film 32 is removed.
  • the lid 35 including the electroless Cu plating film 33 and the electrolytic Cu plating portion 34 is formed.
  • the diameter of the concave portion is, for example, about 100 / m.
  • the concave portion can be formed on the organic substrate outside the region when the first member is projected onto the organic substrate before the flip chip bonding.
  • FIG. 21 is a schematic sectional view of the semiconductor device according to the present embodiment.
  • the semiconductor chip 2 as the first member and the semiconductor chip 1 as the second member are joined by a flip chip via a bump 11, and an underfill resin 20 is inserted into a gap between the semiconductor chip 1 and the semiconductor chip 2. This is the same as in the semiconductor device in the first embodiment.
  • the electrode pad 13 is formed on the outer peripheral portion of the semiconductor chip 2 and the gold wire 15 is connected to the electrode pad 13 as in the semiconductor device according to the first embodiment.
  • a protective film 19 is formed instead of the concave portion.
  • the protective film 19 is formed to prevent the occurrence of cracks in the semiconductor chip 2.
  • the protective film 19 in the present embodiment is formed of a polyimide resin.
  • the protective film 19 is formed by, for example, photolithography using a photosensitive polyimide resin.
  • the protective film 19 is formed so as to protrude from the main surface of the semiconductor chip 2.
  • the typical thickness of the protective film to prevent cracks in semiconductor chips is about 5 ⁇ m.
  • the protective film 19 in the present embodiment has a thickness of about 5 ⁇ m.
  • the protective film 19 is arranged outside a region when the semiconductor chip 1 is projected onto the semiconductor chip 2, and is formed so as to surround this region.
  • the protection film 19 is arranged between this region and the electrode pad 13.
  • the protective film 19 is formed such that the planar shape is rectangular, and the long side of the rectangular is substantially parallel to the outer edge of the semiconductor chip 1. That is, the semiconductor device in the present embodiment is formed continuously so that the protective film functions as a weir, and the concave portion of the first semiconductor device in Embodiment 1 (see FIGS. 1 and 2) is used as the protective film. It has a replaced configuration.
  • the underfill resin 20 is injected into a gap between the semiconductor chip 1 and the semiconductor chip 2, and is arranged from the gap toward the outside of the semiconductor chip 2 to a portion where the protective film 19 is formed. .
  • the semiconductor chip 1 and the semiconductor chip 2 are flip-chip bonded by a thermocompression bonding method or a thermocompression bonding method using ultrasonic waves.
  • the protective film 19 is formed on the semiconductor chip 2 in advance.
  • the underfill resin 20 is injected into the gap between the semiconductor chip 1 and the semiconductor chip 2.
  • the under fin resin 20 is injected into the gap and flows toward the outside of the semiconductor chip 2, but is blocked by the protective film 19.
  • the underfill resin 20 can be prevented from reaching the electrode pads 13 formed on the outer peripheral portion of the semiconductor chip 2, and the electrode pads 13 can be prevented from being contaminated by the underfill resin 20.
  • a protective film for preventing cracks in a semiconductor chip is provided by a conventional semiconductor chip.
  • the semiconductor device according to the present invention can be manufactured only by changing the mask pattern for forming the protective film and the thickness of the protective film. In manufacturing, it is not necessary to add a new manufacturing process or a new material, so that it is possible to easily provide a semiconductor device in which contamination of an electrode pad or the like is prevented.
  • protective film 19 in the present embodiment is formed so as to surround a region where semiconductor chip 1 is projected onto semiconductor chip 2.
  • the thickness of the protective film in the present embodiment is about 5 ⁇ m, depending on the width of the gap between the first member and the second member and the type of the underfill resin, the thickness of the protective film may vary. Preferably.
  • Embodiment 4 A semiconductor device and a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS.
  • FIG. 22 is a schematic cross-sectional view of the semiconductor device according to the present embodiment.
  • the semiconductor device according to the present embodiment includes a semiconductor chip 52 as a first member and a semiconductor chip 51 as a second member.
  • the semiconductor chip 51 and the semiconductor chip 52 are arranged with a gap so that the surfaces are substantially parallel to each other.
  • a pad 64 is formed as a first pad for connecting a connection line to the outside.
  • the pad 64 is arranged outside a shadowed area when the semiconductor chip 51 is projected onto the semiconductor chip 52.
  • a pad 65 is formed as a second pad for connecting the semiconductor chip 51.
  • the pad 65 is arranged in a shadowed area when the semiconductor chip 51 is projected on the semiconductor chip 52.
  • a polyimide film 55 is formed on the surface of the semiconductor chip 52 and a part of the surfaces of the pads 64 and 65. The polyimide film 55 is formed to prevent a soft error.
  • a force raising portion 74a is formed on the surface of the pad 64.
  • 74a is conductive. This is a portion formed so that the height of the portion having the property is increased.
  • the force raising portion 74a is formed in a rectangular parallelepiped shape.
  • the raising portion 74a includes a non-metal layer 72a and an Au bump 73a.
  • a force raising portion 74b is formed on the surface of the pad 65.
  • the force-raising portion 74b includes a non-metal layer 72b and an Au bump 73b.
  • barrier metal layer 72a and barrier metal layer 72b are formed in the same manufacturing process and are formed of the same material.
  • the Au bump 73a and the Au bump 73b are formed in the same manufacturing process and are formed of the same material.
  • the barrier metal layers 72a and 72b in the present embodiment are a laminate in which the surface forces of the pads 64 and 65, the TiN layer, the TiW layer, and the Au layer are laminated in this order.
  • the barrier metal layers 72a and 72b are formed for bringing the Au pumps 73a and 73b into close contact with the nodes 64 and 65 and for obtaining a diffusion barrier effect.
  • pads 63 for connection with the semiconductor chip 52 are formed on the surface of the semiconductor chip 51.
  • a polyimide film 56 is formed on the surface of the semiconductor chip 51 and a part of the surface of the pad 63.
  • the pad 63 is joined to the lifting portion 74b.
  • the semiconductor chip 51 and the semiconductor chip 52 are fixed with a gap therebetween via the conductive member, and are electrically connected to each other.
  • An underfill resin 92 is disposed between the semiconductor chip 51 and the semiconductor chip 52.
  • the underfill resin 92 is arranged so as to spread outward from a region where the semiconductor chip 51 is arranged. In the portion where the pad 64 of the semiconductor chip 52 is formed, the force increasing portion 74 a is higher than the height of the underfill resin 92.
  • the semiconductor chip 52 is fixed to the wiring board 81 via an adhesive 91.
  • a land 84 is formed on the outer peripheral portion of the surface of 81.
  • the pads 64 of the semiconductor chip 52 and the lands 84 of the wiring board 81 are electrically connected to each other by gold wires 61.
  • the gold wire 61 includes a spherical gold ball portion 71 at an end connected to the force raising portion 74a.
  • a sealing resin 90 is arranged on the upper surface of the wiring board 81 so as to include the semiconductor chips 51 and 52 and the gold wires 61 therein.
  • the semiconductor chip 52 is arranged on the main surface of the wiring board 81.
  • Lands 82 and solder balls 83 are arranged on the main surface opposite to the side on which they are placed.
  • FIG. 23 is a plan view of the semiconductor device according to the present embodiment when the sealing resin is removed.
  • FIG. 24 is a bottom view of the semiconductor device according to the present embodiment. Referring to FIG. 23, the semiconductor device in the present embodiment is arranged such that semiconductor chips 51 and 52 have a substantially square planar shape. The semiconductor chip 51 and the semiconductor chip 52 are arranged such that their respective centers of gravity overlap in plan view.
  • the force raising portion 74 a is arranged in a peripheral portion of the semiconductor chip 52.
  • the force raising portion 74 a is arranged along the outer edge of the semiconductor chip 52.
  • Lands 84 are formed on the surface of the wiring board 81 so as to correspond to the positions of the force and the raised portions 74a.
  • the underfill resin 92 is arranged from a region where the semiconductor chip 51 is formed to a region where the raised portion 74a is formed.
  • the underfill resin 92 is arranged so as not to protrude outside the semiconductor chip 52.
  • solder balls 83 are formed via lands.
  • a plurality of solder balls 83 are formed so as to be regularly arranged.
  • a force increasing portion 74 a is formed on the surface of pad 64 of semiconductor chip 52.
  • the height of the top surface of the portion connecting the gold wire 61 can be increased, and even if the underfill resin 92 flows outward, the portion connecting the gold wire 61 can be increased. Surface contamination can be prevented. Therefore, it is possible to prevent the bonding strength between the gold wire 61 and the raised portion 74a from being reduced, and to reliably bond the gold ball portion 71. Further, it is possible to prevent the gold ball portion 71 from coming off and coming off later.
  • the force raising portion 74a preferably has a height sufficient to prevent the top surface from being contaminated by the underfill resin 92.
  • the height of the force and the raised portion 74 a is preferably 20 ⁇ m or more and 25 zm or less from the surface of the pad 64.
  • FIG. 25 to FIG. 34 are schematic cross-sectional views in each step.
  • an electric circuit is formed on a semiconductor substrate 58 such as a silicon substrate as a first member.
  • Pads 64 and 65 are formed on the surface of the semiconductor substrate 58.
  • the pad 64 is a pad for making an electrical connection to the outside later.
  • the pad 64 is arranged at a peripheral portion of a region to be a semiconductor chip.
  • the pad 64 is arranged outside a region where a semiconductor chip as a second member to be connected later is arranged.
  • the pad 65 is a pad for making an electrical connection with a semiconductor chip as a second member to be connected later.
  • the pad 65 is arranged in a projection area of a semiconductor chip to be connected later.
  • a polyimide film 55 is formed so as to cover the surface of the semiconductor substrate 58 and part of the surfaces of the pads 64 and 65.
  • a step of forming a raised portion is performed.
  • a barrier metal layer 72 is formed so as to cover the exposed portions of the pads 64 and 65 and the polyimide film 55.
  • the rear metal layer 72 is formed, for example, by a sputtering method.
  • the barrier metal layer is formed by sequentially stacking three layers of a TiN layer, a TiW layer, and an Au layer.
  • a photoresist layer 77 having an opening 78 is formed.
  • the opening 78 is formed in a region where the nodes 64 and 65 are arranged.
  • the photoresist layer 77 for example, after applying a photoresist by a spin coating method, exposure and image formation are performed to form an opening 78.
  • the opening 78 is formed so that the planar shape becomes a square.
  • Au bumps 73a and 73b are formed by electrolytic plating.
  • a positive voltage is applied to the barrier metal layer 72 while the semiconductor substrate is immersed in a plating solution containing Au ions, so that the Au layer is formed in the opening 78 of the photoresist layer 77. Is precipitated.
  • the Au bumps 73a and 73b are formed along the shape of the opening 78.
  • the Au bumps 73a and 73b are formed in a substantially rectangular parallelepiped shape.
  • the rear metal layer is removed.
  • the removal of the barrier metal layer is performed, for example, by etching. In this way, a raised portion 74a including the barrier metal layer 72a and the Au bump 73a and a raised portion 74b including the barrier metal layer 72b and the Au bump 73b are formed.
  • the semiconductor substrate 58 is cut by dicing to form individual semiconductor chips.
  • the semiconductor chip 52 is bonded to the wiring board 81 with an adhesive 91.
  • a land 84 is formed on the main surface of the wiring substrate 81 on which the semiconductor chip 52 is arranged. Further, a land 82 is formed on the main surface of the wiring substrate 81 opposite to the side on which the semiconductor chip 52 is arranged.
  • the semiconductor chip 51 manufactured in another manufacturing process is electrically connected to the semiconductor chip 52 and fixed.
  • the pad 63 and the polyimide film 56 are formed on the surface of the semiconductor chip 51 in the same manner as the semiconductor chip 52.
  • bonding is performed while applying heat and ultrasonic waves by, for example, flip-chip bonding so that the pad 63 of the semiconductor chip 51 is connected to the raised portion 74b.
  • an underfill resin arranging step of arranging underfill resin 92 between semiconductor chip 51 and semiconductor chip 52 is performed.
  • the underfill resin 92 may flow outwardly, a force-raising portion 74a is formed on the surface of the force pad 64, thereby preventing the top surface of the force-raising portion 74a from being contaminated. can do.
  • the gold wire 61 is formed using a wire bonding apparatus.
  • a gold ball portion 71 is formed by extruding a small amount of gold wire 61 into the tip of a cavity 85 of a wire bonding apparatus in advance. After joining the gold ball portion 71 to the top surface of the force / raising portion 74a, the cabillary 85 is moved to connect the gold wire 61 to the land 84.
  • the device is sealed with a sealing resin 90.
  • the sealing is performed so as to include all of the semiconductor chips 51 and 52 and the gold wire 61.
  • the solder balls 83 are formed on the lands 82 of the wiring board 81.
  • the first path for connecting an external connection line is provided.
  • a raised portion forming step in which a conductive member is disposed on the surface of the pad to form a raised portion, and after the step of forming the raised portion, the under member is placed between the first member and the second member.
  • the method includes an underfill resin disposing step of disposing a fill resin.
  • the raised portion forming step in the present embodiment includes a step of forming a barrier metal layer on the surface of the first pad, a step of disposing a resist layer on the surface of the barrier metal layer, and a step of forming the first layer of the resist layer. Forming an opening in the portion of the pad, and forming an Au bump as a conductive portion in the opening by an electrolytic plating method. Further, the method includes a step of removing the resist layer and a step of removing the barrier metal layer in a region other than a region where the conductive portion is formed. By employing this method, the force and the raised portion can be easily formed. In addition, in the electroplating method, the height of the raised portion can be easily adjusted by adjusting the magnitude of the applied voltage and the time during which the metal is deposited.
  • the resin in the underfill resin arranging step, after the first member and the second member are joined, the resin is arranged in a gap between the first member and the second member. Performing the step. By employing this method, the resin can be easily arranged between the first member and the second member.
  • the force in which the force-raising portion is formed on both the pad for connecting the gold wire and the pad for connecting the semiconductor chip is limited to this mode. Instead, it is only necessary that the pad for connecting the gold wire has a raised portion.
  • gold bumps may be arranged on pads 65 for connecting semiconductor chip 51, and the first member and the second member may be connected and fixed.
  • FIG. 35 is a schematic cross-sectional view of the semiconductor device according to the present embodiment.
  • the semiconductor device according to the present embodiment is different from the semiconductor device according to the fourth embodiment in the configuration of the force raising portion and the connection between the first member and the second member.
  • the force and the raised portion are formed of gold balls.
  • a substantially spherical raised portion 75 is formed on the surface of the pad 64 of the semiconductor chip 52 as the first member.
  • the gold ball portion 71 of the gold wire 61 is joined to the force / raising portion 75.
  • the force raising portion 75 and the gold ball portion 71 are integrated.
  • a barrier metal layer 79 is formed on the surface of the pad 63 of the semiconductor chip 51, and an Au bump 80 is formed on the surface of the nodal metal layer 79. Have been.
  • the pad 65 formed on the surface of the semiconductor chip 52 is bonded to the Au bump 80.
  • the raised portion is formed in a spherical shape.
  • the force increasing portion can be easily formed using a known wire bonding apparatus.
  • FIGS. 36 to 40 are schematic cross-sectional views in respective manufacturing steps.
  • a polyimide film 55 is formed. Next, a step of forming a raised portion is performed.
  • a raised portion 75 is formed on the surface of the pad 64 by using a wire bonding apparatus.
  • the lifting portion 75 is a conductive ball (ball). In the present embodiment, it is formed of gold.
  • a small amount of gold is discharged from the cavities 85 of the wire bonding apparatus to form a gold ball portion, and then the gold ball portion is bonded to the surface of the pad 64. After joining the gold balls, the gold is cut by moving the cabillary 85 in the direction perpendicular to arrow 95 or arrow 95.
  • the raised portion 75 in the present embodiment can be formed by a method similar to the method of forming a stud bump.
  • One raised portion 75 is formed on the surface of each pad 64.
  • the semiconductor substrate is cut by dicing to fragment into individual semiconductor chips 52.
  • the semiconductor chip 52 is fixed to the wiring board 81 using an adhesive 91.
  • the semiconductor chip 51 is manufactured.
  • a pad 63 is formed on the surface of the semiconductor chip 51, and a barrier metal layer 79 and an Au bump 80 are formed on the surface of the pad 63 by a method such as electrolytic plating.
  • the Au bump 80 and the pad 65 are joined by thermocompression bonding while applying ultrasonic waves.
  • an underfill resin disposing step of disposing an underfill resin between the semiconductor chip 51 and the semiconductor chip 52 is performed. Because the underfill resin 92 may flow outward, the raised portion 75 is formed, and the portion of the raised portion 75 to which the gold wire is connected is contaminated by the underfill resin 92. This can be prevented.
  • an electrical connection is made between the force raising portion 75 and the lands 84 formed on the wiring board 81.
  • a gold ball portion 71 is formed at the tip of the cavities by using a wire bonding apparatus.
  • the upper surface of the lifting portion 75 is pressed by the gold ball portion 71, and while the upper surface of the lifting portion 75 is leveled, the heat between the gold ball portion 71 and the lifting portion 75 is heated. Perform crimping.
  • the other end of the gold wire 61 opposite to the gold ball portion 71 is connected to the land 84.
  • the semiconductor device according to the present embodiment can be manufactured by performing resin sealing or the like.
  • the present embodiment includes a step of arranging a gold ball on the surface of the first pad for connecting an external connection line using a wire bonding apparatus.
  • the raised portion can be easily formed. Further, the raised portion can be formed at low cost.
  • the force of forming the nori- tal metal layer 79 and the Au bump 80 on the surface of the pad 63 of the semiconductor chip 51 as the second member is not particularly limited to this form, but may be any connection method.
  • the semiconductor chip 51 and the semiconductor chip 52 can be electrically connected.
  • the surface of the pad 63 of the semiconductor chip 51 is Au A bump may be formed.
  • the semiconductor chip as the first member and the semiconductor chip as the second member can be connected and fixed at low cost.
  • FIG. 41 is a schematic cross-sectional view of the first semiconductor device manufacturing method according to the present embodiment.
  • a paste adhesive NCP: Non Conductive Paste
  • the semiconductor chip 52 as the first member and the semiconductor chip 51 as the second member are arranged before they are fixed to each other.
  • the force increasing portions 74a and 74b are arranged on the surfaces of the pads 64 and 65 on the surface of the semiconductor chip 52.
  • an NCP arranging step of arranging NCPs on semiconductor chip 52 after forming force-raising portions 74a and 74b is performed. Thereafter, as shown by arrow 93, the pad 63 and the raised portion 74b are joined by thermocompression bonding while applying ultrasonic waves. As described above, after the NCP arranging step, the step of connecting the first member and the second member is performed.
  • FIG. 42 shows a schematic cross-sectional view of the method for manufacturing the second semiconductor device in the present embodiment.
  • a film adhesive NCF: Non Conductive Film
  • NCF Non Conductive Film
  • an NCF arranging step of arranging the NCF 89 is performed. NCF placement In the process, the NCF is bonded to the semiconductor chip 51 by thermocompression in advance. Strengthening portions 74a, 74b are formed on the surfaces of the pads 64, 65 of the semiconductor chip 52 as the first member. Next, as shown by an arrow 94, the force and the raised portion 74b and the pad 63 are joined by performing thermocompression bonding while applying ultrasonic waves. As described above, after the NCF arranging step, the step of connecting the first member and the second member is performed.
  • the NCP used in the first method for manufacturing a semiconductor device in the present embodiment has a simple shape and a high viscosity at room temperature.
  • the NCF used in the second method for manufacturing a semiconductor device is in the form of a film.
  • the NCP or NCF may flow toward the outside of the semiconductor chip due to the viscous force due to the heat at the time of joining the semiconductor chips.
  • the raised portion on the pad for making a connection with the outside contamination at the portion where the connection line is joined can be prevented, and a good connection with the connection line can be made.
  • FIGS. 43 to 45 show explanatory views of the third manufacturing method according to the present embodiment.
  • 43 and 44 are schematic cross-sectional views illustrating steps of a third method of manufacturing a semiconductor device according to the present embodiment.
  • FIG. 45 is an enlarged plan view of a part of the manufactured semiconductor device.
  • thermocompression bonding is performed while applying ultrasonic waves to join the Au bumps 80 formed on the semiconductor chip 51 and the pads 65 formed on the semiconductor chip 52.
  • the underfill resin 92 is arranged. As shown by an arrow 100, an underfill resin 92 is disposed in a region between the semiconductor chip 51 and the raised portion 75. The underfill resin 92 is pushed out of the supply nozzle 86 and arranged.
  • FIG. 45 is an enlarged schematic layout view of a corner portion of a manufactured semiconductor device.
  • the underfill resin 92 is continuously arranged while moving in a direction along the outer edge of the semiconductor chip 51 as indicated by an arrow 96.
  • the opposite side of gold wire 61 or the surface of semiconductor chip 51 opposite to the side on which semiconductor chip 52 is arranged is provided.
  • the underfill resin 92 may adhere to the surface of the substrate.
  • the gold wire 61 and the semiconductor chip 51 are sealed with a sealing resin.
  • the underfill resin 92 is attached to one surface of the gold wire or the semiconductor chip 51, The adhered portion becomes an interface with the sealing resin, and the sealing resin is easily peeled off. For this reason, it is preferable that the underfill resin does not adhere to the gold wire or the like.
  • the present invention can be applied to a semiconductor device.
  • the present invention can be advantageously applied to a semiconductor device in which a semiconductor chip is flip-chip bonded to a substrate or the like.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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  • General Physics & Mathematics (AREA)
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  • Wire Bonding (AREA)

Abstract

A semiconductor device is provided with a semiconductor chip (2), a semiconductor chip (1), which is fixed on the semiconductor chip (2) with a space in between so as to have their front planes almost in parallel, and an underfill resin (20) which is applied in the space. In the semiconductor chip (2), a recessed part (27) is formed outside of a region whereupon the semiconductor chip (1) is projected on the semiconductor chip (2).

Description

明 細 書  Specification
半導体装置および半導体装置の製造方法  Semiconductor device and method of manufacturing semiconductor device
技術分野  Technical field
[0001] 本発明は、半導体装置および半導体装置の製造方法に関する。特に、半導体チッ プを基板などにフリップチップ接合した半導体装置に関する。  The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. In particular, it relates to a semiconductor device in which a semiconductor chip is flip-chip bonded to a substrate or the like.
背景技術  Background art
[0002] 半導体チップを基板などに搭載する方法には、金線などのワイヤボンディングによ らず、半導体チップの電極パッドにバンプを形成して、このバンプを基板のランドなど に直接的に結合するフリップチップによる結合方法がある。たとえば、半導体チップ の主表面に形成されたアルミニウム (A1)力もなる複数の電極パッドの主表面上に、 バンプ (突起部）をそれぞれ形成する。このバンプと基板などに形成されたランドとを 直接結合する。バンプには、ワイヤボンディング技術を用いて金 (Au)で形成される、 いわゆるスタツトバンプや、電極パッドの主表面に予めバリアメタルを形成しておいて 、このバリアメタルに半田を用いて形成されるバンプなどがある。  [0002] A method of mounting a semiconductor chip on a substrate or the like is to form a bump on an electrode pad of the semiconductor chip without directly bonding a wire such as a gold wire, and directly connect the bump to a land of the substrate. There is a coupling method using a flip chip. For example, bumps (protrusions) are respectively formed on the main surfaces of a plurality of electrode pads which also have aluminum (A1) force formed on the main surface of a semiconductor chip. The bumps and lands formed on the substrate or the like are directly connected. The bumps are formed of gold (Au) using a wire bonding technique, so-called start bumps, or a barrier metal is formed in advance on the main surface of the electrode pad, and the barrier metal is formed using solder. There are bumps and the like.
[0003] フリップチップによる結合方法は、半導体チップまたは基板などに対してフヱイスダ ゥン方式で、熱圧着による結合方法や超音波を併用した熱圧着による結合方法など が用いられる。フリップチップによって半導体チップを別の半導体チップまたは基板 に対して実装した後には、半導体チップ同士の間または半導体チップと基板との間 ( 隙間）にアンダーフィル樹脂が注入される。アンダーフィル樹脂は、半導体チップ同 士の間の隙間全体または半導体チップと基板との間の隙間全体を埋めるように注入 される。  [0003] A flip chip bonding method is a method of bonding to a semiconductor chip or a substrate in a twisted-down manner by a thermo-compression bonding method or a thermo-compression bonding method using ultrasonic waves. After a semiconductor chip is mounted on another semiconductor chip or substrate by flip chip, an underfill resin is injected between the semiconductor chips or between the semiconductor chip and the substrate (gap). The underfill resin is injected so as to fill the entire gap between the semiconductor chips or the entire gap between the semiconductor chip and the substrate.
[0004] 特開 2003— 234362号公報にぉレ、ては、アンダーフィルの流出を防止するために 、フリップチップの周囲に高粘度の樹脂でダムを形成してからアンダーフィルを注入 する製造方法が開示されている。基板とフリップチップとは、複数の半田バンプによつ てボンディングされる。基板とフリップチップとの間であって、ダムに囲まれた半田バン プが存在しない部分には、アンダーフィルが注入されて固化される、と開示されてい る。 [0005] また、同公報においては、基板と基板上に形成された複数個の半田バンプと、これ らの半田バンプにより基板にボンディングされるフリップチップと、基板とフリップチッ プとの間に注入され固化する樹脂と、基板上にフリップチップの周囲を囲むように形 成され、基板上への樹脂の流出を堰き止める半田ダムとを備えた半導体装置が開示 されている。この半導体装置によれば、樹脂の流出を防ぐダムの形成に必要な面積 を減少させることが可能になり、また、半田バンプの形成の工程と同じ工程で半田ダ ムを形成することができるので、コストアップの要因を排除することが可能になる、と開 示されている。 [0004] Japanese Patent Application Laid-Open No. 2003-234362 discloses a manufacturing method of forming a dam with a high-viscosity resin around a flip chip and then injecting the underfill in order to prevent the underfill from flowing out. Is disclosed. The substrate and the flip chip are bonded by a plurality of solder bumps. It is disclosed that underfill is injected and solidified in a portion between the substrate and the flip chip where no solder bump is surrounded by the dam. [0005] Furthermore, in this publication, a substrate and a plurality of solder bumps formed on the substrate, a flip chip bonded to the substrate by these solder bumps, and a semiconductor chip injected between the substrate and the flip chip are disclosed. A semiconductor device is disclosed that includes a resin to be solidified, and a solder dam formed on the substrate so as to surround the periphery of the flip chip and blocking outflow of the resin onto the substrate. According to this semiconductor device, it is possible to reduce the area required for forming a dam for preventing resin from flowing out, and it is possible to form a solder dam in the same step as the step of forming a solder bump. It has been disclosed that it will be possible to eliminate factors that increase costs.
特許文献 1：特開 2003 - 234362号公報  Patent Document 1: Japanese Patent Application Laid-Open No. 2003-234362
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0006] フリップチップ接合において、一の半導体チップと他の半導体チップとの隙間、また は半導体チップと基板との隙間は、装置の小型化に伴って狭くなつてきている。すな わち、狭ギャップ化が進行している。この狭ギャップ化に伴って、隙間へのアンダーフ ィル樹脂の侵入性は悪化する。アンダーフィル樹脂の侵入性を向上させるために、ァ ンダーフィル樹脂の粘度を下げることが行なわれている。しかし、粘度を下げると、隙 間へのアンダーフィル樹脂の侵入性が向上する一方で、半導体チップまたは基板の 周辺部に配置されている電極パッドや外部ランドに向かってアンダーフィル樹脂が流 れてしまレ、、電極パッドや外部ランドが汚染されるという問題があった。 [0006] In flip-chip bonding, the gap between one semiconductor chip and another semiconductor chip, or the gap between a semiconductor chip and a substrate, has become narrower with miniaturization of the device. In other words, the gap is being narrowed. With this narrowing of the gap, the penetration of the underfill resin into the gap deteriorates. In order to improve the penetration of the underfill resin, the viscosity of the underfill resin has been reduced. However, while lowering the viscosity improves the penetration of the underfill resin into the gaps, the underfill resin flows toward the electrode pads and external lands located around the semiconductor chip or substrate. There was a problem that the electrode pads and external lands were contaminated.
[0007] たとえば、上側に配置される半導体チップと下側に配置される半導体チップとを、フ リップチップによって結合する後に、上側の半導体チップと下側の半導体チップとの 間隙にアンダーフィル樹脂を注入する。この後に、下側の半導体チップの外周に形 成された電極パッドとインターポーザ (基板）のボンディングパッドとをワイヤボンディ ングによって接続する。この際に、下側の半導体チップの電極パッドが、アンダーフィ ル榭脂によって汚染されていると、電極パッドに形成される金 (Au)ボールの接合強 度が小さくなつてしまう。このため、接合された金ボールが剥がれる、または、ワイヤボ ンデイングによって接合することができないという問題があった。 [0007] For example, after a semiconductor chip arranged on the upper side and a semiconductor chip arranged on the lower side are connected by a flip chip, an underfill resin is filled in a gap between the upper semiconductor chip and the lower semiconductor chip. inject. Thereafter, the electrode pads formed on the outer periphery of the lower semiconductor chip and the bonding pads of the interposer (substrate) are connected by wire bonding. At this time, if the electrode pad of the lower semiconductor chip is contaminated with the underfill resin, the bonding strength of the gold (Au) ball formed on the electrode pad is reduced. For this reason, there has been a problem that the bonded gold balls are peeled off or cannot be bonded by wire bonding.
課題を解決するための手段 [0008] 本発明は、アンダーフィル樹脂によって、基板や半導体チップの表面に形成された 電極パッドなどの部品が汚染されることを防止した半導体装置および半導体装置の 製造方法を提供することを目的とする。 Means for solving the problem [0008] An object of the present invention is to provide a semiconductor device and a method of manufacturing a semiconductor device in which components such as an electrode pad formed on the surface of a substrate or a semiconductor chip are prevented from being contaminated by an underfill resin. I do.
[0009] 本発明に基づく半導体装置の第 1の局面では、第 1の部材と、表面同士が互いに 略平行になるように、間隙を空けて第 1の部材に固定された第 2の部材と、上記の間 隙に充填されたアンダーフィル樹脂とを備える。第 1の部材において、第 2の部材を 第 1の部材に投影した領域の外側に、第 1の部材を保護するための保護膜が形成さ れ、保護膜は、第 1の部材の表面から突出して、堰になるように形成されている。  [0009] In a first aspect of the semiconductor device according to the present invention, the first member and the second member fixed to the first member with a gap therebetween so that the surfaces are substantially parallel to each other. And an underfill resin filled in the gap. In the first member, a protective film for protecting the first member is formed outside a region where the second member is projected on the first member, and the protective film is formed from a surface of the first member. It is formed to protrude and become a weir.
[0010] または、本発明に基づく半導体装置の第 2の局面では、第 1の部材と、表面同士が 互いに略平行になるように、間隙を空けて第 1の部材に固定された第 2の部材と、上 記の間隙に充填されたアンダーフィル樹脂とを備える。第 1の部材において、第 2の 部材を第 1の部材に投影した領域の外側に凹部が形成されている。  [0010] Alternatively, in the second aspect of the semiconductor device according to the present invention, the first member and the second member fixed to the first member with a gap therebetween so that the surfaces are substantially parallel to each other. A member and an underfill resin filled in the gap are provided. In the first member, a concave portion is formed outside a region where the second member is projected on the first member.
[0011] または、本発明に基づく半導体装置の第 3の局面では、第 1の部材と、表面同士が 互いに略平行になるように、間隙を空けて第 1の部材に固定された第 2の部材と、上 記の間隙に充填されたアンダーフィル樹脂とを備える。第 1の部材において、第 2の 部材を第 1の部材に投影した領域の外側に、領域を取り囲むように第 1の部材を貫通 する貫通孔が形成されてレ、る。  [0011] Alternatively, in the third aspect of the semiconductor device according to the present invention, the first member and the second member fixed to the first member with a gap therebetween so that the surfaces are substantially parallel to each other. A member and an underfill resin filled in the gap are provided. In the first member, a through-hole penetrating the first member is formed outside the region where the second member is projected on the first member so as to surround the region.
[0012] 本発明に基づく半導体装置の製造方法は、第 1の部材と、表面同士が互いに略平 行になるように、間隙を空けて第 1の部材に固定された第 2の部材と、間隙に配置さ れたアンダーフィル樹脂とを備える半導体装置の製造方法において、第 2の部材の 表面において、第 1の部材が配置されるべき領域の外側に第 1のパッドを形成するェ 程と、第 2の部材の表面において、第 1の部材を接続するための第 2のパッドを形成 する工程と、第 1のパッドの表面に導電性部材を配置して力 ^上げ部を形成するかさ 上げ部形成工程と、力、さ上げ部形成工程の後に、第 1の部材と第 2の部材との間にァ ンダーフィル樹脂を配置するアンダーフィル樹脂配置工程とを含む。  [0012] The method for manufacturing a semiconductor device according to the present invention includes the first member and the second member fixed to the first member with a gap so that the surfaces are substantially parallel to each other; Forming a first pad on a surface of a second member outside a region where the first member is to be arranged, in the method of manufacturing a semiconductor device including the underfill resin disposed in the gap. Forming a second pad for connecting the first member on the surface of the second member, and forming a force-raising portion by disposing a conductive member on the surface of the first pad. After the raising portion forming step and the force and raising portion forming step, an underfill resin arranging step of arranging an underfill resin between the first member and the second member is included.
発明の効果  The invention's effect
[0013] 本発明によれば、電極パッドなどの部品がアンダーフィル樹脂によって汚染される ことを防止した半導体装置および半導体装置の製造方法を提供することができる。 図面の簡単な説明 According to the present invention, it is possible to provide a semiconductor device and a method of manufacturing a semiconductor device in which components such as an electrode pad are prevented from being contaminated by an underfill resin. Brief Description of Drawings
[図 1]実施の形態 1における第 1の半導体装置の概略断面図である。 FIG. 1 is a schematic sectional view of a first semiconductor device according to a first embodiment.
[図 2]実施の形態 1における第 1の半導体装置の概略平面図である。 FIG. 2 is a schematic plan view of a first semiconductor device according to the first embodiment.
[図 3]実施の形態 1における第 2の半導体装置の概略断面図である。 FIG. 3 is a schematic sectional view of a second semiconductor device according to the first embodiment.
[図 4]実施の形態 1における第 3の半導体装置の概略平面図である。 FIG. 4 is a schematic plan view of a third semiconductor device according to the first embodiment.
[図 5]実施の形態 1における第 4の半導体装置の概略平面図である。 FIG. 5 is a schematic plan view of a fourth semiconductor device according to the first embodiment.
[図 6]実施の形態 1における第 5の半導体装置の概略平面図である。 FIG. 6 is a schematic plan view of a fifth semiconductor device according to the first embodiment.
[図 7]実施の形態 1における半導体装置の製造方法の第 1工程説明図である。 FIG. 7 is an explanatory view of a first step in the method for manufacturing a semiconductor device in the first embodiment.
[図 8]実施の形態 1における半導体装置の製造方法の第 2工程説明図である。 FIG. 8 is an explanatory view of a second step in the method for manufacturing a semiconductor device in the first embodiment.
[図 9]実施の形態 1における半導体装置の製造方法の第 3工程説明図である。 FIG. 9 is an explanatory view of a third step in the method for manufacturing a semiconductor device in the first embodiment.
[図 10]実施の形態 1における半導体装置の製造方法の第 4工程説明図である。 FIG. 10 is an explanatory view of a fourth step in the method for manufacturing a semiconductor device in the first embodiment.
[図 11]実施の形態 1における半導体装置の製造方法の第 5工程説明図である。 FIG. 11 is an explanatory view of a fifth step in the method for manufacturing a semiconductor device in the first embodiment.
[図 12]実施の形態 1における半導体装置の製造方法の第 6工程説明図である。 FIG. 12 is an explanatory view of a sixth step of the method for manufacturing a semiconductor device in the first embodiment.
[図 13]実施の形態 2における半導体装置の概略断面図である。 FIG. 13 is a schematic sectional view of a semiconductor device according to a second embodiment.
[図 14]実施の形態 2における半導体装置の製造方法の第 1工程説明図である。 FIG. 14 is an explanatory view of a first step in the method for manufacturing a semiconductor device in the second embodiment.
[図 15]実施の形態 2における半導体装置の製造方法の第 2工程説明図である。 FIG. 15 is an explanatory view of a second step in the method for manufacturing a semiconductor device in the second embodiment.
[図 16]実施の形態 2における半導体装置の製造方法の第 3工程説明図である。 FIG. 16 is an explanatory view of a third step in the method for manufacturing a semiconductor device in the second embodiment.
[図 17]実施の形態 2における半導体装置の製造方法の第 4工程説明図である。 FIG. 17 is an explanatory view of a fourth step in the method for manufacturing a semiconductor device in the second embodiment.
[図 18]実施の形態 2における半導体装置の製造方法の第 5工程説明図である。 FIG. 18 is an explanatory view of a fifth step in the method for manufacturing a semiconductor device in the second embodiment.
[図 19]実施の形態 2における半導体装置の製造方法の第 6工程説明図である。 FIG. 19 is an explanatory view of the sixth step in the method for manufacturing a semiconductor device in the second embodiment.
[図 20]実施の形態 2における半導体装置の製造方法の第 7工程説明図である。 FIG. 20 is an explanatory view of the seventh step in the method for manufacturing a semiconductor device in the second embodiment.
[図 21]実施の形態 3における半導体装置の概略断面図である。 FIG. 21 is a schematic sectional view of a semiconductor device according to a third embodiment.
[図 22]実施の形態 4における半導体装置の概略断面図である。 FIG. 22 is a schematic sectional view of a semiconductor device according to a fourth embodiment.
[図 23]実施の形態 4における半導体装置の概略平面透視図である。 FIG. 23 is a schematic plan perspective view of a semiconductor device according to a fourth embodiment.
[図 24]実施の形態 4における半導体装置の下面図である。 FIG. 24 is a bottom view of the semiconductor device according to the fourth embodiment.
[図 25]実施の形態 4における半導体装置の製造方法の第 1工程説明図である。 FIG. 25 is an explanatory view of a first step in the method for manufacturing a semiconductor device in the fourth embodiment.
[図 26]実施の形態 4における半導体装置の製造方法の第 2工程説明図である。 FIG. 26 is an explanatory view of a second step in the method for manufacturing a semiconductor device in the fourth embodiment.
[図 27]実施の形態 4における半導体装置の製造方法の第 3工程説明図である。 園 28]実施の形態 4における半導体装置の製造方法の第 4工程説明図である。 園 29]実施の形態 4における半導体装置の製造方法の第 5工程説明図である。 園 30]実施の形態 4における半導体装置の製造方法の第 6工程説明図である。 園 31]実施の形態 4における半導体装置の製造方法の第 7工程説明図である。 園 32]実施の形態 4における半導体装置の製造方法の第 8工程説明図である。 園 33]実施の形態 4における半導体装置の製造方法の第 9工程説明図である。 園 34]実施の形態 4における半導体装置の製造方法の第 10工程説明図である。 園 35]実施の形態 5における半導体装置の概略断面図である。 FIG. 27 is an explanatory view of the third step in the method for manufacturing a semiconductor device in the fourth embodiment. FIG. 28 is an explanatory view of the fourth step of the method for manufacturing a semiconductor device in the fourth embodiment. FIG. 29 is an explanatory view of the fifth step of the method for manufacturing a semiconductor device in the fourth embodiment. FIG. 30 is an explanatory view of the sixth step in the method for manufacturing the semiconductor device in the fourth embodiment. FIG. 31 is an explanatory view of the seventh step in the method for manufacturing the semiconductor device in the fourth embodiment. FIG. 32 is an eighth step explanatory view of the method for manufacturing a semiconductor device in the fourth embodiment. 33 is an explanatory view of the ninth step of the method for manufacturing a semiconductor device in the fourth embodiment. FIG. FIG. 34 is an explanatory view of the tenth step of the method for manufacturing a semiconductor device in the fourth embodiment. FIG. 35 is a schematic sectional view of a semiconductor device in a fifth embodiment.
園 36]実施の形態 5における半導体装置の製造方法の第 1工程説明図である。 園 37]実施の形態 5における半導体装置の製造方法の第 2工程説明図である。 園 38]実施の形態 5における半導体装置の製造方法の第 3工程説明図である。 園 39]実施の形態 5における半導体装置の製造方法の第 4工程説明図である。 園 40]実施の形態 5における半導体装置の製造方法の第 6工程説明図である。 園 41]実施の形態 6における第 1の半導体装置の製造方法の説明図である。 FIG. 36 is an explanatory view of the first step in the method for manufacturing a semiconductor device in the fifth embodiment. FIG. 37 is an explanatory view of the second step in the method for manufacturing the semiconductor device in the fifth embodiment. 38 illustrates a third step of the method for manufacturing a semiconductor device in the fifth embodiment. FIG. FIG. 39 is an explanatory view of the fourth step in the method for manufacturing the semiconductor device in the fifth embodiment. FIG. 40 is an explanatory view of the sixth step in the method for manufacturing the semiconductor device in the fifth embodiment. FIG. 41 is an explanatory diagram of the method for manufacturing the first semiconductor device in the sixth embodiment.
園 42]実施の形態 6における第 2の半導体装置の製造方法の説明図である。 FIG. 42 is an explanatory diagram of the method for manufacturing the second semiconductor device in the sixth embodiment.
園 43]実施の形態 6における第 3の半導体装置の製造方法の第 1工程説明図である 園 44]実施の形態 6における第 3の半導体装置の製造方法の第 2工程説明図である 園 45]実施の形態 6における半導体装置の部分拡大図である。 Garden 43] is a first step explanatory view of the third semiconductor device manufacturing method in the sixth embodiment. Garden 44] is a second step explanatory view of the third semiconductor device manufacturing method in the sixth embodiment. FIG. 15 is a partially enlarged view of a semiconductor device in a sixth embodiment.
符号の説明 Explanation of symbols
1 , 2, 3 半導体チップ、 4, 31 有機基板、 5, 8 貫通孑し、 6， 7, 9, 10， 27, 28 凹き ^ 11 ノ ンプ、 12, 13 電極ノ ッド、 14 外咅 Bランド、 15， 16 金泉、 17, 18, 2 5, 35 蓋、 19 保護膜、 20 アンダーフィル樹脂、 21 Si基板、 22 層間絶縁膜、 2 3 SiN膜、 24, 30 Cu膜、 26, 37 切欠き部、 32 絶縁膜、 33 無電解 Cuめっき 膜、 34 電解 Cuめっき部、 36 Cuめっき膜、 51, 52 半導体チップ、 55, 56 ポリ イミド莫、 58 半導体基板、 61 金 ,線、 63一 65 ノヽ。ッド、 71 金ボーノレ咅 72, 72a, 72b, 79 バリアメタノレ層、 73a, 73b, 80 Auバンプ、 74a, 74b, 75 力さ上げ咅 77 フォトレジスト層、 78 開口部、 81 配線基板、 82, 84 ランド、 83 半田ボール 、 85 キヤビラリ、 86 供給ノス、ノレ、 88 NCP、 89 NCF、 90 封止榭)!旨、 91 接着 材、 92 アンダーフィル樹脂、 93— 100 矢印。 1, 2, 3 semiconductor chip, 4, 31 organic substrate, 5, 8 penetrating moss, 6, 7, 9, 10, 27, 28 recessed ^ 11 knob, 12, 13 electrode node, 14 outer layer B land, 15, 16 Kinsen, 17, 18, 25, 35 Lid, 19 protective film, 20 underfill resin, 21 Si substrate, 22 interlayer insulating film, 23 SiN film, 24, 30 Cu film, 26, 37 Notch, 32 Insulation film, 33 Electroless Cu plating film, 34 Electrolytic Cu plating portion, 36 Cu plating film, 51, 52 Semiconductor chip, 55, 56 Polyimide, 58 Semiconductor substrate, 61 gold, wire, 63 65 No. 72, 72a, 72b, 79 Barrier methanol layer, 73a, 73b, 80 Au bump, 74a, 74b, 75 77 Photoresist layer, 78 Opening, 81 Wiring board, 82, 84 Land, 83 Solder ball, 85 Capillary, 86 Supply nos, Nore, 88 NCP, 89 NCF, 90 Sealing 榭) !, 91 Adhesive, 92 Underfill resin, 93-100 arrow.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0016] (実施の形態 1) (Embodiment 1)
図 1から図 12を参照して、本発明に基づく実施の形態 1における半導体装置につ いて説明する。  The semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.
[0017] 図 1は、本実施の形態における第 1の半導体装置の概略断面図である。第 1の半導 体装置は、第 1の部材としての半導体チップ 2と、第 2の部材としての半導体チップ 1 とを備える。半導体チップ 1および半導体チップ 2は、板状に形成されている。半導体 チップ 1は、主表面が半導体チップ 2の主表面とほぼ平行になるように、間隙をあけて 半導体チップ 2に固定されている。  FIG. 1 is a schematic sectional view of a first semiconductor device according to the present embodiment. The first semiconductor device includes a semiconductor chip 2 as a first member and a semiconductor chip 1 as a second member. The semiconductor chip 1 and the semiconductor chip 2 are formed in a plate shape. The semiconductor chip 1 is fixed to the semiconductor chip 2 with a gap so that the main surface is substantially parallel to the main surface of the semiconductor chip 2.
[0018] 半導体チップ 1の主表面には、アルミニウム（A1)からなる複数の電極パッド 12が形 成され、電極パッド 12の表面には、バンプ（突起） 11が形成されている。バンプ 11は 、それぞれの電極パッド 12に 1つずつ形成されている。バンプ 11としては、たとえば、 金 (Au)の金属を用いて形成されたスタッドバンプが用いられている。  A plurality of electrode pads 12 made of aluminum (A1) are formed on the main surface of the semiconductor chip 1, and bumps (projections) 11 are formed on the surface of the electrode pads 12. One bump 11 is formed on each electrode pad 12. As the bump 11, for example, a stud bump formed using a metal of gold (Au) is used.
[0019] 半導体チップ 2の主表面のうち、半導体チップ 1が結合される側の主表面には、半 導体チップ 1の電極パッド 12の位置に対応するように電極パッドが形成され（図示せ ず）、この電極パッドにバンプ 11が結合固定されている。  On the main surface of the semiconductor chip 2 on the side to which the semiconductor chip 1 is coupled, electrode pads are formed so as to correspond to the positions of the electrode pads 12 of the semiconductor chip 1. ), The bumps 11 are fixedly connected to the electrode pads.
[0020] 半導体チップ 1は、フリップチップによって半導体チップ 2に固定されている。半導 体チップ 1と半導体チップ 2との間の間隙には、アンダーフィル樹脂 20が充填されて いる。アンダーフィル樹脂 20は、流動性の高い低粘度のエポキシ樹脂が主に用いら れる。  The semiconductor chip 1 is fixed to the semiconductor chip 2 by a flip chip. A gap between the semiconductor chip 1 and the semiconductor chip 2 is filled with an underfill resin 20. As the underfill resin 20, an epoxy resin having high fluidity and low viscosity is mainly used.
[0021] 半導体チップ 2の主表面において、半導体チップ 1を半導体チップ 2に投影した領 域の外側には、凹部 27が形成されている。凹部 27は、貫通孔 5および蓋 17を含み、 半導体チップ 2の主表面よりも窪んでいる。貫通孔 5は、半導体チップ 2を貫通するよ うに形成されている。貫通孔 5の内壁には、図示しない銅からなるめっき膜が形成さ れている。 [0022] 半導体チップ 2の主表面のうち、半導体チップ 1が結合されている側と反対側の主 表面には、貫通孔 5の開口部を覆うように、蓋 17が配置されている。蓋 17は、平板状 に形成され、貫通孔 5の平面形状に沿って形成されている。本実施の形態において は、蓋 17は銅から形成されている。このように、半導体チップ 2を貫通する貫通孔 5と 貫通孔 5の一方の開口部を封止するように形成された蓋 17とによって、凹部 27が形 成されている。貫通孔 5の内壁に配置されためつき膜は、蓋 17に接合して電気的に 接続されている。 On the main surface of the semiconductor chip 2, a recess 27 is formed outside a region where the semiconductor chip 1 is projected onto the semiconductor chip 2. The recess 27 includes the through hole 5 and the lid 17 and is recessed from the main surface of the semiconductor chip 2. The through hole 5 is formed so as to penetrate the semiconductor chip 2. On the inner wall of the through hole 5, a plating film (not shown) made of copper is formed. A cover 17 is arranged on the main surface of the semiconductor chip 2 opposite to the side to which the semiconductor chip 1 is coupled so as to cover the opening of the through hole 5. The lid 17 is formed in a flat plate shape and is formed along the plane shape of the through hole 5. In the present embodiment, lid 17 is made of copper. As described above, the recess 27 is formed by the through hole 5 penetrating the semiconductor chip 2 and the lid 17 formed so as to seal one opening of the through hole 5. The accumulating membrane arranged on the inner wall of the through hole 5 is joined to the lid 17 and is electrically connected.
[0023] 電極パッド 13は、半導体チップ 2の主表面のうち、半導体チップ 1が結合されている 側の主表面において、貫通孔 5の外側に形成されている。すなわち、凹部 27は、電 極パッド 13と半導体チップ同士の隙間が形成されている領域との間に配置されてい る。電極パッド 13には、外部の電気回路との接続のための金線 15が接続固定されて いる。  The electrode pad 13 is formed outside the through hole 5 on the main surface of the semiconductor chip 2 on the side to which the semiconductor chip 1 is bonded. That is, the concave portion 27 is disposed between the electrode pad 13 and a region where a gap between the semiconductor chips is formed. A gold wire 15 for connection to an external electric circuit is connected and fixed to the electrode pad 13.
[0024] アンダーフィル樹脂 20は、半導体チップ 1と半導体チップ 2との間隙から、外側に向 力うように配置されている。アンダーフィル樹脂 20は、半導体チップ 2の主表面に沿 つて配置され、一部が凹部 27の内部に配置されている。  [0024] The underfill resin 20 is disposed so as to face outward from the gap between the semiconductor chip 1 and the semiconductor chip 2. The underfill resin 20 is arranged along the main surface of the semiconductor chip 2, and a part is arranged inside the concave portion 27.
[0025] 図 2に、本実施の形態における第 1の半導体装置の平面図を示す。本実施の形態 における第 1の半導体装置の半導体チップ 1および半導体チップ 2は、平面形状が ほぼ正方形になるように形成されてレ、る。  FIG. 2 shows a plan view of the first semiconductor device in the present embodiment. The semiconductor chip 1 and the semiconductor chip 2 of the first semiconductor device according to the present embodiment are formed so that their planar shapes are substantially square.
[0026] 凹部 27は、半導体チップ 1の平面形状の正方形の一辺に沿うように、溝状に形成さ れている。凹部 27は、半導体チップ 1が配置される領域の周りを取り囲むように配置 されている。また、凹部 27は、半導体チップ 1を半導体チップ 2に投影したときの領域 の周りを取り囲むように形成されている。凹部 27は、平面形状においてほぼ長方形 になるように形成されている。第 1の半導体装置における凹部 27の幅は、 100 x m程 度である。凹部 27の外側には、複数の電極パッド 13が形成され、それぞれの電極パ ッド 13には金線 15が接続されている。  [0026] The concave portion 27 is formed in a groove shape along one side of a planar square of the semiconductor chip 1. The concave portion 27 is arranged so as to surround the area where the semiconductor chip 1 is arranged. The recess 27 is formed so as to surround the area when the semiconductor chip 1 is projected onto the semiconductor chip 2. The recess 27 is formed so as to be substantially rectangular in a planar shape. The width of the recess 27 in the first semiconductor device is about 100 × m. A plurality of electrode pads 13 are formed outside the recess 27, and a gold wire 15 is connected to each of the electrode pads 13.
[0027] 図 3に、本実施の形態における第 2の半導体装置の概略断面図を示す。半導体チ ップ 1と半導体チップ 2とがフリップチップによって結合され、 2つの半導体チップ 1， 2 同士の隙間にアンダーフィル樹脂 20が充填されていることは、第 1の半導体装置と 同様である。 FIG. 3 shows a schematic cross-sectional view of the second semiconductor device in the present embodiment. The fact that the semiconductor chip 1 and the semiconductor chip 2 are connected by a flip chip and the gap between the two semiconductor chips 1 and 2 is filled with the underfill resin 20 indicates that the first semiconductor device is It is the same.
[0028] 第 2の半導体装置においては、第 1の半導体装置における貫通孔を含む凹部の代 わりに、凹部 10が形成されている。凹部 10は、半導体チップ 2を貫通しないように、 半導体チップ 2の一部が切り欠かれて形成されている。凹部 10は、溝状に形成され ている。第 2の半導体装置においては、凹部 10の内壁のめっき膜は形成されていな レ、。凹部 10は、半導体チップ 1を半導体チップ 2の主表面に投影したときの領域の周 りに、この領域を取り囲むように形成されている。アンダーフィル樹脂 20は、一部が凹 部 10の内部に配置されている。その他の構成については、第 1の半導体装置と同様 である。  [0028] In the second semiconductor device, a recess 10 is formed instead of the recess including the through hole in the first semiconductor device. The recess 10 is formed by cutting out a part of the semiconductor chip 2 so as not to penetrate the semiconductor chip 2. The concave portion 10 is formed in a groove shape. In the second semiconductor device, the plating film on the inner wall of the recess 10 is not formed. The recess 10 is formed around a region when the semiconductor chip 1 is projected onto the main surface of the semiconductor chip 2 so as to surround this region. The underfill resin 20 is partially disposed inside the recess 10. Other configurations are the same as those of the first semiconductor device.
[0029] 図 4に、本実施の形態における第 3の半導体装置の平面図を示す。図 4においては 、説明のためアンダーフィル樹脂を省略して記載している。半導体チップ 1と半導体 チップ 2とがフリップチップによって結合され、 2つの半導体チップ 1， 2同士の隙間に アンダーフィル樹脂が充填されていることは、第 1の半導体装置と同様である。  FIG. 4 shows a plan view of a third semiconductor device according to the present embodiment. In FIG. 4, the underfill resin is omitted for the sake of explanation. The semiconductor chip 1 and the semiconductor chip 2 are connected by a flip chip, and the gap between the two semiconductor chips 1 and 2 is filled with an underfill resin, as in the first semiconductor device.
[0030] 第 3の半導体装置においては、凹部 6が断続的に形成されている。凹部 6は、半導 体チップ 2の貫通孔を含み、半導体チップ 2の主表面のうち半導体チップ 1が配置さ れている側と反対側の主表面には、貫通孔の開口部を覆うように蓋が形成されてい る。  [0030] In the third semiconductor device, the recess 6 is formed intermittently. The recess 6 includes a through-hole of the semiconductor chip 2, and the main surface of the main surface of the semiconductor chip 2 opposite to the side on which the semiconductor chip 1 is arranged covers the opening of the through-hole. A lid is formed on the door.
[0031] それぞれの凹部 6は、平面形状が長方形になるような溝状に形成され、この長方形 の長辺が、半導体チップ 1の平面形状である正方形の一辺にほぼ平行になるように 配置されている。凹部 6は、 1つの凹部 6が 2つの電極パッド 13に対応するように形成 されている。凹部 6は、ほぼ等間隔で配置され、半導体チップ 1を半導体チップ 2に投 影したときの領域の周りを囲むように形成されている。すなわち、第 3の半導体装置に おける凹部 6は、第 1の半導体装置における凹部を複数に分断した形状を有する。 図示しないアンダーフィル樹脂は、一部が凹部 6の内部に配置されている。その他の 構成については、第 1の半導体装置と同様である。  Each of the recesses 6 is formed in a groove shape having a rectangular planar shape, and is arranged such that a long side of the rectangular shape is substantially parallel to one side of a square which is a planar shape of the semiconductor chip 1. ing. The recess 6 is formed such that one recess 6 corresponds to two electrode pads 13. The recesses 6 are arranged at substantially equal intervals, and are formed so as to surround a region when the semiconductor chip 1 is projected onto the semiconductor chip 2. That is, the recess 6 in the third semiconductor device has a shape obtained by dividing the recess in the first semiconductor device into a plurality. The underfill resin (not shown) is partially disposed inside the recess 6. Other configurations are the same as those of the first semiconductor device.
[0032] 図 5に、本実施の形態における第 4の半導体装置の平面図を示す。図 5においては 、説明のためアンダーフィル樹脂を省略して記載している。半導体チップ 1と半導体 チップ 2とがフリップチップによって結合され、 2つの半導体チップ 1， 2同士の隙間に アンダーフィル樹脂が充填されていることは、第 1の半導体装置と同様である。 FIG. 5 shows a plan view of a fourth semiconductor device in the present embodiment. In FIG. 5, the underfill resin is omitted for the sake of explanation. The semiconductor chip 1 and the semiconductor chip 2 are connected by a flip chip, and a gap between the two semiconductor chips 1 and 2 is formed. The fact that the underfill resin is filled is the same as in the first semiconductor device.
[0033] 第 4の半導体装置においては、円形の平面形状を有する凹部 7が形成されている。  [0033] In the fourth semiconductor device, a concave portion 7 having a circular planar shape is formed.
凹部 7は、半導体チップ 2を貫通する貫通孔を含む。半導体チップ 2の主表面のうち 、半導体チップ 1が結合されている側と反対側の主表面には、貫通孔の開口部を覆う ように、蓋が形成されている。  The recess 7 includes a through hole penetrating the semiconductor chip 2. A lid is formed on the main surface of the semiconductor chip 2 opposite to the side to which the semiconductor chip 1 is coupled so as to cover the opening of the through hole.
[0034] 凹部 7は、複数個形成され、凹部 7が配列している方向と半導体チップ 1の平面形 状である正方形の一辺とが、ほぼ平行になるように配置されている。凹部 7は、電極 パッド 13と半導体チップ 1との間に形成され、それぞれの 1つの電極パッド 13に対応 するように、 1つの凹部 7が形成されている。また、半導体チップ 1を半導体チップ 2に 投影した領域の周りを取り囲むように、凹部 7が配置されている。図示しないアンダー フィル樹脂は、一部が凹部 7の内部に配置されている。その他の構成については、第 1の半導体装置と同様である。  A plurality of recesses 7 are formed, and are arranged such that the direction in which the recesses 7 are arranged and one side of a square of the semiconductor chip 1 are substantially parallel to each other. The recess 7 is formed between the electrode pad 13 and the semiconductor chip 1, and one recess 7 is formed so as to correspond to each one electrode pad 13. In addition, the recess 7 is arranged so as to surround the area where the semiconductor chip 1 is projected onto the semiconductor chip 2. The underfill resin (not shown) is partially disposed inside the recess 7. Other configurations are the same as those of the first semiconductor device.
[0035] 図 6に、本実施の形態における第 5の半導体装置の平面図を示す。図 6においては 、説明のためアンダーフィル樹脂を省略して記載している。半導体チップ 1と半導体 チップ 2とがフリップチップによって結合され、 2つの半導体チップ 1, 2同士の隙間に アンダーフィル樹脂が充填されていることは、第 1の半導体装置と同様である。  FIG. 6 shows a plan view of a fifth semiconductor device in the present embodiment. In FIG. 6, the underfill resin is omitted for the sake of explanation. As in the first semiconductor device, the semiconductor chip 1 and the semiconductor chip 2 are connected by a flip chip, and the gap between the two semiconductor chips 1 and 2 is filled with an underfill resin.
[0036] 第 5の半導体装置においては、平面形状がほぼ正方形の凹部 9が、半導体チップ 同士の間隙と電極パッド 13との間に 2列形成されている。すなわち、凹部 9は、複数 個形成され、半導体チップ 1の側に配置された列と、電極パッド 13の側に配置された 歹 IJとを有するように配置されている。それぞれの列は、半導体チップ 1の平面形状で ある正方形の一辺に対して、ほぼ平行になるように形成されている。  In the fifth semiconductor device, two rows of recesses 9 each having a substantially square planar shape are formed between the gap between the semiconductor chips and the electrode pads 13. That is, the plurality of recesses 9 are formed and arranged so as to have a row arranged on the side of the semiconductor chip 1 and a system IJ arranged on the side of the electrode pad 13. Each row is formed so as to be substantially parallel to one side of a square which is a planar shape of the semiconductor chip 1.
[0037] 電極パッド 13の側に形成された列の凹部 9は、電極パッド 13に対応するように配置 されている。すなわち、それぞれの 1つの電極パッド 13と半導体チップ 1との間に、 1 つの凹部 9が形成されている。半導体チップ 1の側に形成された凹部 9は、電極パッ ド 13の側に配置された列の凹部 9同士の間に対応するように配置されている。このよ うに、第 5の半導体装置においては、凹部 9が形成されている複数の列が、互いにず れるように形成されている。その他の構成については、第 1の半導体装置と同様であ る。 [0038] 本実施の形態における半導体装置は、フリップチップによって、 2つ部材が結合さ れている。特に本実施の形態においては、平板状の部材が主表面同士が互いに平 行になるように結合されている。半導体装置の製造工程においては、半導体チップ 1 、熱圧着工法または超音波を併用した熱圧着工法によって、半導体チップ 2にフリ ップチップ接合される。次に、半導体チップ 1と半導体チップ 2との隙間に、低粘度の アンダーフィル樹脂 20が注入される。 The row of recesses 9 formed on the side of the electrode pad 13 is arranged so as to correspond to the electrode pad 13. That is, one recess 9 is formed between each one electrode pad 13 and the semiconductor chip 1. The recesses 9 formed on the side of the semiconductor chip 1 are arranged so as to correspond between the recesses 9 in the row arranged on the side of the electrode pad 13. Thus, in the fifth semiconductor device, the plurality of rows in which the concave portions 9 are formed are formed so as to be shifted from each other. Other configurations are the same as those of the first semiconductor device. [0038] In the semiconductor device according to the present embodiment, two members are connected by a flip chip. In particular, in the present embodiment, the plate-shaped members are joined such that the main surfaces are parallel to each other. In the semiconductor device manufacturing process, the semiconductor chip 1 is flip-chip bonded to the semiconductor chip 2 by a thermocompression bonding method or a thermocompression bonding method using ultrasonic waves. Next, a low-viscosity underfill resin 20 is injected into the gap between the semiconductor chip 1 and the semiconductor chip 2.
[0039] 図 1および図 2に示す第 1の半導体装置においては、アンダーフィル樹脂 20を隙間 に注入する際に、アンダーフィル樹脂 20のうち一部力 S、半導体チップ 2の外側に向か つて流れようとする。この一部のアンダーフィル樹脂 20は、凹部 27に流れ込む。この ため、アンダーフィル樹脂 20が、電極パッド 13まで到達することを防止できる。この結 果、電極パッド 13が、アンダーフィル樹脂 20によって汚染されない半導体装置を得 ること力 Sできる。  In the first semiconductor device shown in FIGS. 1 and 2, when the underfill resin 20 is injected into the gap, a partial force S of the underfill resin 20 is applied to the outside of the semiconductor chip 2. Try to flow. This part of the underfill resin 20 flows into the recess 27. Therefore, it is possible to prevent the underfill resin 20 from reaching the electrode pad 13. As a result, it is possible to obtain a semiconductor device in which the electrode pad 13 is not contaminated by the underfill resin 20.
[0040] このように、第 1の部材において第 2の部材を第 1の部材に投影した領域の外側に、 凹部が形成されていることによって、電極パッドなどの部品がアンダーフィル樹脂で 汚染されることを防止した半導体装置を提供することができる。本実施の形態におい ては、有底の凹部が形成されている力 凹部の代わりに、第 1の部材を貫通して第 1 の部材の表裏に開口部を有する貫通孔のみが形成され、蓋が形成されていなくても 同様の効果を有する。  As described above, since the concave portion is formed outside the region where the second member is projected on the first member in the first member, components such as the electrode pad are contaminated with the underfill resin. It is possible to provide a semiconductor device in which the occurrence of the semiconductor device is prevented. In the present embodiment, instead of the force concave portion having the bottomed concave portion, only a through hole having an opening on the front and back of the first member is formed through the first member, and The same effect is obtained even if is not formed.
[0041] また、図 1に示すように、第 1の半導体装置においては、凹部が第 1の部材を貫通 する貫通孔と、貫通孔の一方の開口部を封止するように形成された蓋とを含む。本実 施の形態においては、貫通孔の内壁にめっき膜が形成され、めっき膜および蓋は、 共に導電性を有する銅から形成されている。このような構成を採用することにより、凹 部を第 1の部材の表裏の主表面に形成された電気回路を接続するためのビアとして 用いることができる。また、蓋 25が導電性材料で形成されていることによって、蓋 25を 電極パッドとして用いることができる。  Further, as shown in FIG. 1, in the first semiconductor device, a concave portion penetrates through the first member, and a lid formed so as to seal one opening of the through hole. And In the present embodiment, a plating film is formed on the inner wall of the through hole, and the plating film and the lid are both made of conductive copper. By adopting such a configuration, the concave portion can be used as a via for connecting an electric circuit formed on the front and back main surfaces of the first member. Further, since the lid 25 is formed of a conductive material, the lid 25 can be used as an electrode pad.
[0042] また、貫通孔に対して蓋を形成することによって、アンダーフィル樹脂が半導体チッ プの裏面に付着することを防止できる。特に、半導体チップの表裏に貫通孔を介して 接続された配線が形成されてレ、る場合には、裏面にも配線や電極パッドが形成され ている。このため、基板や半導体チップの裏面に対しても、アンダーフィル樹脂で部 品が汚染されることを防止することが好ましぐ蓋を形成することによってこの汚染を 防止することができる。 Further, by forming a lid on the through hole, it is possible to prevent the underfill resin from adhering to the back surface of the semiconductor chip. In particular, when wires connected through through holes are formed on the front and back of the semiconductor chip, wires and electrode pads are also formed on the back. ing. For this reason, even on the back surface of the substrate or the semiconductor chip, it is possible to prevent the contamination by forming a lid which is preferable to prevent the component from being contaminated by the underfill resin.
[0043] また、図 2に示すように、第 1の半導体装置においては、凹部が溝状に形成され、第 2の部材を第 1の部材に投影した領域の周りを取り囲むように形成されてレ、る。この構 成を採用することにより、より効果的に外側に向かって流れるアンダーフィル樹脂を凹 部に導くことができ、より効果的に電極パッドなどの汚染を防止できる。  Further, as shown in FIG. 2, in the first semiconductor device, the concave portion is formed in a groove shape, and is formed so as to surround a region where the second member is projected on the first member. Let's do it. By employing this configuration, the underfill resin flowing outward can be more effectively guided to the concave portion, and contamination of the electrode pads and the like can be more effectively prevented.
[0044] 図 3に示す第 2の半導体装置においては、凹部 10が半導体チップ 2を貫通しない ように切欠かれた部分によって形成されている。この構成を採用することによつても、 半導体チップ 2の外側に向かって流れるアンダーフィル樹脂 20を凹部 10に導くこと ができ、電極パッド 13が汚染することを防止できる。また、第 1の半導体装置に比べ て、半導体チップ 2の片方の主表面に形成する蓋が不要であるため構成が簡単にな る。  In the second semiconductor device shown in FIG. 3, the recess 10 is formed by a notched portion so as not to penetrate the semiconductor chip 2. By adopting this configuration, the underfill resin 20 flowing toward the outside of the semiconductor chip 2 can be guided to the concave portion 10, and the electrode pads 13 can be prevented from being contaminated. Further, compared to the first semiconductor device, the lid is not required to be formed on one main surface of the semiconductor chip 2, so that the configuration is simplified.
[0045] 第 2の半導体装置においては、単一の半導体チップを単一の半導体チップや基板 に接続固定する場合には有用である。一方で、半導体チップを三次元的に積層する 場合には、図 1に示した第 1の半導体装置のように、凹部を半導体チップ同士を接続 するためのビアとして用いることができるため、貫通孔に対して蓋が配置されているこ とが好ましい。その他の作用および効果については第 1の半導体装置と同様である。  [0045] The second semiconductor device is useful when a single semiconductor chip is connected and fixed to a single semiconductor chip or a substrate. On the other hand, when semiconductor chips are three-dimensionally stacked, the recess can be used as a via for connecting the semiconductor chips as in the first semiconductor device shown in FIG. It is preferable that a lid is provided for the fin. Other functions and effects are the same as those of the first semiconductor device.
[0046] 図 4に示す第 3の半導体装置においては、平面形状が長方形になるような貫通孔 が断続的に形成されている。また、図 5に示す第 4の半導体装置においては、平面形 状が円形になるような凹部 7が形成されている。これらのうち、いずれかの構成を採用 することによつても、アンダーフィル樹脂が外側に配置された電極パッドに到達して電 極パッドが汚染されることを防止できる。  In the third semiconductor device shown in FIG. 4, through holes having a rectangular planar shape are formed intermittently. Further, in the fourth semiconductor device shown in FIG. 5, a concave portion 7 having a circular planar shape is formed. By adopting any of these configurations, it is possible to prevent the underfill resin from reaching the electrode pads arranged outside and contaminating the electrode pads.
[0047] 第 3の半導体装置および第 4の半導体装置においては、それぞれの貫通孔が電極 パッドの位置に対応するように配置されている。すなわち、第 3の半導体装置におい ては、 2つの電極パッド 13に対して、 1つの凹部 6が対応するように形成され、外側に 向力 アンダーフィル樹脂が電極パッド 13に到達しないように凹部 6が配置されてい る。また、第 4の半導体装置においては、 1つの電極パッド 13に対応するように 1つの 凹部 7が形成され、それぞれの凹部 7は、外側に向力うアンダーフィル樹脂が電極パ ッド 13に到達しなレ、ように配置されてレ、る。これらのうちいずれかの構成を採用するこ とにより、電極パッドがアンダーフィル樹脂によって汚染されることをより効果的に防 止できる。その他の作用および効果については、第 1の半導体装置と同様である。 [0047] In the third semiconductor device and the fourth semiconductor device, the respective through holes are arranged so as to correspond to the positions of the electrode pads. That is, in the third semiconductor device, one concave portion 6 is formed so as to correspond to two electrode pads 13, and the concave portion 6 is formed so as to prevent the underfill resin from reaching the electrode pad 13. Are arranged. In the fourth semiconductor device, one electrode pad 13 corresponds to one electrode pad 13. The concave portions 7 are formed, and the concave portions 7 are arranged so that the underfill resin facing outward does not reach the electrode pad 13. Employing any of these configurations can more effectively prevent the electrode pads from being contaminated by the underfill resin. Other functions and effects are the same as those of the first semiconductor device.
[0048] 図 6に示す第 5の半導体装置においては、半導体チップ 1と電極パッド 13との間に 、 2列になるように複数の凹部 9が形成されている。このように、複数列の凹部を形成 することによって、アンダーフィル樹脂が電極パッド 13に到達することをより確実に防 止できる。 In the fifth semiconductor device shown in FIG. 6, a plurality of recesses 9 are formed between semiconductor chip 1 and electrode pads 13 in two rows. By forming a plurality of rows of concave portions in this way, it is possible to more reliably prevent the underfill resin from reaching the electrode pads 13.
[0049] 本実施の形態においては、 2つの半導体チップ同士を結合するバンプ材に、金 (A u)から形成されたものを用いたが、特にこの形態に限られず、たとえば、半田からな るバンプ材が用いられていても構わなレ、。また、第 1の部材および第 2の部材は、半 導体チップに限られず、任意の部品を用いることができる。特に、フリップチップ接合 を行なう装置に本発明を適用することができる。  In the present embodiment, the bump material connecting the two semiconductor chips is made of gold (Au). However, the present invention is not particularly limited to this mode. For example, the bump material is made of solder. It doesn't matter if bump material is used. Further, the first member and the second member are not limited to the semiconductor chip, and any parts can be used. In particular, the present invention can be applied to an apparatus for performing flip chip bonding.
[0050] また、第 1の半導体装置、第 2の半導体装置および第 4の半導体装置においては、 形成されている凹部の平面形状が、四角形になるように形成されているが、特にこの 形態に限られず、平面的に見たときに、曲線を含む形状であっても構わない。  Further, in the first semiconductor device, the second semiconductor device, and the fourth semiconductor device, the planar shape of the formed concave portion is formed to be a quadrangle. The shape is not limited, and may be a shape including a curve when viewed in a plan view.
[0051] 本実施の形態における凹部に含まれる貫通孔は、形成されている方向が半導体チ ップ 2の主表面に垂直になっている力 特にこの形態に限られず、半導体チップ 2の 主表面に対して傾斜するように形成されていても構わない。また、それぞれの凹部は 、断面形状が長方形になるように形成されているが、特にこの形態に限られず、たと えば、断面形状が台形になるように形成されていても構わない。  The through hole included in the concave portion in the present embodiment is a force in which the direction in which it is formed is perpendicular to the main surface of semiconductor chip 2. It may be formed so as to be inclined with respect to. Further, each recess is formed to have a rectangular cross-sectional shape, but is not particularly limited to this mode, and may be formed to have a trapezoidal cross-sectional shape, for example.
[0052] また、本実施の形態においては、アンダーフィル樹脂の一部力 凹部の内部に配 置されているが、特にこの形態に限られず、アンダーフィル樹脂が凹部まで到達せず に、凹部の内部にアンダーフィル樹脂が配置されていなくてもよい。  [0052] In the present embodiment, the partial force of the underfill resin is disposed inside the concave portion. However, the present invention is not particularly limited to this mode. The underfill resin may not be disposed inside.
[0053] 図 7から図 12を参照して、本実施の形態における半導体装置に含まれる凹部の製 造方法の例を示す。図 7から図 12は、それぞれの製造工程を説明する概略断面図 である。図 7に示すように、 Si基板 21の上面に開口部を有する層間絶縁膜 22を形成 する。層間絶縁膜 22をマスクにして、 Si基板 21に対してエッチングを行なって切欠き 部 26を形成する。 With reference to FIG. 7 to FIG. 12, an example of a method of manufacturing a concave portion included in the semiconductor device according to the present embodiment will be described. 7 to 12 are schematic cross-sectional views illustrating respective manufacturing steps. As shown in FIG. 7, an interlayer insulating film 22 having an opening is formed on the upper surface of a Si substrate 21. Using the interlayer insulating film 22 as a mask, the Si substrate 21 is etched and Form part 26.
[0054] 次に、図 8に示すように、 CVD (Chemical Vapor D印 osition)法によって、 SiN膜 2 3を層間絶縁膜 22の上面および切欠き部 26の内壁を覆うように形成する。  Next, as shown in FIG. 8, a SiN film 23 is formed by a CVD (Chemical Vapor D mark osition) method so as to cover the upper surface of the interlayer insulating film 22 and the inner wall of the notch 26.
[0055] 次に、 SiN膜 23の表面に、 CVD法によって、図示しない TiN膜を形成する。さらに 、TiN膜の上面に、 CVD法によって図示しない Cu膜を形成する。この後に、図 9に 示すように、 CVD法で形成された Cu膜を電極として、電解 Cuめっき法にて、 Cu膜 2 4を形成する。  Next, a TiN film (not shown) is formed on the surface of the SiN film 23 by a CVD method. Further, a Cu film (not shown) is formed on the upper surface of the TiN film by a CVD method. Thereafter, as shown in FIG. 9, a Cu film 24 is formed by electrolytic Cu plating using the Cu film formed by the CVD method as an electrode.
[0056] 次に、図 10に示すように、 Cu膜 24のうち切欠き部 26の内部に形成されている部分 以外の部分を、 CMP (化学機械研磨）法によって除去する。また、 SiN膜 23のうち切 欠き部 26の内部に形成されている部分以外の部分についても、 CMP法によって除 去する。  Next, as shown in FIG. 10, portions of the Cu film 24 other than the portions formed inside the cutouts 26 are removed by a CMP (chemical mechanical polishing) method. In addition, portions of the SiN film 23 other than the portions formed inside the cutouts 26 are also removed by the CMP method.
[0057] 次に、図 11に示すように、 Si基板 21の裏面に対して研磨を行なって、切欠き部の 底部に形成された Cu膜 24を露出させる。  Next, as shown in FIG. 11, the back surface of the Si substrate 21 is polished to expose the Cu film 24 formed at the bottom of the notch.
[0058] 最後に、図 12に示すように、 Si基板 21の裏面に露出した Cu膜 24に対して、 TiN で形成された拡散防止膜を介して、 Cuで形成された蓋 25を配置する。このように、フ リップチップ接合を行なう前に、凹部を形成することができる。 Finally, as shown in FIG. 12, a lid 25 made of Cu is disposed on the Cu film 24 exposed on the back surface of the Si substrate 21 via a diffusion prevention film made of TiN. . As described above, the concave portion can be formed before the flip chip bonding is performed.
[0059] (実施の形態 2) (Embodiment 2)
図 13から図 20を参照して、本発明に基づく実施の形態 2における半導体装置につ いて説明する。実施の形態 2における半導体装置は、実施の形態 1における第 1の 部材としての半導体チップが有機基板に置き換えられ、さらに、第 2の部材としての 半導体チップが積層された半導体装置である。  The semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. The semiconductor device according to the second embodiment is a semiconductor device in which the semiconductor chip as the first member in the first embodiment is replaced with an organic substrate, and a semiconductor chip as a second member is further laminated.
[0060] 図 13は、本実施の形態における半導体装置の概略断面図である。本実施の形態 における半導体装置は、第 1の部材としての有機基板 4と、第 2の部材として半導体 チップ 1とを備える。有機基板 4と半導体チップ 1とは、それぞれの主表面が互いにほ ぼ平行になるように、間隙をあけて固定されている。  FIG. 13 is a schematic cross-sectional view of the semiconductor device according to the present embodiment. The semiconductor device according to the present embodiment includes an organic substrate 4 as a first member and a semiconductor chip 1 as a second member. The organic substrate 4 and the semiconductor chip 1 are fixed with a gap so that their main surfaces are almost parallel to each other.
[0061] 半導体チップ 1は、バンプ 11を介して、フリップチップによって有機基板 4に結合さ れている。半導体チップ 1に形成された電極パッド 12は、アルミニウム (A1)で形成さ れている。バンプ 11は、たとえば、金 (Au)などの金属から形成されたスタッドバンプ が用いられている。 [0061] The semiconductor chip 1 is coupled to the organic substrate 4 via a bump 11 by a flip chip. The electrode pads 12 formed on the semiconductor chip 1 are formed of aluminum (A1). The bump 11 is, for example, a stud bump formed from a metal such as gold (Au). Is used.
[0062] 半導体チップ 1には他の半導体チップ 3が接合されて、半導体チップが積層されて いる。半導体チップ 3は、金線 16によって、有機基板 4の主表面に形成された外部ラ ンド 14と電気的に結合されている。  [0062] The semiconductor chip 1 is joined to another semiconductor chip 3, and the semiconductor chips are stacked. The semiconductor chip 3 is electrically connected to an external land 14 formed on the main surface of the organic substrate 4 by a gold wire 16.
[0063] 有機基板 4において、半導体チップ 1を有機基板 4に投影した領域の外側には、凹 部 28が形成されている。凹部 28は、貫通孔 8、 Cu膜 30および Cuから形成された蓋 18を含む。貫通孔 8は、有機基板 4を貫通するように形成され、貫通孔 8の半導体チ ップ 1が配置されている側と反対側の開口部には、この開口部を封止する（塞ぐ）よう に、蓋 18が形成されている。蓋 18は、貫通孔 8の開口部の形状に沿うように形成され ている。  In the organic substrate 4, a recess 28 is formed outside a region where the semiconductor chip 1 is projected on the organic substrate 4. The recess 28 includes the through hole 8, the Cu film 30, and the lid 18 formed of Cu. The through-hole 8 is formed so as to penetrate the organic substrate 4, and the opening of the through-hole 8 opposite to the side on which the semiconductor chip 1 is arranged seals (closes) this opening. Thus, a lid 18 is formed. The lid 18 is formed so as to conform to the shape of the opening of the through hole 8.
[0064] 有機基板 4と半導体チップ 1との間の間隙には、アンダーフィル樹脂 20が充填され ている。アンダーフィル樹脂 20は、有機基板 4の外側に向かって延在している。アン ダーフィル樹脂 20の一部は、凹部 28の内部に配置されている。  [0064] The gap between the organic substrate 4 and the semiconductor chip 1 is filled with an underfill resin 20. The underfill resin 20 extends toward the outside of the organic substrate 4. Part of the underfill resin 20 is arranged inside the concave portion 28.
[0065] 凹部 28は、配線層が形成されている有機基板 4の主表面よりも窪んでいる。凹部 2 8の平面形状は、長方形になるように形成されている。凹部 28は、平面形状における 長手方向が、半導体チップ 1の外形に沿うように形成されている。すなわち、凹部 28 の平面形状は、実施の形態 1における第 1の半導体装置の凹部と同様になるように 形成されている。 （図 2参照）。  The recess 28 is recessed from the main surface of the organic substrate 4 on which the wiring layer is formed. The planar shape of the concave portion 28 is formed to be rectangular. The concave portion 28 is formed such that the longitudinal direction of the planar shape follows the outer shape of the semiconductor chip 1. That is, the recess 28 is formed so as to have the same planar shape as the recess of the first semiconductor device in the first embodiment. (See Figure 2).
[0066] 本実施の形態における有機基板 4は、ガラスエポキシ樹脂を用いて形成されている 。バンプ 11が接合される有機基板 4に形成されたランド（図示せず）は、銅（Cu)箔の 上面に、ニッケル (Ni)および金 (Au)のめつきが施されている。有機基板 4に形成さ れているランドは、半導体チップ 1に形成されている電極パッド 12の位置に対応する ように配置されている。  The organic substrate 4 in the present embodiment is formed using a glass epoxy resin. The lands (not shown) formed on the organic substrate 4 to which the bumps 11 are bonded are provided with nickel (Ni) and gold (Au) on the upper surface of a copper (Cu) foil. The lands formed on the organic substrate 4 are arranged so as to correspond to the positions of the electrode pads 12 formed on the semiconductor chip 1.
[0067] その他の構成については、実施の形態 1における第 1の半導体装置と同様である。  The other configuration is the same as that of the first semiconductor device in the first embodiment.
[0068] 半導体チップ 1と有機基板 4とは、熱圧着工法または超音波を併用した熱圧着工法 によってフリップチップ接合されている。有機基板 4に形成されたランドと半導体チッ プ 1に形成された電極パッド 12と力 バンプ 11を介して結合固定されている。 [0068] The semiconductor chip 1 and the organic substrate 4 are flip-chip bonded by a thermocompression bonding method or a thermocompression bonding method using ultrasonic waves. The lands formed on the organic substrate 4 and the electrode pads 12 formed on the semiconductor chip 1 are coupled and fixed via force bumps 11.
[0069] 製造工程において、有機基板 4と半導体チップ 1のフリップチップが終了した後に、 有機基板 4と半導体チップ 1との隙間にアンダーフィル樹脂 20が注入される。この際 に、アンダーフィル樹脂 20は、有機基板 4の外側に向かって流れて、アンダーフィノレ 樹脂 20の一部が凹部 28に流入する。 In the manufacturing process, after the flip chip of the organic substrate 4 and the semiconductor chip 1 is completed, An underfill resin 20 is injected into a gap between the organic substrate 4 and the semiconductor chip 1. At this time, the underfill resin 20 flows toward the outside of the organic substrate 4, and a part of the underfill resin 20 flows into the concave portion.
[0070] このように、半導体チップ 1を有機基板 4に投影した領域の外側に凹部が形成され ていることによって、アンダーフィル樹脂 20が流れて外部ランド 14が汚染されることを 防止できる。すなわち、上記の領域と外部ランド 14との間に、凹部 28を形成すること によって、外部ランド 14がアンダーフィル樹脂 20によって汚染されることを防止できる 。この結果、外部ランド 14がアンダーフィル樹脂によって汚染されていない半導体装 置を提供することができる。  As described above, since the concave portion is formed outside the region where the semiconductor chip 1 is projected on the organic substrate 4, it is possible to prevent the underfill resin 20 from flowing and the external land 14 from being contaminated. That is, by forming the concave portion 28 between the above-mentioned region and the external land 14, the external land 14 can be prevented from being contaminated by the underfill resin 20. As a result, it is possible to provide a semiconductor device in which the outer lands 14 are not contaminated by the underfill resin.
[0071] 本実施の形態においては、凹部 28は、貫通孔 8の内壁に Cu膜 30が形成され、蓋 18が、導電性材料である Cuで形成されている。この構成を採用することにより、有機 基板 4の表側に形成された配線と、裏側に形成された配線とを凹部 28を介して電気 的に接続することができる。  In the present embodiment, concave portion 28 has Cu film 30 formed on the inner wall of through hole 8, and lid 18 is formed of Cu, which is a conductive material. By employing this configuration, the wiring formed on the front side of the organic substrate 4 and the wiring formed on the back side can be electrically connected via the concave portion 28.
[0072] 本実施の形態においては、有機基板を貫通する貫通孔が形成され、貫通孔のー 方の開口部が蓋によって封止されているが、特にこの形態に限られず、有機基板を 貫通しなレ、ような凹部が形成されてレ、てもよレ、。  [0072] In the present embodiment, a through-hole penetrating the organic substrate is formed, and the opening on the other side of the through-hole is sealed with a lid. However, the present invention is not limited to this mode. A concave part is formed, and a concave part is formed.
[0073] また、本実施の形態においては、第 1の部材としての有機基板にガラスエポキシ樹 脂を用いているが、特にこの形態に限られず、たとえば、ポリイミド樹脂を用いて形成 されていてもよい。  Further, in the present embodiment, a glass epoxy resin is used for the organic substrate as the first member. However, the present invention is not limited to this mode. For example, the organic substrate may be formed using a polyimide resin. Good.
[0074] その他の作用および効果については、実施の形態 1と同様であるので、ここでは説 明を繰り返さない。  [0074] Other functions and effects are the same as those of the first embodiment, and thus description thereof will not be repeated here.
[0075] 図 14から図 20を参照して、本実施の形態における半導体装置に含まれる凹部の 製造方法の一例を示す。図 14から図 20は、それぞれの工程を説明する概略断面図 である。  With reference to FIG. 14 to FIG. 20, an example of a method for manufacturing a concave portion included in the semiconductor device according to the present embodiment will be described. 14 to 20 are schematic cross-sectional views illustrating each step.
[0076] 図 14に示すように、有機基板 31に対して、ドリルカ卩ェによって貫通孔を形成した後 に、基板全体に対して、無電解 Cuめっき膜を形成する。このとき、貫通孔の内部に C uめっき膜 36が形成される。  As shown in FIG. 14, after forming a through hole in the organic substrate 31 by drilling, an electroless Cu plating film is formed on the entire substrate. At this time, the Cu plating film 36 is formed inside the through hole.
[0077] 次に、図 15に示すように、ラミネート法によって、有機基板 31の表裏の主表面に、 絶縁膜 32を形成する。このとき、 Cuめっき膜 36で囲まれる領域にも絶縁膜 32の材 料が充填される。 Next, as shown in FIG. 15, the main surface of the front and back of the organic substrate 31 was An insulating film 32 is formed. At this time, the region surrounded by the Cu plating film 36 is also filled with the material of the insulating film 32.
[0078] 次に、図 16に示すように、有機基板 31の裏側から、レーザ加工によって、切欠き部 37を形成する。切欠き部 37は、 Cuめっき膜 36の平面形状に沿うように形成する。次 に、図 17に示すように、絶縁膜 32の粗ィ匕処理を行なった後に、無電解 Cuめっき膜 3 3を形成する。無電解 Cuめっき膜 33を、有機基板 31の裏面側の絶縁膜 32の主表 面および切欠き部 37の内部に形成する。  Next, as shown in FIG. 16, a notch 37 is formed from the back side of the organic substrate 31 by laser processing. The notch 37 is formed so as to follow the planar shape of the Cu plating film 36. Next, as shown in FIG. 17, after performing a roughening treatment on the insulating film 32, an electroless Cu plating film 33 is formed. An electroless Cu plating film 33 is formed on the main surface of the insulating film 32 on the rear surface side of the organic substrate 31 and inside the notch 37.
[0079] 次に、図 18に示すように、図示しないレジストを形成して、電解 Cuめっき部 34を形 成する。電解 Cuめっき部 34は、切欠き部の形状に沿うように形成される。  Next, as shown in FIG. 18, a resist (not shown) is formed to form an electrolytic Cu plated portion 34. The electrolytic Cu plating part 34 is formed so as to follow the shape of the notch.
[0080] 次に、図 19に示すように、絶縁膜 32の主表面に形成されている無電解 Cuめっき 膜 33を除去する。このように、無電解 Cuめっき膜 33および電解 Cuめっき部 34を含 む蓋 35を形成する。  Next, as shown in FIG. 19, the electroless Cu plating film 33 formed on the main surface of the insulating film 32 is removed. Thus, the lid 35 including the electroless Cu plating film 33 and the electrolytic Cu plating portion 34 is formed.
[0081] 次に、図 20に示すように、 Cuめっき膜 36で囲まれた領域に対して、レーザ加工を 行なって、凹部の凹となる部分を形成する。凹となる部分の径は、たとえば 100 / m 程度である。  Next, as shown in FIG. 20, laser processing is performed on a region surrounded by the Cu plating film 36 to form a concave portion of the concave portion. The diameter of the concave portion is, for example, about 100 / m.
[0082] このように、有機基板に対して、フリップチップ接合の前に第 1の部材を有機基板に 投影したときの領域の外側に、凹部を形成することができる。  As described above, the concave portion can be formed on the organic substrate outside the region when the first member is projected onto the organic substrate before the flip chip bonding.
[0083] (実施の形態 3) (Embodiment 3)
図 21を参照して、本発明に基づく実施の形態 3における半導体装置について説明 する。  Referring to FIG. 21, a semiconductor device according to a third embodiment of the present invention will be described.
[0084] 図 21は、本実施の形態における半導体装置の概略断面図である。第 1の部材とし ての半導体チップ 2と第 2の部材としての半導体チップ 1とが、バンプ 11を介してフリ ップチップによって結合され、半導体チップ 1と半導体チップ 2との隙間に、アンダー フィル樹脂 20が注入されていることは、実施の形態 1における半導体装置と同様であ る。また、半導体チップ 2の外周部に電極パッド 13が形成され、電極パッド 13に金線 15が接続されていることも実施の形態 1における半導体装置と同様である。  FIG. 21 is a schematic sectional view of the semiconductor device according to the present embodiment. The semiconductor chip 2 as the first member and the semiconductor chip 1 as the second member are joined by a flip chip via a bump 11, and an underfill resin 20 is inserted into a gap between the semiconductor chip 1 and the semiconductor chip 2. This is the same as in the semiconductor device in the first embodiment. Also, the electrode pad 13 is formed on the outer peripheral portion of the semiconductor chip 2 and the gold wire 15 is connected to the electrode pad 13 as in the semiconductor device according to the first embodiment.
[0085] 本実施の形態における半導体装置は、凹部の代わりに、保護膜 19が形成されてい る。保護膜 19は、半導体チップ 2のクラックの発生を防止するために形成されている 。本実施の形態における保護膜 19は、ポリイミド樹脂で形成されている。保護膜 19 は、たとえば、感光性ポリイミド榭脂を用いたフォトリソグラフィによって形成されている [0085] In the semiconductor device according to the present embodiment, a protective film 19 is formed instead of the concave portion. The protective film 19 is formed to prevent the occurrence of cracks in the semiconductor chip 2. . The protective film 19 in the present embodiment is formed of a polyimide resin. The protective film 19 is formed by, for example, photolithography using a photosensitive polyimide resin.
[0086] 保護膜 19は、半導体チップ 2の主表面から突出するように形成されている。半導体 チップのクラックなどを防止するための保護膜の通常の厚さは 5 μ m程度である。本 実施の形態における保護膜 19は、厚さが 5 μ m程度である。 [0086] The protective film 19 is formed so as to protrude from the main surface of the semiconductor chip 2. The typical thickness of the protective film to prevent cracks in semiconductor chips is about 5 μm. The protective film 19 in the present embodiment has a thickness of about 5 μm.
[0087] 保護膜 19は、半導体チップ 1を半導体チップ 2に投影したときの領域の外側に配置 され、この領域を取り囲むように形成されている。保護膜 19は、この領域と電極パッド 13との間に配置されている。保護膜 19は、平面形状が長方形になるように形成され 、この長方形の長辺が、半導体チップ 1の外縁とほぼ平行になるように形成されてい る。すなわち、本実施の形態における半導体装置は、保護膜が堰になるように連続 的に形成され、実施の形態 1における第 1の半導体装置（図 1および図 2参照）の凹 部を保護膜に置き換えた構成を備える。  [0087] The protective film 19 is arranged outside a region when the semiconductor chip 1 is projected onto the semiconductor chip 2, and is formed so as to surround this region. The protection film 19 is arranged between this region and the electrode pad 13. The protective film 19 is formed such that the planar shape is rectangular, and the long side of the rectangular is substantially parallel to the outer edge of the semiconductor chip 1. That is, the semiconductor device in the present embodiment is formed continuously so that the protective film functions as a weir, and the concave portion of the first semiconductor device in Embodiment 1 (see FIGS. 1 and 2) is used as the protective film. It has a replaced configuration.
[0088] アンダーフィル樹脂 20は、半導体チップ 1と半導体チップ 2との隙間に注入され、こ の隙間から半導体チップ 2の外側に向かって、保護膜 19が形成されている部分まで 配置されている。  [0088] The underfill resin 20 is injected into a gap between the semiconductor chip 1 and the semiconductor chip 2, and is arranged from the gap toward the outside of the semiconductor chip 2 to a portion where the protective film 19 is formed. .
[0089] その他の構成については、実施の形態 1における第 1の半導体装置と同様である ので、ここでは説明を繰り返さない。  [0089] Other configurations are similar to those of the first semiconductor device in First Embodiment, and thus description thereof will not be repeated here.
[0090] 製造工程においては、半導体チップ 1と半導体チップ 2とが、熱圧着工法または超 音波を併用した熱圧着工法によって、フリップチップ接合される。半導体チップ 2には 、予め保護膜 19が形成されている。  [0090] In the manufacturing process, the semiconductor chip 1 and the semiconductor chip 2 are flip-chip bonded by a thermocompression bonding method or a thermocompression bonding method using ultrasonic waves. The protective film 19 is formed on the semiconductor chip 2 in advance.
[0091] 半導体チップ 1と半導体チップ 2とのフリップチップ接合が終了した後に、半導体チ ップ 1と半導体チップ 2との間隙にアンダーフィル樹脂 20を注入する。アンダーフィノレ 樹脂 20は、この間隙に注入されるほかに、半導体チップ 2の外側に向かって流れる が、保護膜 19によって堰き止められる。このように、アンダーフィル樹脂 20が半導体 チップ 2の外周部に形成された電極パッド 13に到達することを防止でき、電極パッド 1 3がアンダーフィル樹脂 20によって汚染されることを防止できる。  After the flip chip bonding between the semiconductor chip 1 and the semiconductor chip 2 is completed, the underfill resin 20 is injected into the gap between the semiconductor chip 1 and the semiconductor chip 2. The under fin resin 20 is injected into the gap and flows toward the outside of the semiconductor chip 2, but is blocked by the protective film 19. As described above, the underfill resin 20 can be prevented from reaching the electrode pads 13 formed on the outer peripheral portion of the semiconductor chip 2, and the electrode pads 13 can be prevented from being contaminated by the underfill resin 20.
[0092] また、半導体チップのクラックを防止する保護膜は、従来の技術における半導体チ ップに対しても形成されているため、保護膜を形成するためのマスクのパターンと、保 護膜の厚さを変更するのみで、本発明に基づく半導体装置を製造することができる。 製造においては、新たな製造工程の追加や、新たな材料の追加が不要であるため、 容易に電極パッドなどの汚染を防止した半導体装置を提供することができる。 [0092] In addition, a protective film for preventing cracks in a semiconductor chip is provided by a conventional semiconductor chip. The semiconductor device according to the present invention can be manufactured only by changing the mask pattern for forming the protective film and the thickness of the protective film. In manufacturing, it is not necessary to add a new manufacturing process or a new material, so that it is possible to easily provide a semiconductor device in which contamination of an electrode pad or the like is prevented.
[0093] また、本実施の形態における保護膜 19は、半導体チップ 1を半導体チップ 2に投影 した領域を取り囲むように形成されている。この構成を採用することにより、より効果的 にアンダーフィル樹脂が電極パッドに到達することを防止できる。  Further, protective film 19 in the present embodiment is formed so as to surround a region where semiconductor chip 1 is projected onto semiconductor chip 2. By employing this configuration, it is possible to more effectively prevent the underfill resin from reaching the electrode pad.
[0094] 本実施の形態における保護膜の厚さは 5 μ m程度であるが、第 1の部材および第 2 の部材同士の間隙の幅、およびアンダーフィル樹脂の種類によっては、保護膜を厚 くすることが好ましい。  [0094] Although the thickness of the protective film in the present embodiment is about 5 μm, depending on the width of the gap between the first member and the second member and the type of the underfill resin, the thickness of the protective film may vary. Preferably.
[0095] その他の作用および効果については実施の形態 1と同様であるのでここでは説明 を繰り返さない。  [0095] Other functions and effects are the same as those of the first embodiment, and therefore description thereof will not be repeated here.
[0096] (実施の形態 4)  (Embodiment 4)
図 22から図 34を参照して、本発明に基づく実施の形態 4における半導体装置およ び半導体装置の製造方法について説明する。  Embodiment 4 A semiconductor device and a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS.
[0097] 図 22は、本実施の形態における半導体装置の概略断面図である。本実施の形態 における半導体装置は、第 1の部材としての半導体チップ 52と、第 2の部材としての 半導体チップ 51とを備える。半導体チップ 51と半導体チップ 52とは、表面同士が互 レ、にほぼ平行になるように間隙をあけて配置されている。半導体チップ 52の表面に は、外部への接続線を接続するための第 1のパッドとしてパッド 64が形成されている 。パッド 64は、半導体チップ 51を半導体チップ 52に投影したときに、影になる領域の 外側に配置されている。  FIG. 22 is a schematic cross-sectional view of the semiconductor device according to the present embodiment. The semiconductor device according to the present embodiment includes a semiconductor chip 52 as a first member and a semiconductor chip 51 as a second member. The semiconductor chip 51 and the semiconductor chip 52 are arranged with a gap so that the surfaces are substantially parallel to each other. On the surface of the semiconductor chip 52, a pad 64 is formed as a first pad for connecting a connection line to the outside. The pad 64 is arranged outside a shadowed area when the semiconductor chip 51 is projected onto the semiconductor chip 52.
[0098] 半導体チップ 52の表面には、半導体チップ 51を接続するための第 2のパッドとして 、パッド 65が形成されている。パッド 65は、半導体チップ 51を半導体チップ 52に投 影したときに、影になる領域に配置されている。半導体チップ 52の表面およびパッド 64, 65の表面の一部にはポリイミド膜 55が形成されている。ポリイミド膜 55は、ソフト エラーの防止のために形成されている。  On the surface of the semiconductor chip 52, a pad 65 is formed as a second pad for connecting the semiconductor chip 51. The pad 65 is arranged in a shadowed area when the semiconductor chip 51 is projected on the semiconductor chip 52. A polyimide film 55 is formed on the surface of the semiconductor chip 52 and a part of the surfaces of the pads 64 and 65. The polyimide film 55 is formed to prevent a soft error.
[0099] パッド 64の表面には、力 ^上げ部 74aが形成されている。力、さ上げ部 74aは、導電 性を有する部分の高さが高くなるように形成された部分である。本実施の形態におい ては、力さ上げ部 74aは直方体状に形成されている。力さ上げ部 74aは、ノ リアメタル 層 72aと Auバンプ 73aとを含む。パッド 65の表面には、力さ上げ部 74bが形成されて いる。力 ^上げ部 74bは、ノ リアメタル層 72bと Auバンプ 73bを含む。 [0099] On the surface of the pad 64, a force raising portion 74a is formed. 74a is conductive. This is a portion formed so that the height of the portion having the property is increased. In the present embodiment, the force raising portion 74a is formed in a rectangular parallelepiped shape. The raising portion 74a includes a non-metal layer 72a and an Au bump 73a. On the surface of the pad 65, a force raising portion 74b is formed. The force-raising portion 74b includes a non-metal layer 72b and an Au bump 73b.
[0100] 本実施の形態においては、後述するようにバリアメタル層 72aとバリアメタル層 72b とは同一の製造工程で形成され、同一の材質で形成されている。また、 Auバンプ 73 aと Auバンプ 73bとは、同じ製造工程で形成され、同一の材質で形成されている。  In the present embodiment, as described later, barrier metal layer 72a and barrier metal layer 72b are formed in the same manufacturing process and are formed of the same material. The Au bump 73a and the Au bump 73b are formed in the same manufacturing process and are formed of the same material.
[0101] 本実施の形態におけるバリアメタル層 72a， 72bは、パッド 64, 65の表面力、ら TiN 層、 TiW層、および Au層の順に積層された積層体である。バリアメタル層 72a, 72b は、 Auノ ンプ 73a, 73bとノ ッド 64， 65とを密着させるため、および拡散バリア効果 を得るために形成されている。  [0101] The barrier metal layers 72a and 72b in the present embodiment are a laminate in which the surface forces of the pads 64 and 65, the TiN layer, the TiW layer, and the Au layer are laminated in this order. The barrier metal layers 72a and 72b are formed for bringing the Au pumps 73a and 73b into close contact with the nodes 64 and 65 and for obtaining a diffusion barrier effect.
[0102] 半導体チップ 51の表面には、半導体チップ 52との接続を行なうためのパッド 63が 形成されている。半導体チップ 51の表面およびパッド 63の表面の一部には、ポリイミ ド膜 56が形成されている。パッド 63は、力さ上げ部 74bに接合されている。このように 、半導体チップ 51と半導体チップ 52とは、導電性部材を介して、間隙をあけて固定 され、互いに電気的に接続されている。  [0102] On the surface of the semiconductor chip 51, pads 63 for connection with the semiconductor chip 52 are formed. A polyimide film 56 is formed on the surface of the semiconductor chip 51 and a part of the surface of the pad 63. The pad 63 is joined to the lifting portion 74b. As described above, the semiconductor chip 51 and the semiconductor chip 52 are fixed with a gap therebetween via the conductive member, and are electrically connected to each other.
[0103] 半導体チップ 51と半導体チップ 52との間には、アンダーフィル樹脂 92が配置され ている。アンダーフィル樹脂 92は、半導体チップ 51が配置されている領域から外側 に向かって広がるように配置されている。半導体チップ 52のパッド 64が形成されてい る部分において、力さ上げ部 74aは、アンダーフィル樹脂 92の高さよりも高くなつてい る。  [0103] An underfill resin 92 is disposed between the semiconductor chip 51 and the semiconductor chip 52. The underfill resin 92 is arranged so as to spread outward from a region where the semiconductor chip 51 is arranged. In the portion where the pad 64 of the semiconductor chip 52 is formed, the force increasing portion 74 a is higher than the height of the underfill resin 92.
[0104] 半導体チップ 52は、接着材 91を介して、配線基板 81に固定されている。配線基板  The semiconductor chip 52 is fixed to the wiring board 81 via an adhesive 91. Wiring board
81の表面の外周部には、ランド 84が形成されている。半導体チップ 52のパッド 64と 配線基板 81のランド 84とは、金線 61によって電気的に互いに接続されている。金線 61は、力 ^上げ部 74aに接続されている端部において、球状の金ボール部 71を含 む。  A land 84 is formed on the outer peripheral portion of the surface of 81. The pads 64 of the semiconductor chip 52 and the lands 84 of the wiring board 81 are electrically connected to each other by gold wires 61. The gold wire 61 includes a spherical gold ball portion 71 at an end connected to the force raising portion 74a.
[0105] 配線基板 81の上面には、内部に半導体チップ 51， 52および金線 61を含むように 封止樹脂 90が配置されている。配線基板 81の主表面のうち、半導体チップ 52が配 置されている側と反対側の主表面には、ランド 82および半田ボール 83が配置されて いる。 A sealing resin 90 is arranged on the upper surface of the wiring board 81 so as to include the semiconductor chips 51 and 52 and the gold wires 61 therein. The semiconductor chip 52 is arranged on the main surface of the wiring board 81. Lands 82 and solder balls 83 are arranged on the main surface opposite to the side on which they are placed.
[0106] 図 23は、本実施の形態における半導体装置の封止樹脂を取除いたときの平面図 である。図 24は、本実施の形態における半導体装置の下面図である。図 23を参照し て、本実施の形態における半導体装置は、半導体チップ 51 , 52の平面形状がほぼ 正方形になるように配置されている。半導体チップ 51と半導体チップ 52とは、それぞ れの重心位置が平面的に見て重なるように配置されている。  FIG. 23 is a plan view of the semiconductor device according to the present embodiment when the sealing resin is removed. FIG. 24 is a bottom view of the semiconductor device according to the present embodiment. Referring to FIG. 23, the semiconductor device in the present embodiment is arranged such that semiconductor chips 51 and 52 have a substantially square planar shape. The semiconductor chip 51 and the semiconductor chip 52 are arranged such that their respective centers of gravity overlap in plan view.
[0107] 力、さ上げ部 74aは、半導体チップ 52の周辺部分に配置されている。力 ^上げ部 74 aは、半導体チップ 52の外縁に沿うように配置されている。配線基板 81の表面には、 力、さ上げ部 74aの位置に対応するようにランド 84が形成されている。アンダーフィル 樹脂 92は、半導体チップ 51が形成されている領域からかさ上げ部 74aが形成されて レ、る領域まで配置されている。アンダーフィル樹脂 92は、半導体チップ 52の外側に 飛び出さなレ、ように配置されてレ、る。  The force raising portion 74 a is arranged in a peripheral portion of the semiconductor chip 52. The force raising portion 74 a is arranged along the outer edge of the semiconductor chip 52. Lands 84 are formed on the surface of the wiring board 81 so as to correspond to the positions of the force and the raised portions 74a. The underfill resin 92 is arranged from a region where the semiconductor chip 51 is formed to a region where the raised portion 74a is formed. The underfill resin 92 is arranged so as not to protrude outside the semiconductor chip 52.
[0108] 図 22を参照して、配線基板 81の下面においては、ランド 82を介して複数の半田ボ ール 83が形成されている。本実施の形態においては、複数の半田ボール 83が規則 的に配列して形成されている。  Referring to FIG. 22, on the lower surface of wiring board 81, a plurality of solder balls 83 are formed via lands. In the present embodiment, a plurality of solder balls 83 are formed so as to be regularly arranged.
[0109] 図 22から図 24を参照して、本実施の形態における半導体装置は、半導体チップ 5 2のパッド 64の表面に、力さ上げ部 74aが形成されている。この構成を採用すること により、金線 61を接続する部分の頂面の高さを高くすることができ、アンダーフィル榭 脂 92が、外側に向かって流れても、金線 61を接続する部分の表面の汚染を防止で きる。したがって、金線 61とかさ上げ部 74aとの接合強度が小さくなることを防止でき 、金ボール部 71を確実に接合することができる。また、後に金ボール部 71が剥がれ 、外れてしまうことを防止できる。  Referring to FIGS. 22 to 24, in the semiconductor device according to the present embodiment, a force increasing portion 74 a is formed on the surface of pad 64 of semiconductor chip 52. By adopting this configuration, the height of the top surface of the portion connecting the gold wire 61 can be increased, and even if the underfill resin 92 flows outward, the portion connecting the gold wire 61 can be increased. Surface contamination can be prevented. Therefore, it is possible to prevent the bonding strength between the gold wire 61 and the raised portion 74a from being reduced, and to reliably bond the gold ball portion 71. Further, it is possible to prevent the gold ball portion 71 from coming off and coming off later.
[0110] 力、さ上げ部 74aとしては、アンダーフィル樹脂 92によって頂面が汚染されないような 十分な高さを有することが好ましい。たとえば、アンダーフィル樹脂 92のおおよそ 10 μ mの厚さに対応させて、力、さ上げ部 74aの高さはパッド 64の表面から 20 μ m以上 25 z m以下が好ましい。  The force raising portion 74a preferably has a height sufficient to prevent the top surface from being contaminated by the underfill resin 92. For example, according to the thickness of the underfill resin 92 of about 10 μm, the height of the force and the raised portion 74 a is preferably 20 μm or more and 25 zm or less from the surface of the pad 64.
[0111] 次に、図 25から図 34を参照して、本実施の形態における半導体装置の製造方法 について説明する。 Next, with reference to FIGS. 25 to 34, a method of manufacturing a semiconductor device in the present embodiment will be described. Will be described.
[0112] 図 25から図 34は、それぞれの工程における概略断面図である。図 25を参照して、 はじめに、電気回路を第 1の部材としてのシリコン基板などの半導体基板 58に形成 する。半導体基板 58の表面にパッド 64， 65を形成する。  FIG. 25 to FIG. 34 are schematic cross-sectional views in each step. Referring to FIG. 25, first, an electric circuit is formed on a semiconductor substrate 58 such as a silicon substrate as a first member. Pads 64 and 65 are formed on the surface of the semiconductor substrate 58.
[0113] パッド 64は、後に外部との電気的な接続を行なうためのパッドである。パッド 64は、 半導体チップとなるべき領域の周辺部に配置する。パッド 64は、後に接続される第 2 の部材としての半導体チップが配置される領域の外側に配置する。  The pad 64 is a pad for making an electrical connection to the outside later. The pad 64 is arranged at a peripheral portion of a region to be a semiconductor chip. The pad 64 is arranged outside a region where a semiconductor chip as a second member to be connected later is arranged.
[0114] パッド 65は、後に接続される第 2の部材としての半導体チップとの電気的な接続を 行なうためのパッドである。パッド 65は、後に接続される半導体チップの投影領域に 配置されている。次に、半導体基板 58の表面およびパッド 64， 65の表面の一部を覆 うように、ポリイミド膜 55を形成する。次に、力、さ上げ部を形成するかさ上げ部形成ェ 程を行なう。  The pad 65 is a pad for making an electrical connection with a semiconductor chip as a second member to be connected later. The pad 65 is arranged in a projection area of a semiconductor chip to be connected later. Next, a polyimide film 55 is formed so as to cover the surface of the semiconductor substrate 58 and part of the surfaces of the pads 64 and 65. Next, a step of forming a raised portion is performed.
[0115] 図 26に示すように、パッド 64, 65の露出した部分およびポリイミド膜 55を覆うように 、バリアメタル層 72を形成する。ノくリアメタル層 72は、たとえば、スパッタ法で形成す る。本実施の形態においては、バリアメタル層として、順に TiN層、 TiW層、 Au層の 3 層を積層して形成する。  As shown in FIG. 26, a barrier metal layer 72 is formed so as to cover the exposed portions of the pads 64 and 65 and the polyimide film 55. The rear metal layer 72 is formed, for example, by a sputtering method. In this embodiment, the barrier metal layer is formed by sequentially stacking three layers of a TiN layer, a TiW layer, and an Au layer.
[0116] 次に、図 27に示すように、開口部 78を有するフォトレジスト層 77を形成する。開口 部 78は、ノ ッド 64, 65が配置されている領域に形成する。フォトレジスト層 77の形成 においては、たとえば、スピン塗布法でフォトレジストを塗布した後に、露光および現 像を行なって開口部 78を形成する。本実施の形態においては、平面形状が四角形 になるように開口部 78を形成する。  Next, as shown in FIG. 27, a photoresist layer 77 having an opening 78 is formed. The opening 78 is formed in a region where the nodes 64 and 65 are arranged. In forming the photoresist layer 77, for example, after applying a photoresist by a spin coating method, exposure and image formation are performed to form an opening 78. In the present embodiment, the opening 78 is formed so that the planar shape becomes a square.
[0117] 次に、図 28に示すように、電解めつき法によって、 Auバンプ 73a， 73bを形成する 。電解めつき法においては、たとえば、 Auイオンを含むめっき液に半導体基板を浸 漬させた状態で、バリアメタル層 72に正の電圧を印加することによって、フォトレジスト 層 77の開口部 78に Auを析出させる。このように、開口部 78の形状に沿って、 Auバ ンプ 73a, 73bを形成する。本実施の形態においては、 Auバンプ 73a， 73bをほぼ 直方体の形状に形成する。  Next, as shown in FIG. 28, Au bumps 73a and 73b are formed by electrolytic plating. In the electroplating method, for example, a positive voltage is applied to the barrier metal layer 72 while the semiconductor substrate is immersed in a plating solution containing Au ions, so that the Au layer is formed in the opening 78 of the photoresist layer 77. Is precipitated. Thus, the Au bumps 73a and 73b are formed along the shape of the opening 78. In the present embodiment, the Au bumps 73a and 73b are formed in a substantially rectangular parallelepiped shape.
[0118] 次に、図 29を参照して、フォトレジスト層を除去した後に、ノ リアメタル層のうち、 Au バンプ 73a, 73bが形成されている領域を避けた領域において、ノくリアメタル層の除 去を行なう。バリアメタル層の除去においては、たとえばエッチングによって行なう。こ のように、バリアメタル層 72aおよび Auバンプ 73aを含む力さ上げ部 74aと、バリアメ タル層 72bおよび Auバンプ 73bを含むかさ上げ部 74bを形成する。この後に、半導 体基板 58をダイシングによって切断して、個々の半導体チップを形成する。 Next, referring to FIG. 29, after removing the photoresist layer, the Au In the region other than the region where the bumps 73a and 73b are formed, the rear metal layer is removed. The removal of the barrier metal layer is performed, for example, by etching. In this way, a raised portion 74a including the barrier metal layer 72a and the Au bump 73a and a raised portion 74b including the barrier metal layer 72b and the Au bump 73b are formed. Thereafter, the semiconductor substrate 58 is cut by dicing to form individual semiconductor chips.
[0119] 次に、図 30に示すように、接着材 91により半導体チップ 52を配線基板 81に接着 する。配線基板 81の主表面のうち、半導体チップ 52が配置される主表面にはランド 84を形成しておく。また、配線基板 81の主表面のうち、半導体チップ 52が配置され る側と反対側の主表面にはランド 82を形成しておく。  Next, as shown in FIG. 30, the semiconductor chip 52 is bonded to the wiring board 81 with an adhesive 91. A land 84 is formed on the main surface of the wiring substrate 81 on which the semiconductor chip 52 is arranged. Further, a land 82 is formed on the main surface of the wiring substrate 81 opposite to the side on which the semiconductor chip 52 is arranged.
[0120] 次に、図 31に示すように、別の製造工程で製造された半導体チップ 51を、半導体 チップ 52に電気的に接続すると共に固定する。半導体チップ 51には、半導体チップ 52と同様にパッド 63およびポリイミド膜 56を表面に形成しておく。矢印 97に示すよう に、半導体チップ 51のパッド 63がかさ上げ部 74bと接続するように、たとえば、フリツ プチップ接合によって熱および超音波を印加しながら接合を行なう。  Next, as shown in FIG. 31, the semiconductor chip 51 manufactured in another manufacturing process is electrically connected to the semiconductor chip 52 and fixed. The pad 63 and the polyimide film 56 are formed on the surface of the semiconductor chip 51 in the same manner as the semiconductor chip 52. As shown by an arrow 97, bonding is performed while applying heat and ultrasonic waves by, for example, flip-chip bonding so that the pad 63 of the semiconductor chip 51 is connected to the raised portion 74b.
[0121] 次に、図 32を参照して、半導体チップ 51と半導体チップ 52との間に、アンダーフィ ル榭脂 92を配置するアンダーフィル樹脂配置工程を行なう。このときに、アンダーフ ィル榭脂 92が外側に向かって流れることがある力 パッド 64の表面に力さ上げ部 74 aが形成されているため、力さ上げ部 74aの頂面の汚染を防止することができる。  Next, referring to FIG. 32, an underfill resin arranging step of arranging underfill resin 92 between semiconductor chip 51 and semiconductor chip 52 is performed. At this time, since the underfill resin 92 may flow outwardly, a force-raising portion 74a is formed on the surface of the force pad 64, thereby preventing the top surface of the force-raising portion 74a from being contaminated. can do.
[0122] 次に、図 33に示すように、半導体チップ 52に形成された力さ上げ部 74aと、配線基 板 81の表面に形成されたランド 84との電気的な接続を行なう。本実施の形態におい ては、ワイヤボンディング装置を用いて、金線 61を形成する。ワイヤボンディング装置 のキヤビラリ 85の先端に予め少量の金線 61を押し出すことにより、金ボール部 71を 形成する。金ボール部 71を、力、さ上げ部 74aの頂面に接合した後にキヤビラリ 85を 移動させて、金線 61をランド 84に接続する。  Next, as shown in FIG. 33, an electrical connection is made between the force increasing portion 74a formed on the semiconductor chip 52 and the land 84 formed on the surface of the wiring board 81. In the present embodiment, the gold wire 61 is formed using a wire bonding apparatus. A gold ball portion 71 is formed by extruding a small amount of gold wire 61 into the tip of a cavity 85 of a wire bonding apparatus in advance. After joining the gold ball portion 71 to the top surface of the force / raising portion 74a, the cabillary 85 is moved to connect the gold wire 61 to the land 84.
[0123] 次に、図 34に示すように、封止樹脂 90で装置の封止を行なう。半導体チップ 51， 5 2および金線 61のすベてを含むように封止を行なう。最後に、配線基板 81のランド 8 2に半田ボール 83を形成する。  Next, as shown in FIG. 34, the device is sealed with a sealing resin 90. The sealing is performed so as to include all of the semiconductor chips 51 and 52 and the gold wire 61. Finally, the solder balls 83 are formed on the lands 82 of the wiring board 81.
[0124] このように、本実施の形態においては、外部への接続線を接続するための第 1のパ ッドの表面に、導電性部材を配置して力さ上げ部を形成するかさ上げ部形成工程と、 力さ上げ部形成工程の後に、第 1の部材と第 2の部材との間にアンダーフィル樹脂を 配置するアンダーフィル樹脂配置工程を含む。この方法を採用することにより、アン ダーフィル樹脂が、第 1の部材の電気的な接続部分の表面を汚染することを防止で きる。この結果、たとえば、本実施の形態においては、金線とパッドとの良好な電気的 な接続を行なうことができる。 As described above, in the present embodiment, the first path for connecting an external connection line is provided. A raised portion forming step in which a conductive member is disposed on the surface of the pad to form a raised portion, and after the step of forming the raised portion, the under member is placed between the first member and the second member. The method includes an underfill resin disposing step of disposing a fill resin. By employing this method, it is possible to prevent the underfill resin from contaminating the surface of the electrical connection portion of the first member. As a result, for example, in the present embodiment, good electrical connection between the gold wire and the pad can be performed.
[0125] 本実施の形態におけるかさ上げ部形成工程は、第 1のパッドの表面にバリアメタル 層を形成する工程と、バリアメタル層の表面にレジスト層を配置する工程と、レジスト 層の第 1のパッドの部分に開口部を形成する工程と、電解めつき法によって、開口部 に導電部としての Auバンプを形成する工程とを含む。さらに、レジスト層を除去する 工程と、導電部が形成されている領域を避けた領域においてバリアメタル層を除去す る工程とを含む。この方法を採用することにより、容易に力、さ上げ部を形成することが できる。また、電解めつき法において、印加する電圧の大きさや金属が析出する時間 などを調整することにより、容易にかさ上げ部の高さを調整することができる。  [0125] The raised portion forming step in the present embodiment includes a step of forming a barrier metal layer on the surface of the first pad, a step of disposing a resist layer on the surface of the barrier metal layer, and a step of forming the first layer of the resist layer. Forming an opening in the portion of the pad, and forming an Au bump as a conductive portion in the opening by an electrolytic plating method. Further, the method includes a step of removing the resist layer and a step of removing the barrier metal layer in a region other than a region where the conductive portion is formed. By employing this method, the force and the raised portion can be easily formed. In addition, in the electroplating method, the height of the raised portion can be easily adjusted by adjusting the magnitude of the applied voltage and the time during which the metal is deposited.
[0126] また、本実施の形態においては、アンダーフィル樹脂配置工程は、第 1の部材と第 2の部材とを結合した後に、第 1の部材と第 2の部材との間隙に樹脂を配置する工程 を含む。この方法を採用することにより、容易に第 1の部材と第 2の部材との間に樹脂 を配置することができる。  Further, in the present embodiment, in the underfill resin arranging step, after the first member and the second member are joined, the resin is arranged in a gap between the first member and the second member. Performing the step. By employing this method, the resin can be easily arranged between the first member and the second member.
[0127] 本実施の形態においては、金線を接続するためのパッドと、半導体チップを接続す るためのパッドとの両方のパッドに対して力さ上げ部を形成した力 この形態に限られ ず、金線を接続するためのパッドにかさ上げ部が形成されていればよい。たとえば、 図 22を参照して、半導体チップ 51を接続するためのパッド 65に対して金バンプを配 置して、第 1の部材と第 2の部材とを接続固定しても構わない。  [0127] In the present embodiment, the force in which the force-raising portion is formed on both the pad for connecting the gold wire and the pad for connecting the semiconductor chip is limited to this mode. Instead, it is only necessary that the pad for connecting the gold wire has a raised portion. For example, referring to FIG. 22, gold bumps may be arranged on pads 65 for connecting semiconductor chip 51, and the first member and the second member may be connected and fixed.
[0128] その他の構成、作用、効果および製造方法については、実施の形態 1と同様である のでここでは説明を繰り返さない。 [0128] Other configurations, operations, effects, and manufacturing methods are the same as those in the first embodiment, and therefore, description thereof will not be repeated here.
[0129] (実施の形態 5) (Embodiment 5)
図 35から図 40を参照して、本発明に基づく実施の形態 5における半導体装置およ び半導体装置の製造方法について説明する。 [0130] 図 35は、本実施の形態における半導体装置の概略断面図である。本実施の形態 における半導体装置においては、力さ上げ部の構成および第 1の部材と第 2の部材 との接続部分が、実施の形態 4における半導体装置と異なる。 Referring to FIGS. 35 to 40, a semiconductor device and a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention will be described. FIG. 35 is a schematic cross-sectional view of the semiconductor device according to the present embodiment. The semiconductor device according to the present embodiment is different from the semiconductor device according to the fourth embodiment in the configuration of the force raising portion and the connection between the first member and the second member.
[0131] 本実施の形態における半導体装置は、力、さ上げ部が金ボールで形成されている。  [0131] In the semiconductor device according to the present embodiment, the force and the raised portion are formed of gold balls.
すなわち、第 1の部材としての半導体チップ 52のパッド 64の表面に、ほぼ球状のかさ 上げ部 75が形成されている。力、さ上げ部 75には、金線 61の金ボール部 71が接合さ れている。力 ^上げ部 75および金ボール部 71は一体的になっている。  That is, a substantially spherical raised portion 75 is formed on the surface of the pad 64 of the semiconductor chip 52 as the first member. The gold ball portion 71 of the gold wire 61 is joined to the force / raising portion 75. The force raising portion 75 and the gold ball portion 71 are integrated.
[0132] また、半導体チップ 51と半導体チップ 52との接続部分においては、半導体チップ 5 1のパッド 63の表面にバリアメタル層 79が形成され、ノ リアメタル層 79の表面に、 Au バンプ 80が形成されている。半導体チップ 52の表面に形成されたパッド 65は、 Au バンプ 80と結合している。  At the connection between the semiconductor chip 51 and the semiconductor chip 52, a barrier metal layer 79 is formed on the surface of the pad 63 of the semiconductor chip 51, and an Au bump 80 is formed on the surface of the nodal metal layer 79. Have been. The pad 65 formed on the surface of the semiconductor chip 52 is bonded to the Au bump 80.
[0133] このように、本実施の形態における半導体装置は、かさ上げ部が球状に形成されて いる。この構成を採用することにより、力さ上げ部を公知のワイヤボンディング装置を 用いて容易に形成することができる。  As described above, in the semiconductor device according to the present embodiment, the raised portion is formed in a spherical shape. By employing this configuration, the force increasing portion can be easily formed using a known wire bonding apparatus.
[0134] 次に、図 36から図 40を参照して、本実施の形態における半導体装置の製造方法 について説明する。図 36から図 40はそれぞれの製造工程における概略断面図であ る。  Next, a method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. 36 to 40 are schematic cross-sectional views in respective manufacturing steps.
[0135] 図 36に示すように、半導体基板 58の表面にパッド 64, 65を形成した後に、ポリイミ ド膜 55を形成する。次に、力さ上げ部を形成するかさ上げ部形成工程を行なう。  As shown in FIG. 36, after forming pads 64 and 65 on the surface of a semiconductor substrate 58, a polyimide film 55 is formed. Next, a step of forming a raised portion is performed.
[0136] 図 37に示すように、ワイヤボンディング装置を用いて、パッド 64の表面にかさ上げ 部 75を形成する。力さ上げ部 75は導電性を有するボール (球）である。本実施の形 態においては、金で形成されている。力、さ上げ部 75の形成においては、ワイヤボン デイング装置のキヤビラリ 85から、少量の金を排出して金ボール部を形成したのちに 、パッド 64の表面に金ボール部を接合する。金ボール部を接合した後に、矢印 95ま たは矢印 95に垂直な方向にキヤビラリ 85を移動することにより金を切断する。本実施 の形態におけるかさ上げ部 75は、スタッドバンプを形成する方法と同様の方法で形 成すること力 Sできる。それぞれのパッド 64の表面に、 1個ずつかさ上げ部 75を形成す る。 [0137] 次に、図 38を参照して、ダイシングにより、半導体基板を切断して個々の半導体チ ップ 52への断片化を行なう。次に、半導体チップ 52を、配線基板 81に接着材 91を 用いて固定する。 As shown in FIG. 37, a raised portion 75 is formed on the surface of the pad 64 by using a wire bonding apparatus. The lifting portion 75 is a conductive ball (ball). In the present embodiment, it is formed of gold. In forming the force-raising portion 75, a small amount of gold is discharged from the cavities 85 of the wire bonding apparatus to form a gold ball portion, and then the gold ball portion is bonded to the surface of the pad 64. After joining the gold balls, the gold is cut by moving the cabillary 85 in the direction perpendicular to arrow 95 or arrow 95. The raised portion 75 in the present embodiment can be formed by a method similar to the method of forming a stud bump. One raised portion 75 is formed on the surface of each pad 64. Next, referring to FIG. 38, the semiconductor substrate is cut by dicing to fragment into individual semiconductor chips 52. Next, the semiconductor chip 52 is fixed to the wiring board 81 using an adhesive 91.
[0138] また、別の製造工程において、半導体チップ 51を製造する。半導体チップ 51の表 面にパッド 63を形成して、電解めつき法などの方法によりパッド 63の表面に、バリアメ タル層 79および Auバンプ 80を形成する。次に、矢印 98に示すように、超音波を印 加しながら熱圧着を行なうことによって、 Auバンプ 80とパッド 65とを接合する。  In another manufacturing process, the semiconductor chip 51 is manufactured. A pad 63 is formed on the surface of the semiconductor chip 51, and a barrier metal layer 79 and an Au bump 80 are formed on the surface of the pad 63 by a method such as electrolytic plating. Next, as shown by an arrow 98, the Au bump 80 and the pad 65 are joined by thermocompression bonding while applying ultrasonic waves.
[0139] 次に、図 39に示すように、半導体チップ 51と半導体チップ 52との間にアンダーフィ ル樹脂の配置を行なうアンダーフィル樹脂配置工程を行なう。アンダーフィル樹脂 92 が外側に向かって流れることがある力 力、さ上げ部 75が形成されていることにより、か さ上げ部 75の金線が接続される部分がアンダーフィル樹脂 92によって汚染されるこ とを防止できる。  Next, as shown in FIG. 39, an underfill resin disposing step of disposing an underfill resin between the semiconductor chip 51 and the semiconductor chip 52 is performed. Because the underfill resin 92 may flow outward, the raised portion 75 is formed, and the portion of the raised portion 75 to which the gold wire is connected is contaminated by the underfill resin 92. This can be prevented.
[0140] 次に、図 40に示すように、力さ上げ部 75と配線基板 81に形成されたランド 84との 電気的な接続を行なう。たとえば、ワイヤボンディング装置を用いて、キヤビラリの先 端に金ボール部 71を形成する。次に、金ボール部 71で力さ上げ部 75の上面を押さ えて、力さ上げ部 75の上面を平坦にするレべリングを行ないながら、金ボール部 71と 力さ上げ部 75との熱圧着を行なう。金線 61の金ボール部 71と反対側の端部は、ラン ド 84に接続する。この後に、樹脂封止などを行なって、本実施の形態における半導 体装置を製造することができる。  Next, as shown in FIG. 40, an electrical connection is made between the force raising portion 75 and the lands 84 formed on the wiring board 81. For example, a gold ball portion 71 is formed at the tip of the cavities by using a wire bonding apparatus. Next, the upper surface of the lifting portion 75 is pressed by the gold ball portion 71, and while the upper surface of the lifting portion 75 is leveled, the heat between the gold ball portion 71 and the lifting portion 75 is heated. Perform crimping. The other end of the gold wire 61 opposite to the gold ball portion 71 is connected to the land 84. Thereafter, the semiconductor device according to the present embodiment can be manufactured by performing resin sealing or the like.
[0141] 本実施の形態においては、ワイヤボンディング装置を用いて、外部への接続線を接 続するための第 1のパッドの表面に金ボールを配置する工程を含む。この方法を採 用することにより、容易にかさ上げ部を形成することができる。また、安価にかさ上げ 部を形成することができる。  [0141] The present embodiment includes a step of arranging a gold ball on the surface of the first pad for connecting an external connection line using a wire bonding apparatus. By employing this method, the raised portion can be easily formed. Further, the raised portion can be formed at low cost.
[0142] 本実施の形態においては、第 2の部材としての半導体チップ 51のパッド 63の表面 に、ノ リアメタル層 79および Auバンプ 80を形成した力 特にこの形態に限られず、 任意の接続方法で、半導体チップ 51と半導体チップ 52との電気的な接続を行なうこ とができる。  [0142] In the present embodiment, the force of forming the nori- tal metal layer 79 and the Au bump 80 on the surface of the pad 63 of the semiconductor chip 51 as the second member is not particularly limited to this form, but may be any connection method. In addition, the semiconductor chip 51 and the semiconductor chip 52 can be electrically connected.
[0143] たとえば、半導体チップ 51のパッド 63の表面にワイヤボンディング装置によって Au バンプを形成しても構わない。この方法を採用することにより、安価に第 1の部材とし ての半導体チップと第 2の部材としての半導体チップとを接続固定することができる。 し力 ながら、半導体チップ 51におけるパッド 63同士のピッチが小さい場合には、電 解めつき法によって Auバンプを形成することが好ましレ、。たとえば、半導体チップ 51 に複数のパッド 63が形成されている場合、ワイヤボンディング装置を用いてそれぞれ のパッドに 1個ずつバンプを形成するよりも、めっき法でバンプを形成した方が効率 力 い場合がある。 [0143] For example, the surface of the pad 63 of the semiconductor chip 51 is Au A bump may be formed. By employing this method, the semiconductor chip as the first member and the semiconductor chip as the second member can be connected and fixed at low cost. However, when the pitch between the pads 63 of the semiconductor chip 51 is small, it is preferable to form the Au bumps by the electrolysis method. For example, when a plurality of pads 63 are formed on a semiconductor chip 51, it is more efficient to form bumps by plating than to form one bump on each pad using a wire bonding apparatus. There is.
[0144] その他の構成、作用、効果および製造方法については、実施の形態 4と同様である のでここでは説明を繰り返さない。  [0144] Other configurations, operations, effects, and manufacturing methods are the same as those of the fourth embodiment, and therefore, description thereof will not be repeated here.
[0145] (実施の形態 6)  (Embodiment 6)
図 41から図 45を参照して、本発明に基づく実施の形態 6における半導体装置の製 造方法について説明する。  With reference to FIGS. 41 to 45, a method of manufacturing a semiconductor device according to the sixth embodiment of the present invention will be described.
[0146] 図 41は、本実施の形態における第 1の半導体装置の製造方法の概略断面図であ る。第 1の製造方法においては、ペースト状接着材（NCP : Non Conductive Paste)を アンダーフィル樹脂として用いる。 NCP88の配置においては、第 1の部材としての半 導体チップ 52と、第 2の部材としての半導体チップ 51とが、互いに結合固定される前 に配置する。図 41に示す例においては、半導体チップ 52の表面のパッド 64, 65の 表面に、力さ上げ部 74a, 74bが配置されている。  FIG. 41 is a schematic cross-sectional view of the first semiconductor device manufacturing method according to the present embodiment. In the first manufacturing method, a paste adhesive (NCP: Non Conductive Paste) is used as the underfill resin. In the arrangement of the NCP 88, the semiconductor chip 52 as the first member and the semiconductor chip 51 as the second member are arranged before they are fixed to each other. In the example shown in FIG. 41, the force increasing portions 74a and 74b are arranged on the surfaces of the pads 64 and 65 on the surface of the semiconductor chip 52.
[0147] 本実施の形態においては、力さ上げ部 74aおよび 74bを形成した後に NCPを半導 体チップ 52に配置する NCP配置工程を行なう。この後に、矢印 93に示すように、超 音波を印加しながら熱圧着を行なうことによって、パッド 63とかさ上げ部 74bとの接合 を行なう。このように、 NCP配置工程の後に、第 1の部材と第 2の部材とを結合するェ 程を行なう。  In the present embodiment, an NCP arranging step of arranging NCPs on semiconductor chip 52 after forming force-raising portions 74a and 74b is performed. Thereafter, as shown by arrow 93, the pad 63 and the raised portion 74b are joined by thermocompression bonding while applying ultrasonic waves. As described above, after the NCP arranging step, the step of connecting the first member and the second member is performed.
[0148] 図 42に、本実施の形態における第 2の半導体装置の製造方法の概略断面図を示 す。第 2の半導体装置の製造方法においては、アンダーフィル樹脂としてフィルム状 接着材（NCF : Non Conductive Film)を用いている。  FIG. 42 shows a schematic cross-sectional view of the method for manufacturing the second semiconductor device in the present embodiment. In the second method for manufacturing a semiconductor device, a film adhesive (NCF: Non Conductive Film) is used as the underfill resin.
[0149] 図 42に示すように、第 2の部材としての半導体チップ 51の表面にパッド 63およびポ リイミド膜 56を形成した後に、 NCF89を配置する NCF配置工程を行なう。 NCF配置 工程においては、予め熱圧着によって NCFを半導体チップ 51に接合しておく。第 1 の部材としての半導体チップ 52のパッド 64, 65の表面には、力さ上げ部 74a, 74b を形成する。次に、矢印 94に示すように、超音波を印加しながら熱圧着を行なうこと により、力、さ上げ部 74bとパッド 63との接合を行なう。このように、 NCF配置工程の後 に第 1の部材と第 2の部材とを結合する工程を行なう。 As shown in FIG. 42, after forming the pad 63 and the polyimide film 56 on the surface of the semiconductor chip 51 as the second member, an NCF arranging step of arranging the NCF 89 is performed. NCF placement In the process, the NCF is bonded to the semiconductor chip 51 by thermocompression in advance. Strengthening portions 74a, 74b are formed on the surfaces of the pads 64, 65 of the semiconductor chip 52 as the first member. Next, as shown by an arrow 94, the force and the raised portion 74b and the pad 63 are joined by performing thermocompression bonding while applying ultrasonic waves. As described above, after the NCF arranging step, the step of connecting the first member and the second member is performed.
[0150] 本実施の形態における第 1の半導体装置の製造方法において用いる NCPは、ぺ 一スト状であり常温では粘度の高い状態である。また、第 2の半導体装置の製造方法 において用いる NCFはフィルム状である。し力 ながら、半導体チップ同士を熱圧着 する際に、 NCPまたは NCFは、半導体チップ同士を接合する際の熱によって、粘度 力 、さくなつて半導体チップの外側に向かって流れることがある。この場合において も、外部との接続を行なうためのパッドにかさ上げ部を形成することにより、接続線を 接合する部分の汚染を防止でき、接続線との良好な接続を行なうことができる。  [0150] The NCP used in the first method for manufacturing a semiconductor device in the present embodiment has a simple shape and a high viscosity at room temperature. The NCF used in the second method for manufacturing a semiconductor device is in the form of a film. However, when the semiconductor chips are thermocompression-bonded to each other, the NCP or NCF may flow toward the outside of the semiconductor chip due to the viscous force due to the heat at the time of joining the semiconductor chips. Also in this case, by forming the raised portion on the pad for making a connection with the outside, contamination at the portion where the connection line is joined can be prevented, and a good connection with the connection line can be made.
[0151] 図 43から図 45に、本実施の形態における第 3の製造方法の説明図を示す。図 43 および図 44は、本実施の形態における第 3の半導体装置の製造方法の工程を説明 する概略断面図であり、図 45は、製造された半導体装置の一部分の拡大平面図で ある。  FIGS. 43 to 45 show explanatory views of the third manufacturing method according to the present embodiment. 43 and 44 are schematic cross-sectional views illustrating steps of a third method of manufacturing a semiconductor device according to the present embodiment. FIG. 45 is an enlarged plan view of a part of the manufactured semiconductor device.
[0152] 図 43を参照して、本実施の形態における第 3の半導体装置の製造方法において は、力さ上げ部 75と配線基板 81のランド 84とを金線 61によって接続した後に、半導 体チップ 51と半導体チップ 52とを接続固定する。  Referring to FIG. 43, in the third method of manufacturing a semiconductor device according to the present embodiment, after connecting force-increasing portion 75 and land 84 of wiring board 81 by gold wire 61, The body chip 51 and the semiconductor chip 52 are connected and fixed.
[0153] 矢印 99に示すように、超音波を印加しながら熱圧着を行なって、半導体チップ 51 に形成された Auバンプ 80と、半導体チップ 52に形成されたパッド 65とを接合する。  [0153] As shown by an arrow 99, thermocompression bonding is performed while applying ultrasonic waves to join the Au bumps 80 formed on the semiconductor chip 51 and the pads 65 formed on the semiconductor chip 52.
[0154] 次に、図 44に示すように、アンダーフィル樹脂 92の配置を行なう。矢印 100に示す ように、半導体チップ 51とかさ上げ部 75との間の領域にアンダーフィル樹脂 92を配 置する。アンダーフィル樹脂 92を供給ノズル 86から押し出して配置する。  Next, as shown in FIG. 44, the underfill resin 92 is arranged. As shown by an arrow 100, an underfill resin 92 is disposed in a region between the semiconductor chip 51 and the raised portion 75. The underfill resin 92 is pushed out of the supply nozzle 86 and arranged.
[0155] 図 45は、製造される半導体装置のコーナ部の拡大概略配置図である。矢印 100に 示す半導体チップ 51とかさ上げ部 75との間の領域において、矢印 96に示すように 半導体チップ 51の外縁に沿う向きに移動しながら、連続的にアンダーフィル樹脂 92 を配置する。 [0156] 図 44を参照して、半導体チップ 51とかさ上げ部 75との距離が近い場合には、金線 61や半導体チップ 51の表面のうち半導体チップ 52が配置されている側と反対側の 表面に、アンダーフィル樹脂 92が付着することがある。後の製造工程で封止樹脂に よって、金線 61や半導体チップ 51を封止するが、このときに、アンダーフィル樹脂 92 が金線や半導体チップ 51の一方の表面に付着していると、付着した部分が封止樹 脂との界面になって封止樹脂が剥離しやすくなる。このため、アンダーフィル樹脂は 、金線などに付着しないことが好ましい。 FIG. 45 is an enlarged schematic layout view of a corner portion of a manufactured semiconductor device. In a region between the semiconductor chip 51 indicated by an arrow 100 and the raised portion 75, the underfill resin 92 is continuously arranged while moving in a direction along the outer edge of the semiconductor chip 51 as indicated by an arrow 96. Referring to FIG. 44, when the distance between semiconductor chip 51 and raising portion 75 is short, the opposite side of gold wire 61 or the surface of semiconductor chip 51 opposite to the side on which semiconductor chip 52 is arranged is provided. The underfill resin 92 may adhere to the surface of the substrate. In a later manufacturing process, the gold wire 61 and the semiconductor chip 51 are sealed with a sealing resin. At this time, if the underfill resin 92 is attached to one surface of the gold wire or the semiconductor chip 51, The adhered portion becomes an interface with the sealing resin, and the sealing resin is easily peeled off. For this reason, it is preferable that the underfill resin does not adhere to the gold wire or the like.
[0157] し力、しながら、図 44に示すように、矢印 100に示す第 2の部材としての半導体チッ プ 51とかさ上げ部 75との距離が小さいと、アンダーフィル樹脂 92が金線 61などに付 着しやすくなる。このような場合においても、アンダーフィル樹脂として、 NCPや NCF を用いることにより、金線などにアンダーフィル樹脂が付着することをより確実に防止 すること力 Sできる。  As shown in FIG. 44, while the distance between the semiconductor chip 51 as the second member and the raising portion 75 as shown by the arrow 100 is small, as shown in FIG. It becomes easier to attach to Even in such a case, by using NCP or NCF as the underfill resin, it is possible to more reliably prevent the underfill resin from adhering to a gold wire or the like.
[0158] その他の製造方法については、実施の形態 4および 5と同様であるので、ここでの 説明を繰り返さない。なお、上記の実施の形態における図において、同一の部分ま たは互いに相当する部分にぉレ、ては、同一の符号を付して説明を省略してレ、る。  [0158] Other manufacturing methods are the same as those of the fourth and fifth embodiments, and thus description thereof will not be repeated. In the drawings of the above-described embodiment, the same portions or portions corresponding to each other will be denoted by the same reference numerals, and description thereof will be omitted.
[0159] なお、今回開示した上記実施の形態はすべての点で例示であつて制限的なもので はない。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求 の範囲と均等の意味および範囲内でのすべての変更を含むものである。  [0159] The above embodiments disclosed this time are illustrative in all aspects and are not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and includes any modifications within the scope and meaning equivalent to the terms of the claims.
産業上の利用可能性  Industrial applicability
[0160] 本発明は、半導体装置に適用されうる。特に、半導体チップを基板などにフリツプチ ップ接合した半導体装置に有利に適用されうる。 The present invention can be applied to a semiconductor device. In particular, the present invention can be advantageously applied to a semiconductor device in which a semiconductor chip is flip-chip bonded to a substrate or the like.

Claims

請求の範囲 The scope of the claims
[1] 第 1の部材（2， 4, 21 , 31)と、 [1] a first member (2, 4, 21, 31);
表面同士が互いに略平行になるように、間隙を空けて前記第 1の部材（2， 4, 21 , 31)に固定された第 2の部材（1)と、  A second member (1) fixed to the first member (2, 4, 21, 31) with a gap so that the surfaces are substantially parallel to each other;
前記間隙に充填されたアンダーフィル樹脂（20， 88， 89, 92)と  Underfill resin (20, 88, 89, 92) filled in the gap and
を備え、  With
前記第 1の部材（2， 4, 21 , 31)において、前記第 2の部材（1)を前記第 1の部材（ 2, 4, 21, 31)に投影した領域の外側に、凹部（6, 7, 9, 10, 27, 28)が形成された 、半導体装置。  In the first member (2, 4, 21, 31), a concave portion (6) is formed outside a region where the second member (1) is projected on the first member (2, 4, 21, 31). , 7, 9, 10, 27, 28).
[2] 前記凹部（6, 10， 27， 28)は、溝状に形成され、前記投影した領域の周りを取り囲 むように形成されてレ、る、請求項 1に記載の半導体装置。  [2] The semiconductor device according to claim 1, wherein the concave portion (6, 10, 27, 28) is formed in a groove shape and formed so as to surround the projected area.
[3] 前記凹部（6, 7， 9， 27, 28)は、前記第 1の部材（2， 4， 21 , 31)を貫通する貫通 孔（5, 8)と、前記貫通孔（5, 8)の一方の開口部を封止するように形成された蓋（17 , 18, 25， 35)とを含む、請求項 1に記載の半導体装置。 [3] The recesses (6, 7, 9, 27, 28) are provided with through holes (5, 8) passing through the first member (2, 4, 21, 31) and the through holes (5, 8). 2. The semiconductor device according to claim 1, further comprising a lid (17, 18, 25, 35) formed so as to seal one opening of (8).
[4] 前記第 1の部材（2， 4, 21 , 31)は、半導体チップ（2, 4， 21)または有機基板（31 )のいずれか一方を含み、 [4] The first member (2, 4, 21, 31) includes one of a semiconductor chip (2, 4, 21) and an organic substrate (31),
前記第 2の部材（1)は、半導体チップ（1)を含む、請求項 1に記載の半導体装置。  The semiconductor device according to claim 1, wherein the second member (1) includes a semiconductor chip (1).
[5] 第 1の部材（2， 4, 21 , 31)と、 [5] a first member (2, 4, 21, 31);
表面同士が互いに略平行になるように、間隙を空けて前記第 1の部材（2， 4, 21 , 31)に固定された第 2の部材（1)と、  A second member (1) fixed to the first member (2, 4, 21, 31) with a gap so that the surfaces are substantially parallel to each other;
前記間隙に充填されたアンダーフィル樹脂（20， 88， 89, 92)と  Underfill resin (20, 88, 89, 92) filled in the gap and
を備え、  With
前記第 1の部材（2， 4, 21 , 31)において、前記第 2の部材（1)を前記第 1の部材（ 2, 4, 21, 31)に投影した領域の外側に、前記領域を取り囲むように前記第 1の部材 (2, 4, 21， 31)を貫通する貫通孔（5, 8)が形成された、半導体装置。  In the first member (2, 4, 21, 31), the region is set outside the region where the second member (1) is projected on the first member (2, 4, 21, 31). A semiconductor device, wherein a through hole (5, 8) penetrating the first member (2, 4, 21, 31) is formed so as to surround the first member.
[6] 前記第 1の部材（2， 4, 21 , 31)は、半導体チップ（2, 4， 21)または有機基板（31 )のいずれか一方を含み、 [6] The first member (2, 4, 21, 31) includes either a semiconductor chip (2, 4, 21, 21) or an organic substrate (31),
前記第 2の部材（1)は、半導体チップ（1)を含む、請求項 5に記載の半導体装置。 The semiconductor device according to claim 5, wherein the second member (1) includes a semiconductor chip (1).
[7] 第 1の部材（2, 4, 21 , 31)と、 [7] a first member (2, 4, 21, 31);
表面同士が互いに略平行になるように、間隙を空けて前記第 1の部材（2， 4, 21 , 31)に固定された第 2の部材（1)と、  A second member (1) fixed to the first member (2, 4, 21, 31) with a gap so that the surfaces are substantially parallel to each other;
前記間隙に充填されたアンダーフィル樹脂（20， 88， 89, 92)と  Underfill resin (20, 88, 89, 92) filled in the gap and
を備え、  With
前記第 1の部材（2， 4, 21 , 31)において、前記第 2の部材（1)を前記第 1の部材（ 2, 4, 21, 31)に投影した領域の外側に、前記第 1の部材（2, 4, 21, 31)を保護す るための保護膜（19)が形成され、  In the first member (2, 4, 21, 31), the first member (2, 4, 21, 31, 31) is positioned outside the region projected onto the first member (2, 4, 21, 31). A protective film (19) for protecting the members (2, 4, 21, 31) is formed,
前記保護膜（19)は、前記第 1の部材（2， 4， 21 , 31)の表面から突出して、堰にな るように形成された、半導体装置。  The semiconductor device, wherein the protective film (19) is formed so as to protrude from the surface of the first member (2, 4, 21, 31) to be a weir.
[8] 前記保護膜（19)は、前記第 1の部材 (2， 4， 21 , 31)を投影した領域を取り囲むよ うに形成された、請求項 7に記載の半導体装置。 [8] The semiconductor device according to claim 7, wherein the protective film (19) is formed so as to surround a region where the first member (2, 4, 21, 31) is projected.
[9] 前記第 1の部材（2， 4, 21 , 31)は、半導体チップ（2, 4， 21)または有機基板（31 )のいずれか一方を含み、 [9] The first member (2, 4, 21, 31) includes one of a semiconductor chip (2, 4, 21, 21) and an organic substrate (31),
前記第 2の部材（1)は、半導体チップ（1)を含む、請求項 7に記載の半導体装置。  The semiconductor device according to claim 7, wherein the second member (1) includes a semiconductor chip (1).
[10] 第 1の部材 (52)と、 [10] a first member (52);
表面同士が互いに略平行になるように、間隙を空けて前記第 1の部材（52)に固定 された第 2の部材（51)と、  A second member (51) fixed to the first member (52) with a gap so that the surfaces are substantially parallel to each other;
前記間隙に配置されたアンダーフィル樹脂（20, 88, 89, 92)と  An underfill resin (20, 88, 89, 92) disposed in the gap;
を備える半導体装置の製造方法において、  In a method for manufacturing a semiconductor device comprising:
前記第 2の部材（51)の表面において、前記第 1の部材が配置されるべき領域の外 側に第 1のパッド（64)を形成する工程と、  Forming a first pad (64) on a surface of the second member (51) outside a region where the first member is to be arranged;
前記第 2の部材（51)の表面において、前記第 1の部材（52)を接続するための第 2 のパッド（65)を形成する工程と、  Forming a second pad (65) on the surface of the second member (51) for connecting the first member (52);
前記第 1のパッド（64)の表面に導電性部材を配置して力、さ上げ部（74a， 75)を形 成するかさ上げ部形成工程と、  A raised part forming step of forming a raised part (74a, 75) by disposing a conductive member on the surface of the first pad (64);
前記力、さ上げ部形成工程の後に、前記第 1の部材（52)と前記第 2の部材（51)との 間に前記アンダーフィル樹脂（20, 92, 88， 89)を配置するアンダーフィル樹脂配置 工程と An underfill for disposing the underfill resin (20, 92, 88, 89) between the first member (52) and the second member (51) after the step of forming the force and the raised portion; Resin arrangement Process and
を含む、半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
[11] 前記力さ上げ部形成工程は、前記第 1のパッド（64)の表面にバリアメタル層（72，  [11] In the step of forming a force raising portion, the barrier metal layer (72,
72b)を形成する工程と、  Forming 72b);
前記バリアメタル層（72, 72b)の表面にレジスト層（77)を配置する工程と、 前記レジスト層（77)の前記第 1のパッド（64)の部分に開口部（78)を形成するェ 程と、  Disposing a resist layer (77) on the surface of the barrier metal layer (72, 72b); and forming an opening (78) in the portion of the resist layer (77) at the first pad (64). About
電界めつき法によって前記開口部（78)に導電部（73a)を形成する工程と、 前記レジスト層（77)を除去する工程と、  Forming a conductive portion (73a) in the opening (78) by an electric field plating method; and removing the resist layer (77);
前記導電部（73a)が形成されている領域を避けた領域において、前記ノ リアメタル 層（72)を除去する工程と  Removing the nori metal layer (72) in a region other than the region where the conductive portion (73a) is formed;
を含む、請求項 10に記載の半導体装置の製造方法。  11. The method for manufacturing a semiconductor device according to claim 10, comprising:
[12] 前記力さ上げ部形成工程は、ワイヤボンディング装置を用いて、前記第 1のパッド（ [12] In the step of forming a force-raising portion, the first pad (
64)の表面に導電性ボール（75)を配置する工程を含む、請求項 10に記載の半導 体装置の製造方法。  11. The method for manufacturing a semiconductor device according to claim 10, comprising a step of disposing conductive balls (75) on the surface of (64).
[13] 前記アンダーフィル樹脂配置工程は、前記第 1の部材（52)と前記第 2の部材（51) とを結合した後に、前記隙間にアンダーフィル樹脂（20， 88, 89， 92)を配置するェ 程を含む、請求項 10に記載の半導体装置の製造方法。  [13] In the underfill resin disposing step, after the first member (52) and the second member (51) are combined, the underfill resin (20, 88, 89, 92) is filled in the gap. 11. The method for manufacturing a semiconductor device according to claim 10, including a step of disposing.
[14] 前記アンダーフィル樹脂配置工程は、前記第 2の部材（51)の表面にペースト状接 着材（88)を配置する NCP配置工程と、 [14] The underfill resin disposing step includes an NCP disposing step of disposing a paste-like adhesive (88) on the surface of the second member (51).
前記 NCP配置工程の後に、前記第 1の部材（52)と前記第 2の部材（51)とを結合 する工程と  Joining the first member (52) and the second member (51) after the NCP arranging step;
を含む、請求項 10に記載の半導体装置の製造方法。  11. The method for manufacturing a semiconductor device according to claim 10, comprising:
[15] 前記アンダーフィル樹脂配置工程は、前記第 1の部材（52)の表面にフィルム状接 着材（89)を配置する NCF配置工程と、 [15] The underfill resin arranging step is an NCF arranging step of arranging a film adhesive (89) on the surface of the first member (52).
前記 NCF配置工程の後に、前記第 1の部材（52)と前記第 2の部材（51)とを結合 する工程と  Joining the first member (52) and the second member (51) after the NCF disposing step;
を含む、請求項 10に記載の半導体装置の製造方法。  11. The method for manufacturing a semiconductor device according to claim 10, comprising:
PCT/JP2005/000905 2004-02-05 2005-01-25 Semiconductor device and method for manufacturing semiconductor device WO2005076352A1 (en)

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