JP2010034590A - Semiconductor device and method of mounting the same - Google Patents

Semiconductor device and method of mounting the same Download PDF

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JP2010034590A
JP2010034590A JP2009256088A JP2009256088A JP2010034590A JP 2010034590 A JP2010034590 A JP 2010034590A JP 2009256088 A JP2009256088 A JP 2009256088A JP 2009256088 A JP2009256088 A JP 2009256088A JP 2010034590 A JP2010034590 A JP 2010034590A
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circuit board
semiconductor element
sealing resin
semiconductor device
resin
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JP5230580B2 (en
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Eishin Nishikawa
英信 西川
Kazuto Nishida
一人 西田
Kazumichi Shimizu
一路 清水
Kentaro Kumazawa
謙太郎 熊澤
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Panasonic Corp
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Panasonic Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents breakage of a mounted part by rapid volume expansion of absorbed moisture and suppresses loads to bonded parts of the semiconductor device. <P>SOLUTION: The semiconductor device is constructed such that a semiconductor chip 1 and a circuit board 3 are electrically connected via bumps 2 formed on the electrodes of the semiconductor chip 1 and via wiring 4 formed on the circuit board 3, while a sealing resin 5 is interposed between the semiconductor chip 1 and the circuit board 3. A structure capable of reducing stresses caused by the absorbed moisture contained in the sealing resin 5 is constructed by through-holes 21 formed in the circuit board 3, wherein the through-holes 21 are positioned at corners of the semiconductor-chip mounted region 3a of the circuit board 3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、一般電気製品に使用される半導体素子を実装した高品質実装構造を有する半導体装置とその実装方法に関する。   The present invention relates to a semiconductor device having a high-quality mounting structure on which a semiconductor element used for a general electric product is mounted, and a mounting method thereof.

近年、電気製品の小型、薄型化から電子回路基板も小型化が強く望まれている。そして、携帯電話端末をはじめとするモバイル機器は機能の増加が著しく、回路基板のICチップを樹脂モールドされたパッケージでなく裸のまま搭載するフリップチップ実装が強く求められている。   In recent years, downsizing of electronic circuit boards has been strongly demanded from the downsizing and thinning of electrical products. Mobile devices such as mobile phone terminals have a remarkable increase in functions, and there is a strong demand for flip chip mounting in which an IC chip of a circuit board is mounted barely instead of a resin molded package.

このため、様々な半導体素子の実装方法が提案、実用化されており、たとえば液晶モジュールにおけるフレキシブル基板に対するドライバ半導体素子の実装などでは、一般に導電性の粒子を分散させた異方性導電フィルムを半導体素子の実装における封止材として使用する半導体素子の実装方法が多く実用化されてきた。しかしながら、この実装方法では、半導体素子の狭ピッチ進化に対して、接合隣接の絶縁性などの限界が近づきつつあり、また耐湿信頼性の品質の面でも厳しくなってきている。このような問題点に対し、導電粒子を含まない樹脂のフィルムを半導体素子実装における封止材に用いた実装方法が特許文献1に開示されている。   For this reason, various semiconductor element mounting methods have been proposed and put into practical use. For example, in mounting a driver semiconductor element on a flexible substrate in a liquid crystal module, an anisotropic conductive film in which conductive particles are dispersed is generally used as a semiconductor. Many mounting methods of semiconductor elements used as a sealing material in mounting of elements have been put into practical use. However, in this mounting method, the limit of insulation adjacent to the junction is approaching the evolution of the narrow pitch of the semiconductor element, and the quality of moisture resistance reliability is becoming strict. In order to solve such a problem, Patent Document 1 discloses a mounting method in which a resin film containing no conductive particles is used as a sealing material in semiconductor element mounting.

この電子機器の回路基板へICチップを接合する方法について、以下に説明する。図6(a1)(a2)に示すように、ウエハをダイシング装置により分割して半導体素子31を個片化し、この半導体素子31の電極パッド上に、Au線を用いたスタッドバンプ32をそれぞれ形成する。これらスタッドバンプ32の高さは通常70〜80μmである。   A method for bonding the IC chip to the circuit board of the electronic device will be described below. As shown in FIGS. 6A1 and 6A2, the wafer is divided by a dicing apparatus to divide the semiconductor element 31 into individual pieces, and stud bumps 32 using Au wires are formed on the electrode pads of the semiconductor element 31, respectively. To do. The height of these stud bumps 32 is usually 70 to 80 μm.

次に図6(b)に示すように、回路基板33上の半導体素子実装領域に、導電粒子を含まない樹脂シート(封止樹脂)35を置き、圧着ツールを用いて加熱、加圧を行って前記樹脂シート35を回路基板33上に貼り付ける。この時、加熱は樹脂シート35が硬化反応を起こさないで、樹脂シート35の軟化を起こさせ、回路基板33への貼り付けを容易にする温度にすることが必要であり、この時の樹脂シート35の加熱温度は通常60〜100℃で行う。   Next, as shown in FIG. 6B, a resin sheet (sealing resin) 35 not containing conductive particles is placed in the semiconductor element mounting region on the circuit board 33, and heated and pressed using a crimping tool. Then, the resin sheet 35 is stuck on the circuit board 33. At this time, it is necessary to heat the resin sheet 35 without causing a curing reaction, to cause the resin sheet 35 to soften and to be easily attached to the circuit board 33. The heating temperature of 35 is normally 60-100 degreeC.

樹脂シート35上面に貼り付けられたセパレーターと呼ばれるフィルム35aをはがし、図6(c)に示すように、回路基板33上の基板電極34とスタッドバンプ32が接するように半導体素子31を位置合わせして、回路基板33上にマウントする。   The film 35a called a separator attached to the upper surface of the resin sheet 35 is peeled off, and the semiconductor element 31 is aligned so that the substrate electrode 34 on the circuit board 33 and the stud bump 32 are in contact with each other as shown in FIG. Then, it is mounted on the circuit board 33.

図6(d)に示すように、加熱可能な圧着ツール37により、半導体素子31を回路基板33上に加熱、加圧して樹脂シート35の硬化反応を起こさせて圧着する。このときの圧着条件は通常180〜240℃、8〜30秒で行う。   As shown in FIG. 6D, the semiconductor element 31 is heated and pressed on the circuit board 33 by a heatable pressure bonding tool 37 to cause a curing reaction of the resin sheet 35 and pressure bonding. The crimping conditions at this time are usually 180 to 240 ° C. and 8 to 30 seconds.

上記工程により、半導体素子31の実装を容易に短時間に行え、かつ信頼性の高いCSP(チップサイズパッケージ)と呼ばれる半導体パッケージなどが提供されていた。   Through the above process, a semiconductor package called a CSP (chip size package) that can easily mount the semiconductor element 31 in a short time and has high reliability has been provided.

特許第3150347号公報Japanese Patent No. 3150347

しかしながら、上記従来の半導体素子の実装方法は、以下のような問題点を有する。   However, the conventional method for mounting a semiconductor device has the following problems.

一般に、半導体パッケージにおいては、半導体素子を実装した半導体装置を回路基板にはんだ付けリフローする必要がある。しかしながら、半導体装置の封止の機能を有する樹脂シートが吸湿している場合では、はんだ付けリフローの急激な温度上昇によって半導体装置内の吸湿水分が急激に体積膨張を起こし、半導体装置の実装部が破壊されたり、また半導体装置の接合部の品質が低下するという問題が生じる。   In general, in a semiconductor package, it is necessary to solder and reflow a semiconductor device on which a semiconductor element is mounted on a circuit board. However, when the resin sheet having the function of sealing the semiconductor device absorbs moisture, the moisture absorption in the semiconductor device rapidly expands due to the rapid temperature rise of the soldering reflow, and the mounting portion of the semiconductor device becomes There arises a problem that the semiconductor device is broken or the quality of the junction of the semiconductor device is deteriorated.

そのため、従来の対策として、はんだ付け前に、半導体装置の乾燥工程を行うか、または半導体装置の保管時に高精度で湿度管理を行っており、これら乾燥工程および湿度管理が高コスト化の一因となっていた。   Therefore, as a conventional measure, the drying process of the semiconductor device is performed before soldering, or the humidity management is performed with high accuracy when the semiconductor device is stored, and the drying process and the humidity management are a cause of high cost. It was.

本発明は、上記問題点を解決する半導体装置およびその実装方法を提供することを目的とする。   An object of the present invention is to provide a semiconductor device that solves the above-described problems and a mounting method thereof.

請求項1記載の発明は、半導体素子と回路基板とを、前記半導体素子の電極上に形成したバンプと、前記回路基板上に設けた配線とを介して電気的に接合し、前記半導体素子と回路基板の間に封止樹脂を介在させた半導体装置において、前記封止樹脂に含まれる吸湿成分により発生する応力を減少可能な構造が、回路基板に形成された貫通穴により構成され、前記貫通穴の位置が、回路基板の半導体素子実装領域の隅部に形成されたものである。   According to the first aspect of the present invention, a semiconductor element and a circuit board are electrically joined to each other through a bump formed on an electrode of the semiconductor element and a wiring provided on the circuit board. In a semiconductor device in which a sealing resin is interposed between circuit boards, a structure capable of reducing the stress generated by a moisture absorption component contained in the sealing resin is configured by a through hole formed in the circuit board, and the through hole The positions of the holes are formed in the corners of the semiconductor element mounting region of the circuit board.

請求項2記載の発明は、吸湿成分により発生する応力を減少可能な構造が、回路基板に形成された貫通穴により構成され、前記貫通穴の位置が、回路基板の半導体素子実装領域の隣接する2辺から0.6mm以内の隅部に形成されたものである。   According to a second aspect of the present invention, the structure capable of reducing the stress generated by the moisture absorption component is constituted by a through hole formed in the circuit board, and the position of the through hole is adjacent to the semiconductor element mounting region of the circuit board. It is formed at the corner within 0.6 mm from the two sides.

請求項3記載の発明は、貫通穴内に、封止樹脂の漏出を防止する閉塞用樹脂が充填されたものである。   According to the third aspect of the present invention, the through hole is filled with a closing resin for preventing leakage of the sealing resin.

請求項4記載の発明は、半導体素子の実装面と反対の面の貫通穴の開口部が、封止樹脂の漏出を防止する閉塞用シート状樹脂フィルムにより覆われたものである。   According to a fourth aspect of the present invention, the opening of the through hole on the surface opposite to the mounting surface of the semiconductor element is covered with a closing sheet-like resin film that prevents leakage of the sealing resin.

請求項5記載の発明は、半導体素子と回路基板とを、前記半導体素子の電極上に形成したバンプと、前記回路基板上に設けた配線とを介して電気的に接合し、前記半導体素子と回路基板の間に封止樹脂を介在させた半導体装置において、前記封止樹脂に含まれる吸湿成分により発生する応力を減少可能な材質として、封止樹脂の樹脂材料の透湿度が32〜58g/m2の範囲とされたものである。 According to a fifth aspect of the present invention, a semiconductor element and a circuit board are electrically joined to each other through a bump formed on an electrode of the semiconductor element and a wiring provided on the circuit board. In a semiconductor device in which a sealing resin is interposed between circuit boards, the moisture permeability of the resin material of the sealing resin is 32 to 58 g / as a material capable of reducing the stress generated by the moisture absorption component contained in the sealing resin. The range is m 2 .

請求項6記載の発明は、半導体素子と回路基板とを、前記半導体素子の電極上に形成したバンプと、前記回路基板上に設けた配線とを介して電気的に接合し、前記半導体素子と回路基板の間に封止樹脂を介在させた半導体装置において、前記封止樹脂に含まれる吸湿成分により発生する応力を減少可能な材質として、封止樹脂の樹脂材料に添加される無機フィラー量が40〜60w%の範囲とされたものである。   According to a sixth aspect of the present invention, a semiconductor element and a circuit board are electrically joined to each other via a bump formed on an electrode of the semiconductor element and a wiring provided on the circuit board. In a semiconductor device in which a sealing resin is interposed between circuit boards, the amount of inorganic filler added to the resin material of the sealing resin is a material that can reduce the stress generated by the moisture absorption component contained in the sealing resin. The range is 40 to 60 w%.

請求項7記載の発明は、回路基板上に設けた配線上に、封止樹脂を介して半導体素子電極上のバンプを電気的に接合するに際し、回路基板上の半導体素子実装領域の隅部に、貫通穴を形成し、前記半導体素子、回路基板、封止樹脂のいずれかを加熱して封止樹脂に含まれる吸湿水を前記貫通穴から脱湿しつつ前記半導体素子と回路基板とを加圧し、封止樹脂を硬化させて半導体素子のバンプと回路基板の配線とを接合するものである。   According to the seventh aspect of the present invention, when the bump on the semiconductor element electrode is electrically bonded to the wiring provided on the circuit board via the sealing resin, the corner of the semiconductor element mounting region on the circuit board is formed. Forming a through hole, and heating the semiconductor element, the circuit board, or the sealing resin to add the semiconductor element and the circuit board while dehumidifying moisture contained in the sealing resin from the through hole. The sealing resin is cured and the bumps of the semiconductor element are bonded to the wiring of the circuit board.

請求項8記載の発明は、前記貫通穴内に閉塞用樹脂を充填した後、加熱して脱湿しつつ加圧して接合し、前記閉塞用樹脂により封止樹脂の漏出を防止するものである。   According to an eighth aspect of the present invention, after the closing resin is filled in the through hole, heating and dehumidification are performed while applying pressure and bonding, and the sealing resin prevents leakage of the sealing resin.

請求項9記載の発明は、前記半導体素子の実装面に反対の面の貫通穴の開口部を閉塞用シート状樹脂フィルムにより覆った後、加熱して脱湿しつつ加圧して接合し、前記閉塞用シート状樹脂フィルムにより貫通穴からの封止樹脂の漏出を防止するものである。   In the invention according to claim 9, after the opening portion of the through hole on the opposite surface to the mounting surface of the semiconductor element is covered with a closing sheet-like resin film, it is heated and dehumidified to be pressed and bonded, The sealing resin sheet prevents leakage of the sealing resin from the through hole.

請求項10記載の発明は、回路基板上に設けた配線上に、封止樹脂を介して半導体素子電極上のバンプを電気的に接合するに際し、前記封止樹脂の樹脂材料の透湿度を、32g/m2以上で58g/m2以下とし、前記半導体素子、回路基板、封止樹脂のいずれかを加熱して封止樹脂に含まれる吸湿水を脱湿しつつ前記半導体素子と回路基板とを加圧して封止樹脂を硬化させ半導体素子のバンプと回路基板の配線とを接合するものである。 In the invention according to claim 10, when the bumps on the semiconductor element electrode are electrically bonded to the wiring provided on the circuit board through the sealing resin, the moisture permeability of the resin material of the sealing resin is 32 g / m 2 or more and 58 g / m 2 or less, and heating the semiconductor element, the circuit board, or the sealing resin to dehumidify moisture absorbed in the sealing resin, Is applied to cure the sealing resin to bond the bumps of the semiconductor element and the wiring of the circuit board.

請求項11記載の発明は、回路基板上に設けた配線上に、封止樹脂を介して半導体素子電極上のバンプを電気的に接合するに際し、前記封止樹脂の樹脂材料の無機フィラー量を、40〜60w%の範囲とし、前記半導体素子、回路基板、封止樹脂のいずれかを加熱して封止樹脂に含まれる吸湿水を脱湿しつつ前記半導体素子と回路基板とを加圧して封止樹脂を硬化させ半導体素子のバンプと回路基板の配線とを接合するものである。   The invention according to claim 11 is a method of electrically bonding the bumps on the semiconductor element electrodes to the wiring provided on the circuit board through the sealing resin, and the amount of the inorganic filler in the resin material of the sealing resin. The semiconductor element and the circuit board are pressed while heating any one of the semiconductor element, the circuit board, and the sealing resin to dehumidify the moisture absorption water contained in the sealing resin. The sealing resin is cured to bond the bumps of the semiconductor element and the wiring of the circuit board.

請求項12記載の発明は、半導体素子の圧着時の封止樹脂の加熱温度を240〜280℃の範囲としたものである。   In the invention of claim 12, the heating temperature of the sealing resin at the time of pressure bonding of the semiconductor element is in the range of 240 to 280 ° C.

本発明によれば、加熱、加圧接合時に、封止樹脂の吸湿水分が効果的に脱湿されるので、吸湿水分の急激な体積膨張による実装部の破壊や、半導体装置の接合部への負荷を抑制でき、品質を低下させることがない。   According to the present invention, the moisture absorption moisture of the sealing resin is effectively dehumidified at the time of heating and pressure bonding, so that the mounting portion is destroyed due to the rapid volume expansion of moisture absorption moisture, or the semiconductor device is bonded to the junction. The load can be suppressed and the quality is not reduced.

請求項1、2または7記載の発明によれば、はんだ付けリフロー時に吸湿水分の急激な膨張により破壊されやすい半導体素子の隅部に対応する実装領域の隅部に貫通穴を形成することにより、封止樹脂からの脱湿を効果的に行うことができ、回路基板の実装部が破壊されるのを未然に防止することができる。   According to the invention of claim 1, 2 or 7, by forming a through hole in the corner of the mounting region corresponding to the corner of the semiconductor element that is easily destroyed by rapid expansion of moisture absorption during soldering reflow, Dehumidification from the sealing resin can be performed effectively, and the mounting portion of the circuit board can be prevented from being destroyed.

請求項3または8記載の発明によれば、はんだ付けリフロー時に、閉塞用樹脂により、貫通穴から封止樹脂が外部に漏出するのを防止することができる。   According to invention of Claim 3 or 8, it can prevent that sealing resin leaks outside from a through-hole by the resin for obstruction | occlusion at the time of soldering reflow.

請求項4または9記載の発明によれば、はんだ付けリフロー時に、閉塞用シート状樹脂フィルムにより、貫通穴から封止樹脂が外部に漏出するのを防止することができる。   According to invention of Claim 4 or 9, it can prevent that sealing resin leaks outside from a through-hole by the sheet-like resin film for closure at the time of soldering reflow.

請求項5または10記載の発明によれば、封止樹脂の透湿度を32g/m2以上で58g/m2以下とすることにより、封止樹脂からの吸湿水分の脱湿を容易にして、吸湿水分の急激な体積膨張による実装部の破壊や、半導体装置の接合部の品質低下を防止することができる。 According to the invention of claim 5 or 10, by making the moisture permeability of the sealing resin 32 g / m 2 or more and 58 g / m 2 or less, it is easy to dehumidify moisture from the sealing resin, It is possible to prevent the mounting portion from being broken and the quality of the joint portion of the semiconductor device from being deteriorated due to rapid volume expansion of moisture absorption moisture.

請求項6または11記載の発明によれば、封止樹脂の樹脂材料の無機フィラー量を40〜60w%とすることにより、特に吸湿後のリフロー接続信頼性を向上することができる。   According to invention of Claim 6 or 11, the reflow connection reliability especially after moisture absorption can be improved by the amount of inorganic fillers of the resin material of sealing resin being 40-60 w%.

請求項12記載の発明によれば、封止樹脂の加熱温度を240〜280℃とすることにより、樹脂硬化時の架橋密度を下げ、半導体装置の封止樹脂からの脱湿を容易にすることができる。   According to the twelfth aspect of the present invention, by setting the heating temperature of the sealing resin to 240 to 280 ° C., the crosslink density at the time of resin curing is lowered, and the dehumidification of the semiconductor device from the sealing resin is facilitated. Can do.

(a)〜(e)は本発明の第1の実施の形態に係る半導体素子と回路基板への半導体素子の実装方法を示し、(a1)は半導体素子の側面断面図、(a2)は半導体素子の底面図、(a3)は半導体素子のコーナ部の拡大底面図、(b)〜(d)(e1)はそれぞれ回路基板への半導体素子の実装方法を示す側面断面図、(e2)は(e1)の部分拡大図である。(A)-(e) shows the semiconductor element concerning the 1st Embodiment of this invention, and the mounting method of the semiconductor element to a circuit board, (a1) is side sectional drawing of a semiconductor element, (a2) is a semiconductor The bottom view of the element, (a3) is an enlarged bottom view of the corner portion of the semiconductor element, (b) to (d) and (e1) are side sectional views showing how to mount the semiconductor element on the circuit board, and (e2) is It is the elements on larger scale of (e1). (a)〜(c)は本発明の第2の実施の形態に係る半導体装置を示し、(a)は半導体素子実装状態の側面断面図、(b)は(a)の要部拡大図、(c)は半導体素子実装領域のコーナ部の拡大平面図である。(A)-(c) shows the semiconductor device which concerns on the 2nd Embodiment of this invention, (a) is side surface sectional drawing of a semiconductor element mounting state, (b) is the principal part enlarged view of (a), (C) is an enlarged plan view of a corner portion of a semiconductor element mounting region. 第2の実施の形態に係る半導体装置の第1の変形例を示す要部の部分拡大断面図である。It is a partial expanded sectional view of the principal part which shows the 1st modification of the semiconductor device which concerns on 2nd Embodiment. 第2の実施の形態に係る半導体装置の第2の変形例を示す要部の部分拡大断面図である。It is a partial expanded sectional view of the principal part which shows the 2nd modification of the semiconductor device which concerns on 2nd Embodiment. (a)〜(e2)は第3ないし第5の実施の形態に係る半導体素子と回路基板への半導体素子の実装方法を示し、(a1)は半導体素子の側面断面図、(a2)は半導体素子の底面図、(b)〜(d)(e1)はそれぞれ回路基板への半導体素子の実装方法を示す側面断面図、(e2)は(e1)の要部の部分拡大図である。(A)-(e2) shows the semiconductor element which concerns on 3rd thru | or 5th Embodiment, and the mounting method of the semiconductor element to a circuit board, (a1) is side sectional drawing of a semiconductor element, (a2) is a semiconductor The bottom view of an element, (b)-(d) (e1) is side sectional drawing which shows the mounting method of the semiconductor element to a circuit board, respectively, (e2) is the elements on larger scale of the principal part of (e1). (a)〜(e2)はそれぞれ従来の半導体素子と回路基板への半導体素子の実装方法を示し、(a1)は半導体素子の側面断面図、(a2)は半導体素子の底面図、(b)〜(d)(e1)はそれぞれ回路基板への半導体素子の実装方法を示す側面断面図、(e2)は(e1)の要部の部分拡大図である。(A)-(e2) each shows the conventional semiconductor element and the mounting method of the semiconductor element to a circuit board, (a1) is side surface sectional drawing of a semiconductor element, (a2) is a bottom view of a semiconductor element, (b) (D) and (e1) are side sectional views showing a method of mounting a semiconductor element on a circuit board, respectively, and (e2) is a partially enlarged view of the main part of (e1).

以下、本発明に係る半導体装置およびその実装方法の実施の形態を図1〜図5を用いて説明する。   Embodiments of a semiconductor device and a mounting method thereof according to the present invention will be described below with reference to FIGS.

(第1の実施の形態)
まず、半導体装置およびその実装方法の第1の実施の形態を図1を用いて説明する。この第1の実施の形態では、はんだ付け時の温度上昇に起因して樹脂シート5に含まれる吸湿成分により発生する応力を減少可能な構造が、半導体素子1に形成された貫通穴11により構成されている。
(First embodiment)
First, a first embodiment of a semiconductor device and its mounting method will be described with reference to FIG. In the first embodiment, the structure capable of reducing the stress generated by the moisture absorption component contained in the resin sheet 5 due to the temperature rise during soldering is constituted by the through hole 11 formed in the semiconductor element 1. Has been.

図1(a)〜(e)は回路基板への半導体素子の実装方法と構造体を示している。   1A to 1E show a method for mounting a semiconductor element on a circuit board and a structure.

図1(a1)〜(a3)に示すように、半導体素子1は、たとえば厚みが0.4mm、サイズが12mm×12mmに形成され、4つの隅部にそれぞれ貫通穴11が形成されている。これら貫通穴11は、隣接する2辺から距離x1=0.6mm以内,y1=0.6mm以内の隅部に中心を有し、内径d1がたとえば0.3mmに形成されている。   As shown in FIGS. 1 (a1) to (a3), the semiconductor element 1 has a thickness of 0.4 mm and a size of 12 mm × 12 mm, for example, and has through holes 11 at four corners. These through-holes 11 have centers at corners within a distance x1 = 0.6 mm and y1 = 0.6 mm from two adjacent sides, and have an inner diameter d1 of, for example, 0.3 mm.

またこの半導体素子1の電極上に形成されたバンプ2の最小ピッチは120μmで、バンプ2としてスタッドバンプ形成方式で金バンプを形成し、このバンプ2の台座サイズは80μmとした。   The minimum pitch of the bumps 2 formed on the electrodes of the semiconductor element 1 is 120 μm, and gold bumps are formed as the bumps 2 by a stud bump formation method. The base size of the bumps 2 is 80 μm.

ここで前記貫通穴11は、4つの隅部のうち少なくとも1箇所以上に形成されればよい。もちろん、四隅以外に貫通穴11を形成してもよいが、半導体素子1の四隅以外に貫通穴11を形成可能な領域がないためである。また貫通穴11の位置が、隣接する2辺から距離x1=0.6mm以内,y1=0.6mm以内であるのは、距離x1,y1を越えると、ICアクティブ領域に入るためである。さらに貫通穴11の内径d1は、0.1〜0.5mmの範囲が有効である。これは、貫通穴11は内径d1が0.1mm未満では穿孔できないためであり、また内径d1が0.5mmを越えると後述する樹脂シート5の樹脂漏れが発生するからである。なお、貫通穴11は1つの隅部に複数個を形成してもよい。   Here, the through hole 11 may be formed in at least one of the four corners. Of course, the through holes 11 may be formed in areas other than the four corners, but there is no region where the through holes 11 can be formed in areas other than the four corners of the semiconductor element 1. Further, the reason why the position of the through hole 11 is within the distance x1 = 0.6 mm and y1 = 0.6 mm from the two adjacent sides is that when the distance x1 and y1 are exceeded, the IC active region is entered. Further, the inner diameter d1 of the through hole 11 is effectively in the range of 0.1 to 0.5 mm. This is because the through-hole 11 cannot be drilled when the inner diameter d1 is less than 0.1 mm, and when the inner diameter d1 exceeds 0.5 mm, resin leakage of the resin sheet 5 described later occurs. A plurality of through holes 11 may be formed at one corner.

図1(b)に示すように、回路基板3はアルミナを主成分(96wt%)とするセラミック基板で、厚みが0.4mmに形成されている。前記回路基板3上に形成された電極4の材質はタングステンで、その表面に金メッキが施されている。この回路基板3に、厚みが60μmのエポキシ樹脂を主成分とする樹脂シート(封止樹脂)5が半導体素子1の実装領域に貼り付けられる。この樹脂シート5の貼り付け条件は、加熱温度が80℃で、加圧時間が3秒である。   As shown in FIG. 1B, the circuit board 3 is a ceramic substrate having alumina as a main component (96 wt%) and has a thickness of 0.4 mm. The electrode 4 formed on the circuit board 3 is made of tungsten, and the surface thereof is plated with gold. A resin sheet (sealing resin) 5 mainly composed of an epoxy resin having a thickness of 60 μm is attached to the circuit board 3 in a mounting region of the semiconductor element 1. The resin sheet 5 is attached with a heating temperature of 80 ° C. and a pressurization time of 3 seconds.

図1(c)に示すように、回路基板3の電極4と半導体素子1のバンプ2が接するように位置合わせし、次いで実装ヘッドによりマウントされる。マウント時には、回路基板3を保持するステージ温度、実装ヘッド温度は常温とする。   As shown in FIG. 1C, the electrodes 4 of the circuit board 3 and the bumps 2 of the semiconductor element 1 are aligned so as to contact each other, and then mounted by a mounting head. At the time of mounting, the stage temperature for holding the circuit board 3 and the mounting head temperature are set to room temperature.

図1(d)に示すように、圧着ツール7により、半導体素子1を上面から温度260℃に加熱して20秒間加圧し、回路基板3の電極4と半導体素子1のバンプ2とを接続し、封止機能を有する樹脂シート5の硬化を同時に行う。この時の接続抵抗値は10Ω/バンプである。   As shown in FIG. 1D, the crimping tool 7 heats the semiconductor element 1 from the upper surface to a temperature of 260 ° C. and pressurizes it for 20 seconds to connect the electrodes 4 of the circuit board 3 and the bumps 2 of the semiconductor element 1. The resin sheet 5 having a sealing function is simultaneously cured. The connection resistance value at this time is 10Ω / bump.

図1(e1)(e2)は、半導体素子1を実装した半導体装置の構造を示している。   FIGS. 1E1 and 1E2 show the structure of a semiconductor device on which the semiconductor element 1 is mounted.

上記第1の実施の形態によれば、半導体素子1の隅部に形成された貫通穴11により、貫通穴11を介して樹脂シート5の吸湿成分を良好に逃がすことができ、吸湿成分による体積膨張に起因して発生する応力発生を抑制することができる。また貫通穴11により残った応力を吸収することができる。したがって、はんだ付けリフローによる実装部の破壊や接合部の品質低下を防止することができ、接続信頼性を向上して、乾燥工程や高精度な湿度管理が不要となり、半導体装置の製造コストを低減できる。   According to the first embodiment, the through holes 11 formed in the corners of the semiconductor element 1 allow the moisture absorbing component of the resin sheet 5 to escape well through the through holes 11, and the volume by the moisture absorbing component. Generation of stress due to expansion can be suppressed. Further, the remaining stress can be absorbed by the through hole 11. Therefore, it is possible to prevent damage to the mounting part and deterioration of the joint quality due to soldering reflow, improve connection reliability, eliminate the need for a drying process and high-precision humidity management, and reduce the manufacturing cost of semiconductor devices. it can.

上記実装方法により製造された半導体装置のリフロー試験(一定環境で吸湿させた後リフローにより熱処理する試験:規格としてJEDECレベル1〜3があり、本評価はレベル2)を実施した結果を表1に示す。   Table 1 shows the results of performing a reflow test of a semiconductor device manufactured by the above mounting method (test for heat treatment by reflow after moisture absorption in a constant environment: JEDEC levels 1 to 3 are standard, this evaluation is level 2) Show.

Figure 2010034590
ここで評価レベルの条件は、吸湿条件が85℃、165%−168時間放置後、リフロー(240℃以上、10秒)である。上記実験によれば、全体に良好な結果を得た。
Figure 2010034590
The condition of the evaluation level is reflow (240 ° C. or more, 10 seconds) after leaving the moisture absorption condition at 85 ° C. and 165% -168 hours. According to the above experiment, good results were obtained overall.

(第2の実施の形態)
第2の実施の形態に係る半導体装置および回路基板への半導体素子の実装方法を図2を用いて説明する。この第2の実施の形態では、はんだ付け時の温度上昇に起因して樹脂シート5に含まれる吸湿成分により発生する応力を減少可能な構造が、回路基板3に形成された貫通穴21により構成されている。なお、第1の実施の形態と同一部材には同一符号を付して説明を省略する。
(Second Embodiment)
A semiconductor device and a method for mounting a semiconductor element on a circuit board according to the second embodiment will be described with reference to FIG. In the second embodiment, the structure capable of reducing the stress generated by the hygroscopic component contained in the resin sheet 5 due to the temperature rise during soldering is constituted by the through hole 21 formed in the circuit board 3. Has been. Note that the same members as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

図2(a)〜(c)に示すように、この半導体装置は、前記貫通穴を有しない半導体素子1を用いて、第1の実施の形態と同一条件で実装されたものである。   As shown in FIGS. 2A to 2C, this semiconductor device is mounted using the semiconductor element 1 that does not have the through hole under the same conditions as those in the first embodiment.

すなわち、樹脂シート(封止樹脂)5が取り付けられる回路基板3の半導体素子実装領域3aの4つの隅部に貫通穴21がそれぞれ形成されている。これら貫通穴21は、半導体素子実装領域3aの隣接する2辺から距離x2=0.6mm以内,y2=0.6mm以内に中心を有し、内径d2がたとえば0.3mmに形成されている。   That is, the through holes 21 are formed in the four corners of the semiconductor element mounting region 3a of the circuit board 3 to which the resin sheet (sealing resin) 5 is attached. These through holes 21 have a center within a distance x2 = 0.6 mm and y2 = 0.6 mm from two adjacent sides of the semiconductor element mounting region 3a, and have an inner diameter d2 of, for example, 0.3 mm.

ここで前記貫通穴21は、回路基板3の半導体素子実装領域3aの4つの隅部のうち少なくとも1箇所以上であればよい。また貫通穴21の位置は、隣接する2辺から距離x2=0.6mm以内,y2=0.6mm以内であるのは、その距離x2,y2を越えるとICアクティブ領域に入るためである。さらに貫通穴21の内径d2は、0.1〜0.5mmの範囲が有効である。これは、貫通穴21は内径d2が0.1mm未満では穿孔できないためであり、また内径d2が0.5mmを越えると樹脂シート5の樹脂漏れが発生するからである。なお、貫通穴21は1つの隅部に複数個を形成してもよい。   Here, the through hole 21 may be at least one of the four corners of the semiconductor element mounting region 3 a of the circuit board 3. The positions of the through holes 21 are within the distance x2 = 0.6 mm and y2 = 0.6 mm from the two adjacent sides because the IC active region is entered when the distances x2 and y2 are exceeded. Further, the inner diameter d2 of the through hole 21 is effectively in the range of 0.1 to 0.5 mm. This is because the through hole 21 cannot be drilled when the inner diameter d2 is less than 0.1 mm, and when the inner diameter d2 exceeds 0.5 mm, resin leakage of the resin sheet 5 occurs. A plurality of through holes 21 may be formed at one corner.

上記第2の実施の形態によれば、回路基板3の半導体素子実装領域3aの隅部に形成された貫通穴21により、樹脂シート5の吸湿成分を良好に逃がすことができ、吸湿成分による体積膨張に起因して発生する応力発生を抑制することができる。また貫通穴21により残った応力を吸収することができる。したがって、はんだ付けリフローによる実装部の破壊や接合部の品質低下を防止することができ、接続信頼性を向上して、乾燥工程や高精度な湿度管理が不要となり、半導体装置の製造コストを低減できる。   According to the second embodiment, the through-holes 21 formed in the corners of the semiconductor element mounting region 3a of the circuit board 3 can favorably release the moisture absorption component of the resin sheet 5, and the volume due to the moisture absorption component. Generation of stress due to expansion can be suppressed. Further, the remaining stress can be absorbed by the through hole 21. Therefore, it is possible to prevent damage to the mounting part and deterioration of the joint quality due to soldering reflow, improve connection reliability, eliminate the need for a drying process and high-precision humidity management, and reduce the manufacturing cost of semiconductor devices. it can.

上記実装方法により製造された半導体装置のリフロー試験(一定環境で吸湿させた後リフローにより熱処理する試験:規格としてJEDECレベル1〜3があり、本評価はレベル2)を実施した結果を表2に示す。   Table 2 shows the results of performing a reflow test of a semiconductor device manufactured by the above mounting method (test to heat-treat by reflow after absorbing moisture in a constant environment: JEDEC levels 1 to 3 are standard, this evaluation is level 2) Show.

Figure 2010034590
ここで評価レベルの条件は、吸湿条件が85℃、165%−168時間放置後、リフロー(240℃以上、10秒)である。
Figure 2010034590
The condition of the evaluation level is reflow (240 ° C. or more, 10 seconds) after leaving the moisture absorption condition at 85 ° C. and 165% -168 hours.

上記実験によれば、回路基板3に貫通穴21を設けることにより、吸湿リフロー試験における接続信頼性を向上することができた。このときの1接続当たりの接続抵抗値は10Ω/バンプであった。   According to the above experiment, the connection reliability in the moisture absorption reflow test could be improved by providing the through hole 21 in the circuit board 3. The connection resistance value per connection at this time was 10Ω / bump.

図3は、第2の実施の形態の第1変形例を示し、樹脂シート5の封止樹脂の漏れを防止するために貫通穴21に閉塞用樹脂22を充填した構造を示している。これにより、封止樹脂である樹脂シート5に替えて、液状樹脂を使用した場合でも、貫通穴21からの樹脂漏れを防止することができる。   FIG. 3 shows a first modification of the second embodiment, and shows a structure in which the through hole 21 is filled with a closing resin 22 in order to prevent leakage of the sealing resin of the resin sheet 5. Thereby, it can replace with the resin sheet 5 which is sealing resin, and can prevent the resin leak from the through-hole 21, even when liquid resin is used.

図4は、第2の実施の形態の第2変形例を示し、封止樹脂の漏れを防止するために、貫通穴21の実装面の反対面を閉塞用樹脂シート(閉塞用シート状樹脂フィルム)23で覆う構造を示している。これにより、樹脂シート5に替えて液状樹脂を封止樹脂として使用した場合でも、閉塞用樹脂シート23により、貫通穴21からの樹脂漏れを防止することができる。   FIG. 4 shows a second modification of the second embodiment. In order to prevent leakage of the sealing resin, the surface opposite to the mounting surface of the through hole 21 is closed with a blocking resin sheet (blocking sheet-like resin film). ) 23 shows the structure covered. Thereby, even if it replaces with the resin sheet 5 and uses liquid resin as sealing resin, the resin sheet 23 for closure can prevent the resin leak from the through-hole 21. FIG.

(第3の実施の形態)
本発明に係る半導体装置および半導体素子の実装方法の第3の実施の形態を説明する。この第3の実施の形態では、はんだ付け時の温度上昇に起因して樹脂シート5に含まれる吸湿成分により発生する応力を減少可能な材質が、樹脂シート5の透湿度を選択することにより構成されている。なお、第1の実施の形態と同一部材には同一符号を付して説明を省略する。
(Third embodiment)
A semiconductor device and a semiconductor element mounting method according to a third embodiment of the present invention will be described. In the third embodiment, the material capable of reducing the stress generated by the moisture absorption component contained in the resin sheet 5 due to the temperature rise during soldering is configured by selecting the moisture permeability of the resin sheet 5. Has been. Note that the same members as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

図5に示すように、第1および第2の実施の形態における貫通穴11,21を有しない半導体素子1と回路基板3、および透湿度の異なる樹脂シート5を用いて、図1と同様の条件で半導体素子の実装を行ったものである。この実験では、樹脂シート5の透湿度が、17〜65g/m2の範囲内で6種類選択された。 As shown in FIG. 5, using the semiconductor element 1 and the circuit board 3 that do not have the through holes 11 and 21 and the resin sheet 5 having different moisture permeability in the first and second embodiments, The semiconductor element is mounted under conditions. In this experiment, the moisture permeability of the resin sheet 5 was selected within the range of 17 to 65 g / m 2 .

ここで樹脂シート5は、熱硬化性樹脂であり、エポキシ系樹脂が選択されている。たとえばこのエポキシ系樹脂は、ビスフェノールA,Fを主成分とし、透湿性向上剤としてアクリル変性エポキシまたは熱可塑性樹脂であるブタジエンゴム、アクリロニトリル、アクリルが添加されたものである。   Here, the resin sheet 5 is a thermosetting resin, and an epoxy resin is selected. For example, this epoxy resin has bisphenol A and F as the main components, and is added with butadiene rubber, acrylonitrile, and acryl, which are acrylic-modified epoxy or thermoplastic resin, as a moisture permeability improver.

Figure 2010034590
表3にリフロー試験による樹脂シート5の透湿度条件とその結果を示している。樹脂シート5の透湿度を32〜58g/m2の範囲内として脱湿構造とすることにより、吸湿リフロー試験における接続信頼性を向上することができた。
Figure 2010034590
Table 3 shows the moisture permeability conditions of the resin sheet 5 and the results of the reflow test. By making the moisture permeability of the resin sheet 5 in the range of 32 to 58 g / m 2 and adopting a dehumidifying structure, connection reliability in the moisture absorption reflow test could be improved.

上記第3の実施の形態によれば、樹脂シート5の脱湿構造を、透湿度が32〜58g/m2の範囲内とすることで、樹脂シート5の吸湿成分を良好に逃がすことができ、吸湿成分により発生する体積膨張に起因して発生する応力発生を抑制することができる。したがって、はんだ付けリフローによる実装部の破壊や接合部の品質低下を防止することができ、接続信頼性を向上して、乾燥工程や高精度な湿度管理が不要となり、半導体装置の製造コストを低減できる。 According to the said 3rd Embodiment, the moisture absorption component of the resin sheet 5 can be escaped favorably by making the moisture-removal structure of the resin sheet 5 into the range of 32-58 g / m < 2 > of moisture permeability. In addition, it is possible to suppress the generation of stress caused by the volume expansion generated by the hygroscopic component. Therefore, it is possible to prevent damage to the mounting part and deterioration of the joint quality due to soldering reflow, improve connection reliability, eliminate the need for a drying process and high-precision humidity management, and reduce the manufacturing cost of semiconductor devices. it can.

(第4の実施の形態)
本発明に係る半導体装置および半導体素子の実装方法の第4の実施の形態を説明する。はんだ付け時の温度上昇に起因して樹脂シート5に含まれる吸湿成分により発生する応力を減少可能な材質が、樹脂シート5への無機フィラー添加量を選択して吸湿量を調整することにより構成されている。なお、第4の実施の形態は図5と同様であり、第1の実施の形態と同一部材には同一符号を付して説明を省略する。
(Fourth embodiment)
A semiconductor device and a semiconductor element mounting method according to a fourth embodiment of the present invention will be described. The material capable of reducing the stress generated by the moisture absorption component contained in the resin sheet 5 due to the temperature rise during soldering is configured by selecting the amount of inorganic filler added to the resin sheet 5 and adjusting the moisture absorption amount Has been. Note that the fourth embodiment is the same as that in FIG. 5, and the same members as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted.

半導体装置は、貫通穴11を有しない半導体素子1を第1の実施の形態と同一条件で実装した。封止機能を有する樹脂シート5に、ほとんど吸湿しない無機フィラーを40〜60wt%の割合で添加することにより、シート全体で吸湿する樹脂の量を減少させ、樹脂シート5全体の吸湿量を減らしている。   In the semiconductor device, the semiconductor element 1 not having the through hole 11 was mounted under the same conditions as in the first embodiment. By adding 40-60 wt% of an inorganic filler that hardly absorbs moisture to the resin sheet 5 having a sealing function, the amount of resin that absorbs moisture in the entire sheet is reduced, and the amount of moisture absorbed in the entire resin sheet 5 is reduced. Yes.

前記樹脂シート5は熱硬化性樹脂であり、エポキシ系樹脂が選択されている。たとえばこのエポキシ系樹脂は、ビスフェノールA,Fを主成分とし、透湿性向上剤としてアクリル変性エポキシまたは熱可塑性樹脂であるブタジエンゴム、アクリロニトリル、アクリルが添加されたものが採用された。また無機フィラーとして、シリカSiO2、またはアルミナAl2Oが採用される。このときの1接続当たりの接続抵抗値は10Ω/バンプであった。 The resin sheet 5 is a thermosetting resin, and an epoxy resin is selected. For example, this epoxy resin is mainly composed of bisphenol A and F and added with butadiene rubber, acrylonitrile, or acrylic resin, which is an acrylic-modified epoxy or thermoplastic resin, as a moisture permeability improver. Silica SiO 2 or alumina Al 2 O 3 is used as the inorganic filler. The connection resistance value per connection at this time was 10Ω / bump.

Figure 2010034590
表4にリフロー試験の条件と結果を示している。樹脂シート5の吸湿量を無機フィラーをより減少させることで、吸湿リフロー試験における接続信頼性を向上することができた。
Figure 2010034590
Table 4 shows the reflow test conditions and results. The connection reliability in the moisture absorption reflow test could be improved by further reducing the amount of moisture absorption of the resin sheet 5 with the inorganic filler.

上記第4の実施の形態によれば、樹脂シート5に添加する無機フィラーを40〜60wt%の割合とすることにより、樹脂シート5の吸湿量を大幅に減少させ、吸湿成分による体積膨張に起因して発生する応力発生を抑制することができる。したがって、はんだ付けリフローによる実装部の破壊や接合部の品質低下を防止することができ、接続信頼性を向上して、乾燥工程や高精度な湿度管理が不要となり、半導体装置の製造コストを低減できる。   According to the fourth embodiment, by setting the inorganic filler added to the resin sheet 5 to a ratio of 40 to 60 wt%, the moisture absorption amount of the resin sheet 5 is greatly reduced, resulting from volume expansion due to moisture absorption components. Generation of stress can be suppressed. Therefore, it is possible to prevent damage to the mounting part and deterioration of the joint quality due to soldering reflow, improve connection reliability, eliminate the need for a drying process and high-precision humidity management, and reduce the manufacturing cost of semiconductor devices. it can.

(第5の実施の形態)
本発明に係る半導体装置および半導体素子の実装方法の第5の実施の形態を説明する。この第5の実施の形態では、はんだ付け時の温度上昇に起因して樹脂シート5に含まれる吸湿成分により発生する応力を減少可能な方法として、半導体素子1と回路基板3との圧着温度条件を選択している。なお、第1の実施の形態と同一部材には同一符号を付して説明を省略する。
(Fifth embodiment)
A fifth embodiment of a semiconductor device and a semiconductor element mounting method according to the present invention will be described. In the fifth embodiment, as a method capable of reducing the stress generated by the hygroscopic component contained in the resin sheet 5 due to the temperature rise during soldering, the pressure bonding temperature condition between the semiconductor element 1 and the circuit board 3 can be reduced. Is selected. Note that the same members as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

この半導体装置は、第1および第2の実施の形態における貫通穴11,21を有しない半導体素子1と回路基板3とを、圧着ツール7を用いて、圧着温度条件を200〜320℃の範囲で変化させて、加圧(加熱)時間20秒で圧着して製造したもので、前記表3に示すように、樹脂シート5は、その透湿度を17から65g/m2の範囲で異なるものを選択している。この時、セラミック製の回路基板3の電極4と半導体素子1上のバンプ2の接続と封止機能を有する樹脂シート5の硬化が同時に行われている。このときの1接続当たりの接続抵抗値は10Ω/バンプであった。 This semiconductor device uses a crimping tool 7 to bond the semiconductor element 1 and the circuit board 3 that do not have the through holes 11 and 21 according to the first and second embodiments to a temperature range of 200 to 320 ° C. The resin sheet 5 is manufactured by pressure bonding (heating) with a pressure (heating) time of 20 seconds. As shown in Table 3, the resin sheet 5 has a moisture permeability of 17 to 65 g / m 2. Is selected. At this time, the connection of the electrodes 4 of the ceramic circuit board 3 and the bumps 2 on the semiconductor element 1 and the curing of the resin sheet 5 having a sealing function are performed simultaneously. The connection resistance value per connection at this time was 10Ω / bump.

前記表3に上記半導体装置のリフロー試験による樹脂シート5の透湿度条件とその結果を示している。   Table 3 shows the moisture permeability conditions and the results of the resin sheet 5 by the reflow test of the semiconductor device.

前記表3によれば、圧着温度が240〜280℃の範囲で吸湿リフロー試験における接続信頼性を向上することができた。ここで、圧着温度が240℃未満では、リフロー加熱時の応力が大きく、実装部の破壊や接合部の品質低下が生じるおそれがあるからであり、また圧着温度が280℃を越えると、逆方向の応力が大きくなりすぎるためである。   According to Table 3, the connection reliability in the moisture absorption reflow test could be improved when the pressure bonding temperature was 240 to 280 ° C. Here, when the pressure bonding temperature is less than 240 ° C., the stress during reflow heating is large, and there is a possibility that the mounting portion may be broken or the quality of the bonded portion may be deteriorated. This is because the stress of becomes too large.

また加圧時間は20秒としたが、加圧時間は5〜30秒の範囲が好ましく、5秒未満では、樹脂シート5の硬化が不十分となり、また30秒を越えると、生産性が低下するからである。   The pressurization time is 20 seconds, but the pressurization time is preferably in the range of 5 to 30 seconds. If the pressurization time is less than 5 seconds, the resin sheet 5 is not sufficiently cured, and if it exceeds 30 seconds, the productivity decreases. Because it does.

上記第5の実施の形態によれば、樹脂シート5の透湿度を32〜58g/m2の範囲とし、かつ半導体素子1と回路基板3との圧着温度条件を240〜280℃の範囲とすることにより、樹脂シート5の吸湿成分を良好に逃がすことができ、吸湿成分による体積膨張に起因して発生する応力発生を抑制することができる。したがって、はんだ付けリフローによる実装部の破壊や接合部の品質低下を防止することができ、接続信頼性を向上して、乾燥工程や高精度な湿度管理が不要となり、半導体装置の製造コストを低減できる。 According to the fifth embodiment, the moisture permeability of the resin sheet 5 is in the range of 32 to 58 g / m 2 , and the pressure bonding temperature condition between the semiconductor element 1 and the circuit board 3 is in the range of 240 to 280 ° C. Thereby, the moisture absorption component of the resin sheet 5 can be escaped favorably, and the generation of stress due to volume expansion due to the moisture absorption component can be suppressed. Therefore, it is possible to prevent damage to the mounting part and deterioration of the joint quality due to soldering reflow, improve connection reliability, eliminate the need for a drying process and high-precision humidity management, and reduce the manufacturing cost of semiconductor devices. it can.

なお、上記第1〜第5の実施の形態を任意に選択して組合わせることもできる。   The first to fifth embodiments can be arbitrarily selected and combined.

本発明にかかる半導体装置およびその実装方法は、加熱、加圧接合時に、封止樹脂の吸湿水分が効果的に脱湿されるので、吸湿水分の急激な体積膨張による実装部の破壊や、半導体装置の接合部への負荷を抑制でき、品質を低下させることがなく、例えばCSPタイプの半導体装置に有用である。また例えば、携帯電話端末をはじめとするモバイル機器に供される半導体装置、例えば液晶モジュールのドライバに有用である。   In the semiconductor device and the mounting method thereof according to the present invention, the moisture absorption moisture of the sealing resin is effectively dehumidified at the time of heating and pressure bonding. The load on the junction of the device can be suppressed, and the quality is not deteriorated. For example, it is useful for a CSP type semiconductor device. For example, it is useful for a driver of a semiconductor device such as a liquid crystal module used in a mobile device such as a mobile phone terminal.

1 半導体素子
2 バンプ
3 回路基板
4 電極
5 樹脂シート
7 圧着ツール
11 貫通穴
21 貫通穴
22 閉塞用樹脂
23 閉塞用樹脂シート(閉塞用シート状樹脂フィルム)
DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Bump 3 Circuit board 4 Electrode 5 Resin sheet 7 Crimping tool 11 Through hole 21 Through hole 22 Closing resin 23 Closing resin sheet (closing sheet-like resin film)

Claims (12)

半導体素子と回路基板とを、前記半導体素子の電極上に形成したバンプと、前記回路基板上に設けた配線とを介して電気的に接合し、前記半導体素子と回路基板の間に封止樹脂を介在させた半導体装置において、
前記封止樹脂に含まれる吸湿成分により発生する応力を減少可能な構造が、回路基板に形成された貫通穴により構成され、前記貫通穴の位置が、回路基板の半導体素子実装領域の隅部に形成されたことを特徴とする半導体装置。
A semiconductor element and a circuit board are electrically bonded via bumps formed on the electrodes of the semiconductor element and wirings provided on the circuit board, and a sealing resin is provided between the semiconductor element and the circuit board. In a semiconductor device interposing
The structure capable of reducing the stress generated by the hygroscopic component contained in the sealing resin is constituted by a through hole formed in the circuit board, and the position of the through hole is at the corner of the semiconductor element mounting region of the circuit board. A semiconductor device formed.
吸湿成分により発生する応力を減少可能な構造が、回路基板に形成された貫通穴により構成され、前記貫通穴の位置が、回路基板の半導体素子実装領域の隣接する2辺から0.6mm以内の隅部に形成されたことを特徴とする請求項1記載の半導体装置。   The structure capable of reducing the stress generated by the moisture absorption component is constituted by a through hole formed in the circuit board, and the position of the through hole is within 0.6 mm from two adjacent sides of the semiconductor element mounting region of the circuit board. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed at a corner. 貫通穴内に、封止樹脂の漏出を防止する閉塞用樹脂が充填されたことを特徴とする請求項1もしくは2のいずれかに記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the through hole is filled with a closing resin for preventing leakage of the sealing resin. 半導体素子の実装面と反対の面の貫通穴の開口部が、封止樹脂の漏出を防止する閉塞用シート状樹脂フィルムにより覆われたことを特徴とする請求項1もしくは2のいずれかに記載の半導体装置。   The opening of the through hole on the surface opposite to the mounting surface of the semiconductor element is covered with a closing sheet-like resin film that prevents leakage of the sealing resin. Semiconductor device. 半導体素子と回路基板とを、前記半導体素子の電極上に形成したバンプと、前記回路基板上に設けた配線とを介して電気的に接合し、前記半導体素子と回路基板の間に封止樹脂を介在させた半導体装置において、
前記封止樹脂に含まれる吸湿成分により発生する応力を減少可能な材質として、封止樹脂の樹脂材料の透湿度が32〜58g/m2の範囲とされたことを特徴とする半導体装置。
A semiconductor element and a circuit board are electrically bonded via bumps formed on the electrodes of the semiconductor element and wirings provided on the circuit board, and a sealing resin is provided between the semiconductor element and the circuit board. In a semiconductor device interposing
A semiconductor device characterized in that the moisture permeability of the resin material of the sealing resin is in the range of 32 to 58 g / m 2 as a material capable of reducing the stress generated by the moisture absorption component contained in the sealing resin.
半導体素子と回路基板とを、前記半導体素子の電極上に形成したバンプと、前記回路基板上に設けた配線とを介して電気的に接合し、前記半導体素子と回路基板の間に封止樹脂を介在させた半導体装置において、
前記封止樹脂に含まれる吸湿成分により発生する応力を減少可能な材質として、封止樹脂の樹脂材料に添加される無機フィラー量が40〜60w%の範囲とされたことを特徴とする半導体装置。
A semiconductor element and a circuit board are electrically bonded via bumps formed on the electrodes of the semiconductor element and wirings provided on the circuit board, and a sealing resin is provided between the semiconductor element and the circuit board. In a semiconductor device interposing
A semiconductor device characterized in that the amount of inorganic filler added to the resin material of the sealing resin is in the range of 40 to 60 w% as a material capable of reducing the stress generated by the moisture absorption component contained in the sealing resin. .
回路基板上に設けた配線上に、封止樹脂を介して半導体素子電極上のバンプを電気的に接合するに際し、
回路基板上の半導体素子実装領域の隅部に、貫通穴を形成し、
前記半導体素子、回路基板、封止樹脂のいずれかを加熱して封止樹脂に含まれる吸湿水を前記貫通穴から脱湿しつつ前記半導体素子と回路基板とを加圧し、封止樹脂を硬化させて半導体素子のバンプと回路基板の配線とを接合する
ことを特徴とする半導体装置の実装方法。
When electrically connecting the bumps on the semiconductor element electrode on the wiring provided on the circuit board via the sealing resin,
In the corner of the semiconductor element mounting area on the circuit board, through holes are formed,
Either the semiconductor element, the circuit board, or the sealing resin is heated to pressurize the semiconductor element and the circuit board while dehumidifying moisture contained in the sealing resin from the through hole, and the sealing resin is cured. A semiconductor device mounting method comprising bonding a bump of a semiconductor element and a wiring of a circuit board.
前記貫通穴内に閉塞用樹脂を充填した後、加熱して脱湿しつつ加圧して接合し、前記閉塞用樹脂により封止樹脂の漏出を防止することを特徴とする請求項7記載の半導体装置の実装方法。   8. The semiconductor device according to claim 7, wherein the through hole is filled with a closing resin, and then heated and dehumidified and pressurized and bonded, and the sealing resin prevents leakage of the sealing resin. How to implement 前記半導体素子の実装面に反対の面の貫通穴の開口部を閉塞用シート状樹脂フィルムにより覆った後、加熱して脱湿しつつ加圧して接合し、前記閉塞用シート状樹脂フィルムにより貫通穴からの封止樹脂の漏出を防止することを特徴とする請求項7記載の半導体装置の実装方法。   The opening of the through hole on the surface opposite to the mounting surface of the semiconductor element is covered with a closing sheet-like resin film, and then heated and dehumidified to pressurize and join, and penetrated by the closing sheet-like resin film 8. The semiconductor device mounting method according to claim 7, wherein leakage of the sealing resin from the hole is prevented. 回路基板上に設けた配線上に、封止樹脂を介して半導体素子電極上のバンプを電気的に接合するに際し、
前記封止樹脂の樹脂材料の透湿度を、32g/m2以上で58g/m2以下とし、
前記半導体素子、回路基板、封止樹脂のいずれかを加熱して封止樹脂に含まれる吸湿水を脱湿しつつ前記半導体素子と回路基板とを加圧して封止樹脂を硬化させ半導体素子のバンプと回路基板の配線とを接合する
ことを特徴とする半導体装置の実装方法。
When electrically connecting the bumps on the semiconductor element electrode on the wiring provided on the circuit board via the sealing resin,
The moisture permeability of the resin material of the sealing resin is 32 g / m 2 or more and 58 g / m 2 or less,
The semiconductor element, the circuit board, or the sealing resin is heated to dehumidify moisture contained in the sealing resin and pressurize the semiconductor element and the circuit board to cure the sealing resin. A method of mounting a semiconductor device, comprising bonding a bump and a wiring of a circuit board.
回路基板上に設けた配線上に、封止樹脂を介して半導体素子電極上のバンプを電気的に接合するに際し、
前記封止樹脂の樹脂材料の無機フィラー量を、40〜60w%の範囲とし、
前記半導体素子、回路基板、封止樹脂のいずれかを加熱して封止樹脂に含まれる吸湿水を脱湿しつつ前記半導体素子と回路基板とを加圧して封止樹脂を硬化させ半導体素子のバンプと回路基板の配線とを接合する
ことを特徴とする半導体装置の実装方法。
When electrically connecting the bumps on the semiconductor element electrode on the wiring provided on the circuit board via the sealing resin,
The amount of inorganic filler in the resin material of the sealing resin is in the range of 40 to 60 w%,
The semiconductor element, the circuit board, or the sealing resin is heated to dehumidify moisture contained in the sealing resin and pressurize the semiconductor element and the circuit board to cure the sealing resin. A method of mounting a semiconductor device, comprising bonding a bump and a wiring of a circuit board.
半導体素子の圧着時の封止樹脂の加熱温度を240〜280℃の範囲としたことを特徴とする請求項10もしくは11のいずれかに記載の半導体装置の実装方法。
The method for mounting a semiconductor device according to claim 10, wherein the heating temperature of the sealing resin at the time of pressure bonding of the semiconductor element is in a range of 240 to 280 ° C.
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JP2002076059A (en) * 2000-09-01 2002-03-15 Misuzu Kogyo:Kk Circuit board

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JPH09260433A (en) * 1996-03-22 1997-10-03 Nitto Denko Corp Manufacture of semiconductor device and semiconductor device provided thereby
JPH1126627A (en) * 1997-07-03 1999-01-29 Mitsui Chem Inc Semiconductor mounting board
JP2001127194A (en) * 1999-10-28 2001-05-11 Sharp Corp Flip chip semiconductor device and its manufacturing method
JP2002076059A (en) * 2000-09-01 2002-03-15 Misuzu Kogyo:Kk Circuit board

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014174100A (en) * 2013-03-12 2014-09-22 Asahi Kasei Electronics Co Ltd Humidity sensor

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