JP5851952B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and can be suitably used for, for example, a method for manufacturing a semiconductor device using flip-chip connection and using an underfill resin.

  A semiconductor device is manufactured by flip-chip mounting a semiconductor chip on a wiring board. The space between the wiring board and the semiconductor chip is filled with an underfill resin.

  Japanese Patent Laid-Open No. 2002-151551 (Patent Document 1) describes a technique related to flip chip mounting.

  Japanese Patent Application Laid-Open No. 2003-049050 (Patent Document 2) describes a technique related to an epoxy resin composition containing a pregelling agent.

  Non-Patent Document 1 describes a technique related to an adhesive in which core / shell acrylic fine particles are dispersed in an epoxy resin.

JP 2002-151551 A JP 2003-049050 A

"Adhesives and bonding technology", author: Koji Nagata, CMMC Publishing, 2007, p19-20

  Even when a semiconductor device is manufactured by flip-chip mounting a semiconductor chip on a wiring board, it is desired to improve the reliability of the semiconductor device as much as possible. Alternatively, it is desired to improve the manufacturing yield of semiconductor devices. Alternatively, it is desirable to realize both.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, after placing the wiring board on the stage, the paste-like resin having the first viscosity containing the expandable filler is supplied onto the wiring board, and the wiring board is placed on the wiring board. The viscosity of the resin is increased to a second viscosity that is higher than the first viscosity. Thereafter, the semiconductor chip is mounted face down on the wiring substrate on which the resin is disposed, and the resin is cured.

  According to one embodiment, the reliability of a semiconductor device can be improved.

  In addition, according to the embodiment, the manufacturing yield of the semiconductor device can be improved.

  Moreover, according to one embodiment, the reliability of the semiconductor device can be improved and the manufacturing yield of the semiconductor device can be improved.

It is a top view of the semiconductor device which is one embodiment. It is sectional drawing of the semiconductor device which is one embodiment. It is a top view of the wiring board used for manufacture of the semiconductor device which is one embodiment. It is sectional drawing of the wiring board used for manufacture of the semiconductor device which is one embodiment. It is a top view of the semiconductor chip used for manufacture of the semiconductor device which is one embodiment. It is sectional drawing of the semiconductor chip used for manufacture of the semiconductor device which is one embodiment. It is a manufacturing process flowchart which shows the manufacturing process of the semiconductor device of one embodiment. It is a manufacturing process flowchart which shows the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of one embodiment. It is a graph which shows typically the viscosity of a thermosetting resin. It is a graph which shows typically the viscosity of resin used in one embodiment. It is explanatory drawing of resin used by one Embodiment. It is explanatory drawing of resin used by one Embodiment. It is explanatory drawing of resin used by one Embodiment. It is explanatory drawing of the manufacturing process of the semiconductor device of a modification. It is explanatory drawing of the manufacturing process of the semiconductor device of a modification. It is explanatory drawing of the manufacturing process of the semiconductor device of a modification. It is explanatory drawing of the manufacturing process of the semiconductor device of a modification.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment)
<Structure of semiconductor device>
The semiconductor device of the present embodiment will be described with reference to the drawings.

  FIG. 1 is a plan view of the semiconductor device PKG of the present embodiment, and shows a plan view of the upper surface side of the semiconductor device PKG. FIG. 2 is a cross-sectional view of the semiconductor device PKG. A cross section of the semiconductor device PKG taken along line A1-A1 in FIG. 1 substantially corresponds to FIG. 3 and 4 are a plan view and a cross-sectional view of a wiring board CB used for manufacturing the semiconductor device PKG, and FIGS. 5 and 6 are a plan view and a cross-sectional view of a semiconductor chip CP used for manufacturing the semiconductor device PKG. FIG. 3 is a plan view of the upper surface CBa side of the wiring board CB, and FIG. 4 substantially corresponds to a cross-sectional view of the wiring board CB along the line A2-A2 of FIG. FIG. 5 is a plan view of the surface CPa side of the semiconductor chip CP, and FIG. 6 substantially corresponds to the cross-sectional view of the semiconductor chip CP taken along the line A3-A3 of FIG. However, in FIG. 4, the cross section of the wiring board CB is shown with the lower surface CBb side of the wiring board CB facing downward, but in FIG. 6, the surface CPa side of the semiconductor chip CP is facing downward. The cross section of the semiconductor chip CP is shown.

  The semiconductor device PKG of the present embodiment shown in FIGS. 1 and 2 is a semiconductor device in the form of a semiconductor package.

  As shown in FIGS. 1 and 2, the semiconductor device PKG of the present embodiment includes a wiring board CB, a semiconductor chip CP mounted (arranged) on the upper surface CBa of the wiring board CB, and the semiconductor chip CP and the wiring. It has a resin portion (underfill resin portion) UFR that fills the space between the substrate CB and a plurality of solder balls (external terminals, bump electrodes, solder bumps) BA provided on the lower surface CBb of the wiring substrate CB.

  The semiconductor chip CP has a rectangular (quadrangle) planar shape that intersects its thickness. For example, various semiconductor elements or semiconductor integrated circuits are formed on the main surface of a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like. Thereafter, the semiconductor substrate is separated into each semiconductor chip and manufactured by dicing or the like.

  The semiconductor chip CP has a front surface CPa that is a main surface on the semiconductor element formation side and a back surface CPb that is a main surface opposite to the front surface CPa, and a plurality of bondings are formed on the front surface CPa of the semiconductor chip CP. Pads (pad electrodes, electrode pads) PD are formed, and a plurality of bump electrodes (projection electrodes, projection electrodes) BP, which are projection electrodes, are formed on the plurality of bonding pads PD, respectively. Accordingly, in the semiconductor chip CP, the main surface on the side where the bonding pad PD (and the bump electrode BP thereon) is formed is the surface CPa of the semiconductor chip CP, and the main surface on the opposite side is the surface of the semiconductor chip CP. It becomes the back surface CPb.

  Each bonding pad PD of the semiconductor chip CP and the bump electrode BP on the bonding pad PD are electrically connected to a semiconductor element or a semiconductor integrated circuit formed inside or on the surface layer of the semiconductor chip CP via an internal wiring layer of the semiconductor chip CP. It is connected to the. The bump electrode BP is a protruding electrode and functions as a mounting electrode for flip-chip connecting the semiconductor chip CP onto the wiring substrate CB. The bump electrode BP is, for example, a gold bump (a bump electrode made of gold).

  Further, the bonding pad PD and the bump electrode BP thereon are provided on the peripheral portion (peripheral portion) of the surface CPa of the semiconductor chip CP.

  In the semiconductor device PKG, the semiconductor chip CP is flip-chip mounted on the upper surface CBa of the wiring board CB. That is, the semiconductor chip CP has the back surface CPb side of the semiconductor chip CP facing upward, and the front surface CPa of the semiconductor chip CP faces the upper surface CBa of the wiring substrate CB, and the wiring substrate CB is connected via the plurality of bump electrodes BP. It is mounted (mounted) on the upper surface CBa. Therefore, the semiconductor chip CP is face-down bonded to the upper surface CBa of the wiring board CB.

  The plurality of bump electrodes BP on the surface CPa of the semiconductor chip CP are respectively joined to the plurality of bonding leads (bonding fingers, lands, conductive lands, substrate-side terminals, electrodes) BL on the upper surface CBa of the wiring board CB. Therefore, the plurality of bump electrodes BP on the surface CPa of the semiconductor chip CP are electrically and mechanically connected to the plurality of bonding leads BL on the upper surface CBa of the wiring board CB, respectively. Accordingly, the plurality of bonding pads PD on the surface CPa of the semiconductor chip CP are respectively joined and electrically connected to the plurality of bonding leads BL on the upper surface CBa of the wiring board CB via the bump electrodes BP. Thus, the semiconductor integrated circuit formed on the semiconductor chip CP is electrically connected to the bonding lead BL on the upper surface CBa of the wiring board CB via the bonding pad PD and the bump electrode BP.

  In the semiconductor device PKG, a resin portion UFR as an underfill resin is filled between the semiconductor chip CP and the upper surface CBa of the wiring board CB. By the resin portion UFR, the connection portion between the bump electrode BP and the bonding lead BL can be sealed and protected. In addition, the resin portion UFR can buffer a burden on the bump electrode BP due to a difference in thermal expansion coefficient between the semiconductor chip CP and the wiring substrate CB. Thereby, the reliability of the semiconductor device PKG can be improved. The resin portion UFR is made of a resin material (thermosetting resin material) such as an epoxy resin, and contains a filler (silica or the like).

  The wiring board (package substrate) CB has a rectangular (quadrangle) planar shape that intersects its thickness, and has an upper surface (front surface) CBa that is one main surface and a lower surface that is a main surface opposite to the upper surface CBa ( Back surface) CBb. Of the upper surface CBa of the wiring board CB, the chip mounting area (the area where the semiconductor chip CP is mounted) has an arrangement corresponding to the arrangement of the bonding pads PD (and the bump electrodes BP thereon) on the surface CPa of the semiconductor chip CP. A plurality of bonding leads BL are arranged. In other words, when the semiconductor chip CP is mounted on the chip mounting region of the upper surface CBa of the wiring board CB, the wiring is so arranged that the plurality of bump electrodes BP of the semiconductor chip CP and the plurality of bonding leads BL of the wiring board CB face each other. A plurality of bonding leads BL are arranged in the chip mounting region on the upper surface CBa of the substrate CB.

  The chip mounting region on the upper surface CBa of the wiring board CB is a region where the semiconductor chip CP is mounted on the upper surface CBa of the wiring substrate CB at a stage after the semiconductor chip CP is mounted on the upper surface CBa of the wiring substrate CB. That is, it corresponds to a region of the upper surface CBa of the wiring board CB that overlaps the semiconductor chip CP in plan view. Further, the chip mounting area on the upper surface CBa of the wiring board CB means that the semiconductor chip CP is mounted later on the upper surface CBa of the wiring board CB in the stage before mounting the semiconductor chip CP on the upper surface CBa of the wiring board CB. Corresponds to the area to be scheduled. Therefore, the chip mounting area on the upper surface CBa of the wiring board CB indicates the same area before and after mounting the semiconductor chip CP. That is, a region of the upper surface CBa of the wiring board CB that overlaps the semiconductor chip CP in plan view when the semiconductor chip CP is mounted is a chip mounting region regardless of whether the semiconductor chip CP is mounted before or after mounting. Here, the plan view refers to a case of viewing in a plane parallel to the upper surface CBa of the wiring board CB.

  4 shows a wiring board CB used for manufacturing the semiconductor device PKG. In the wiring board CB of FIG. 4, a solder layer SD1 is formed on the bonding lead BL on the upper surface CBa of the wiring board CB. However, in the manufactured semiconductor device PKG shown in FIG. 2, the solder layer SD1 is melted and re-solidified to become solder SD2. In the semiconductor device PKG, the bump electrode BP is connected to the bonding lead BL (connected by thermocompression bonding or heat and ultrasonic waves), and is bonded and fixed via the solder SD2.

  In the semiconductor device PKG, a plurality of conductive lands (electrodes, pads, terminals) LA for connecting the solder balls BA are formed on the lower surface CBb of the wiring board CB.

  The wiring board CB is, for example, a multilayer wiring board (multilayer board) in which a plurality of insulator layers (dielectric layers) and a plurality of conductor layers (wiring layers, conductor pattern layers) are stacked and integrated. The bonding lead BL on the upper surface CBa of the wiring board CB is electrically connected to the land LA on the lower surface CBb of the wiring board CB via the wiring of the wiring board CB or via wiring formed inside the via of the wiring board CB. Has been.

  Further, a resist layer (solder resist layer, solder resist layer) SR1 which is an insulating film (insulating layer) is formed on the uppermost layer on the upper surface CBa side of the wiring board CB, and the bonding lead BL is formed of the resist layer SR1. It is exposed from the opening OP. Further, a resist layer (solder resist layer, solder resist layer) SR2 which is an insulating film (insulating layer) is formed on the uppermost layer on the lower surface CBb side of the wiring board CB, and the land LA is an opening of the resist layer SR2. It is exposed from the part.

  In the wiring board CB, the opening OP of the resist layer SR1 is formed in an annular shape (ring shape) in plan view so as to expose the plurality of bonding leads BL arranged along the four sides of the chip mounting region. That is, a plurality of bonding leads BL are exposed from one opening OP provided in a ring shape in the resist layer SR1.

  In FIG. 5, on the surface CPa of the semiconductor chip CP, five bonding pads PD and bump electrodes BP thereon are arranged along the four sides of the outer periphery, and correspondingly, in FIG. In the chip mounting portion of the upper surface CBa of the substrate CB, five bonding leads BL are arranged along the four sides of the outer periphery of the chip mounting portion and per side. This is an example. The number of arrangement (5 in the case of FIGS. 3 and 5) can be variously changed. For example, in the present embodiment, as shown in FIG. 5, a so-called peripheral structure in which a plurality of bonding pads PD and bump electrodes BP thereon are provided on the peripheral portion (peripheral portion) of the surface CPa of the semiconductor chip CP. As described above, a so-called area array in which a plurality of bonding pads PD and bump electrodes BP thereon are also provided in the central portion (region surrounded by the plurality of bonding pads PD shown in FIG. 5) on the surface CPa of the semiconductor chip CP. It may be a structure. In this case, the arrangement of the plurality of bonding leads BL provided in the chip mounting portion on the upper surface CBa of the wiring board CB is made to correspond to the arrangement of the semiconductor chips CP. That is, the bonding lead BL is also arranged in the center portion (the region surrounded by the plurality of bonding leads BL shown in FIG. 3) in the chip mounting region shown in FIG.

  For simplification of the drawings, in FIGS. 2 and 4, the bonding lead BL on the upper surface CBa of the wiring substrate CB, the land LA on the lower surface CBb of the wiring substrate CB, and the resist layer SR1 on the upper surface CBa side of the wiring substrate CB are used. In addition, except for the resist layer SR2 on the lower surface CBb side of the wiring board CB, a plurality of insulator layers and wiring layers constituting the wiring board CB are shown in an integrated manner without being separated into individual layers. Although FIG. 3 is a plan view, for easy understanding, the bonding lead BL is hatched with a thin line on the upper surface CBa of the wiring board CB, and the resist layer SR1 is formed. The area is hatched with a thick line.

  On the lower surface CBb of the wiring board CB, the lands LA are arranged (arranged) in a single or a plurality of rows along the outer periphery of the lower surface CBb of the wiring board CB. A solder ball BA is connected (formed) to each land LA. Therefore, in the semiconductor device PKG, a plurality of solder balls BA are arranged on the lower surface CBb of the wiring board CB, and the solder balls BA function as external terminals (external connection terminals) of the semiconductor device PKG. can do.

  Each bonding pad PD of the semiconductor chip CP is electrically connected to each bonding lead BL on the upper surface CBa of the wiring board CB via the bump electrode BP, and further, via the wiring of the wiring board CB and via wiring, the wiring board. The lower surface CBb of the CB is electrically connected to the land LA and the solder ball BA connected to the land LA. In addition, the plurality of solder balls BA arranged on the lower surface CBb of the wiring board CB can include solder balls that are not electrically connected to the bonding pads PD of the semiconductor chip CP, and these can be used for heat dissipation. it can.

<Manufacturing process of semiconductor device>
Next, a manufacturing method (manufacturing process) of the semiconductor device according to the present embodiment will be described.

  7 and 8 are manufacturing process flowcharts showing the manufacturing process of the semiconductor device of the present embodiment. FIG. 8 shows a process flow in which step S2 is detailed in the process flow of FIG. That is, step S2 in FIG. 7 is configured by steps S2a to S2f in FIG.

  9 to 24 are explanatory diagrams of the manufacturing process of the semiconductor device of the present embodiment, and a plan view or a cross-sectional view is shown. 9 to 24, FIGS. 9, 11, 17, 18, 20, and 22 to 24 are cross-sectional views showing cross sections corresponding to FIG. 1. 9 to 24, FIGS. 10, 12 to 16, 19, and 21 are plan views.

  In order to manufacture the semiconductor device PKG, first, the wiring board CB and the semiconductor chip CP are prepared (prepared) (step S1 in FIG. 7).

  The semiconductor chip CP is shown in FIGS. 5 and 6, and as described above, the semiconductor chip CP includes the surface CPa, the plurality of bonding pads PD formed on the surface of the semiconductor chip CP, and the plurality of bondings. Each has a plurality of bump electrodes BP formed on the pad PD and a back surface CPb opposite to the front surface CPa. The bump electrode BP can be regarded as an electrode member formed on the bonding pad PD. A Cu post (copper columnar electrode) PS, which will be described later, can also be regarded as an electrode member formed on the bonding pad PD.

  Further, the wiring board CB is shown in FIGS. 3 and 4, and as described above, the wiring board CB includes the upper surface CBa and a plurality of bonding leads BL formed in the chip mounting region of the upper surface CBa. It has a lower surface CBb opposite to the upper surface CBa and a plurality of lands LA formed on the lower surface CBb.

  The wiring board CB can be manufactured by various manufacturing methods. For example, the wiring board CB can be manufactured using a build-up method, a subtractive method, a printing method, a sheet lamination method, a semi-additive method, an additive method, or the like.

  The semiconductor substrate CP is prepared after the wiring substrate CB is prepared first, the wiring substrate CB is prepared after the semiconductor chip CP is prepared first, or the wiring substrate CB and the semiconductor chip CP are prepared simultaneously. May be. Further, when the semiconductor chip CP is not prepared in step S1, the semiconductor chip CP may be prepared until a step of arranging the semiconductor chip CP on the wiring board CB in step S2d described later is performed.

  A solder layer SD1 made of solder (solder material) is formed on the bonding lead BL on the upper surface CBa of the wiring board CB. That is, the wiring board CB having the solder layer SD1 formed on the bonding lead BL is prepared (manufactured) in step S1. As another form, after preparing the wiring board CB in which the solder layer SD1 is not formed on the bonding lead BL in step S1, before performing step S2 described later, soldering is performed on the bonding lead BL of the wiring board CB. The layer SD1 can also be formed.

  In addition, a plating layer such as an Au / Ni plating layer (a laminated plating layer of an upper Au plating layer and a lower Ni plating layer) is formed on the surface of the land LA on the lower surface CBb of the wiring board CB. However, the illustration is omitted here.

  Next, a resin supply and flip chip connection process is performed (step S2 in FIG. 7). The resin supply and flip-chip connection process in step S2 has several sub-steps (corresponding to S2a to S2f in FIG. 8). That is, by performing the following steps S2a to S2f, the resin supply and flip chip connection process of step S2 is performed.

  First, as shown in FIG. 9 (cross-sectional view), the wiring board CB is placed (placed) on a stage (heating stage, heat stage, placement stage) STG heated (set) to a temperature T2. (Step S2a in FIG. 8). At this time, the wiring substrate CB is disposed on the stage STG so that the lower surface CBb of the wiring substrate CB faces the upper surface of the stage STG, in other words, the upper surface CBa of the wiring substrate CB faces upward.

  The stage STG incorporates a heating mechanism such as a heater, and is heated (set) to a desired temperature so that the temperature can be maintained. In step S2a, the wiring board CB is placed on the stage STG that is heated (set) and held at the temperature T2. As a result, the wiring substrate CB disposed on the stage STG is also heated to almost the temperature T2. The temperature T2 is preferably 50 to 100 ° C., and is set to about 75 ° C., for example.

  Next, in the wiring board CB heated by being disposed on the stage STG, as shown in FIG. 10 (plan view) and FIG. 11 (cross-sectional view), a chip mounting scheduled area on the upper surface CBa of the wiring board CB Next, a paste-like (fluid) resin RS is arranged (supplied and applied) (step S2b in FIG. 8).

  This resin RS will later become the resin portion (underfill resin) UFR. The resin RS is a thermosetting resin, but contains an expandable filler (filler FL1 described later) and another filler (filler FL2 described later). The material of the resin RS will be further described later.

  In step S2b, as shown in FIG. 11, the resin RS is supplied from the resin supply nozzle (resin coating device nozzle, resin supply device nozzle) NZL to the chip mounting planned area of the upper surface CBa of the wiring board CB. . The temperature of the nozzle NZL is set to a temperature T1, and this temperature T1 is lower than the temperature T2 of the stage STG (that is, T1 <T2). By setting the temperature of the nozzle NZL to the temperature T1, the temperature of the resin RS in the nozzle NZL is substantially the temperature T1. Therefore, immediately before the resin RS is supplied onto the wiring board CB from the nozzle NZL, immediately after the supply, and immediately after the supply, the temperature of the resin RS (approximately equal to the temperature T1) is the temperature of the wiring board CB (approximately the same). It is lower than the temperature T2. The temperature T1 is set to about 30 to 50 ° C., for example.

  In step S2b, it is preferable to apply the resin RS from the nozzle NZL in a plurality of directions intersecting each other in the chip mounting region on the upper surface CBa of the wiring board CB. An example of this will be described with reference to FIGS.

  In step S2b, first, as shown in FIG. 12, in the chip mounting region on the upper surface CBa of the wiring board CB, the resin RS is applied in the direction DR1 indicated by the arrow, and the resin RS applied along the direction DR1. Is shown in FIG. 12 as resin RS1. Then, as shown in FIG. 13, in the chip mounting region on the upper surface CBa of the wiring board CB, the resin RS is applied in the direction DR2 indicated by the arrow, and the resin RS applied along the direction DR2 is used as the resin RS2. This is shown in FIG. Then, as shown in FIG. 14, in the chip mounting region on the upper surface CBa of the wiring board CB, the resin RS is applied in the direction DR3 indicated by the arrow, and the resin RS applied along the direction DR3 is used as the resin RS3. It is shown in FIG. Then, as shown in FIG. 15, in the chip mounting region of the upper surface CBa of the wiring board CB, the resin RS is applied in the direction DR4 indicated by the arrow, and the resin RS applied along the direction DR4 is used as the resin RS4. It is shown in FIG. The directions DR1, DR2, DR3, DR4 are directions that cross each other. In this manner, in the chip mounting region on the upper surface CBa of the wiring board CB, the resin RS is applied from the nozzle NZL in a plurality of directions intersecting with each other (DR1, DR2, DR3, DR4 in the case of FIGS. 12 to 15). Can do. As a result, the resin RS can be easily arranged evenly on the chip mounting region of the upper surface CBa of the wiring board CB, and when the semiconductor chip CP is mounted on the wiring board CB later, the wiring RS is not located between the wiring board CB and the semiconductor chip CP. It becomes easy to spread the resin RS evenly over the entire area.

  In the present embodiment, an example in which one nozzle NZL, that is, resin RS is supplied onto the wiring board CB through one supply path has been described. However, a so-called multi-channel having a plurality of supply paths is provided. When a nozzle is used, it is possible to omit a plurality of operations at once. Furthermore, the number of steps shown in FIGS. 12 to 15 can be reduced by using a nozzle having a cross-shaped nozzle (X-shaped or + -shaped).

  Next, as shown in FIG. 16 (plan view) and FIG. 17 (cross-sectional view), a process for increasing the viscosity of the resin RS is performed (step S2c in FIG. 8). That is, in step S2c, the viscosity of the resin RS is increased to a viscosity V2 that is higher than the viscosity V1. The increase in the viscosity of the resin RS in step S2c can be realized by expanding the expandable filler contained in the resin RS.

  In step S2c, the viscosity of the resin RS is increased (increased or increased) by expanding a filler (corresponding to an expandable filler FL1 described later) contained in the resin RS instead of causing a crosslinking reaction in the resin RS. Let Specifically, the state in which the resin RS is disposed on the wiring board CB heated to the temperature T2 by the stage STG set (heated) at the temperature T2 is maintained for a predetermined time to increase the temperature of the resin RS. Along with this, an expandable filler (corresponding to an expandable filler FL1 described later) contained in the resin RS expands to increase (increase) the viscosity of the resin RS.

  That is, in step S2c, the stage STG is heated (set) to the temperature T2, and the wiring board CB is heated to almost the temperature T2 by the stage STG, so that the resin RS disposed on the wiring board CB is also heated. As a result, the temperature of the resin RS rises (rises to a temperature T2), whereby the expandable filler in the resin RS expands and the viscosity of the resin RS rises. For this reason, at the temperature T2, the expandable filler contained in the resin RS (corresponding to the expandable filler FL1 described later) expands and the viscosity of the resin RS rises accurately, but the crosslinking reaction occurs too much in the resin RS. Set the temperature so that it does not exist. The temperature T2 is preferably 50 to 100 ° C., and is set to about 75 ° C., for example.

  If the viscosity of the resin RS when the resin RS is arranged (supplied) on the wiring board CB in step S2b is the viscosity V1, the viscosity of the resin RS increases (increases) to a viscosity V2 larger than the viscosity V1 in step S2c. (Ie, V2> V1). The viscosity increase (viscosity increase) step in step S2c will be further described later.

  Next, as shown in FIG. 18 (cross-sectional view), FIG. 19 (plan view), and FIG. 20 (cross-sectional view), the semiconductor chip CP is disposed in the chip mounting planned region of the upper surface CBa of the wiring board CB (FIG. 8). Step S2d).

  18 is a cross-sectional view schematically showing a state in which the semiconductor chip CP held by the tool TL is approaching the wiring board CB, and the cross-sectional view of FIG. 20 shows wiring of the semiconductor chip CP from the state of FIG. A state in which the tip of the bump electrode BP of the semiconductor chip CP is in contact with the bonding lead BL (upper solder layer SD1) of the upper surface CBa of the wiring substrate CB is shown closer to the substrate CB. FIG. 19 is a plan view of the state of FIG. 20, but the tool TL is not shown in FIG.

  In Step S2d, the semiconductor chip CP is mounted on the chip mounting region of the upper surface CBa of the wiring substrate CB via the resin RS and the plurality of bump electrodes BP so that the surface CPa of the semiconductor chip CP faces the upper surface CBa of the wiring substrate CB. To place. Since the resin RS is disposed in the chip mounting scheduled area of the wiring substrate CB in step S2b, the semiconductor chip CP is disposed in the chip mounting planned area in which the resin RS is disposed in step S2d. .

  Specifically, the back surface CPb of the semiconductor chip CP is held (sucked) by a tool (bonding tool, bonding head) TL, and the semiconductor chip CP held (sucked) by the tool TL is wired as shown in FIG. Close to the substrate CB, as shown in FIG. 19 and FIG. 20, it is arranged in the chip mounting planned area on the upper surface CBa of the wiring substrate CB. The semiconductor chip CP faces down on the upper surface CBa of the wiring substrate CB so that the back surface CPb side of the semiconductor chip CP faces upward and the front surface CPa side of the semiconductor chip CP faces downward (that is, the upper surface CBa side of the wiring substrate CB). The plurality of bump electrodes BP on the surface CPa of the semiconductor chip CP are aligned so as to face the plurality of bonding leads BL on the upper surface CBa of the wiring board CB. Since the solder layer SD1 is formed on the bonding lead BL, the bump electrode BP is in contact with the solder layer SD1 on the bonding lead BL.

  In step S2d, in a state where the paste-like (that is, fluid) resin RS is arranged in the chip mounting scheduled region on the upper surface CBa of the wiring board CB (that is, in a state where the resin RS is not cured), the semiconductor chip CP. Are arranged in a chip mounting planned area on the upper surface CBa of the wiring board CB. For this reason, the resin RS is expanded by the semiconductor chip CP (the front surface CPa), and the resin RS spreads over the entire region between the semiconductor chip CP (the front surface CPa) and the wiring substrate CB (the upper surface CBa). . As a result, the resin RS is filled between the wiring board CB (the upper surface CBa) and the semiconductor chip CP (the front surface CPa).

  In step S2d, the tool TL is heated (set) to the temperature T3. For this reason, in step S2d, the semiconductor chip CP held by the tool TL is also heated to substantially the temperature T3.

  In step S2d, the temperature T3 of the tool TL is preferably set to a temperature lower than the solder melting point (melting point of the solder constituting the solder layer SD1).

  In step S2d, it is preferable to set the temperature T3 of the tool TL to a temperature at which the crosslinking reaction does not proceed so much in the resin RS in contact with the semiconductor chip CP (therefore, the resin RS is not thermally cured). As a result, in step S2d, the resin RS is prevented from being thermally cured, and the resin RS can be accurately spread over the entire region between the semiconductor chip CP (the front surface CPa) and the wiring substrate CB (the upper surface CBa). it can.

  However, if the temperature T3 of the tool TL is too low, the total time required for step S2d and step S2e may be increased. Therefore, the temperature T3 of the tool TL is preferably set to a somewhat high temperature.

  Therefore, in step S2d, it is preferable to set the temperature T3 of the tool TL to a high temperature as long as the solder layer SD does not melt and the thermal curing (curing by the crosslinking reaction) of the resin RS does not proceed so much.

  From such a viewpoint, the temperature T3 of the tool TL in step S2d is preferably 100 to 220 ° C. Thereby, in step S2d, the total time required for step S2d and step S2e can be shortened while preventing melting of the solder layer SD1 and suppressing thermal curing (curing by the crosslinking reaction) of the resin RS. The solder melting point (melting point of the solder constituting the solder layer SD1) is approximately 220 ° C. or higher.

  In addition, the temperature (heating temperature) of the stage STG in step S2d is such that the cross-linking reaction occurs so much in the resin RS on the wiring board CB before the semiconductor chip CP held and heated by the tool TL contacts the resin RS. It is preferable to set it to a temperature that does not (does not advance). From this viewpoint, the temperature (heating temperature) of the stage STG in step S2d is preferably about 70 to 100 ° C. Thereby, since the cross-linking reaction in the resin RS can be suppressed or prevented until the semiconductor chip CP held and heated by the tool TL contacts the resin RS, the viscosity of the resin in step S2d is set to a suitable viscosity range. It becomes easier to control. Also, the total time required for step S2d and step S2e can be shortened.

  After the semiconductor chip CP is arranged on the upper surface CBa of the wiring board CB in step S2d, the temperature of the tool TL is quickly raised to the temperature T4 as shown in FIGS. 21 and 22, and the semiconductor chip CP is used by the tool TL. By applying a predetermined load to the back surface CPb, the semiconductor chip CP is pressed (pressed) toward the wiring board CB by the tool TL (step S2e in FIG. 8). In step S2e, the tool TL is heated (set) to a temperature T4, and this temperature T4 is higher than the temperature T3 (tool temperature T3 in step S2d) (ie, T4> T3). That is, in step S2d, the temperature of the tool TL is the temperature T3, but in step S2e, the temperature of the tool TL is increased from the temperature T3 to the temperature T4. For this reason, in step S2e, the semiconductor chip CP held by the tool TL is also heated to substantially the temperature T4 (that is, the temperature of the semiconductor chip CP increases from approximately the temperature T3 to approximately the temperature T4).

  In step S2e, the heated tool TL presses the semiconductor chip CP to the wiring board CB side with a predetermined load (pressure), thereby pressing (pressurizing) the semiconductor chip CP to the wiring board CB side while being heated by the tool TL. Accordingly, the bump electrode BP is pressed and connected to the bonding lead BL while being heated.

  In step S2e, the back surface CPb of the semiconductor chip CP is pressed with the tool TL, thereby pressing the semiconductor chip CP toward the wiring board CB. In step S2e, the back surface CPb of the semiconductor chip CP is pressed with the tool TL. It is more preferable to apply ultrasonic waves from the tool TL to the semiconductor chip CP. By applying ultrasonic waves by pressing the back surface CPb of the semiconductor chip CP with the tool TL, ultrasonic waves can be applied to the connection portion (contact portion) between the bump electrode BP and the bonding lead BL, and bonding with the bump electrode BP is performed. The lead BL can be more reliably connected (joined).

  Accordingly, in step S2e, heat (more preferably heat and ultrasonic waves) is applied to the connection portion between the bump electrode BP and the bonding lead BL while the bump electrode BP is pressed against the bonding lead BL.

  The temperature of the tool TL can be raised, for example, by heating the tool TL with a heating mechanism (such as a heater) built in the tool TL. When the tool TL is heated, the semiconductor chip CP pressed by the tool TL is also heated, the bump electrode BP bonded to the bonding pad PD of the semiconductor chip CP is also heated, and the heated bump electrode BP is bonded to the bonding lead BL. Therefore, the bonding lead BL and the solder layer SD1 on the surface of the bonding lead BL are also heated.

  The solder layer SD1 is formed on the bonding lead BL. In step S2e, it is preferable to set the temperature TL of the tool TL so that the solder layer SD1 is melted. That is, at least the temperature T4 of the tool TL is set to a temperature higher than the solder melting point, and preferably, the temperature T4 of the tool TL is set to a temperature sufficient to melt the solder layer SD1. Note that the solder melting point is a melting point of solder that contributes to the connection between the electrode member (here, the bump electrode BP) of the semiconductor chip CP and the bonding lead BL of the wiring board CB. Here, the solder layer SD1 is formed. This corresponds to the melting point of the solder, and in the case of modified examples shown in FIGS. 30 to 33 described later, this corresponds to the melting point of the solder constituting the solder layers SD1 and SD3.

  Thereby, in step S2e, the temperature of the semiconductor chip CP and the bump electrode BP becomes higher than the solder melting point, the temperature of the solder layer SD1 in contact with the bump electrode BP becomes higher than the solder melting point, and the solder layer SD1. Melts to become solder SD2 (molten solder SD2). Therefore, in step S2e, the solder layer SD1 is melted and the plurality of bump electrodes BP of the semiconductor chip CP and the plurality of bonding leads BL of the wiring board CB are in contact with each other. At this time, it is more preferable that the bump electrode BP pressed in contact with the bonding lead BL is connected (crimped) to the bonding lead BL by heat or heat and ultrasonic waves. Then, the solder SD2 (molten solder SD2) composed of the melted solder layer SD1 surrounds the connection portion between the bump electrode BP and the bonding lead BL, and is wetted around the bump electrode BP. . In step S2e, the solder SD2 is in a molten state, but after the completion of step S2e, the solder SD2 is solidified as the temperature decreases, and the bump electrode BP is connected to the bonding lead BL via the solder SD2 (solidified solder SD2). Will be joined. Therefore, the bump electrode BP is pressed against the bonding lead BL while being heated, so that the bump electrode BP is pressed against the bonding lead BL and bonded via the solder SD2.

  In step S2e, the state in which the semiconductor chip CP is pressed by the tool TL toward the wiring substrate CB side (the state in which the bump electrode BP is pressed against the bonding lead BL while being heated) is maintained for a predetermined time.

  In step S2e, while the resin RS is filled between the wiring board CB (the upper surface CBa) and the semiconductor chip CP (the front surface CPa), the semiconductor chip CP is heated to the wiring board CB side with the tool TL. In order to press, resin RS (resin RS between wiring board CB and semiconductor chip CP) will also be heated. Since the resin RS is a thermosetting resin, the resin RS is cured by heating the resin RS in step S2e. That is, in step S2e, the resin RS is cured by a crosslinking reaction. That is, in step S2e, the resin RS is heated to a temperature at which the crosslinking reaction of the resin RS occurs (advances), whereby the resin RS is cured by the crosslinking reaction.

  For this reason, in step S2e, the temperature T4 of the tool TL is set so that the solder layer SD1 is melted and the thermosetting of the resin RS (curing by the crosslinking reaction) proceeds, so that the bump electrode BP via the solder is Bonding with the bonding lead BL and thermosetting of the resin RS are performed.

  From such a viewpoint, the temperature T4 of the tool TL in step S2e is preferably 220 to 400 ° C. Thereby, in step S2e, the solder layer SD1 can be melted and the resin RS can be cured (cured by a crosslinking reaction).

  The load applied to the back surface CPb of the semiconductor chip CP by the tool TL in step S2e depends on the viscosity of the resin RS and the area of the semiconductor chip CP, but the distance (distance) between the semiconductor chip CP and the wiring substrate CB. ) Is set to such a load that can reach the distance (distance) at which the bump electrode BP and the bonding lead BL can be joined.

  As described above, in step S2e, the back surface CPb of the semiconductor chip CP is pressed by the tool TL, whereby the plurality of bump electrodes BP of the semiconductor chip CP and the plurality of bonding leads BL of the wiring substrate CB are brought into contact with each other, and the plurality of bumps are contacted. The resin RS is cured by setting the joint portion between the electrode BP and the plurality of bonding leads BL to a temperature T5. The temperature T5 is higher than the temperatures T1 and T2 (T5> T1, T5> T2), preferably higher than the solder melting point (melting point of the solder constituting the solder layer SD1). Moreover, it is temperature which can accelerate | stimulate the crosslinking reaction of resin RS and can harden resin RS. Since the semiconductor chip CP is heated by the tool TL and the joint between the bump electrode BP and the bonding lead BL is also heated, in step S2e, the temperature (T5) of the joint between the bump electrode BP and the bonding lead BL is It almost corresponds to the temperature (T4) of the tool TL.

  Further, the temperature (heating temperature) of the stage STG in step S2e is preferably about the same as the temperature (heating temperature) of the stage STG in step S2d. If the temperature (heating temperature) of the stage STG in step S2d is the same as the temperature (heating temperature) of the stage STG in step S2e, the temperature control of the stage STG can be easily performed when sequentially manufacturing a plurality of semiconductor devices. Thus, the throughput of the semiconductor device can be improved. For this reason, the temperature (heating temperature) of the stage STG in step S2e is preferably about 70 to 100 ° C. as in step S2d.

  In step S2e, the semiconductor chip CP is pressed against the wiring board CB for a predetermined time while the semiconductor chip CP is heated by the tool TL (more preferably, ultrasonic waves are also applied), and then the semiconductor chip CP is pressed by the tool TL. Then, as shown in FIG. 23, the tool TL is separated from the semiconductor chip CP (step S2f in FIG. 8). As a result, the semiconductor chip CP is not pressed against the wiring board CB side, but the resin RS is already cured, and the bump electrodes BP of the semiconductor chip CP are bonded to the bonding leads BL of the wiring board CB. The semiconductor chip CP is fixed (fixed) to the wiring board CB.

  If the tool TL is moved away from the semiconductor chip CP in step S2f, the semiconductor chip CP is no longer heated by the tool TL, so that the temperature of the semiconductor chip CP is lowered and the periphery of the connection portion between the bump electrode BP and the bonding lead BL is reduced. The solder SD2 existing in the solder is solidified, and the bump electrode BP and the bonding lead BL are firmly joined (connected) with the solidified solder SD2. The wiring board CB (the upper surface CBa) and the semiconductor chip CP (the front surface CPa) are filled with a cured resin RS. The cured resin RS is an underfill resin. This is the resin part UFR. That is, the resin portion UFR that fills between the semiconductor chip CP and the wiring substrate CB is formed by the cured resin RS.

  The semiconductor chip CP is mounted (mounted) on the upper surface CBa of the wiring board CB by performing the resin supply and the flip chip connection process in step S2 having steps S2a, S2b, S2c, S2d, S2e, and S2f. A structure in which the resin part UFR is filled between the wiring board CB and the semiconductor chip CP can be obtained.

  The plurality of bump electrodes BP on the surface CPa of the semiconductor chip CP are respectively joined and electrically connected to the plurality of bonding leads BL on the upper surface CBa of the wiring board CB. Accordingly, the plurality of bonding pads PD on the surface CPa of the semiconductor chip CP are respectively joined and electrically connected to the plurality of bonding leads BL on the upper surface CBa of the wiring board CB via the bump electrodes BP. Further, the resin portion UFR as an underfill resin is filled between the semiconductor chip CP and the upper surface CBa of the wiring board CB.

  Next, as shown in FIG. 24, the solder ball BA is connected (bonded and formed) to the land LA on the lower surface CBb of the wiring board CB (step S3 in FIG. 7).

  In the solder ball BA connecting step of step S3, for example, the lower surface CBb of the wiring board CB is directed upward, and the solder balls BA are respectively arranged (mounted) on the plurality of lands LA of the lower surface CBb of the wiring board CB, and then flux is used. The solder ball BA and the land LA on the lower surface CBb of the wiring board CB can be joined by temporarily fixing and performing a reflow process (solder reflow process, heat treatment) to melt the solder. Thereafter, a cleaning process may be performed as necessary to remove the flux and the like attached to the surface of the solder ball BA. In this manner, the solder balls BA as external terminals (external connection terminals) of the semiconductor device PKG are joined (formed).

  In the present embodiment, the case where the solder ball BA is joined as the external terminal of the semiconductor device PKG has been described. However, the present invention is not limited to this. For example, instead of the solder ball BA, a printing method or the like may be used on the land LA. It is also possible to form external terminals (bump electrodes, solder bumps) made of solder of the semiconductor device PKG by supplying solder. In this case, solder is supplied to the plurality of lands LA on the lower surface CBb of the wiring board CB, and then solder reflow processing is performed, so that external terminals (bump electrodes, solder bumps) made of solder are respectively formed on the plurality of lands LA. Can be formed. Also, an external terminal (bump electrode) can be formed on each land LA by performing a plating process or the like.

  Thus, in step S3, external connection terminals (here, solder balls BA) are respectively formed on the plurality of lands LA on the lower surface CBb of the wiring board CB.

  In this way, the semiconductor device PKG is manufactured.

  As another form, a multi-piece wiring board can be used as the wiring board. In this case, the wiring board prepared in step S1 is a multi-piece wiring board having a plurality of semiconductor device regions. In step S2, resin supply and flipping are performed on the plurality of semiconductor device regions of the wiring substrate. A chip connection process is performed, and in step S3, a solder ball connection process is performed on a plurality of semiconductor device regions of the wiring board. Thereafter, the wiring board is cut and divided into semiconductor devices, whereby a semiconductor device can be manufactured from each semiconductor device region.

<Resin supply system>
In a semiconductor device manufactured by flip chip bonding (FCB: Flip Chip Bonding), a bonding portion between an electrode member (bump electrode, columnar electrode, etc.) formed on a bonding pad of a semiconductor chip and a bonding lead of a wiring board is made of resin ( Protection (sealing) with an underfill resin is effective in improving the reliability of the semiconductor device.

  As a method of forming (supplying) this resin (underfill resin), for example, after placing a semiconductor chip on a wiring board, a resin (a paste-like resin material) having fluidity between the semiconductor chip and the wiring board is used. There is a post-injection method to supply. In addition, there is a pre-coating method in which a resin having fluidity is arranged in advance in a chip mounting scheduled area on the wiring board before the semiconductor chip is arranged on the wiring board.

  In recent years, the pitch of bonding pads (pad pitch) in a semiconductor chip tends to be reduced due to the influence of miniaturization and high functionality of a semiconductor device. As a result, the interval between the electrode members (bump electrodes, columnar electrodes, etc.) formed on the bonding pad is becoming narrower. For this reason, in the case of the post-injection method in which the resin is supplied after mounting the semiconductor chip, it is difficult to fill the resin between the semiconductor chip and the wiring board (the resin is difficult to spread and spread). In this case, it is preferable to adopt the pre-coating method rather than the post-injection method.

<Examination of pre-coating method>
Thus, various studies were made on the pre-coating method, and it was found by the inventors that the following problems occur depending on the viscosity of the resin used.

  First, if the viscosity of the resin is too low, the resin wettability (easiness of wetting and spreading) on the wiring board is good, but the resin will wet and spread more than necessary. When placed above, the resin hardly remains in the vicinity of the joint between the electrode member (bump electrode, columnar electrode, etc.) and the bonding lead. That is, voids (voids formed in the underfill resin) are generated.

  On the other hand, when the viscosity of the resin is increased, the above-described voids are less likely to be generated, but the resin wettability (easiness of spreading) on the wiring board is reduced, or the resin is difficult to be supplied from the resin supply nozzle. Become.

  For this reason, the viscosity of the resin to be used is preferably not too low and not too high, and is desirably set within a desired range.

  Then, when this inventor performed the flip chip process using resin which consists of said viscosity in said desired range, the following subject was newly discovered.

  That is, when the resin to be used is a thermosetting resin, as shown in FIG. 25, when a certain temperature T6 is reached, a crosslinking reaction (a reaction for curing the resin) starts, but the temperature just before reaching this certain temperature T6. Then, it turned out that the viscosity of resin becomes low compared with the normal temperature.

  Here, FIG. 25 is a graph schematically showing the viscosity of the thermosetting resin. The horizontal axis of the graph of FIG. 25 corresponds to the temperature of the resin, and the vertical axis of the graph of FIG. Corresponds to an arbitrary unit).

  As shown in the graph of FIG. 25, when the temperature of the resin is increased, the crosslinking reaction hardly occurs at a temperature lower than the temperature T6. However, when the temperature is higher than the temperature T6, the crosslinking reaction occurs and the resin is cured. The viscosity of the resin increases rapidly. In the temperature range where the crosslinking reaction does not occur (range lower than the temperature T6), the higher the resin temperature, the lower the resin viscosity.

  Curing by the cross-linking reaction is an irreversible change. Once the cross-linking reaction occurs and the viscosity increases (becomes a cured state), even if the temperature is lowered, it does not return to the low-viscosity state before curing and remains cured. However, if the temperature is within a temperature range where the cross-linking reaction does not occur (range lower than the temperature T6), the viscosity decreases as the temperature increases, and the viscosity increases as the temperature decreases and returns to the original temperature. Will return to its original viscosity.

  For this reason, when comparing the resin when the resin is supplied onto the wiring board by the first coating method and the resin when the semiconductor chip is arranged on the wiring board in the flip chip mounting process, the latter should be hotter. For example, the latter has a lower viscosity.

  When the resin is supplied onto the wiring board by the pre-coating method, it is necessary to prevent the crosslinking reaction from occurring as much as possible in the resin. If a cross-linking reaction occurs in the resin in the resin supply nozzle, the viscosity of the resin may increase, making it difficult to supply (apply and discharge) the resin from the nozzle onto the wiring board. For this reason, when the resin is supplied onto the wiring substrate by the pre-coating method, it is preferable to set the temperature of the resin to a certain level in order to prevent the resin crosslinking reaction from occurring. On the other hand, when the semiconductor chip is placed on the wiring board in the flip chip mounting process, if the temperature of the resin placed on the wiring board is too low, the time required for subsequent resin curing becomes longer and the throughput decreases. There is a risk of doing. For this reason, when the semiconductor chip is arranged on the wiring substrate in the flip chip mounting process, it is preferable to set the temperature of the resin to be somewhat high. Therefore, when comparing the resin when the resin is supplied onto the wiring board by the first coating method and the resin when the semiconductor chip is arranged on the wiring board in the flip chip mounting process, the temperature of the latter resin is compared. It is preferable that the temperature is higher than the temperature of the resin.

  As a result, the temperature of the resin when the semiconductor chip is arranged on the wiring substrate in the flip chip mounting process becomes higher than the temperature of the resin when the resin is supplied onto the wiring substrate by the pre-coating method. The viscosity of the resin when the semiconductor chip is arranged on the wiring board in the flip chip mounting process is lower than the viscosity of the resin when the resin is supplied onto the wiring board by the method. As a result, when the semiconductor chip is arranged on the wiring board in the flip chip mounting process, the resin viscosity is low, so that the resin spreads more than necessary on the wiring board, and the electrode member (bump electrode, columnar electrode) Etc.) and the bonding lead in the vicinity of the bonding lead, it becomes difficult for the resin to remain, and voids (voids formed in the underfill resin) are generated. Generation | occurrence | production of a void will reduce the reliability of the manufactured semiconductor device.

  The inventor is also considering setting the temperature of the stage on which the wiring board is placed to a temperature higher than the normal temperature. By setting the temperature of the stage on which the wiring board is arranged to a temperature higher than room temperature, the flip chip mounting process can be performed in as short a time as possible. Therefore, the wiring board arranged on the stage and further the resin arranged on the wiring board are heated together. As a result, when the temperature of the stage is higher than the temperature of the resin when placed on the wiring board, the semiconductor chip is placed on the wiring board when the semiconductor chip is placed on the wiring board in the subsequent flip chip mounting process. The viscosity of the resin becomes lower than the viscosity when the resin is placed on the wiring board, and the above voids are generated.

  In addition, when the semiconductor chip is arranged on the wiring substrate in the flip chip mounting process, the resin viscosity is lowered by the amount of the resin temperature higher than when the resin is supplied onto the wiring substrate by the first coating method. In consideration of the above, as shown by a dotted line in the graph of FIG. 25, a method of using a resin in which the viscosity at the time of application in the first application method is higher than the desired viscosity (upper limit value in the desired range). Is also possible. However, this method is not effective for the above-described reason that it becomes difficult to supply (discharge) the resin onto the wiring board from the nozzle for supplying the resin at the time of application by the first application method.

  In other words, in the case of the viscosity curve indicated by the solid line in the graph of FIG. 25, the semiconductor chip is connected to the wiring board in the flip chip mounting process even if the resin viscosity is just good when the resin is supplied onto the wiring board by the pre-coating method. When placed on the top, the viscosity of the resin is too low, and voids (voids formed in the underfill resin) may occur. On the other hand, in the case of the viscosity curve indicated by the dotted line in the graph of FIG. 25, even if the viscosity of the resin when the semiconductor chip is arranged on the wiring board in the flip chip mounting process is just right, it is applied on the wiring board by the first coating method. When the resin is supplied, since the viscosity of the resin is too high, it may be difficult to supply (apply and discharge) the resin from the resin supply nozzle onto the wiring board. Therefore, in the case of the viscosity curve as shown in FIG. 25, the resin is used both when supplying the resin onto the wiring board by the first coating method and when placing the semiconductor chip on the wiring board in the flip chip mounting process. It is difficult to optimize the viscosity.

<About main features>
On the other hand, in the present embodiment, the pre-coating method is adopted, but between step S2b in which the resin RS is arranged on the wiring substrate CB and step S2d in which the semiconductor chip CP is arranged on the wiring substrate CB. In addition, step S2c, which is a process for increasing the viscosity of the resin RS, is performed.

  FIG. 26 is a graph schematically showing the viscosity of the resin (RS) used in the present embodiment. The horizontal axis of the graph of FIG. 26 corresponds to the temperature of the resin, and the vertical axis of the graph of FIG. 26 is the resin. Corresponds to an arbitrary unit (arbitrary unit).

  In the present embodiment, the resin RS is arranged (supplied) on the wiring board CB in step S2b, and the viscosity of the resin RS at this time is set to the viscosity V1. That is, in step S2b, the resin RS having the viscosity V1 is arranged (supplied) on the wiring board CB. In step S2d, the semiconductor chip CP is disposed on the wiring board CB. At this time, the viscosity of the resin RS is set to the viscosity V3. That is, in step S2d, the semiconductor chip CP is disposed on the wiring board CB via the resin RS having a viscosity V3. In step S2c (step S2c is performed after step S2b and before step S2d), the viscosity of the resin RS is increased to a viscosity V2 higher than the viscosity V1 (V2> V1). That is, the viscosity of the resin RS becomes the viscosity V2 by step S2c, but this viscosity V2 is higher than the viscosity V1 of the resin RS in step S2b.

  In step S2b, the resin RS having the viscosity V1 can be arranged (supplied) on the wiring board CB by adjusting the temperature of the resin supply nozzle NZL. Specifically, for the resin RS, when the resin temperature at which the viscosity becomes the viscosity V1 is the temperature T1, by setting the temperature of the resin supply nozzle NZL to the temperature T1, the nozzle in step S2b A resin RS having a viscosity V1 from NZL can be arranged (supplied) on the wiring board CB.

  One of the main features of the present embodiment is that the viscosity increasing step of Step S2c is performed. Unlike the present embodiment, when the viscosity increasing step of Step S2c is not performed, as described with reference to the graph of FIG. 25, the viscosity V3 of the resin RS in Step S2d is the same as that of the resin RS in Step S2b. It becomes considerably lower than the viscosity V1.

  On the other hand, in the present embodiment, the viscosity increasing step of step S2c is performed. For this reason, assuming that the viscosity V1 of the resin RS in step S2b is the same, the case where the viscosity increasing step of step S2c is not performed and the case where the viscosity increasing step of step S2c is performed (corresponding to the present embodiment) are compared. The viscosity V3 of the resin RS in step S2d can be higher when the viscosity increasing step in step S2c is performed (corresponding to the present embodiment).

  That is, in this embodiment, between steps S2b and S2d, by increasing the viscosity of the resin RS in step S2c, the viscosity in step S2b does not have to be increased in step S2d. The viscosity V3 of the resin RS can be increased.

  Unlike the present embodiment, when the viscosity increasing step of Step S2c is not performed, in order to increase the viscosity V3 of the resin RS in Step S2d, the viscosity V1 of the resin RS in Step S2b must be increased. If the viscosity V1 of the resin RS in step S2b is too high, there is a concern that it is difficult to supply the resin RS onto the wiring board CB from the resin supply nozzle NZL in step S2b. Further, unlike the present embodiment, when the viscosity increasing step of step S2c is not performed, the resin viscosity V1 in step S2b is set to a viscosity suitable for performing step S2b. There is a concern that the viscosity V3 of RS becomes too low and the resin RS wets and spreads more than necessary, making it difficult for the resin RS to remain in the vicinity of the joint between the bump electrode BP and the bonding lead BL, resulting in a void. That is, unlike the present embodiment, when the viscosity increasing step in step S2c is not performed, both the viscosity V1 of the resin RS in step S2b and the viscosity V3 of the resin RS in step S2d are optimized. It is difficult.

  Therefore, as in the present embodiment, the viscosity of step S2c is after step S2b in which resin RS is arranged on wiring substrate CB and before step S2d in which semiconductor chip CP is arranged on wiring substrate CB. It is important to perform the ascending process. In the present embodiment, in the temperature region where the cross-linking reaction does not occur, considering that the viscosity of the resin decreases as the temperature increases, the viscosity increasing process of Step S2c is performed, whereby the resin RS in Step S2b is changed. Even without changing the viscosity V1, the viscosity V3 of the resin RS in step S2d can be increased. Thereby, in this Embodiment, by performing the viscosity raising process of step S2c, it is possible to optimize both the viscosity V1 of the resin RS in step S2b and the viscosity V3 of the resin RS in step S2d. it can.

  That is, in this embodiment, by performing the viscosity increasing step in step S2c, the viscosity V3 of the resin RS in step S2d can be increased without increasing the viscosity V1 of the resin RS in step S2b. Without considering the viscosity of the resin RS in S2d, the viscosity V1 of the resin RS in step S2b can be set to a viscosity suitable for step S2b. For this reason, the resin RS can be accurately supplied onto the wiring board CB from the resin supply nozzle NZL in step S2b. Further, in step S2b, the wettability (easiness of wetting and spreading) of the resin RS on the wiring board CB can be optimized.

  In the present embodiment, by performing the viscosity increasing step in step S2c, the resin viscosity V1 in step S2b is set to a viscosity suitable for performing step S2b, while the resin RS in step S2d is set. Since the viscosity V3 can be increased, it is possible to prevent the viscosity of the resin RS in step S2d from becoming lower than the viscosity suitable for step S2d. That is, while setting the viscosity V1 of the resin in step S2b to a viscosity suitable for performing step S2b, the viscosity V3 of the resin in step S2d can also be set to a viscosity suitable for performing step S2d. it can. For this reason, in step S2d, it can be prevented that the viscosity of the resin RS becomes too low and voids are generated in the resin portion UFR.

  Further, the viscosity V1 of the resin RS in step S2b is more preferably within a range of 10 to 200 Pa · s (that is, 10 Pa · s ≦ V1 ≦ 200 Pa · s). Thereby, step S2b can be performed accurately.

  Further, the viscosity V3 of the resin RS in step S2d is more preferably within a range of 10 to 200 Pa · s (that is, 10 Pa · s ≦ V3 ≦ 200 Pa · s). Thereby, step S2d can be performed accurately.

  The viscosity V2 of the resin RS increased in step S2c is more preferably in the range of 1000 to 7000 Pa · s (that is, 1000 Pa · s ≦ V2 ≦ 7000 Pa · s). Thereby, it becomes easy to set the viscosity V3 of the resin RS in step S2d to a viscosity suitable for step S2d (that is, 10 Pa · s ≦ V3 ≦ 200 Pa · s).

  Thus, in this Embodiment, both the resin application process of step S2b and the chip | tip arrangement | positioning process of step S2d can be optimized. Therefore, the reliability of the manufactured semiconductor device can be improved. In addition, the manufacturing of the semiconductor device can be facilitated.

  Further, in the viscosity increasing step of step S2c, the viscosity of the resin RS is increased to a viscosity V2 higher than the viscosity V1, and this is because the resin RS supplied onto the wiring board CB in step S2b is expandable. It can be realized by containing the filler.

  27 to 29 are explanatory views of the resin RS used in the present embodiment, and show a case where a filler having a core / shell structure is used as the expandable filler FL1 contained in the resin RS. 27 to 29, FIG. 27 shows an enlarged view of the resin RS before supplying the resin RS onto the wiring board CB in step S2b, and FIG. 28 shows the viscosity increasing step in step S2c. FIG. 29 shows an enlarged view of the resin RS at the stage after the chip placement step of Step S2c. 27 to 29 are schematic cross-sectional views, but hatching is omitted for easy understanding of the drawings.

  The resin RS supplied onto the wiring board CB in step S2b is a resin material (matrix resin, base material resin, base resin) MTR made of epoxy resin or the like, an expandable filler FL1, and an expandable filler FL1. Filler FL2 is included. That is, the resin RS supplied onto the wiring board CB in step S2b is obtained by dispersing the filler FL1 and the filler FL2 in the resin material MTR. The filler FL2 is a non-expandable filler. The expandable filler FL1 is an organic filler (organic particles), and the filler FL2 is an inorganic filler (inorganic particles).

  The resin material MTR is a thermosetting resin material and is made of an epoxy resin (epoxy resin), but an acrylic resin (acrylic resin) can also be used. The resin RS is cured (cured resin portion UFR) by the resin material MTR being cured by a crosslinking reaction.

  Silica or the like can be suitably used as the filler FL2. The filler FL2 is mixed in the resin RS in order to ensure the hardness after curing of the resin RS (that is, the hardness of the resin portion UFR). Therefore, the filler FL2 is preferably an inorganic filler, and silica is particularly preferable. The filler FL2 hardly expands in the resin RS, and the particle size hardly changes (that is, the volume hardly changes). That is, the filler FL2 is a non-expandable filler.

  The expandable filler FL1 is capable of expanding in the resin RS to increase the particle size (that is, increase the volume). In the resin RS, when the expandable filler FL1 expands and the particle size of the filler FL1 increases (that is, the volume of the filler FL1 increases), the viscosity of the entire resin RS increases. Accordingly, the resin RS contains the expandable filler FL1, and in step S2c, the expandable filler FL1 expands to increase the viscosity of the resin RS. The expandable filler FL1 can also be regarded as a pregelling agent.

  Accordingly, in step S2c, in the resin RS, the filler FL1 expands and the particle size of the filler FL1 increases (that is, the volume of the filler FL1 increases), but the filler FL2 hardly expands and the particle size is almost the same. Does not change (ie, volume hardly changes).

  As the expandable filler FL1, a filler having a core / shell structure as shown in FIG. 27 can be used. The core / shell structure is a structure in which a core portion (core material) CR is covered with a shell portion (shell material) SL. The outer peripheral portion (surface layer portion) of the filler FL1 having a core / shell structure is the shell portion SL, and the inside (core portion) is the core portion CR. The core portion CR is made of, for example, an acrylic resin (acrylic resin). The shell portion SL is made of, for example, an acrylic resin (acrylic resin).

  The shell portion SL in the filler FL1 having a core / shell structure has a property of expanding (swelling) by absorbing the surrounding resin material MTR when the temperature of the resin RS becomes equal to or higher than a predetermined temperature. In step S2b, the temperature of the resin RS is lower than the predetermined temperature (temperature at which the shell portion SL expands), and in step S2c, the temperature is equal to or higher than the predetermined temperature (temperature at which the shell portion SL expands). The resin RS is heated to the temperature of.

  In FIG. 28, the shell portion SL is in an expanded (swelled) state by absorbing the resin material MTR. That is, the shell portion SL is in a wet state with the resin material MTR. As shown in FIG. 28, when the shell portion SL expands (swells), the effective particle size of the filler FL1 having a core / shell structure increases (that is, the volume increases), and the viscosity of the entire resin RS increases. It will be. That is, when the state of FIG. 27 is compared with the state of FIG. 28, in the state of FIG. 28, the shell portion SL in the filler FL1 absorbs the resin material MTR and expands (swells). The particle size (volume) of the filler FL1 in the state of FIG. 28 is larger than the particle size (volume) of the filler FL1 of FIG. 28. Therefore, the viscosity of the resin RS in the state of FIG. The viscosity of the resin RS increases.

  An example of a thermosetting epoxy resin in which fine particles (fillers) having such a core / shell structure are dispersed is described in Non-Patent Document 1, for example.

  The core / shell structure filler FL1 contained in the resin RS expands (swells) the shell portion SL in the resin RS, whereby the particle size of the filler FL1 increases and the volume of the filler FL1 increases. be able to. This phenomenon occurs and is promoted when the temperature of the resin RS becomes equal to or higher than a predetermined temperature. That is, when the resin RS supplied onto the wiring board CB in step S2b is heated at a predetermined temperature or higher, the expandable filler FL1 expands and the viscosity of the resin RS increases.

  As shown in FIG. 27, the expandable filler FL1 having a core / shell structure dispersed in the resin RS expanded as shown in FIG. 28 in step S2c to increase the viscosity of the resin RS. After that, in step S2d and step S2e, it deforms into an indefinite shape as shown in FIG. 29, and infiltrates into the resin material MTR of the resin RS and is dispersed almost uniformly. For this reason, the filler FL1 cannot be distinguished from the resin material MTR in the cured resin RS (that is, in the resin portion UFR). On the other hand, since the filler FL2 is made of an inorganic material such as silica, it can be distinguished from the resin material MTR even in the cured resin RS (that is, in the resin portion UFR).

  Curing of the resin RS by a crosslinking reaction is an irreversible change. The expansion of the expandable filler FL1 is an irreversible change. Further, in the temperature range where the crosslinking reaction does not occur, the viscosity change of the resin RS due to the movement (vibration) of the molecule due to thermal energy, not the expansion of the filler FL1, is a reversible change. For this reason, after supplying the resin RS onto the wiring board CB in step S2b, as shown in the graph of FIG. 26, the viscosity once decreases as the temperature rises (this viscosity phenomenon is caused by an increase in thermal energy). The viscosity of the resin RS increases due to the expansion of the expandable filler FL1 (corresponding to step S2c, and the viscosity of the resin RS increases to the viscosity V2). ). For this reason, in step S2c, it is preferable to heat the resin RS at a temperature and a time at which the filler FL1 is sufficiently expanded in the resin RS. However, in step S2c, the cross-linking reaction is prevented from occurring in the resin RS as much as possible. That is, in step S2c, the expandable filler FL1 contained in the resin RS expands, but the resin RS is heated to a temperature at which no cross-linking reaction occurs in the resin RS (or the cross-linking reaction is not desired). By maintaining this state, the expandable filler FL1 is expanded while suppressing the crosslinking reaction, and the viscosity of the resin RS is increased. In step S2c, the heating temperature of the resin RS is higher than the temperature of the resin RS at the time of resin supply in step S2b (corresponding to the temperature T1), but the solder layer SD1 (described later in the case of a modification described later) The temperature is such that the solder layer SD3 is not melted (temperature lower than the melting point of the solder layers SD1 and SD3).

  In step S2c, almost no crosslinking reaction has occurred in the resin RS, and the increase in viscosity is not due to the crosslinking reaction but due to the expansion of the filler FL1. For this reason, the temperature of the resin RS in step S2d becomes higher than the heating temperature of the resin RS in step S2c (corresponding to the temperature T2), which increases molecular movement (vibration) due to an increase in thermal energy. As a result, the viscosity of the resin RS in step S2d becomes lower than the viscosity V2 (viscosity V2 when increased in step S2c) (see FIG. 26). Thereafter, a crosslinking reaction occurs (promoted) in step S2e, and the resin RS is cured (viscosity is remarkably increased). In step S2e, the heating temperature of the resin RS is a temperature at which the crosslinking reaction in the resin RS is promoted and the resin RS is cured, and the solder layer SD1 (in the case of a later-described modification, a later-described solder layer SD3 is also used). ) Is melted (temperature above the melting point of the solder layers SD1 and SD3).

  When the example of content of the filler of resin RS is given, when using a silica filler as filler FL2, about 50 to 70 weight% silica filler can be contained in resin RS, for example. Further, when an acrylic resin-based core / shell structure filler is used as the expandable filler FL1, for example, about 1 to 15% by weight of a core / shell structure filler can be contained in the resin RS. In the resin RS, it is preferable that the organic filler (filler FL1) has a smaller content rate (content) than the inorganic filler (filler FL2). In other words, in the resin RS, it is preferable that the inorganic filler (filler FL2) has a higher content rate (content) than the organic filler (filler FL1). In the resin RS, if the content (content) of the inorganic filler (filler FL2) is larger than that of the organic filler (filler FL1), the hardness of the resin RS after curing (that is, the hardness of the resin part UFR) is increased. The filler (filler FL2) can be secured accurately. The filler content in the resin RS described here is the content before the viscosity increasing step in step S2c (the state before the filler FL1 expands), that is, on the wiring board CB in step S2b. It corresponds to the content at the stage of supplying the resin RS.

  In the present embodiment, in step S2b, the resin RS is supplied from the resin supply nozzle NZL to the chip mounting scheduled area on the upper surface CBa of the wiring board CB. At this time, since the temperature of the nozzle NZL is set to a temperature T1 (for example, about 30 to 50 ° C.), when the resin RS is filled in the nozzle NZL and from the nozzle NZL onto the wiring board CB, the resin RS Immediately after is supplied, the temperature of the resin RS is substantially the temperature T1. At this temperature T1, the expandable filler FL1 in the resin RS hardly expands (swells), and the crosslinking reaction hardly occurs in the resin RS. That is, the temperature T1 is preferably set to a temperature at which the expandable filler FL1 in the resin RS hardly expands (swells) and hardly causes a crosslinking reaction in the resin RS. For this reason, it is necessary to set the temperature T1 to a somewhat low temperature. However, if the temperature T1 is too low, the temperature tends to fluctuate depending on the outside air temperature. Therefore, the temperature T1 may be set to a temperature slightly higher than room temperature, for example, about 30 to 50 ° C. preferable.

  The stage STG is heated (set) to a temperature T2 higher than the temperature T1, and the wiring board CB disposed on the stage STG is also heated to the temperature T2, and the wiring board CB is placed on the wiring board CB in step S2b. Resin RS is arranged and this state is maintained for a predetermined time. This holding period corresponds to the viscosity increasing step of step S2c.

  In a state where the wiring substrate CB is heated to the temperature T2 together with the stage STG, the resin RS is disposed on the wiring substrate CB in step S2b, and when this state is held for a predetermined time in step S2c, the wiring substrate is held during this holding. The resin RS disposed on the CB is also heated, and the temperature of the resin RS gradually increases toward the temperature of the wiring board CB (that is, the temperature T2). When the temperature of the resin RS on the wiring board CB becomes substantially the same as the temperature of the wiring board CB (that is, the temperature T2), the temperature of the resin RS is also held at the temperature T2.

  The resin RS on the wiring board CB is heated through the wiring board CB (heated toward the temperature T2), whereby the expandable filler FL1 in the resin RS expands (in the case of the core / shell structure, the shell RS The portion SL expands), and the viscosity of the resin RS increases due to the expansion of the filler FL1. In step S2c, the resin RS is heated through the wiring board CB by the stage STG (internal heating mechanism), but the temperature is set so that the expandable filler FL1 in the resin RS expands and the viscosity of the resin RS can be accurately increased. T2 and the holding time of step S2c are set. However, the temperature T2 is set to a temperature at which no crosslinking reaction occurs in the resin RS and the solder layer SD1 is not melted. The temperature T2 is preferably set in the range of 50 to 100 ° C., for example, about 75 ° C., and the holding time in step S2c is set to 10 minutes or more, for example.

  In step S2c, the expandable filler FL1 expands in the resin RS, thereby increasing the viscosity of the resin RS, thereby increasing the viscosity of the resin RS to a viscosity V2 higher than the viscosity V1 (V2). > V1).

  In step S2c, the resin RS is disposed in step S2b on the wiring board CB heated to a temperature (temperature T2) higher than the temperature of the resin RS (corresponding to the temperature T1) supplied from the nozzle NZL. During step S2c, the resin RS is also heated through the wiring board CB, thereby expanding the expandable filler FL1 to increase the viscosity of the resin RS. For this reason, step S2c is performed by continuing the state in which the resin RS is arranged on the wiring board CB heated to the temperature T2 for a predetermined time. During this predetermined time, the temperature of the resin RS becomes high. It is preferable to set the time sufficient for the expandable filler FL1 to expand and increase the viscosity of the resin RS. For this reason, the time required for step S2c needs to be increased to some extent, and a longer processing time (for example, 10 minutes or more) than the processing time required for step S2a, step S2b, step S2d, and step S2e is required. To do. That is, the longest processing time among steps S2a, S2b, S2c, S2d, and S2e is step S2c. By setting the step S2c to a relatively long time, the viscosity of the resin RS can be increased accurately in the step S2c, and the steps S2a, S2b, S2d, and S2e can be performed by setting the processing time to be relatively short. The throughput of the apparatus can be improved.

  Step S2c is preferably performed using an apparatus different from the apparatus used in step S2b (resin coating apparatus) and the apparatus used in steps S2d and S2e (flip chip bonding apparatus). Thereby, even if a long processing time is required for step S2c, it does not affect step S2b (resin supply process) or steps S2d, S2e (chip mounting process and resin curing process), so that the throughput can be improved.

  Further, the temperature of the resin RS immediately before being supplied onto the wiring board CB in step S2b is a temperature (that is, temperature T1) lower than the temperature T2 of the stage STG (and hence the temperature T2 of the wiring board CB), and in step S2c The temperature of the resin RS becomes higher than that temperature (that is, the temperature T1). Due to the temperature rise of the resin RS, the expandable filler FL1 in the resin RS expands, whereby the viscosity of the resin RS can be increased (increased). For this reason, since the viscosity of the resin RS can be controlled by a simple process, both the simplification of the manufacturing process of the semiconductor device and the improvement of the reliability of the manufactured semiconductor device can be achieved.

  In the present embodiment, the case where the stage STG and the wiring board CB placed thereon are heated to the temperature T2 in advance in the step S2b has been described. As another form, the temperature of the stage STG is set to a relatively low temperature in steps S2a and S2b (a temperature lower than the temperature of the resin RS in step S2c, for example, about 30 to 50 ° C.). Resin RS is supplied in step S2b onto wiring board CB that is substantially the same as the temperature, and then the temperature of stage STG is increased (to the above temperature T2), and the viscosity of resin RS is set to (V1). It is also possible to raise it from V2 to V2. In this case, the temperature of the wiring board CB at the time of resin supply in step S2b is lower than the temperature necessary for the expandable filler FL1 to expand and the viscosity of the resin RS to increase. Even if the resin RS is supplied, if the temperature of the stage STG is not increased thereafter (that is, the temperature of the wiring board CB is not increased), the process does not proceed to the viscosity increasing step of step S2c. That is, in this case, in order to shift to the viscosity increasing step of Step S2c after the resin supplying step of Step S2b, the temperature of the resin RS (resin is increased by heating the stage STG (that is, heating the wiring board CB). It is necessary to set the temperature of RS to a temperature higher than that necessary for the filler FL1 to expand and the viscosity of the resin RS to increase. For this reason, the resin supply process of step S2b and the viscosity increase process of step S2c can be performed separately without being continuous. This facilitates management of the resin supply process in step S2b and the viscosity increase process in step S2c.

  On the other hand, the stage STG and the wiring board CB placed thereon are heated in advance to the temperature T2, and the resin RS (a temperature T1 lower than the temperature T2 is set on the wiring board CB heated to the temperature T2 in step S2b. If the resin RS) is supplied, the time from the supply of the resin RS on the wiring board CB in step S2b to the transition to the viscosity increasing step of step S2c can be shortened. Furthermore, if the temperature T2 at which the stage STG is heated in advance is set to a temperature necessary for increasing the viscosity of the resin RS in step S2c (a temperature at which the expandable filler FL1 can expand), Without changing the temperature, it is possible to shift from the resin supply process of step S2b to the viscosity increasing process of step S2c. For this reason, the time required to shift from the resin supply process of step S2b to the viscosity increase process of step S2c can be further shortened, and the throughput can be improved. In other words, the temperature of the stage STG can be made approximately the same in steps S2a, S2b, and S2c, so that the temperature control of the stage STG can be facilitated and the throughput can be improved.

  In step S2b, the resin RS is supplied to the chip mounting area of the wiring board CB from the nozzle NZL heated (set) to a temperature T1 lower than the temperature T2 of the stage STG (and hence the temperature T2 of the wiring board CB). For this reason, the viscosity V1 and temperature of the resin RS can be set to the optimum resin viscosity and resin temperature at the time of resin supply in the first application method (ie, step S2b), and the resin RS is supplied onto the wiring board CB in step S2b. Then, the temperature of the resin RS arranged on the wiring board CB can be increased (increased so as to reach the temperature T2). As a result, the viscosity V1 and temperature of the resin RS in step S2b can be optimized, and the process can be quickly shifted from step S2b to step S2c, and the time required from step S2b to completion of step S2c can be reduced. can do. For this reason, the throughput of the semiconductor device can be improved.

  In step S2c, the temperature of the resin RS rises as a predetermined time elapses in a state where the resin RS is disposed on the wiring board CB. Due to this temperature increase, the expandable filler FL1 in the resin RS expands, whereby the viscosity of the resin RS can be increased (increased). For this reason, since the viscosity of the resin RS can be controlled by a simple process, both the simplification of the manufacturing process of the semiconductor device and the improvement of the reliability of the manufactured semiconductor device can be achieved.

  Further, a resist layer (solder resist layer, solder resist layer) SR1 which is an insulating film (insulating layer) is formed on the upper surface CBa of the wiring board CB, and is provided in an annular shape (annular in plan view) on the resist layer SR1. A plurality of bonding leads BL are exposed from the opening OP. As another form, in the wiring board CB, the opening OP may not be connected in a ring shape, and the opening OP may be separated for each side. In addition, an opening (an opening provided in the resist layer SR1) can be individually provided for each bonding lead BL. Further, not only the outer periphery of the chip mounting region on the upper surface CBa of the wiring board CB but also the bonding lead BL can be provided on the inner side (center portion).

  However, the manufacturing process of the present embodiment is more effective when applied to a case where a plurality of bonding leads BL are exposed from the opening OP provided in an annular shape as shown in FIG. This is because when a plurality of bonding leads BL are exposed from the annular opening OP, the resin RS is supplied in step S2b onto the resist layer SR1 in a portion surrounded by the annular opening OP. Thus, when the semiconductor chip CP is arranged on the wiring substrate CB in step S2d, the resin RS spreads beyond the annular opening OP, but voids are easily formed when exceeding the annular OP. In this embodiment, since the viscosity of the resin RS can be optimized in step S2b and step S2d, a plurality of bonding leads BL are exposed from the opening OP provided in an annular shape as shown in FIG. Even if it is a case, it can prevent that a void is formed in resin RS by step S2d and S2e, and it can prevent that a void is formed in the resin part UFR in the manufactured semiconductor device. Therefore, the reliability of the semiconductor device can be improved accurately.

  Further, the viscosity of the resin RS is increased to the viscosity V2 in step S2c, but the viscosity V3 of the resin RS in step S2d (semiconductor chip CP placement step) is set to a viscosity lower than the viscosity V2 (that is, V3 <V2). Can do. This is because if the temperature of the resin RS in step S2d (semiconductor chip CP placement step) is low, the time required for the subsequent resin curing (curing of the resin RS in step S2e) becomes long, and the throughput may be reduced. Because. Therefore, when the semiconductor chip CP is disposed on the wiring board CB in step S2d, the temperature T3 of the tool TL is set to a temperature (T3> T2) higher than the temperature T2 after the increase in step S2c, and step S2d (semiconductor It is preferable to raise the temperature of the resin RS to a certain degree (higher than the temperature T2) in the chip CP placement step). In such a case, the viscosity V3 of the resin RS in step S2d (semiconductor chip CP placement step) is lower than the viscosity V2.

  In step S2e, the back surface CPb of the semiconductor chip CP is pressed with the tool TL heated (set) to a temperature T4 higher than the temperature T1. In other words, since the temperature T2 is lower than the temperature T1, in step S2e, the back surface CPb of the semiconductor chip CP is pressed with the tool TL heated (set) to the temperature T4 higher than the temperatures T1 and T2. That is, in step S2e, the temperature of the tool TL is increased to the temperature T4, and the back surface CPb of the semiconductor chip CP is pressed to the wiring board CB side with the tool TL heated (set) to the temperature T4. The temperature is higher than the temperatures T1 and T2. Thereby, in step S2b and S2c, the temperature of resin RS can be suppressed and the crosslinking reaction in resin RS can be suppressed, and in step S2e, the temperature of resin RS is increased to promote the crosslinking reaction in resin RS and the resin RS is cured. Can be made.

<About modification>
A case where a Cu post PS that is a copper (Cu) columnar electrode is used as the bump electrode BP (hereinafter referred to as a modified example) will be described with reference to FIGS. 30 to 33 are explanatory diagrams of the manufacturing process of the semiconductor device according to the modification of the present embodiment, in which a cross-sectional view is shown.

  FIG. 30 corresponds to FIG. 6 and shows a cross-sectional view of the semiconductor chip CP2.

  In the case of the manufacturing process of the semiconductor device of the modified example, in the semiconductor chip CP2 of FIG. 30 prepared in step S1, Cu post PS which is a copper (Cu) columnar electrode is provided on each bonding pad PD as a bump electrode BP. Is formed. Also, a solder layer SD3 is formed on the front end surface of each Cu post PS (the side opposite to the side connected to the bonding pad PD in the Cu post PS is the front end surface). Since the other configuration of the semiconductor chip CP2 is the same as that of the semiconductor chip CP of FIG. 6, the description thereof is omitted here. In the modification, the wiring board CB prepared in step S1 is the same as the wiring board CB shown in FIGS.

  Also in the modified example, among steps S2, steps S2a, S2b, and S2c are the same as described above, and therefore, repeated description thereof is omitted here.

  In the case of the modification, in step S2d, as shown in FIGS. 31 and 32, the semiconductor chip CP2 is disposed in the chip mounting scheduled area on the upper surface CBa of the wiring board CB.

  FIG. 31 corresponds to FIG. 18 described above, and shows a cross-sectional view schematically showing a state in which the semiconductor chip CP2 held by the tool TL is approaching the wiring board CB. FIG. 32 corresponds to FIG. 20 described above. From the state of FIG. 31, the semiconductor chip CP2 is brought closer to the wiring board CB, and the tip of the Cu post PS (the solder layer SD3) of the semiconductor chip CP2 is the wiring board. A state where the upper surface CBa of the CB is in contact with the bonding lead BL (upper solder layer SD1) is shown.

  Step S2d in the modification of FIGS. 31 and 32 differs from step S2d in the case of FIGS. 18 to 20 in the following points. That is, in step S2d in the case of FIGS. 18 to 20, the tip of the bump electrode BP is in contact with the solder layer SD1 on the surface of the bonding lead BL, whereas step S2d in the modification of FIGS. 31 and 32. Then, the solder layer SD3 on the front end surface of the Cu post PS is in contact with the solder layer SD1 on the surface of the bonding lead BL. In step S2d, the solder layers SD1 and SD3 are not melted. Otherwise, step S2d in the modified example of FIGS. 31 and 32 is the same as step S2d in the case of FIGS.

  In the case of the modification, in step S2e, as shown in FIG. 33, the temperature of the tool TL is quickly raised, and the semiconductor chip CP2 is pressed (pressed) toward the wiring board CB by the tool TL.

  33 differs from step S2e in the case of FIG. 21 and FIG. 22 in the following points. That is, in step S2e in the case of FIG. 21 and FIG. 22, since the solder layer SD1 is melted, the bump electrode BP is connected to the bonding lead BL, and the solder SD2 composed of the melted solder layer SD1 is replaced with the bump electrode BP. And the periphery of the connection portion between the bonding lead BL and the bump electrode BP. On the other hand, in step S2e in the modification of FIG. 33, the solder layers SD1 and SD3 are melted, and the solder SD2 composed of the melted solder layers SD1 and SD3 is interposed between the tip surface of the Cu post PS and the bonding lead BL. Intervene. For this reason, when the solder SD2 is solidified later (in step S2f), the Cu post PS is connected to the bonding lead BL by the solidified solder SD2. Otherwise, step S2e in the modification of FIG. 33 is the same as step S2e in the case of FIG. 21 and FIG. Note that the solder SD2 is solidified in step S2f after step S2e in both the modification of FIG. 33 and the case of FIG. 21 and FIG.

  Step S2f and step S3 are the same as in the case of FIG. 23 and FIG. 24 in the case of the modified example, and thus the repeated description thereof is omitted here.

  In this manner, a semiconductor device using Cu post PS as the bump electrode BP can be manufactured.

  As another modification of the present embodiment, each semiconductor device is manufactured using a multi-piece wiring board (wiring board mother body) formed by connecting a plurality of wiring boards CB in a line or array. It can also be manufactured. In this case, the wiring board prepared in step S1 is a multi-piece wiring board (wiring board base) formed by connecting a plurality of wiring boards CB in a line or in an array. In step S2a, the multi-piece wiring board is arranged on the stage STG. In step S2b, a paste-like pattern is formed on the chip mounting scheduled area in each semiconductor device region (unit board area) of the multi-piece wiring board. Resin RS is arranged, and in step S2c, the viscosity of the resin RS is increased. Here, each semiconductor device region in a multi-piece wiring substrate is a region from which one semiconductor device is formed, and each of the plurality of wiring substrates CB connected in a row or in an array is a semiconductor device region. It corresponds to. Then, steps S2d, S2e, and S2f are performed on each semiconductor device region of the multi-piece wiring board to flip-chip-connect the semiconductor chip CP. Then, in step S3, solder balls BA are connected to the lower surface side of the plurality of semiconductor device regions of the multi-piece wiring board. Thereafter, the semiconductor device can be manufactured from each semiconductor device region by cutting the multi-piece wiring substrate and dividing it into each semiconductor device region.

  As still another modification of the present embodiment, another semiconductor chip (second-stage semiconductor chip) is flipped onto the semiconductor chip CP (first-stage semiconductor chip) mounted on the wiring board CB. Chip connection is also possible. That is, the present embodiment can be applied to a semiconductor device having a COC (Chip On Chip) structure in which a plurality of semiconductor chips are stacked. In this case, the first-stage semiconductor chip CB flip-chip connected to the wiring board CB has a plurality of electrodes (for example, through electrodes) on the back surface side. Then, the steps S2a to S2f are performed as described above, and the semiconductor chip CP is flip-chip connected to the wiring substrate CB via the resin RS, and then the second-stage semiconductor via the resin RS on the back surface of the semiconductor chip CP. Chips are flip-chip connected. The technique of flip-chip connecting the second-stage semiconductor chip via the resin RS on the back surface of the semiconductor chip CP is the technique of flip-chip connecting the semiconductor chip CP via the resin RS to the wiring board CB described above (that is, the above-described method). Steps S2b to S2f) are basically the same. However, when the second-stage semiconductor chip is flip-chip connected to the back surface of the semiconductor chip CP via the resin RS, the resin RS is disposed on the back surface of the semiconductor chip CP in step S2b. It is the resin RS on the back surface of the semiconductor chip CP that increases the viscosity, and it is the back surface of the semiconductor chip CP that mounts the second-stage semiconductor chip in steps S2d to S2f. When the second-stage semiconductor chip is flip-chip connected to the back surface of the first-stage semiconductor chip CP, the plurality of bump electrodes of the second-stage semiconductor chip have the plurality of bump electrodes on the back surface side of the first-stage semiconductor chip CP. Each is connected to an electrode. In the same manner, the third-stage semiconductor chip can be flip-chip connected to the back surface of the second-stage semiconductor chip via the resin RS. By repeating this, the number of stacked semiconductor chips can be increased. You can also. Thereafter, the solder ball BA connecting step of step S3 may be performed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

BA Solder ball BL Bonding lead CB Wiring substrate CBa Upper surface CBb Lower surface CP, CP2 Semiconductor chip CPa Front surface CPb Back surface CR Core portion FL1, FL2 Filler LA Land MTR Resin material PKG Semiconductor device OP Opening portion PD Bonding pad PS Cu post RS, RS1, RS2, RS3, RS4 Resin SD1, SD3 Solder layer SD2 Solder SL Shell part SR1, SR2 Resist layer STG Stage TL Tool UFR Resin part

Claims (15)

A semiconductor device manufacturing method including the following steps:
(A) placing a wiring board having an upper surface, a plurality of bonding leads formed in a chip mounting region on the upper surface, and a lower surface opposite to the upper surface on a stage set at a first temperature;
(B) After the step (a), a step of disposing a paste-like resin containing the first filler and the expandable second filler and having the first viscosity in the chip mounting region of the wiring board. ;
(C) after the step (b), increasing the viscosity of the resin to a second viscosity higher than the first viscosity;
(D) After the step (c), a main surface, a plurality of bonding pads formed on the main surface, a plurality of electrode members respectively formed on the plurality of bonding pads, and a side opposite to the main surface Placing a semiconductor chip having a back surface in the chip mounting region of the wiring board via the resin and the plurality of electrode members such that the main surface of the semiconductor chip faces the upper surface of the wiring board; ;
(E) After the step (d), the plurality of electrode members and the plurality of bonding leads are brought into contact with each other by pressing the back surface of the semiconductor chip with a tool, respectively. The step of curing the resin by setting the joint portion with the bonding lead to a second temperature higher than the first temperature. A method of manufacturing a semiconductor device according to claim 1,
In the step (e), the resin is cured by a crosslinking reaction. A method of manufacturing a semiconductor device according to claim 2,
The temperature of the resin immediately before being supplied to the wiring board in the step (b) is a third temperature,
In the step (c), the temperature of the resin is higher than the third temperature and lower than the second temperature. A method of manufacturing a semiconductor device according to claim 3,
In the step (c), the temperature of the resin rises as a predetermined time elapses in a state where the resin is disposed on the wiring board. A method of manufacturing a semiconductor device according to claim 4,
In the step (c), the method of manufacturing a semiconductor device, wherein the second filler expands. A method of manufacturing a semiconductor device according to claim 5,
The method for manufacturing a semiconductor device, wherein the first filler does not expand in the step (c). A method of manufacturing a semiconductor device according to claim 6,
The first filler is an inorganic filler,
The method for manufacturing a semiconductor device, wherein the second filler is an organic filler. A method of manufacturing a semiconductor device according to claim 7,
The method for manufacturing a semiconductor device, wherein the viscosity of the resin in the step (d) is lower than the second viscosity. A method for manufacturing a semiconductor device according to claim 8, comprising:
In the step (e), a method of manufacturing a semiconductor device, wherein the back surface of the semiconductor chip is pressed with the tool set to a fourth temperature higher than the first temperature. A method of manufacturing a semiconductor device according to claim 9,
In the step (b),
A method for manufacturing a semiconductor device, wherein the resin is supplied to the chip mounting region of the wiring board from a nozzle set at a temperature lower than the first temperature. A method of manufacturing a semiconductor device according to claim 1,
The process (c) is a method for manufacturing a semiconductor device, wherein the processing time is the longest among the processes (a) to (e). A method of manufacturing a semiconductor device according to claim 1,
In the step (b), in the chip mounting region of the wiring board, the resin is applied from a nozzle in a plurality of directions intersecting each other. A method of manufacturing a semiconductor device according to claim 1,
An insulating film is formed on the upper surface of the wiring board, and the plurality of bonding leads are exposed from openings of the insulating film, and the openings are formed in an annular shape in plan view. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1,
The method (c) is a method for manufacturing a semiconductor device, which is performed using an apparatus different from the steps (b) and (d). A method of manufacturing a semiconductor device according to claim 1,
In the step (e), a method of manufacturing a semiconductor device, wherein the ultrasonic wave is applied by pressing the back surface of the semiconductor chip with the tool.

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