JP2012015446A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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JP2012015446A
JP2012015446A JP2010152994A JP2010152994A JP2012015446A JP 2012015446 A JP2012015446 A JP 2012015446A JP 2010152994 A JP2010152994 A JP 2010152994A JP 2010152994 A JP2010152994 A JP 2010152994A JP 2012015446 A JP2012015446 A JP 2012015446A
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chip
recess
chip stack
sealing material
semiconductor
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Tomoyuki Fujishima
智之 藤嶋
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Micron Memory Japan Ltd
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Elpida Memory Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

PROBLEM TO BE SOLVED: To uniformize an outline of a chip lamination body after sealing.SOLUTION: A method of manufacturing a semiconductor device having a chip lamination body 11 in which a plurality of semiconductor chips 10 is laminated, includes: a step of arranging the chip lamination body 11 in which the plurality of semiconductor chips 10 is laminated via a bump electrode 12, in a recess part 122 formed on a stage 120; a step of injecting a liquid sealing material 14 into the recess part 122 from a gap 124 between the chip lamination body 11 in the recess part 122 and a side surface of the recess part 122; and a step of hardening the sealing material 14.

Description

本発明は、ＣｏＣ（chip on chip）型の半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a CoC (chip on chip) type semiconductor device.

近年、電子機器の小型化および高機能化に伴って、貫通電極を有する複数の半導体チップが積層されたＣｏＣ型の半導体装置が提案されている。ＣｏＣ型の半導体装置では、通常、各々の半導体チップ間に封止樹脂が配設されている。特開２００７−３６１８４号（以下、特許文献１）は、このような、ＣｏＣ型の半導体装置およびその製造方法を開示している。   In recent years, CoC type semiconductor devices in which a plurality of semiconductor chips having through electrodes are stacked have been proposed with downsizing and higher functionality of electronic devices. In a CoC type semiconductor device, a sealing resin is usually disposed between each semiconductor chip. Japanese Patent Laying-Open No. 2007-36184 (hereinafter referred to as Patent Document 1) discloses such a CoC type semiconductor device and a method for manufacturing the same.

特許文献１には、液状の封止樹脂が予め塗布された複数のチップを積層配置することが記載されている。また、複数のチップを積層配置し、チップ間に液状の封止樹脂を注入することも記載されている。封止樹脂は、一般に、液滴吐出法により、半導体チップの側方から半導体チップ間の隙間に注入される。   Patent Document 1 describes that a plurality of chips to which a liquid sealing resin is applied in advance are stacked. It also describes that a plurality of chips are stacked and liquid sealing resin is injected between the chips. The sealing resin is generally injected into the gap between the semiconductor chips from the side of the semiconductor chip by a droplet discharge method.

特開２００７−３６１８４号公報JP 2007-36184 A

封止樹脂は、液滴吐出法により、半導体チップ間の側方から半導体チップ間の隙間に注入される。この封止樹脂は、積層した半導体チップ（チップ積層体）の周囲にも形成され、チップ積層体の周囲にフィレットを構成する。封止樹脂のフィレットの形状は、吐出される封止樹脂の吐出方向や周囲の環境などに依存するため、製造されたチップ積層体毎にばらついてしまうという問題がある。   The sealing resin is injected into the gap between the semiconductor chips from the side between the semiconductor chips by a droplet discharge method. This sealing resin is also formed around the laminated semiconductor chips (chip laminated body), and constitutes a fillet around the chip laminated body. Since the shape of the fillet of the sealing resin depends on the discharge direction of the discharged sealing resin, the surrounding environment, and the like, there is a problem in that it varies for each manufactured chip stack.

これらのチップ積層体は、例えば、画像処理法により多数個取りの配線基板（ウエハ）に搭載されて、半導体装置を構成する。したがって、複数のチップ積層体の外形が均一でない場合、チップ積層体のウエハへの実装精度が低下する。   These chip stacks are mounted on a multi-piece wiring board (wafer) by, for example, an image processing method to constitute a semiconductor device. Therefore, when the external shape of the plurality of chip stacks is not uniform, the mounting accuracy of the chip stacks on the wafer is lowered.

したがって、均一の形状の封止材を形成できる、半導体装置の製造方法を提供することが望まれる。   Therefore, it is desired to provide a method for manufacturing a semiconductor device that can form a sealing material having a uniform shape.

一態様における半導体装置の製造方法は、複数の半導体チップが積層されたチップ積層体を有する半導体装置を製造する方法に関する。この製造方法は、複数の半導体チップがバンプ電極を介して積載されたチップ積層体を、ステージ上に形成された凹部内に配置する工程と、液状の封止材を、凹部内のチップ積層体と凹部の側面との間の隙間から凹部内へ注入する工程と、封止材を硬化させる工程と、を有する。   The manufacturing method of the semiconductor device in one mode is related with the method of manufacturing the semiconductor device which has the chip lamination object in which a plurality of semiconductor chips were laminated. This manufacturing method includes a step of disposing a chip laminated body in which a plurality of semiconductor chips are stacked via bump electrodes in a recess formed on a stage, and a liquid sealing material for the chip laminated body in the recess. And a step of injecting into the recess from a gap between the recess and the side surface of the recess, and a step of curing the sealing material.

本発明によれば、ステージの凹部内にチップ積層体を保持した状態で、凹部内に封止材を供給するため、封止後の複数のチップ積層体の外形を均一化することができる。これにより、チップ積層体を精度良く配線基板へ実装できるという利点がある。また、凹部内に封止体を供給するだけで、半導体チップ間の隙間やチップ積層体の周りに、容易に封止材を形成することができる。   According to the present invention, since the sealing material is supplied into the recess while the chip stack is held in the recess of the stage, the outer shapes of the plurality of chip stacks after sealing can be made uniform. Thereby, there exists an advantage that a chip laminated body can be accurately mounted in a wiring board. Moreover, the sealing material can be easily formed around the gaps between the semiconductor chips and around the chip laminated body simply by supplying the sealing body into the recesses.

複数の半導体チップを積層する工程を示す工程図である。It is process drawing which shows the process of laminating | stacking a several semiconductor chip. チップ積層体に封止材を形成する工程を示す工程図である。It is process drawing which shows the process of forming a sealing material in a chip laminated body. ステージの凹部内にチップ積層体が置かれた状態を示す上面図である。It is a top view which shows the state by which the chip laminated body was put in the recessed part of a stage. チップ積層体を配線基板に搭載する工程を示す工程図である。It is process drawing which shows the process of mounting a chip laminated body on a wiring board. チップ積層体が搭載された配線基板に外部端子を取り付ける工程を示す工程図である。It is process drawing which shows the process of attaching an external terminal to the wiring board with which the chip laminated body was mounted. 第１の実施例における半導体装置の製造方法によって製造された半導体装置の概略断面図である。It is a schematic sectional drawing of the semiconductor device manufactured by the manufacturing method of the semiconductor device in a 1st Example. チップ積層体に封止材を形成する別の工程を示す工程図である。It is process drawing which shows another process of forming a sealing material in a chip laminated body. 第２の実施例において、ステージの凹部内にチップ積層体が置かれた状態を示す上面図である。In a 2nd Example, it is a top view which shows the state by which the chip | tip laminated body was put in the recessed part of a stage. 第２の実施例における半導体装置の製造方法によって製造された半導体装置の概略断面図である。It is a schematic sectional drawing of the semiconductor device manufactured by the manufacturing method of the semiconductor device in a 2nd Example.

以下、図面を参照して、本発明の実施例について説明する。本発明は、例えばメモリチップのような半導体チップが積層されたチップ積層体を有する半導体装置の製造方法に関する。   Embodiments of the present invention will be described below with reference to the drawings. The present invention relates to a method for manufacturing a semiconductor device having a chip stack in which semiconductor chips such as memory chips are stacked.

第１の実施例における半導体装置の製造方法では、まず、複数の半導体チップが積層されたチップ積層体を準備する。図１は、チップ積層体を構成する手順の一例を示している。   In the method of manufacturing a semiconductor device according to the first embodiment, first, a chip stacked body in which a plurality of semiconductor chips are stacked is prepared. FIG. 1 shows an example of a procedure for forming a chip stack.

まず、バンプ電極１２を有する複数の半導体チップ１０を準備する。半導体チップ１０は、略四角形の板状のシリコン等からなる基板を含み、基板の一方の面にメモリ回路等の所定の回路が形成されている。本実施例では、半導体チップ１０の両面にバンプ電極１２が設けられており、両面のバンプ電極１２は、貫通電極１３で電気的に接続されている。   First, a plurality of semiconductor chips 10 having bump electrodes 12 are prepared. The semiconductor chip 10 includes a substrate made of substantially rectangular plate-like silicon or the like, and a predetermined circuit such as a memory circuit is formed on one surface of the substrate. In this embodiment, bump electrodes 12 are provided on both surfaces of the semiconductor chip 10, and the bump electrodes 12 on both surfaces are electrically connected by through electrodes 13.

半導体チップ１０は、図１（ａ）に示す吸着ステージ１００上に、所定の回路が形成された一方の面を上方に向けて載置される。図１（ａ）に示すように、吸着ステージ１００は、凹部１０１を備え、半導体チップ１０は凹部１０１内に収容される。   The semiconductor chip 10 is placed on the suction stage 100 shown in FIG. 1A with one surface on which a predetermined circuit is formed facing upward. As shown in FIG. 1A, the suction stage 100 includes a recess 101, and the semiconductor chip 10 is accommodated in the recess 101.

半導体チップ１０は、吸着ステージ１００に設けられた吸着孔１０２を介して、不図示の真空装置により真空吸引されることで、吸着ステージ１００上に保持される(図１（ａ）参照)。   The semiconductor chip 10 is held on the suction stage 100 by being sucked by a vacuum device (not shown) through a suction hole 102 provided in the suction stage 100 (see FIG. 1A).

凹部１０１の内側面はすり鉢状のテーパ部１０３となっており、テーパ部１０３は吸着ステージ１００上に載置された半導体チップ１０を所定の位置に案内する。また、テーパ部１０３と半導体チップ１０の側面とが密着し、密閉空間を形成することで、半導体チップ１０を吸着ステージ１００上に良好に吸着保持できる。   The inner surface of the recess 101 is a mortar-shaped tapered portion 103, and the tapered portion 103 guides the semiconductor chip 10 mounted on the suction stage 100 to a predetermined position. Further, the taper portion 103 and the side surface of the semiconductor chip 10 are in close contact with each other to form a sealed space, whereby the semiconductor chip 10 can be satisfactorily held on the suction stage 100.

吸着ステージ１００上に保持した１段目の半導体チップ１０上には、２段目の半導体チップ１０が搭載される（図１（ｂ）参照。）。１段目の半導体チップ１０の一方の面のバンプ電極１２と、２段目の半導体チップ１０の回路が形成されていない他方の面のバンプ電極１２とが互いに接合される。このように、２段目の半導体チップ１０は、１段目の半導体チップ１０上に接続固定される。   The second-stage semiconductor chip 10 is mounted on the first-stage semiconductor chip 10 held on the suction stage 100 (see FIG. 1B). The bump electrode 12 on one surface of the first-stage semiconductor chip 10 and the bump electrode 12 on the other surface where the circuit of the second-stage semiconductor chip 10 is not formed are bonded to each other. Thus, the second-stage semiconductor chip 10 is connected and fixed on the first-stage semiconductor chip 10.

バンプ電極１２同士の接合には、例えば、高温（例えば３００℃程度）に設定したボンディングツール１１０により半導体チップ１０に所定の荷重を加える熱圧着法が用いられる。なお、半導体チップ１０同士の接合には、熱圧着法だけでなく、超音波を印加しつつ圧着する超音波圧着法、あるいはこれらを併用する超音波熱圧着法を用いることができる。ボンディングツール１１０は、吸着孔１１２を有することが好ましく、半導体チップ１０を吸着保持できる。   For bonding the bump electrodes 12, for example, a thermocompression bonding method in which a predetermined load is applied to the semiconductor chip 10 by the bonding tool 110 set to a high temperature (for example, about 300 ° C.) is used. For joining the semiconductor chips 10, not only a thermocompression bonding method but also an ultrasonic pressure bonding method in which a pressure is applied while applying an ultrasonic wave, or an ultrasonic thermocompression bonding method using these in combination can be used. The bonding tool 110 preferably has a suction hole 112 and can hold the semiconductor chip 10 by suction.

２段目の半導体チップ１０上には、上記と同様の手順で３段目の半導体チップ１０を接続固定し、３段目の半導体チップ１０上には、上記と同様の手順で４段目の半導体チップ１０を接続固定する(図１（ｃ）参照)。このようにして、４つの半導体チップ１０が積層されたチップ積層体１１が構成される。本実施例の態様に限定されず、チップ積層体１１は、２つ以上の半導体チップ１０を含んでいれば良い。   The third-stage semiconductor chip 10 is connected and fixed on the second-stage semiconductor chip 10 in the same procedure as above, and the fourth-stage on the third-stage semiconductor chip 10 in the same procedure as above. The semiconductor chip 10 is connected and fixed (see FIG. 1C). In this way, a chip stack 11 in which four semiconductor chips 10 are stacked is configured. Without being limited to the aspect of the present embodiment, the chip stacked body 11 only needs to include two or more semiconductor chips 10.

次に、図２（ａ）に示すように、チップ積層体１１を、ステージ１２０上に形成された凹部１２２内に配置する。ステージ１２０に形成された凹部１２２の表面には塗布用シート１２１が貼られている。塗布用シート１２１は、フッ素系シートやシリコン系接着材が塗布されたシート等のように、封止材（アンダーフィル材）１４に対する濡れ性が悪い材料であることが好ましい。これは、封止材の熱硬化時に、封止材１４が塗布用シート１２１へ付着することを防止するためである。   Next, as shown in FIG. 2A, the chip stack 11 is placed in a recess 122 formed on the stage 120. A coating sheet 121 is attached to the surface of the recess 122 formed in the stage 120. The coating sheet 121 is preferably a material having poor wettability with respect to the sealing material (underfill material) 14 such as a fluorine-based sheet or a sheet coated with a silicon-based adhesive. This is to prevent the sealing material 14 from adhering to the coating sheet 121 when the sealing material is thermally cured.

ステージ１２０の凹部１２２の底には、吸着孔１２３が設けられていることが好ましい。これにより、吸着孔１２３によりチップ積層体１１を吸引することで、チップ積層体１１が凹部１２２内に保持される。   An adsorption hole 123 is preferably provided at the bottom of the recess 122 of the stage 120. As a result, the chip stack 11 is held in the recess 122 by sucking the chip stack 11 through the suction holes 123.

一例として、チップ積層体１１は略直方体形状であり、凹部１２２はチップ積層体１１よりも大きい直方体形状である。これにより、チップ積層体１１の一側面３１と凹部１２２の側面３２との間に隙間１２４が生じる。   As an example, the chip stacked body 11 has a substantially rectangular parallelepiped shape, and the recess 122 has a rectangular parallelepiped shape larger than the chip stacked body 11. As a result, a gap 124 is generated between one side 31 of the chip stack 11 and the side 32 of the recess 122.

次に、液状の封止材１４を、チップ積層体１１と凹部１２２の側面３２との間の隙間１２４から凹部１２２内へ注入する（図２（ｂ）参照。）。封止材１４は、ディスペンサ１３０により供給することができる。   Next, the liquid sealing material 14 is injected into the recess 122 from the gap 124 between the chip stack 11 and the side surface 32 of the recess 122 (see FIG. 2B). The sealing material 14 can be supplied by the dispenser 130.

凹部１２２の深さは、チップ積層体１１の下面から最上段の半導体チップ１０の下面までの距離より大きく、かつ、チップ積層体１１の下面から最上段の半導体チップ１０の上面までの距離より小さい範囲にあることが好ましい。これにより、液状の封止材１４は、半導体チップ１０間の隙間へ毛細管現象によって進入し、半導体チップ１０間の隙間を埋める。また、チップ積層体１１の上面、つまりバンプ電極１２が存在する面に封止材１１が付着することが防止される。封止材１４は、例えば熱硬化性の樹脂が用いられる。   The depth of the recess 122 is larger than the distance from the lower surface of the chip stack 11 to the lower surface of the uppermost semiconductor chip 10 and smaller than the distance from the lower surface of the chip stack 11 to the upper surface of the uppermost semiconductor chip 10. It is preferable to be in the range. As a result, the liquid sealing material 14 enters the gap between the semiconductor chips 10 by capillary action, and fills the gap between the semiconductor chips 10. Further, the sealing material 11 is prevented from adhering to the upper surface of the chip stacked body 11, that is, the surface where the bump electrode 12 exists. As the sealing material 14, for example, a thermosetting resin is used.

図３は、ステージ１２０の凹部１２２内にチップ積層体１１が置かれた状態を示す上面図である。ステージ１２０の表面には、凹部１２２に接続された流出溝１２８が形成されていることが好ましい。流出溝１２８の底面は、凹部１２２に配置されたチップ積層体１１の最上段の半導体チップ１０の上面よりも低い位置にある。これにより、余分な封止材１４は、この流出溝１２８を通って外部へ流出するため、封止材１４がチップ積層体１１の上面へ這い上がることが防止される。したがって、チップ積層体１１を配線基板へ実装する際に、封止材１４の這い上がりに起因した接続不良が抑制できる。   FIG. 3 is a top view showing a state where the chip stack 11 is placed in the recess 122 of the stage 120. An outflow groove 128 connected to the recess 122 is preferably formed on the surface of the stage 120. The bottom surface of the outflow groove 128 is at a position lower than the top surface of the uppermost semiconductor chip 10 of the chip stack 11 disposed in the recess 122. As a result, excess sealing material 14 flows out to the outside through the outflow groove 128, so that the sealing material 14 is prevented from creeping up to the upper surface of the chip stack 11. Therefore, when the chip stack 11 is mounted on the wiring board, connection failure due to the creeping of the sealing material 14 can be suppressed.

本実施例では、図２に示すように、チップ積層体１１の、図中左側の側面３３が凹部１２２の側面３４に接するように、チップ積層体１１が配置されている。これにより、チップ積層体１１を、凹部１２２内の所定の位置に容易に位置決めできる。チップ積層体１１は、少なくとも１つの側面が凹部１２２に接することが好ましいが、図３に示すように、チップ積層体１１の３つの側面３３が凹部の３つの側面３４に接することがより好ましい。これにより、封止材１４に対するチップ積層体１１の位置が精度良く決定される。   In the present embodiment, as shown in FIG. 2, the chip stack 11 is arranged such that the left side 33 of the chip stack 11 is in contact with the side 34 of the recess 122. Thereby, the chip stacked body 11 can be easily positioned at a predetermined position in the recess 122. It is preferable that at least one side surface of the chip stacked body 11 is in contact with the recess 122, but as shown in FIG. 3, it is more preferable that the three side surfaces 33 of the chip stacked body 11 are in contact with the three side surfaces 34 of the recess. Thereby, the position of the chip laminated body 11 with respect to the sealing material 14 is determined with high accuracy.

次に、封止材１４を硬化させる（図２（ｃ）参照。）。封止材１４は、所定の温度、例えば１５０℃程度でキュア(熱処理)することで熱硬化される。ステージ１２０は、ヒータ１２６を備えていることが好ましい。そして、熱硬化の際、ステージ１２０の少なくとも凹部１２２周辺をヒータ１２６によって加熱する。これにより、凹部１２２の底面だけでなく凹部の側面も加熱することができ、チップ積層体１１の上部と下部とにおける温度差が抑制される。したがって、封止材１４の充填性が向上し、ボイドの発生が抑制できる。封止材１４の硬化後、封止材１４を含むチップ積層体１１はステージ１２０の凹部１２２から取りだされる（図２（ｄ）参照。）。   Next, the sealing material 14 is cured (see FIG. 2C). The sealing material 14 is thermally cured by curing (heat treatment) at a predetermined temperature, for example, about 150 ° C. The stage 120 preferably includes a heater 126. Then, at the time of thermosetting, at least the periphery of the recess 122 of the stage 120 is heated by the heater 126. Thereby, not only the bottom surface of the recess 122 but also the side surface of the recess can be heated, and the temperature difference between the upper part and the lower part of the chip stack 11 is suppressed. Therefore, the filling property of the sealing material 14 is improved, and generation of voids can be suppressed. After the sealing material 14 is cured, the chip stack 11 including the sealing material 14 is taken out from the concave portion 122 of the stage 120 (see FIG. 2D).

上記の製造方法によれば、ステージ１２０の凹部１２２内にチップ積層体１１を保持した状態で、凹部１２２内に封止材１４を供給するため、複数製造されたチップ積層体１１の外形を均一化することができる。そのため、チップ積層体１１の、配線基板への実装精度を向上できる。また、凹部１２２内に封止体１４を供給するだけで、半導体チップ１０間の隙間やチップ積層体１１の周りに、容易に封止材１４を構成することができる。   According to the manufacturing method described above, the sealing material 14 is supplied into the recess 122 in a state where the chip stack 11 is held in the recess 122 of the stage 120. Therefore, the outer shape of the plurality of manufactured chip stacks 11 is uniform. Can be Therefore, the mounting accuracy of the chip stack 11 on the wiring board can be improved. In addition, the sealing material 14 can be easily formed around the gaps between the semiconductor chips 10 and around the chip stack 11 only by supplying the sealing body 14 into the recess 122.

次に、上記のチップ積層体１１を含む半導体装置の組み立ての手順について、図４及び図５を用いて説明する。図４及び図５は、複数のチップ積層体１１を用い、複数の半導体装置を一括して形成するための組み立て手順の一例を示している。   Next, a procedure for assembling the semiconductor device including the chip stack 11 will be described with reference to FIGS. 4 and 5. 4 and 5 show an example of an assembly procedure for collectively forming a plurality of semiconductor devices using a plurality of chip stacks 11.

まず、マトリックス状に配置された複数の製品形成部２６を備えた配線基板２０を準備する。製品形成部２６とは、各々の半導体装置の配線基板２０となる部位である。各製品形成部２６には所定のパターンの配線が形成されている。各配線は、接続パッド２１及びランド２３の部分を除いてゾルダーレジスト膜等の絶縁膜によって覆われている。配線基板２０の、製品形成部２６間には、個々の製品形成部２６に切り離す際のダイシングラインが形成されている。   First, the wiring board 20 provided with the several product formation part 26 arrange | positioned at matrix form is prepared. The product forming part 26 is a part that becomes the wiring board 20 of each semiconductor device. Each product forming section 26 is formed with a predetermined pattern of wiring. Each wiring is covered with an insulating film such as a solder resist film except for the connection pad 21 and the land 23. A dicing line is formed between the product forming portions 26 of the wiring board 20 when the wiring substrate 20 is separated into individual product forming portions 26.

配線基板２０の一方の面には、チップ積層体１１と電気的に接続される複数の接続パッド２１が形成されている。配線基板２０の他方の面には外部端子となる金属ボールが搭載される複数のランド２３が形成されている。これら接続パッド２１は、対応するランド２３と配線によって電気的に接続されている。配線基板２０の接続パッド２１には、チップ積層体１１のバンプ電極１２と接続されるワイヤバンプ１５が搭載されている。   A plurality of connection pads 21 that are electrically connected to the chip stack 11 are formed on one surface of the wiring board 20. A plurality of lands 23 on which metal balls to be external terminals are mounted are formed on the other surface of the wiring board 20. These connection pads 21 are electrically connected to corresponding lands 23 by wiring. Wire bumps 15 connected to the bump electrodes 12 of the chip stack 11 are mounted on the connection pads 21 of the wiring board 20.

配線基板２０の準備が完了すると、図４（ａ）に示すように、配線基板２０の各製品形成部２６上に、絶縁性の接着部材２４、例えば非導電性ペースト（Non Conductive Paste：ＮＣＰ）をディスペンサ１５０により塗布する。   When the preparation of the wiring board 20 is completed, as shown in FIG. 4A, an insulating adhesive member 24 such as a non-conductive paste (NCP) is formed on each product forming portion 26 of the wiring board 20. Is applied by a dispenser 150.

次に、上述した方法により封止材１４が形成されたチップ積層体１１を、配線基板２０に搭載する。具体的には、チップ積層体１１をボンディングツール１６０等で吸着保持し、配線基板２０のそれぞれの製品形成部２６に搭載する（図４（ｂ）参照）。そして、チップ積層体１１のバンプ電極１２と各接続パッド２１上のワイヤバンプとを、例えば熱圧着法を用いて接合する。このとき、配線基板２０上に塗布していた接着部材２４が、チップ積層体１１と配線基板２０との間に充填され、配線基板２０とチップ積層体１１とが接着固定される（図４（ｃ）参照）。   Next, the chip stack 11 on which the sealing material 14 is formed by the above-described method is mounted on the wiring board 20. Specifically, the chip stack 11 is sucked and held by the bonding tool 160 or the like and mounted on each product forming portion 26 of the wiring board 20 (see FIG. 4B). And the bump electrode 12 of the chip | tip laminated body 11 and the wire bump on each connection pad 21 are joined, for example using a thermocompression bonding method. At this time, the adhesive member 24 applied on the wiring board 20 is filled between the chip stack 11 and the wiring board 20, and the wiring board 20 and the chip stack 11 are bonded and fixed (FIG. 4 ( c)).

ここで、複数のチップ積層体１１の外形は均一であるため、チップ積層体１１を精度良く配線基板に搭載できる。また、個々のチップ積層体１１において、封止材１４に対する半導体チップ１０の位置が正確に決められていることで、半導体チップ１０のバンプ電極１２と配線基板２０の接続パッド２１とを、精度良く位置決めできる。   Here, since the external shape of the plurality of chip stacks 11 is uniform, the chip stacks 11 can be mounted on the wiring board with high accuracy. In addition, since the position of the semiconductor chip 10 with respect to the sealing material 14 is accurately determined in each chip stacked body 11, the bump electrodes 12 of the semiconductor chip 10 and the connection pads 21 of the wiring substrate 20 can be accurately connected. Can be positioned.

チップ積層体１１が搭載された配線基板２０は、不図示のトランスファモールド装置の、上型と下型とから成る成型金型にセットされ、モールド工程が行われる。成型金型には、複数のチップ積層体１１を一括して覆う不図示のキャビティが形成されており、該キャビティ内に配線基板２０上に搭載されたチップ積層体１１が収容される。   The wiring board 20 on which the chip stack 11 is mounted is set in a molding die composed of an upper mold and a lower mold in a transfer mold apparatus (not shown), and a molding process is performed. The molding die is formed with a cavity (not shown) that collectively covers the plurality of chip stacks 11, and the chip stacks 11 mounted on the wiring board 20 are accommodated in the cavities.

次に、成型金型のキャビティ内に加熱溶融させた封止樹脂２５を注入し、配線基板２０上の複数のチップ積層体１１全体を覆う封止樹脂２５を形成する。封止樹脂２５には、エポキシ樹脂等の熱硬化性樹脂を用いることができる。   Next, the sealing resin 25 that is heated and melted is injected into the cavity of the molding die to form the sealing resin 25 that covers the entire plurality of chip stacks 11 on the wiring substrate 20. As the sealing resin 25, a thermosetting resin such as an epoxy resin can be used.

続いて、所定の温度、例えば１８０℃程度でキュアすることで、封止樹脂２５を熱硬化させる。これにより、図５（ａ）に示すように、複数の製品形成部２６上に搭載された複数のチップ積層体１１全体を覆う封止樹脂２５が形成される。さらに、所定の温度でベークすることで、封止樹脂２５を完全に硬化させる。   Subsequently, the sealing resin 25 is cured by curing at a predetermined temperature, for example, about 180 ° C. As a result, as shown in FIG. 5A, the sealing resin 25 that covers the entire plurality of chip stacks 11 mounted on the plurality of product forming portions 26 is formed. Further, the sealing resin 25 is completely cured by baking at a predetermined temperature.

本実施例では、チップ積層体１１を構成する半導体チップ１０間を封止材１４で封止した後、複数のチップ積層体１１全体を覆う別の封止樹脂２５を形成する。そのため、半導体チップ１０間の隙間でボイドが発生することが抑制される。   In this example, after sealing between the semiconductor chips 10 constituting the chip stacked body 11 with the sealing material 14, another sealing resin 25 covering the whole of the plurality of chip stacked bodies 11 is formed. Therefore, generation of voids in the gap between the semiconductor chips 10 is suppressed.

次に、ボールマウント工程を実施し、図５（ｂ）に示すように、配線基板２０の他方の面に形成されたランド２３に、外部端子を接続する。外部端子としては、導電性の金属ボール２２、例えば半田ボールを用いることができる。   Next, a ball mounting process is performed, and external terminals are connected to the lands 23 formed on the other surface of the wiring board 20 as shown in FIG. As the external terminal, a conductive metal ball 22, such as a solder ball, can be used.

ボールマウント工程では、好ましくは、複数の吸着孔を備えたマウントツール１７０が用いられる。吸着孔の位置は、配線基板２０の各ランド２３の位置と一致する。吸着孔は金属ボール２２を吸着保持する。マウントツール１７０は、金属ボール２２にフラックスを転写した後、各金属ボール２２を配線基板２０のランド２３上に一括して搭載する。全ての製品形成部２６に金属ボール２２を搭載した後、配線基板２０をリフローすることで各金属ボール２２と各ランド２３とを接続する。   In the ball mounting process, preferably, a mounting tool 170 having a plurality of suction holes is used. The position of the suction hole coincides with the position of each land 23 of the wiring board 20. The suction hole holds the metal ball 22 by suction. The mount tool 170 transfers the flux to the metal balls 22 and then mounts the metal balls 22 on the lands 23 of the wiring board 20 in a lump. After the metal balls 22 are mounted on all the product forming portions 26, the wiring balls 20 are reflowed to connect the metal balls 22 and the lands 23.

金属ボール２２の接続が完了すると、基板ダイシング工程に移行を実施する。基板ダイシング工程では、所定のダイシングラインに沿って、配線基板２０を製品形成部２６毎に切断および分離することで半導体装置１を形成する。   When the connection of the metal balls 22 is completed, a transition is made to the substrate dicing process. In the substrate dicing step, the semiconductor device 1 is formed by cutting and separating the wiring substrate 20 for each product forming portion 26 along a predetermined dicing line.

基板ダイシング工程では、封止樹脂２５にダイシングテープ１８０を貼着することで製品形成部２６を支持する。そして、図５（ｃ）に示すように、不図示のダイシング装置が備えるダイシングブレード１８１により所定のダイシングラインに沿って配線基板２０を切断する。これにより、製品形成部２６毎に配線基板２０が分離される。その後、ダイシングテープ１８０から製品形成部２６をピックアップすることで、図６に示すようなＣｏＣ型の半導体装置１が得られる。   In the substrate dicing process, the product forming portion 26 is supported by sticking the dicing tape 180 to the sealing resin 25. Then, as shown in FIG. 5C, the wiring board 20 is cut along a predetermined dicing line by a dicing blade 181 provided in a dicing device (not shown). As a result, the wiring board 20 is separated for each product forming portion 26. Thereafter, by picking up the product forming portion 26 from the dicing tape 180, a CoC type semiconductor device 1 as shown in FIG. 6 is obtained.

本実施例によれば、複数の半導体チップ１０を積載したチップ積層体１１を先に作成し、その後、配線基板２０に該チップ積層体１１を接続固定する。これにより、製造中の熱によって、半導体チップ１０と配線基板２０との熱膨張係数や剛性の違いに起因して、半導体チップ１０間の接続部や半導体チップ１０へ加わる熱応力が低減される。そのため、半導体チップ１０間の接続部の破断や、半導体チップ１０にクラックが発生することを抑制できる。   According to the present embodiment, the chip stack 11 on which the plurality of semiconductor chips 10 are stacked is first created, and then the chip stack 11 is connected and fixed to the wiring board 20. Thereby, the thermal stress applied to the connection part between the semiconductor chips 10 and the semiconductor chip 10 due to the difference in thermal expansion coefficient and rigidity between the semiconductor chip 10 and the wiring substrate 20 due to heat during manufacture is reduced. Therefore, it is possible to suppress the breakage of the connection portion between the semiconductor chips 10 and the occurrence of cracks in the semiconductor chip 10.

平坦なステージ上で、チップ積層体に封止材を供給すると、封止材が広がり、幅広のフィレットを形成することがある。本実施例では、封止材１４の外形は、ステージ１２０に形成された凹部１２２の形状で決定されるため、フィレットの広がりに起因する、半導体装置サイズの大型化が抑制される。   When a sealing material is supplied to the chip stack on a flat stage, the sealing material may spread and form a wide fillet. In this embodiment, since the outer shape of the sealing material 14 is determined by the shape of the recess 122 formed in the stage 120, an increase in the size of the semiconductor device due to the spread of the fillet is suppressed.

さらに、各々のチップ積層体１１の上下での封止材１４の厚さを均一化できるため、封止材１４の硬化や収縮等に起因して半導体チップにかかる応力を分散化でき、バンプ接続の信頼性を向上できる。   Furthermore, since the thickness of the sealing material 14 above and below each chip stack 11 can be made uniform, the stress applied to the semiconductor chip due to hardening or shrinkage of the sealing material 14 can be dispersed, and bump connection Can improve the reliability.

次に、第２の実施例における半導体装置の製造方法について、図７および図８を参照して説明する。第２の実施例における半導体装置の製造方法は、第１の実施例とほぼ同様であるが、チップ積層体１１に封止材１４を塗布する工程が異なっている。   Next, a semiconductor device manufacturing method according to the second embodiment will be described with reference to FIGS. The manufacturing method of the semiconductor device in the second embodiment is almost the same as that of the first embodiment, but the process of applying the sealing material 14 to the chip stack 11 is different.

本実施例では、複数の半導体チップ１０がバンプ電極１２を介して互いに積載されたチップ積層体１１を、ステージ１２０の凹部１２２の中央に配置する。具体的には、図７（ａ）および図８に示すように、チップ積層体１１の互いに対向する２つの側面４１と凹部１２２の側面４２との間に、互いに同じ間隔の隙間１２４が開けられている。さらに、チップ積層体１１の他の２つの側面４３は凹部１２２の側面４４に接している。   In this embodiment, a chip stack 11 in which a plurality of semiconductor chips 10 are stacked on each other via bump electrodes 12 is arranged at the center of the recess 122 of the stage 120. Specifically, as shown in FIGS. 7A and 8, a gap 124 having the same interval is opened between the two side surfaces 41 facing each other of the chip stack 11 and the side surface 42 of the recess 122. ing. Further, the other two side surfaces 43 of the chip stack 11 are in contact with the side surface 44 of the recess 122.

この状態で、吸着孔１２３よりチップ積層体１１を、吸引し、保持する。この後、ステージ１２０の凹部１２２の側面とチップ積層体１１との間の隙間１２４から、封止材１４を凹部１２２内に供給する。これ以降の工程は、第１の実施例と同様に行い、その結果、図９に示す半導体装置１が完成する。第２の実施例の製造方法では、第１の実施例と同様に、チップ積層体の外形を均一化や、容易にアンダーフィルを塗布することができる。   In this state, the chip stack 11 is sucked and held through the suction holes 123. Thereafter, the sealing material 14 is supplied into the recess 122 from the gap 124 between the side surface of the recess 122 of the stage 120 and the chip stack 11. Subsequent steps are performed in the same manner as in the first embodiment. As a result, the semiconductor device 1 shown in FIG. 9 is completed. In the manufacturing method of the second embodiment, as in the first embodiment, the outer shape of the chip stack can be made uniform or the underfill can be easily applied.

また、本実施例では、チップ積層体１１を凹部１２２の中央に配置するため、チップ積層体１１の両側に均等に封止材１４が形成される（図７（ｄ）および図９参照。）。これにより、封止材１４の硬化後に生じる、チップ積層体１１の反りのバランスが良くなるという利点がある。   In this embodiment, since the chip stack 11 is disposed at the center of the recess 122, the sealing material 14 is formed evenly on both sides of the chip stack 11 (see FIGS. 7D and 9). . Thereby, there exists an advantage that the balance of the curvature of the chip | tip laminated body 11 produced after hardening of the sealing material 14 becomes good.

以上、本発明者によってなされた発明を実施例に基づき説明したが、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   As mentioned above, although the invention made | formed by this inventor was demonstrated based on the Example, this invention is not limited to the said Example, It cannot be overemphasized that it can change variously in the range which does not deviate from the summary.

例えば、チップ積層体は、メモリチップが積層したものであってもよいが、メモリチップとロジックチップ等、どのようなチップの組み合わせから構成されていても良い。   For example, the chip stack may be a stack of memory chips, but may be formed of any combination of chips such as a memory chip and a logic chip.

また、図では、同じサイズの半導体チップが積層したチップ積層体が示されているが、異なるサイズの半導体チップが積層したチップ積層体を用いても良い。   Further, in the drawing, a chip stacked body in which semiconductor chips of the same size are stacked is shown, but a chip stacked body in which semiconductor chips of different sizes are stacked may be used.

また、本発明は、ＢＧＡ型の半導体装置だけではなく、例えばＬＧＡ（Ｌａｎｄ Ｇｒｉｄ Ａｒｒａｙ）型のような、他の型の半導体装置に適用することもできる。   Further, the present invention can be applied not only to a BGA type semiconductor device but also to other types of semiconductor devices such as an LGA (Land Grid Array) type.

１ 半導体装置
１０ 半導体チップ
１１ チップ積層体
１２ バンプ電極
１３ 貫通電極
１４ 封止材
１５ ワイヤバンプ
２０ 配線基板
２１ 接続パッド
２２ 金属ボール
２３ ランド
２４ 接着部材
２５ 封止樹脂
２６ 製品形成部
１００ 吸着ステージ
１０１ 凹部
１０２ 吸着孔
１０３ テーパ部
１１０，１６０ ボンディングツール
１１２ 吸着孔
１２０ ステージ
１２１ 塗布用シート
１２２ 凹部
１２３ 吸着孔
１２４ 隙間
１２６ ヒータ
１２８ 流出溝
１３０，１５０ ディスペンサ
１７０ マウントツール
１８０ ダイシングテープ
１８１ ダイシングブレード DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor chip 11 Chip laminated body 12 Bump electrode 13 Through electrode 14 Sealing material 15 Wire bump 20 Wiring board 21 Connection pad 22 Metal ball 23 Land 24 Adhesive member 25 Sealing resin 26 Product formation part 100 Adsorption stage 101 Recess 102 Adsorption hole 103 Tapered part 110, 160 Bonding tool 112 Adsorption hole 120 Stage 121 Application sheet 122 Recess 123 Adsorption hole 124 Clearance 126 Heater 128 Outflow groove 130, 150 Dispenser 170 Mounting tool 180 Dicing tape 181 Dicing blade

Claims (7)

複数の半導体チップが積層されたチップ積層体を有する半導体装置を製造する方法であって、
複数の半導体チップがバンプ電極を介して積載されたチップ積層体を、ステージ上に形成された凹部内に配置する工程と、
液状の封止材を、前記凹部内の前記チップ積層体と前記凹部の側面との間の隙間から前記凹部内へ注入する工程と、
前記封止材を硬化させる工程と、を有する半導体装置の製造方法。 A method of manufacturing a semiconductor device having a chip stack in which a plurality of semiconductor chips are stacked,
A step of arranging a chip stack in which a plurality of semiconductor chips are stacked via bump electrodes in a recess formed on the stage;
Injecting a liquid sealing material into the recess from a gap between the chip stack in the recess and a side surface of the recess;
And a step of curing the sealing material. 前記凹部の深さは、前記チップ積層体の下面から前記チップ積層体の最上段の半導体チップの下面までの距離より大きく、かつ、前記チップ積層体の前記下面から前記最上段の半導体チップの上面までの距離より小さい、請求項１に記載の半導体装置の製造方法。   The depth of the recess is greater than the distance from the lower surface of the chip stack to the lower surface of the uppermost semiconductor chip of the chip stack, and the upper surface of the uppermost semiconductor chip from the lower surface of the chip stack. The method for manufacturing a semiconductor device according to claim 1, wherein the method is smaller than the distance to 前記凹部に接続された溝が前記ステージの表面に形成されており、
前記溝の底面が、前記凹部内に配置された前記チップ積層体の最上段の半導体チップの上面よりも低い位置にある、請求項１または２に記載の半導体装置の製造方法。 A groove connected to the recess is formed on the surface of the stage,
3. The method of manufacturing a semiconductor device according to claim 1, wherein a bottom surface of the groove is at a position lower than an upper surface of the uppermost semiconductor chip of the chip stack disposed in the recess. 前記封止材は熱硬化性樹脂であり、
前記ステージの少なくとも前記凹部の周辺を加熱することによって、前記凹部内の前記熱硬化性樹脂を硬化させる、請求項１から３のいずれか１項に記載の半導体装置の製造方法。 The sealing material is a thermosetting resin,
4. The method of manufacturing a semiconductor device according to claim 1, wherein the thermosetting resin in the recess is cured by heating at least the periphery of the recess of the stage. 5. 前記チップ積層体の少なくとも１つの側面が前記凹部の側面に接するように、前記チップ積層体を前記凹部内に配置する、請求項１から４のいずれか１項に記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 1, wherein the chip stack is disposed in the recess so that at least one side of the chip stack contacts the side of the recess. 前記チップ積層体を前記凹部の中央に配置する、請求項１から４のいずれか１項に記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 1, wherein the chip stack is disposed at a center of the recess. 複数の半導体チップがバンプ電極を介して積載されたチップ積層体を、ステージ上に形成された凹部内に配置する工程と、
液状の封止材を、前記凹部内の前記チップ積層体と前記凹部の側面との間の隙間から前記凹部内へ注入する工程と、
前記封止材を硬化させる工程と、を実施して前記封止材が形成された前記チップ積層体を複数作り、
前記封止材が形成された前記複数のチップ積層体を、所定の配線が形成された製品形成部を複数有する配線基板上の、それぞれの前記製品形成部に搭載する工程と、
前記配線基板上の前記複数のチップ積層体全体を封止樹脂で覆う工程と、
前記配線基板を、前記製品形成部毎に切断分離する工程と、をさらに有する半導体装置の製造方法。 A step of arranging a chip stack in which a plurality of semiconductor chips are stacked via bump electrodes in a recess formed on the stage;
Injecting a liquid sealing material into the recess from a gap between the chip stack in the recess and a side surface of the recess;
The step of curing the sealing material, and making a plurality of the chip stack body on which the sealing material is formed,
Mounting the plurality of chip stacks on which the sealing material is formed on each of the product formation portions on a wiring substrate having a plurality of product formation portions on which predetermined wiring is formed; and
Covering the whole of the plurality of chip stacks on the wiring board with a sealing resin;
And a step of cutting and separating the wiring board for each product forming section.
JP2010152994A 2010-07-05 2010-07-05 Method of manufacturing semiconductor device Pending JP2012015446A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013222859A (en) * 2012-04-17 2013-10-28 Sumitomo Bakelite Co Ltd Method for manufacturing laminate
JP2014029955A (en) * 2012-07-31 2014-02-13 Toyota Industries Corp Sealing part molding jig, semiconductor device, and method for manufacturing semiconductor device
US11929332B2 (en) 2020-07-07 2024-03-12 Kioxia Corporation Semiconductor device and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013222859A (en) * 2012-04-17 2013-10-28 Sumitomo Bakelite Co Ltd Method for manufacturing laminate
JP2014029955A (en) * 2012-07-31 2014-02-13 Toyota Industries Corp Sealing part molding jig, semiconductor device, and method for manufacturing semiconductor device
US11929332B2 (en) 2020-07-07 2024-03-12 Kioxia Corporation Semiconductor device and manufacturing method thereof

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