JP2009135279A - Ceramic chip component - Google Patents

Ceramic chip component Download PDF

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Publication number
JP2009135279A
JP2009135279A JP2007310316A JP2007310316A JP2009135279A JP 2009135279 A JP2009135279 A JP 2009135279A JP 2007310316 A JP2007310316 A JP 2007310316A JP 2007310316 A JP2007310316 A JP 2007310316A JP 2009135279 A JP2009135279 A JP 2009135279A
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ceramic chip
chip component
ceramic
stress relaxation
insulating resin
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Atsushi Onohara
淳 小野原
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Toppan Inc
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Toppan Printing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein a stress is concentrated on the surface of a ceramic material and peeling from an insulating resin occurs, in a ceramic chip component of a ceramic chip resistor or a ceramic chip capacitor incorporated or sealed in a wiring board, a semiconductor package, a function module or the like. <P>SOLUTION: In the ceramic chip component 103 of the ceramic chip resistor or the ceramic chip capacitor sealed with the insulating resin and incorporated in the wiring board, the semiconductor package or the function module, a stress mitigation layer 103a is provided on the entire surface of the ceramic material which is the insulation part of the ceramic chip component. The stress mitigation layer comprises a polymer selected from polyimide, benzocyclobutene, fluorinated polyimide and porous PTFE. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、配線基板、半導体パッケージあるいは機能モジュール等に絶縁性樹脂で封止されて内蔵されるセラミックチップ部品に関する。   The present invention relates to a ceramic chip component that is sealed and embedded in an insulating resin in a wiring board, a semiconductor package, a functional module, or the like.

配線基板へ抵抗体あるいはコンデンサを埋め込む要求は、近年の電子機器の小型化高密度化に伴いますます高まってきている。抵抗体、コンデンサ等の受動部品を基板へ埋め込む技術としては大きく分けて次の２種類がある。ひとつは既存の表面実装用セラミックチップ部品を直接埋め込む方法であり、もうひとつは配線基板等の製造技術を応用して抵抗体等を造りこむ方法である。両者とも長所短所を備えており、現在も活発に開発が進められている。   The demand for embedding a resistor or a capacitor in a wiring board is increasing with the recent miniaturization and higher density of electronic devices. There are the following two types of techniques for embedding passive components such as resistors and capacitors in a substrate. One is a method of directly embedding an existing ceramic chip component for surface mounting, and the other is a method of building a resistor or the like by applying a manufacturing technique such as a wiring board. Both have strengths and weaknesses and are still under active development.

一方、半導体素子の封止に関しては、ＱＦＰやＳＯＰなどさまざまな形態が実用化されており、例えば特許文献１においては、半導体チップの上面にポリイミド層の応力緩和層を形成している。   On the other hand, various forms such as QFP and SOP have been put into practical use for sealing semiconductor elements. For example, in Patent Document 1, a stress relaxation layer of a polyimide layer is formed on the upper surface of a semiconductor chip.

以下に公知文献を記す。
特開平５−２１６５３号公報 The known literature is described below.
JP-A-5-21653

従来は、配線基板、半導体パッケージ、あるいは機能モジュール等に、埋め込み用のセラミックチップ抵抗またはセラミックチップコンデンサのセラミックチップ部品を絶縁性樹脂で封止して内蔵すると、そのセラミックチップ部品とそれを覆う絶縁性樹脂の密着性が悪く、恒温吸湿等の信頼性試験を行うと、セラミックチップ部品と絶縁性樹脂が剥離する問題を生じた。その原因は、セラミックチップ部品のセラミックス材料の表面に応力が集中して絶縁性樹脂との間で剥離を生じるためと考えられる。この対策として、特許文献１のように半導体素子の上面に応力緩和層を設ける技術をセラミックチップ部品に適用しても有効な効果を生じるかは、セラミックチップ部品は半導体素子とは寸法と形状と材質が違うため、それが有効であるか不明であった。そのため、本発明者は、絶縁性樹脂との密着性を向上させるに、セラミックチップ部品の表面に応力緩和層を設ける技術を研究し本発明を得た。   Conventionally, when a ceramic chip resistor or ceramic chip capacitor for embedding is sealed in an insulating resin and embedded in a wiring board, semiconductor package, or functional module, the ceramic chip component and the insulation covering it The adhesiveness of the conductive resin was poor, and when a reliability test such as constant temperature moisture absorption was performed, there was a problem that the ceramic chip component and the insulating resin peeled off. The cause is considered to be that stress concentrates on the surface of the ceramic material of the ceramic chip part and peeling occurs between the insulating resin. As a countermeasure against this, whether or not the technique of providing a stress relaxation layer on the upper surface of a semiconductor element as in Patent Document 1 can produce an effective effect is applied to the ceramic chip part. Since the material was different, it was unknown whether it was effective. Therefore, the present inventor has studied the technique of providing a stress relaxation layer on the surface of the ceramic chip component in order to improve the adhesion with the insulating resin, and obtained the present invention.

本発明は、この課題を解決するために、配線基板、半導体パッケージ又は機能モジュールに絶縁性樹脂で封止されて内蔵されるセラミックチップ抵抗またはセラミックチップコンデンサのセラミックチップ部品において、前記セラミックチップ部品の絶縁部であるセラミックス材料の全表面に応力緩和層を有することを特徴とするセラミックチップ部品である。   In order to solve this problem, the present invention provides a ceramic chip resistor or ceramic chip capacitor ceramic chip component embedded in a wiring board, a semiconductor package or a functional module by being sealed with an insulating resin. A ceramic chip component comprising a stress relaxation layer on the entire surface of a ceramic material as an insulating portion.

また、本発明は、上記応力緩和層の厚みが０．５μｍ以上２０μｍ以下であることを特徴とする上記のセラミックチップ部品である。   The present invention also provides the above ceramic chip component, wherein the stress relaxation layer has a thickness of 0.5 μm or more and 20 μm or less.

また、本発明は、上記応力緩和層が、ポリイミド、ベンゾシクロブテン、フッ素化ポリイミド、多孔質ＰＴＦＥから選択されたポリマーからなることを特徴とする上記のセラミックチップ部品である。   The present invention is the above ceramic chip component, wherein the stress relaxation layer is made of a polymer selected from polyimide, benzocyclobutene, fluorinated polyimide, and porous PTFE.

本発明は、配線基板、半導体パッケージ、あるいは機能モジュール等に内蔵、封止されるセラミックチップ抵抗またはセラミックチップコンデンサ等のセラミックチップ部品において、絶縁部のセラミックス材料の全表面に厚さが０．５μｍ〜２０μｍの応力緩和層を設けて、そのセラミックチップ部品を半導体パッケージ等に絶縁性樹脂で接着して埋め込むことにより、絶縁性樹脂との剥離を防ぎ信頼性が高い配線基板、半導体パッケージ、あるいは機能モジュールが得られる効果がある。   The present invention provides a ceramic chip component such as a ceramic chip resistor or a ceramic chip capacitor that is embedded and sealed in a wiring board, a semiconductor package, or a functional module, and has a thickness of 0.5 μm on the entire surface of the ceramic material of the insulating portion. By providing a stress relaxation layer of ˜20 μm and embedding the ceramic chip component by adhering it to the semiconductor package or the like with an insulating resin, it is possible to prevent peeling from the insulating resin and to provide a highly reliable wiring board, semiconductor package or function There is an effect that a module is obtained.

本発明のセラミックチップ部品１０３を基板に内蔵する製造方法は、図１のように、先ず、導電パターンを形成してある導電箔を用意して、少なくとも回路素子の搭載部を多数個用意してあるパターンを形成した導電箔１０１の上に回路素子を固着する第１の工程と、前記導電箔の前記ブロック周辺の残余部をモールド金型で挟み、前記ブロックの各搭載部分を同一の面内に配置して絶縁性樹脂１０５でトランスファーモールドする第２の工程と、前記ブロックの絶縁性樹脂１０５を各搭載毎にダイシングにより分離する第３の工程とから成る。   As shown in FIG. 1, in the manufacturing method for incorporating the ceramic chip component 103 of the present invention into a substrate, first, a conductive foil having a conductive pattern is prepared, and at least a large number of circuit element mounting portions are prepared. A first step of fixing a circuit element on the conductive foil 101 on which a certain pattern is formed, and a remaining portion around the block of the conductive foil are sandwiched by a mold, and each mounting portion of the block is in the same plane And the second step of transfer molding with the insulating resin 105 and the third step of separating the insulating resin 105 of the block by dicing for each mounting.

この製造方法で用いる、本発明のセラミックチップ部品１０３は、縦横の寸法が０．２ｍｍから１ｍｍで高さが０．２ｍｍから０．５ｍｍのセラミックチップ抵抗またはセラミックチップコンデンサのセラミックチップ部品１０３に、その絶縁部のセラミックス材料の全表面に厚さが０．５μｍ〜２０μｍの応力緩和層１０３ａを設ける。   The ceramic chip component 103 of the present invention used in this manufacturing method is a ceramic chip resistor or ceramic chip capacitor 103 having a vertical and horizontal dimension of 0.2 mm to 1 mm and a height of 0.2 mm to 0.5 mm. A stress relaxation layer 103a having a thickness of 0.5 μm to 20 μm is provided on the entire surface of the ceramic material of the insulating portion.

以下に、本発明に係るセラミックチップ部品１０３を内蔵する基板の一実施例を図面に基づいて詳細に説明する。
（工程１）
図１（ａ）に示すように、回路素子の搭載部のパターンを形成したリードフレームの導電箔１０１を用意した。この導電箔１０１はロウ材の付着性、ボンディング性、めっき性が考慮されてその材料を選択し、材料としては、銅を主体とした導電箔１０１、またはＦｅ−Ｎｉ等の合金からなる導電箔１０１を用いた。 Hereinafter, an embodiment of a substrate incorporating a ceramic chip component 103 according to the present invention will be described in detail with reference to the drawings.
(Process 1)
As shown in FIG. 1A, a lead frame conductive foil 101 having a circuit element mounting portion pattern formed thereon was prepared. The conductive foil 101 is selected in consideration of the adhesiveness, bonding property, and plating property of the brazing material. As the material, the conductive foil 101 made mainly of copper or the conductive foil made of an alloy such as Fe-Ni is used. 101 was used.

（工程２）
次に、図１（ｂ）に示す如く、所望の導電パターンの各搭載部に回路素子を固着し、各搭載部の電極と所望の導電パターンと電気的に接続する接続手段を形成した。以下に、工程２の内容を詳しく説明する。 (Process 2)
Next, as shown in FIG. 1B, a circuit element was fixed to each mounting portion of the desired conductive pattern, and a connection means for electrically connecting the electrode of each mounting portion to the desired conductive pattern was formed. Below, the content of the process 2 is demonstrated in detail.

工程２で実装する回路素子は、トランジスタ、ダイオード、ＩＣチップ１０２等の半導体素子、セラミックチップコンデンサ、セラミックチップ抵抗等の受動部品である。また、厚みは厚くなるが、ＣＳＰ、ＢＧＡ等のフェイスダウンの半導体素子も実装できる。本実施例では、図２（ａ）の平面図で示すように、ＩＣチップ１０２と、縦横高さが０．６ｍｍ×０．３ｍｍ×０．３ｍｍのセラミックチップコンデンサのセラミックチップ部品１０３を実装した。   Circuit elements to be mounted in step 2 are transistors, diodes, semiconductor elements such as an IC chip 102, passive components such as ceramic chip capacitors and ceramic chip resistors. Although the thickness is increased, face-down semiconductor elements such as CSP and BGA can also be mounted. In this embodiment, as shown in the plan view of FIG. 2A, an IC chip 102 and a ceramic chip component 103 of a ceramic chip capacitor having a height and width of 0.6 mm × 0.3 mm × 0.3 mm are mounted. .

（工程２−１）
このセラミックチップ部品１０３は、搭載する以前に、絶縁部のセラミックス材料の側面を含む全表面に、ポリイミド、ベンゾシクロブテン、フッ素化ポリイミド、多孔質ＰＴＦＥ等のポリマーをスピンコート法で設置した応力緩和層１０３ａを形成しておく。応力緩和層１０３ａは、スピンコート法以外に蒸着重合法で形成することも可能である。応力緩和層１０３ａの厚さは、後の絶縁性樹脂１０５との密着性を考慮すると０．５μｍ〜２０μｍであることが好ましく、ここでは厚みが１０μｍの応力緩和層１０３を形成した。
応力緩和層１０３ａが０．５μｍ未満であると応力緩和層１０３ａとして不十分であり、２０μｍを超えると実装時に接続する導電ペースト１０３ｂ等の厚みを確保するのが困難となる。また、後に信頼性試験で比較するために、比較例として、図２（ｂ）に示す配置で、応力緩和層１０３ａが無いセラミックチップコンデンサのセラミックチップ部品２０１を実装した基板も作製した。 (Step 2-1)
Before mounting this ceramic chip component 103, stress relaxation is achieved by installing a polymer such as polyimide, benzocyclobutene, fluorinated polyimide, porous PTFE, etc. on the entire surface including the side surface of the ceramic material of the insulating portion by spin coating. A layer 103a is formed. The stress relaxation layer 103a can also be formed by a vapor deposition polymerization method other than the spin coating method. The thickness of the stress relaxation layer 103a is preferably 0.5 μm to 20 μm in consideration of the adhesion to the insulating resin 105 later, and here, the stress relaxation layer 103 having a thickness of 10 μm is formed.
When the stress relaxation layer 103a is less than 0.5 μm, the stress relaxation layer 103a is insufficient, and when it exceeds 20 μm, it is difficult to secure the thickness of the conductive paste 103b and the like to be connected during mounting. Further, for comparison in a reliability test later, as a comparative example, a substrate on which the ceramic chip component 201 of the ceramic chip capacitor without the stress relaxation layer 103a was mounted in the arrangement shown in FIG.

（工程２−２）
次に、図１（ｃ）に示すように、ベアのトランジスタチップを導電パターンにダイボンディングし、エミッタ電極と導電パターン、ベース電極と導電パターンを、熱圧着によるボールディングあるいは超音波によるウェッヂボンディング等で固着した金配線１０４を介して接続する。またセラミック部品１０３は、はんだ等のロウ材または導電ペースト１０３ｂで固着した。 (Process 2-2)
Next, as shown in FIG. 1C, the bare transistor chip is die-bonded to the conductive pattern, and the emitter electrode and the conductive pattern, the base electrode and the conductive pattern are bonded by thermo-bonding or ultrasonic bonding. The connection is made through the gold wiring 104 fixed in the above. The ceramic component 103 was fixed with a brazing material such as solder or a conductive paste 103b.

（工程３）
次に、図１（ｄ）に示すごとく、導電箔のブロック周辺の残余部をモールド金型で挟み、ブロックの各搭載部を同一のキャビティ内に配置し、絶縁性樹脂１０５でトランスファーモールドした。 (Process 3)
Next, as shown in FIG. 1 (d), the remaining portion around the block of the conductive foil was sandwiched between mold dies, each mounting portion of the block was placed in the same cavity, and transfer molded with insulating resin 105.

（工程４）
次に、図３に示すごとく、絶縁性樹脂１０５を搭載部毎にダイシングにより分離して機能モジュールを得た。 (Process 4)
Next, as shown in FIG. 3, the insulating resin 105 was separated by dicing for each mounting portion to obtain a functional module.

（温度サイクル（ＴＣＴ）による信頼性評価結果）
実施例によって得られた一括モールド基板について、ＪＥＤＥＣ（合同電子デバイス委員会、Joint Electron Device Engineering Council）発行規格、ＪＥＳＤ２２−Ａ１１３Ｄに規定されている手順で前処理を行なった。具体的には、まず−４０℃から６０℃の温度サイクルに５サイクル通し、次に１２５℃のオーブンに２４時間入れ、その後、３０℃―６０％ＲＨの恒温恒湿槽にて１９２時保存し、そこから取り出して直ちに、鉛フリーはんだ使用を想定したリフロープロファイルにて、３サイクルのリフロー過程に通した。 (Reliability evaluation result by temperature cycle (TCT))
The batch mold substrate obtained in the example was pretreated by the procedure specified in JEDEC (Joint Electron Device Engineering Council) standard, JESD22-A113D. Specifically, it is first passed through a temperature cycle of −40 ° C. to 60 ° C. for 5 cycles, then placed in an oven at 125 ° C. for 24 hours, and then stored at 192 hours in a constant temperature and humidity chamber of 30 ° C.-60% RH. Immediately after taking it out, it was passed through a reflow process of 3 cycles with a reflow profile assuming use of lead-free solder.

次に、ＴＣＴ試験を行なった。具体的には、気相にて−５５℃の温度条件で３０分曝し、次に１２５℃の温度条件で３０分曝すサイクルを１０００回繰り返した。各温度の切り替え時間については、装置の能力の許す限り速やかに行なった。   Next, a TCT test was performed. Specifically, the cycle of exposure in the gas phase at −55 ° C. for 30 minutes and then exposure to 125 ° C. for 30 minutes was repeated 1000 times. The switching time of each temperature was performed as quickly as the capacity of the apparatus allowed.

その後、超音波探査映像装置(Scanning Acoustic Tomgraph ; ＳＡＴ)にて非破壊で絶縁性樹脂１０５内部の観察をした。観察した結果は、セラミックス材料の表面に応力緩和層１０３ａを形成したセラミックチップ部品１０３では、セラミックス材料と絶縁性樹脂１０５の界面で剥離がなく良好であった。しかし、応力緩和層１０３ａがないセラミックス材料と絶縁性樹脂１０５の界面では絶縁性樹脂１０５との間で剥離がみられた。これは、温度サイクル試験により絶縁性樹脂１０５が収縮することによりその部分のセラミックス材料の表面から絶縁性樹脂１０５が剥離したからである。これにより、従来の半導体素子の技術をそのまま適用し上面にのみ応力緩和層を設けたのでは、セラミックチップ部品側面で絶縁性樹脂１０５が剥離する問題を生じる知見が得られた。そのため、本発明のセラミックチップ部品１０３では、セラミックス材料の側面を含む全表面に応力緩和層１０３ａを形成する。このように、ＴＣＴ試験を行った結果、応力緩和層１０３ａをセラミックス材料の全表面に形成したセラミックチップ部品１０３においては、高い信頼性を維持することができる知見が得られた。   Thereafter, the inside of the insulating resin 105 was observed in a non-destructive manner with an ultrasonic exploration imaging device (Scanning Acoustic Tomgraph; SAT). As a result of the observation, in the ceramic chip component 103 in which the stress relaxation layer 103a is formed on the surface of the ceramic material, there was no peeling at the interface between the ceramic material and the insulating resin 105, which was good. However, peeling was observed between the insulating resin 105 at the interface between the ceramic material without the stress relaxation layer 103 a and the insulating resin 105. This is because the insulating resin 105 is peeled from the surface of the ceramic material of the portion due to the shrinkage of the insulating resin 105 in the temperature cycle test. As a result, it has been found that if the conventional semiconductor element technology is applied as it is and the stress relaxation layer is provided only on the upper surface, the insulating resin 105 peels off on the side surface of the ceramic chip component. Therefore, in the ceramic chip component 103 of the present invention, the stress relaxation layer 103a is formed on the entire surface including the side surface of the ceramic material. As described above, as a result of the TCT test, it was found that the ceramic chip component 103 in which the stress relaxation layer 103a is formed on the entire surface of the ceramic material can maintain high reliability.

本発明は、配線基板、半導体パッケージ、あるいは機能モジュール等に内蔵、封止され
るセラミックチップ抵抗またはセラミックチップコンデンサ等のセラミックチップ部品１０３に使用できる。 The present invention can be used for a ceramic chip component 103 such as a ceramic chip resistor or a ceramic chip capacitor embedded and sealed in a wiring board, a semiconductor package, or a functional module.

本発明の実施の形態における機能モジュールの製造工程を示す模式断面図である。It is a schematic cross section which shows the manufacturing process of the functional module in embodiment of this invention. 本発明の実施例の機能モジュールの製造方法を説明する図である。It is a figure explaining the manufacturing method of the functional module of the Example of this invention. 本発明の実施例の機能モジュールの製造方法を説明する図である。It is a figure explaining the manufacturing method of the functional module of the Example of this invention.

符号の説明Explanation of symbols

１０１・・・導電箔
１０２・・・ＩＣチップ
１０３・・・（応力緩和層を有する）セラミックチップ部品
１０３ａ・・・応力緩和層
１０３ｂ・・・導電ペースト
１０４・・・金配線
１０５・・・絶縁性樹脂
２０１・・・（応力緩和層が無い）セラミックチップ部品 DESCRIPTION OF SYMBOLS 101 ... Conductive foil 102 ... IC chip 103 ... Ceramic chip component 103a (with stress relaxation layer) ... Stress relaxation layer 103b ... Conductive paste 104 ... Gold wiring 105 ... Insulation Resin 201 ... (no stress relief layer) ceramic chip parts

Claims (3)

配線基板、半導体パッケージ又は機能モジュールに絶縁性樹脂で封止されて内蔵されるセラミックチップ抵抗またはセラミックチップコンデンサのセラミックチップ部品において、前記セラミックチップ部品の絶縁部であるセラミックス材料の全表面に応力緩和層を有することを特徴とするセラミックチップ部品。   In a ceramic chip resistor or ceramic chip capacitor ceramic chip component that is sealed in an insulating resin and embedded in a wiring board, semiconductor package or functional module, stress relaxation is applied to the entire surface of the ceramic material that is the insulating portion of the ceramic chip component. A ceramic chip component comprising a layer. 前記応力緩和層の厚みが０．５μｍ以上２０μｍ以下であることを特徴とする請求項１記載のセラミックチップ部品。   The ceramic chip component according to claim 1, wherein the stress relaxation layer has a thickness of 0.5 μm to 20 μm. 前記応力緩和層が、ポリイミド、ベンゾシクロブテン、フッ素化ポリイミド、多孔質ＰＴＦＥから選択されたポリマーからなることを特徴とする請求項１又は２に記載のセラミックチップ部品。   3. The ceramic chip component according to claim 1, wherein the stress relaxation layer is made of a polymer selected from polyimide, benzocyclobutene, fluorinated polyimide, and porous PTFE. 4.
JP2007310316A 2007-11-30 2007-11-30 Ceramic chip component Pending JP2009135279A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014099487A (en) * 2012-11-14 2014-05-29 Toyota Motor Corp Semiconductor device
JP2017152603A (en) * 2016-02-26 2017-08-31 三菱電機株式会社 Power semiconductor module and manufacturing method of the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014099487A (en) * 2012-11-14 2014-05-29 Toyota Motor Corp Semiconductor device
US9013047B2 (en) 2012-11-14 2015-04-21 Toyota Jidosha Kabushiki Kaisha Semiconductor device
JP2017152603A (en) * 2016-02-26 2017-08-31 三菱電機株式会社 Power semiconductor module and manufacturing method of the same

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