JP2009188392A - Semiconductor device and method of manufacturing semiconductor device - Google Patents
Semiconductor device and method of manufacturing semiconductor device Download PDFInfo
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- JP2009188392A JP2009188392A JP2009001419A JP2009001419A JP2009188392A JP 2009188392 A JP2009188392 A JP 2009188392A JP 2009001419 A JP2009001419 A JP 2009001419A JP 2009001419 A JP2009001419 A JP 2009001419A JP 2009188392 A JP2009188392 A JP 2009188392A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
本発明は、配線基板、半導体パッケージあるいは機能モジュール等の半導体装置に関する。 The present invention relates to a semiconductor device such as a wiring board, a semiconductor package, or a functional module.
従来の半導体チップを含む配線基板、半導体パッケージ、あるいは機能モジュール等では、半導体チップと封止用の絶縁性樹脂との間において密着性が悪く、剥離等の問題を生じていた。特にワイヤボンディング接続等のフェイスアップの半導体チップでは、剥離によってワイヤー断線等の問題が生じるため、半導体チップの回路形成面に、応力緩和のための樹脂層を形成するという方法が用いられている（特許文献１、２参照）。この問題は、フリップチップ接続の場合についても同様である。 In a conventional wiring board, semiconductor package, or functional module including a semiconductor chip, the adhesion between the semiconductor chip and the insulating resin for sealing is poor, causing problems such as peeling. In particular, in a face-up semiconductor chip such as a wire bonding connection, a problem such as wire breakage occurs due to peeling, so a method of forming a resin layer for stress relaxation on the circuit formation surface of the semiconductor chip is used ( (See Patent Documents 1 and 2). This problem also applies to the case of flip chip connection.
近年、半導体チップの高集積化に伴い、チップサイズの大型化が進んでおり、特に大型半導体チップを用いた半導体装置では、チップおよび封止に用いる絶縁性樹脂にかかる応力が増大することから、回路形成面以外の界面でも剥離が生じ、恒温吸湿等の信頼性試験において問題となる。 In recent years, with the high integration of semiconductor chips, the chip size has been increased, and particularly in a semiconductor device using a large semiconductor chip, the stress applied to the insulating resin used for the chip and sealing increases. Peeling occurs at the interface other than the circuit forming surface, which causes a problem in reliability tests such as constant temperature moisture absorption.
そこで本願発明では、チップサイズの大型化に際しても、封止用絶縁樹脂と半導体チップ間での剥離を抑制し、信頼性の優れた半導体チップ及びその製造方法を提供することを目的とする。 Accordingly, an object of the present invention is to provide a highly reliable semiconductor chip and a method for manufacturing the same, in which peeling between the sealing insulating resin and the semiconductor chip is suppressed even when the chip size is increased.
上記課題を解決するために為された本発明の請求項１に係る発明は、少なくとも回路形成面の裏面に応力緩和層を有する半導体チップを、導電パターンを有する配線基板に搭載し、絶縁性樹脂にて封止したことを特徴とする半導体装置。
半導体装置である。
The invention according to claim 1 of the present invention, which has been made to solve the above-mentioned problems, includes mounting a semiconductor chip having a stress relaxation layer on at least the back surface of the circuit forming surface on a wiring substrate having a conductive pattern, and insulating resin. A semiconductor device characterized by being sealed with.
It is a semiconductor device.
本発明の請求項２に係る発明は、請求項１に係る発明において、前記応力緩和層の厚みが０．５ｕｍ〜２０ｕｍであることを特徴とする半導体装置である。 The invention according to claim 2 of the present invention is the semiconductor device according to claim 1, wherein the stress relaxation layer has a thickness of 0.5 μm to 20 μm.
本発明の請求項３に係る発明は、請求項１、２に係る発明において、前記応力緩和層が、ポリイミド、ベンゾシクロブテン、フッ素化ポリイミド、多孔質ＰＴＦＥから選択されたポリマーからなることを特徴とする半導体装置である。 The invention according to claim 3 of the present invention is the invention according to claims 1 and 2, wherein the stress relaxation layer is made of a polymer selected from polyimide, benzocyclobutene, fluorinated polyimide, and porous PTFE. This is a semiconductor device.
本発明の請求項４に係る発明は、請求項１から３に係る発明において、前記配線基板封止用絶縁樹脂の弾性率をＥ１とし、前記応力緩和層の弾性率をＥ２としたとき、Ｅ１／Ｅ２＝３〜９となるようにしたことを特徴とする半導体装置である。 The invention according to claim 4 of the present invention is the invention according to claims 1 to 3, wherein E1 is an elastic modulus of the insulating resin for sealing the wiring board, and E2 is an elastic modulus of the stress relaxation layer. / E2 = 3 to 9 is a semiconductor device characterized by that.
本発明の請求項５に係る発明は、請求項１から４に係る発明において、前記半導体チップの少なくとも一辺が１０ｍｍ以上であることを特徴とする半導体装置である。 The invention according to claim 5 of the present invention is the semiconductor device according to claims 1 to 4, wherein at least one side of the semiconductor chip is 10 mm or more.
本発明の請求項６に係る発明は、前記半導体チップと導電パターンを有する配線基板が、フリップチップ接続されていることを特徴とする半導体装置である。 The invention according to claim 6 of the present invention is a semiconductor device characterized in that the semiconductor chip and a wiring substrate having a conductive pattern are flip-chip connected.
本発明の請求項７に係る発明は、請求項１から６に係る発明において、該半導体チップを、導電パターンを有する配線基板に搭載後、アンダーフィル樹脂を含む２種類の樹脂を用いて封止したことを特徴とする半導体装置である。 The invention according to claim 7 of the present invention is the invention according to claims 1 to 6, wherein the semiconductor chip is mounted on a wiring board having a conductive pattern and then sealed with two types of resins including an underfill resin. This is a semiconductor device.
本発明の請求項８に係る発明は、請求項１から６に係る発明において、前記半導体チップが、１種類の樹脂を用いて封止されていることを特徴とする半導体装置である。 The invention according to claim 8 of the present invention is the semiconductor device according to any one of claims 1 to 6, wherein the semiconductor chip is sealed using one kind of resin.
本発明の請求項９に係る発明は、少なくとも回路形成面の裏面に応力緩和層を有する半導体チップを、導電パターンを有する配線基板に搭載する工程と、
前記半導体チップを搭載した配線基板を絶縁性樹脂で封止する工程と、を有する半導体装置の製造方法である。
The invention according to claim 9 of the present invention includes a step of mounting a semiconductor chip having a stress relaxation layer on at least the back surface of the circuit formation surface on a wiring board having a conductive pattern;
Sealing a wiring board on which the semiconductor chip is mounted with an insulating resin.
本発明の請求項１０に係る発明は、請求項９記載の半導体装置の製造方法において、前記導電パターンのブロックごとに半導体チップを搭載し、前記半導体チップを搭載した配線基板を絶縁性樹脂で封止する工程の後、前記ブロックごとにダイシングにより分離することを特徴とする半導体装置の製造方法である。 According to a tenth aspect of the present invention, in the semiconductor device manufacturing method according to the ninth aspect, a semiconductor chip is mounted for each block of the conductive pattern, and the wiring board on which the semiconductor chip is mounted is sealed with an insulating resin. After the step of stopping, the semiconductor device is manufactured by dicing each block.
半導体チップの回路形成面の裏面に応力緩和層を形成することにより、封止用絶縁性樹脂との剥離を防ぎ、信頼性が高い配線基板、半導体パッケージ、あるいは機能モジュール等となる。 By forming a stress relaxation layer on the back surface of the circuit formation surface of the semiconductor chip, peeling from the sealing insulating resin is prevented, and a highly reliable wiring board, semiconductor package, or functional module is obtained.
本発明の半導体装置は、図１（ａ）に示されるように、半導体チップ１０２がリードフレーム１０１等の導電パターンを有する配線基板に搭載され、少なくとも該半導体チップの回路形成面の裏面に応力緩和層１０２ａを形成し、該半導体装置を覆うように絶縁樹脂１０５で封止されていることを特徴とする半導体装置である。 In the semiconductor device of the present invention, as shown in FIG. 1A, a semiconductor chip 102 is mounted on a wiring board having a conductive pattern such as a lead frame 101, and stress relaxation is performed at least on the back surface of the circuit formation surface of the semiconductor chip. A semiconductor device is characterized in that a layer 102a is formed and sealed with an insulating resin 105 so as to cover the semiconductor device.
本発明の半導体装置では、封止用絶縁樹脂１０５と半導体チップの表面との間に応力緩和層１０２ａが存在することにより、温度変化による封止用絶縁樹脂の形状変化の影響を緩和し、封止用絶縁樹脂の剥離を防ぐことができる。この効果は、特に半導体チップのチップサイズが大きい場合に有効である。チップサイズが大きくなるとともに、回路が形成されていない裏面では封止用絶縁樹脂の形状変化の影響も大きくなるためである。具体的には、少なくとも半導体チップの一辺が１０ｍｍ以上の大きさの半導体チップで特に有効である。また、回路形成面にも同様に応力緩和層１０２ａを形成してもよい。半導体チップの接続部分での断線を防ぐことができる。これらの応力緩和層に用いる材料としては、ポリイミド、ベンゾシクロブテン、フッ素化ポリイミド、多孔質ＰＴＦＥ等のポリマー樹脂を好適に用いることができる。これにより、半導体チップと封止用絶縁樹脂との熱膨張係数の差によるクラックの発生を防止することができる。 In the semiconductor device of the present invention, since the stress relaxation layer 102a exists between the sealing insulating resin 105 and the surface of the semiconductor chip, the influence of the shape change of the sealing insulating resin due to the temperature change is reduced, and the sealing is performed. The peeling of the insulating resin for stopping can be prevented. This effect is particularly effective when the chip size of the semiconductor chip is large. This is because the chip size is increased and the influence of the shape change of the sealing insulating resin is increased on the back surface where the circuit is not formed. Specifically, it is particularly effective for a semiconductor chip having a size of at least 10 mm on one side of the semiconductor chip. Similarly, the stress relaxation layer 102a may be formed on the circuit formation surface. Disconnection at the connection portion of the semiconductor chip can be prevented. As materials used for these stress relaxation layers, polymer resins such as polyimide, benzocyclobutene, fluorinated polyimide, and porous PTFE can be suitably used. Thereby, generation | occurrence | production of the crack by the difference in the thermal expansion coefficient of a semiconductor chip and the insulating resin for sealing can be prevented.
さらに、封止用絶縁樹脂１０５の弾性率をＥ１、応力緩和層の弾性率をＥ２としたとき、Ｅ１／Ｅ２＝３〜９となるようにすると、応力緩和層を形成した効果がより大きくなる。Ｅ１／Ｅ２が３未満であると、応力緩和層の効果が十分でないことが考えられる。Ｅ１／Ｅ２が９より大きくなると、クラック等の不具合が発生する虞がある。なお上記弾性率は貯蔵弾性率（動的弾性率）を意味するものとする。当該弾性率はＪＩＳＫ ７２４４に記載される方法で測定することができる。 Furthermore, when the elastic modulus of the sealing insulating resin 105 is E1 and the elastic modulus of the stress relaxation layer is E2, the effect of forming the stress relaxation layer becomes greater when E1 / E2 = 3-9. . If E1 / E2 is less than 3, it is considered that the effect of the stress relaxation layer is not sufficient. When E1 / E2 is larger than 9, there is a risk that defects such as cracks may occur. The elastic modulus means storage elastic modulus (dynamic elastic modulus). The elastic modulus can be measured by the method described in JISK 7244.
応力緩和層１０２ａの厚みは、封止用絶縁性樹脂１０５との密着性及び応力緩和層としての機能を考慮すると０．５μｍ〜２０μｍであることが好ましい。０．５μｍ以下だと応力緩和層としての効果が十分でない虞があり、２０μｍ以上だと密着性に問題が生じる虞がある。 The thickness of the stress relaxation layer 102a is preferably 0.5 μm to 20 μm in consideration of the adhesion with the sealing insulating resin 105 and the function as the stress relaxation layer. If it is 0.5 μm or less, the effect as a stress relaxation layer may not be sufficient, and if it is 20 μm or more, there may be a problem in adhesion.
本発明に用いる封止用絶縁樹脂１０５としては、公知の絶縁樹脂を用いることが可能である。具体的には、シリカ等のフィラーを含有したエポキシ樹脂等を用いることができる。 As the insulating resin 105 for sealing used in the present invention, a known insulating resin can be used. Specifically, an epoxy resin containing a filler such as silica can be used.
本発明に用いる半導体チップとしては、トランジスタ、ダイオード、ＩＣチップ等、さらには、セラミックコンデンサ、セラミック抵抗等の受動部品も搭載可能である。特にフリップチップ接続では、半導体チップの回路形成面の裏面が基板の反対側に位置し、チップ上にモールドされた封止用絶縁樹脂１０５の形状変化の影響を大きく受けることから特に効果的であるが、ワイヤボンディング等フェイスアップの半導体チップでも同様に実装することができる。 As semiconductor chips used in the present invention, transistors, diodes, IC chips, and the like, and passive components such as ceramic capacitors and ceramic resistors can be mounted. In particular, flip chip connection is particularly effective because the back surface of the circuit formation surface of the semiconductor chip is located on the opposite side of the substrate and is greatly affected by the shape change of the sealing insulating resin 105 molded on the chip. However, a face-up semiconductor chip such as wire bonding can be similarly mounted.
また半導体チップを覆う封止用絶縁樹脂の他に、半導体チップと配線基板の間にアンダーフィル層１０４を挿入し、アンダーフィル樹脂を含む２種類の樹脂を用いて封止されている構成としても良い。これにより配線基板と半導体チップ間の熱膨張等による応力を緩和することができる。 In addition to the sealing insulating resin that covers the semiconductor chip, an underfill layer 104 is inserted between the semiconductor chip and the wiring board, and sealing is performed using two types of resins including the underfill resin. good. Thereby, stress due to thermal expansion or the like between the wiring board and the semiconductor chip can be relaxed.
また、図１（ｂ）に示すように、半導体の上部にリッドを配置しても良い。リッドとしては、セラミックス、ガラス、金属等公知の材料を用いることができる。リッドを配置することにより、放熱および外部からの保護等の効果を期待できる。リッドを配置した場合においても、応力緩和層を半導体チップ上に形成することにより、同様に剥離を防ぐことができる。 In addition, as shown in FIG. 1B, a lid may be disposed on the semiconductor. As the lid, known materials such as ceramics, glass, and metal can be used. By arranging the lid, effects such as heat radiation and external protection can be expected. Even in the case where the lid is disposed, peeling can be similarly prevented by forming the stress relaxation layer on the semiconductor chip.
本発明に用いるリードフレーム（導電パターン）１０１の材料としては、はんだ等のロウ材の付着性、ボンディング性、めっき性を考慮する必要があるが、公知のリードフレーム材料を用いることができる。具体的には、Ｃｕを主体とした導電箔またはＦｅ−Ｎｉ等の合金からなる導電箔を用いることができる。 As a material of the lead frame (conductive pattern) 101 used in the present invention, it is necessary to consider the adhesiveness, bonding property, and plating property of a brazing material such as solder, but a known lead frame material can be used. Specifically, a conductive foil mainly composed of Cu or a conductive foil made of an alloy such as Fe—Ni can be used.
次に、本発明の半導体装置の製造方法について説明する。 Next, a method for manufacturing a semiconductor device of the present invention will be described.
本発明の製造方法は、導電パターンが形成された配線基板の該導電パターン上に、少なくとも回路形成面の裏面に応力緩和層を有する半導体チップを実装する工程と、該半導体チップを搭載した配線基板を絶縁性樹脂で封止する工程とから構成されている。以下に詳細に説明する。 The manufacturing method of the present invention includes a step of mounting a semiconductor chip having a stress relaxation layer on at least the back surface of the circuit formation surface on the conductive pattern of the wiring substrate on which the conductive pattern is formed, and a wiring substrate on which the semiconductor chip is mounted. And a step of sealing with an insulating resin. This will be described in detail below.
まず、半導体チップを基板に実装する前に、応力緩和層１０２ａを形成する。形成方法としては、ウェハー状態の半導体チップの表面に液状の樹脂を所定のマスクを用いて塗布することができる。塗布方法としては、塗布方法はスピンコート、スクリーン印刷等の公知の塗布方法を用いることができる。その後、必要に応じて焼成、エッチングを行って、応力緩和層を形成する。回路形成面にも応力緩和層を形成する場合は、バンプ等の接続部分以外の場所に同様の工程で形成する。 First, the stress relaxation layer 102a is formed before mounting the semiconductor chip on the substrate. As a forming method, a liquid resin can be applied to the surface of a semiconductor chip in a wafer state using a predetermined mask. As the coating method, a known coating method such as spin coating or screen printing can be used. Thereafter, firing and etching are performed as necessary to form a stress relaxation layer. When the stress relaxation layer is formed also on the circuit formation surface, it is formed in the same process at a place other than the connection portion such as a bump.
次に、配線基板上に応力緩和層を形成した半導体チップを実装する（図２（ｂ））。具体的には導電パターンを形成した導電箔を用意して、少なくとも半導体チップの搭載部を用意してある導電箔の上に半導体チップを固着する。前述のように、実装方法としてはフリップチップ接続、ワイヤボンディング接続等の公知の接続方法を用いることができる。また、このとき必要に応じてアンダーフィル層１０４を形成する（図２（ｃ））。ただしアンダーフィル樹脂を必要とせず、１種類の樹脂で封止できる場合には、アンダーフィル工程を省略でき、製造工程を簡略化できる。 Next, a semiconductor chip having a stress relaxation layer formed on the wiring board is mounted (FIG. 2B). Specifically, a conductive foil having a conductive pattern is prepared, and the semiconductor chip is fixed on the conductive foil on which at least a semiconductor chip mounting portion is prepared. As described above, a known connection method such as flip chip connection or wire bonding connection can be used as the mounting method. At this time, an underfill layer 104 is formed as necessary (FIG. 2C). However, when an underfill resin is not required and sealing can be performed with one type of resin, the underfill process can be omitted, and the manufacturing process can be simplified.
アンダーフィル層を形成する材料については、公知の絶縁樹脂を用いることが可能である。具体的には、シリカ等のフィラーを含有したエポキシ樹脂を用いることができる。このときアンダーフィル樹脂の流動性を高め、半導体チップと配線基板間に充填しやすくするために、封止用絶縁樹脂よりもフィラーの含有量を少なくすることが好ましい。 As a material for forming the underfill layer, a known insulating resin can be used. Specifically, an epoxy resin containing a filler such as silica can be used. At this time, in order to increase the fluidity of the underfill resin and facilitate filling between the semiconductor chip and the wiring substrate, it is preferable to reduce the filler content as compared with the sealing insulating resin.
次に、図２（ｄ）に示すように、封止樹脂により、半導体チップが搭載された配線基板を封止する。樹脂封止の方法としては、具体的には図３に示すように導電パターンの各ブロック周辺の残余部をモールド金型で挟み、ブロックの各搭載部を同一のキャビティ内に配置し、絶縁性樹脂１０５でトランスファーモールドすることができる。あるいは、オーバーコート等の公知の塗布形成方法を用いてもよい。また、図１（ｂ）で示したように、半導体チップ上にリッドを含んだ構造としてもよい。 Next, as shown in FIG. 2D, the wiring substrate on which the semiconductor chip is mounted is sealed with a sealing resin. Specifically, as shown in FIG. 3, the resin sealing method is performed by sandwiching the remaining portion around each block of the conductive pattern with a mold, and placing each mounting portion of the block in the same cavity, thereby insulating the resin. Transfer molding can be performed with the resin 105. Or you may use well-known coating formation methods, such as overcoat. Further, as shown in FIG. 1B, a structure including a lid on a semiconductor chip may be used.
次に、導電パターンのブロックごとにダイシングにより分離して、本発明の半導体装置となる。この工程は、前記樹脂封止する工程と相前後しても良いが、樹脂封止する工程の後に分離すれば、各ブロックを一括で樹脂封止することができるために好ましい。
以上の工程で、本発明の半導体装置を製造することができる。
Next, each block of the conductive pattern is separated by dicing to obtain the semiconductor device of the present invention. This step may be performed in parallel with the resin sealing step, but it is preferable to separate the blocks after the resin sealing step because the blocks can be collectively resin-sealed.
Through the above steps, the semiconductor device of the present invention can be manufactured.
本発明に係る半導体装置の実施形態の一例を図面に基づいて以下に説明する。 An example of an embodiment of a semiconductor device according to the present invention will be described below with reference to the drawings.
まず図２（ａ）に示すようなリードフレームを用意する。材料としては、Ｃｕを主体とした導電箔を用いた。 First, a lead frame as shown in FIG. As a material, a conductive foil mainly composed of Cu was used.
次に、図２（ｂ）に示すように、所望の導電パターンの搭載部に半導体チップを固着し、搭載部の電極と所望の導電箔と電気的に接続した。ここでは、半導体チップ１０２とセラミックコンデンサ１０３を実装した。 Next, as shown in FIG. 2B, the semiconductor chip was fixed to the mounting portion of the desired conductive pattern, and the electrode of the mounting portion and the desired conductive foil were electrically connected. Here, the semiconductor chip 102 and the ceramic capacitor 103 are mounted.
半導体チップ１０２は導電箔にフリップチップ接続した。またセラミックコンデンサ１０３は、はんだ等のロウ材または導電ペースト１０３ｂで固着される。フリップチップ接続後、図２（ｃ）に示すように、半導体チップの回路形成面と配線基板の導電パターンとの間にアンダーフィル層を形成する。 The semiconductor chip 102 was flip-chip connected to the conductive foil. Further, the ceramic capacitor 103 is fixed with a brazing material such as solder or a conductive paste 103b. After the flip chip connection, as shown in FIG. 2C, an underfill layer is formed between the circuit formation surface of the semiconductor chip and the conductive pattern of the wiring board.
半導体チップ１０２は、その両面に応力緩和層１０２ａを形成したものである。応力緩和層は、ウェハー状態の半導体チップの表面に液状の樹脂を所定のマスクを用いて塗布し、その後、焼成、エッチングを行い形成した。ここで形成した応力緩和層の厚みは１０ｕｍであった。また、応力緩和層の曲げ弾性率Ｅ２は３．６ＧＰａである。 The semiconductor chip 102 has a stress relaxation layer 102a formed on both sides thereof. The stress relaxation layer was formed by applying a liquid resin to the surface of a semiconductor chip in a wafer state using a predetermined mask, followed by baking and etching. The thickness of the stress relaxation layer formed here was 10 μm. Moreover, the bending elastic modulus E2 of the stress relaxation layer is 3.6 GPa.
次に、図２（ｄ）に示すように、導電箔のブロック周辺の残余部をモールド金型で挟み、ブロックの各搭載部を同一のキャビティ内に配置し、絶縁性樹脂１０５でトランスファーモールドにより樹脂封止した。絶縁性樹脂の曲げ弾性率Ｅ１は２３ＧＰａであり、Ｅ１／Ｅ２＝６．４となった。 Next, as shown in FIG. 2D, the remaining portion around the block of the conductive foil is sandwiched between mold dies, each mounting portion of the block is placed in the same cavity, and the insulating resin 105 is used for transfer molding. Resin sealed. The bending elastic modulus E1 of the insulating resin was 23 GPa, and E1 / E2 = 6.4.
最後に、図３に示すように、絶縁性樹脂を搭載部毎にダイシングにより各半導体装置を分離して、信頼性評価試験用の本発明の半導体装置の半導体装置を作製した。また、比較例として、半導体チップの両面に応力緩和層のない半導体チップを実装した基板についても応力緩和層を形成しない点以外は同様の工程で作製した。 Finally, as shown in FIG. 3, each semiconductor device was separated by dicing for each mounting portion of an insulating resin, and a semiconductor device of the semiconductor device of the present invention for a reliability evaluation test was manufactured. Further, as a comparative example, a substrate on which a semiconductor chip without a stress relaxation layer was mounted on both sides of the semiconductor chip was manufactured in the same process except that the stress relaxation layer was not formed.
［温度サイクル（ＴＣＴ）による信頼性評価］
実施例によって得られた一括モールド基板について、信頼性評価試験を行った。試験に用いた半導体チップの大きさは、８．５ｍｍ角、１０ｍｍ角、１５ｍｍ角の３種類である。まず、ＪＥＤＥＣ（合同電子デバイス委員会、Ｊｏｉｎｔ Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅ Ｅｎｇｉｎｅｅｒｉｎｇ Ｃｏｕｎｃｉｌ）発行規格、ＪＥＳＤ２２−Ａ１１３Ｄに規定されている手順で前処理を行なった。具体的には、まず−４０℃から６０℃の温度サイクルに５サイクル通し、次に１２５℃のオーブンに２４時間入れ、その後、３０℃―６０％ＲＨの恒温恒湿槽にて１９２時間保存し、そこから取り出して直ちに、鉛フリーはんだ使用を想定したリフロープロファイルにて、３サイクルのリフロー過程に通した。
[Reliability evaluation by temperature cycle (TCT)]
A reliability evaluation test was performed on the collective mold substrate obtained in the example. There are three types of semiconductor chips used in the test: 8.5 mm square, 10 mm square, and 15 mm square. First, pre-processing was performed according to the procedure specified in JEDEC (Joint Electronic Device Engineering Council), JESD22-A113D. Specifically, it is first passed through a temperature cycle from -40 ° C to 60 ° C for 5 cycles, then placed in an oven at 125 ° C for 24 hours, and then stored in a thermostatic chamber at 30 ° C-60% RH for 192 hours. Immediately after taking it out, it was passed through a reflow process of 3 cycles with a reflow profile assuming use of lead-free solder.
次に、ＴＣＴ試験を行った。具体的には、気相にて−５５℃の温度条件を３０分と１２５℃の温度条件に３０分さらすサイクルを１、０００回繰り返した。各温度の切り替え時間については、装置の能力の許す限り速やかに行った。 Next, a TCT test was performed. Specifically, a cycle in which the temperature condition of −55 ° C. was exposed to the temperature condition of 30 minutes and 125 ° C. for 30 minutes in the gas phase was repeated 1,000 times. The switching time of each temperature was performed as quickly as the capacity of the apparatus allowed.
その後、超音波探査映像装置（Ｓｃａｎｎｉｎｇ Ａｃｏｕｓｔｉｃ Ｔｏｍｇｒａｐｈ ； ＳＡＴ）にて非破壊で絶縁性樹脂内部の観察をした。８．５ｍｍ角チップでは、応力緩和層の有無に関わりなく、半導体チップと絶縁性樹脂との界面で剥離は見られなかった。１０ｍｍおよび１５ｍｍ角チップでは、応力緩和層を有した半導体チップにおいて、絶縁性樹脂との界面で剥離がなく良好であった。一方、応力緩和層がない半導体チップでは、絶縁性樹脂との間で剥離がみられた。これは温度サイクル試験により絶縁性樹脂が収縮し、半導体チップの表面と剥離が生じたからである。この結果、１０ｍｍ角以上の大きさの半導体チップでは、応力緩和層を有する場合、ＴＣＴ試験において高い信頼性を維持することが示された。 Thereafter, the inside of the insulating resin was observed in a non-destructive manner with an ultrasonic exploration imaging apparatus (Scanning Acoustic Tomography; SAT). In the 8.5 mm square chip, no peeling was observed at the interface between the semiconductor chip and the insulating resin regardless of the presence or absence of the stress relaxation layer. In the 10 mm and 15 mm square chips, the semiconductor chip having the stress relaxation layer was good without peeling at the interface with the insulating resin. On the other hand, in the semiconductor chip without the stress relaxation layer, peeling was observed between the insulating resin. This is because the insulating resin shrunk by the temperature cycle test and peeled off from the surface of the semiconductor chip. As a result, it was shown that a semiconductor chip having a size of 10 mm square or more maintains high reliability in the TCT test when it has a stress relaxation layer.
本発明は、配線基板、半導体パッケージ、あるいは機能モジュール等の半導体装置に使用できる。 The present invention can be used for a semiconductor device such as a wiring board, a semiconductor package, or a functional module.
１０１・・・リードフレーム
１０２・・・半導体チップ
１０２ａ・・・応力緩和層
１０２ｂ・・・応力緩和層
１０３・・・セラミックコンデンサ
１０３ｂ・・・導電ペースト
１０４・・・アンダーフィル
１０５・・・絶縁性樹脂
１０６・・・リッド
１０７・・・バンプ
DESCRIPTION OF SYMBOLS 101 ... Lead frame 102 ... Semiconductor chip 102a ... Stress relaxation layer 102b ... Stress relaxation layer 103 ... Ceramic capacitor 103b ... Conductive paste 104 ... Underfill 105 ... Insulation Resin 106 ... Lid 107 ... Bump
Claims (10)
前記半導体チップを搭載した配線基板を絶縁性樹脂で封止する工程と、
を有する半導体装置の製造方法。 Mounting a semiconductor chip having a stress relaxation layer on at least the back surface of the circuit forming surface on a wiring substrate having a conductive pattern;
Sealing the wiring board on which the semiconductor chip is mounted with an insulating resin;
A method for manufacturing a semiconductor device comprising:
前記導電パターンのブロックごとに半導体チップを搭載し、
前記半導体チップを搭載した配線基板を絶縁性樹脂で封止する工程の後、前記ブロックごとにダイシングにより分離することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 9,
A semiconductor chip is mounted for each block of the conductive pattern,
A method of manufacturing a semiconductor device, wherein after the step of sealing the wiring substrate on which the semiconductor chip is mounted with an insulating resin, the blocks are separated by dicing.
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