JP3303162B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JP3303162B2
JP3303162B2 JP33884398A JP33884398A JP3303162B2 JP 3303162 B2 JP3303162 B2 JP 3303162B2 JP 33884398 A JP33884398 A JP 33884398A JP 33884398 A JP33884398 A JP 33884398A JP 3303162 B2 JP3303162 B2 JP 3303162B2
Authority
JP
Japan
Prior art keywords
semiconductor element
resin
semiconductor device
resin layer
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP33884398A
Other languages
Japanese (ja)
Other versions
JP2000164610A (en
Inventor
信行 堀田
和朗 徳重
正也 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NGK Spark Plug Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP33884398A priority Critical patent/JP3303162B2/en
Publication of JP2000164610A publication Critical patent/JP2000164610A/en
Application granted granted Critical
Publication of JP3303162B2 publication Critical patent/JP3303162B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、配線基板に半導体素子
をバンプ電極を介して実装する構造、いわゆるフリップ
チップ（以下、Ｆ／Ｃとも称する）実装構造を具備する
半導体装置及びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure in which a semiconductor element is mounted on a wiring board via bump electrodes, that is, a so-called flip-chip (hereinafter also referred to as F / C) mounting structure, and a method of manufacturing the same. Things.

【０００２】[0002]

【従来の技術】近年、半導体装置の高密度実装化、低背
化が進んでおり、従来のワイヤボンディングやＴＡＢ
（Tape Automated Bonding）等の実装方法で対応する
には限界があった。そこで、半導体素子に直接形成した
複数の電極端子を配線基板上の接続端子にダイレクトに
接続するフリップチップ（Ｆ／Ｃ）接続法が注目されて
いる。2. Description of the Related Art In recent years, high-density packaging and reduction in height of semiconductor devices have been progressing, and conventional wire bonding and TAB have been required.
(Tape Automated Bonding) and other mounting methods have limitations. Therefore, a flip chip (F / C) connection method in which a plurality of electrode terminals formed directly on a semiconductor element are directly connected to connection terminals on a wiring board has attracted attention.

【０００３】図１２乃至図１５は、従来のＦ／Ｃ接続法
の具体例である。図１２は、いわゆるＣ４（Controlled
Collapse Chip Connection）法と呼ばれるものであ
る。半導体素子２をはんだバンプ５を介して配線基板１
上の電極４にはんだリフローにより接続する。その後、
半導体素子２と配線基板１の間に応力緩和のための樹脂
層６を形成する。FIGS. 12 to 15 show specific examples of a conventional F / C connection method. FIG. 12 shows a so-called C4 (Controlled
Collapse Chip Connection) method. The semiconductor element 2 is connected to the wiring board 1 via the solder bumps 5.
The upper electrode 4 is connected by solder reflow. afterwards,
A resin layer for relaxing stress is formed between the semiconductor element and the wiring board.

【０００４】図１３は、いわゆるＳＳＢ（Stud Bump
Bonding）法と呼ばれるものである。半導体素子２をバ
ンプ７を介して配線基板１上の電極４に導電性接着剤８
により接続する。その後、半導体素子２と配線基板１の
間に応力緩和のための樹脂層６を形成する。FIG. 13 shows a so-called SSB (Stud Bump).
Bonding) method. The semiconductor element 2 is connected to the electrodes 4 on the wiring board 1 via the bumps 7 by a conductive adhesive 8.
Connect with Thereafter, a resin layer 6 for relaxing stress is formed between the semiconductor element 2 and the wiring board 1.

【０００５】図１４は、いわゆるＡＣＦ（Anisotropic
Conductive Film）法と呼ばれるものである。半導体
素子２をバンプ７を介して配線基板１上の電極４に導電
粒子１０を含有する異方性導電シート９によって接続す
る。この場合、前記バンプ７と前記電極４との間の電気
的接続は、導電粒子１０を介して行われる。FIG. 14 shows a so-called ACF (Anisotropic).
Conductive Film) method. The semiconductor element 2 is connected to the electrode 4 on the wiring board 1 via the bump 7 by an anisotropic conductive sheet 9 containing conductive particles 10. In this case, the electrical connection between the bump 7 and the electrode 4 is made via the conductive particles 10.

【０００６】図１５は、いわゆるＭＢＢ（Micro Bump
Bonding）法と呼ばれるものである。半導体素子２をバ
ンプ７を介して電極４上に配置する。その後、半導体素
子２と配線基板１の間に光硬化性樹脂を充填し、紫外線
等を照射して光硬化させて樹脂層１１を形成する。この
場合、前記バンプ７と前記電極４との間の電気的接続
は、樹脂層１１の光硬化時の収縮応力による圧接によっ
て行われる。FIG. 15 shows a so-called MBB (Micro Bump).
Bonding) method. The semiconductor element 2 is arranged on the electrode 4 via the bump 7. After that, the space between the semiconductor element 2 and the wiring board 1 is filled with a photocurable resin, and the resin layer 11 is formed by irradiating ultraviolet rays or the like and photocuring. In this case, the electrical connection between the bump 7 and the electrode 4 is performed by pressure contact due to shrinkage stress during photo-curing of the resin layer 11.

【０００７】上記の従来技術においては、半導体素子の
大面積化に伴い、実装時に半導体素子にクラックが発生
する不具合（以下、チップクラックと称する）が見受け
られた。図１６は、「チップクラック」の発生メカニズ
ムの概念図である。加熱下での半導体素子の実装時にお
いて、半導体素子２と配線基板１の熱膨張係数の違いに
より、半導体素子２の上面に引張り応力σが働き、チッ
プクラック１２が発生する。In the above-mentioned prior art, a defect that a crack occurs in the semiconductor element at the time of mounting (hereinafter, referred to as a chip crack) has been observed with an increase in the area of the semiconductor element. FIG. 16 is a conceptual diagram of a mechanism of occurrence of “chip crack”. At the time of mounting the semiconductor element under heating, a tensile stress σ acts on the upper surface of the semiconductor element 2 due to a difference in thermal expansion coefficient between the semiconductor element 2 and the wiring board 1, and a chip crack 12 occurs.

【０００８】従来より、チップクラックは半導体素子の
実装面と対向する上面側のエッジ部近傍から発生するこ
とが知られていた。この理由は、半導体素子のエッジ部
近傍にダイシング（切り出し）時に微細なチッピング等
の欠損部が生じ、この欠損部に上記引張り応力σに基づ
く応力集中が発生するからと推察される。Conventionally, it has been known that chip cracks occur near the edge of the upper surface facing the mounting surface of the semiconductor element. It is presumed that the reason for this is that, during dicing (cutting), a defective portion such as fine chipping is generated near the edge portion of the semiconductor element, and stress concentration based on the tensile stress σ is generated in the defective portion.

【０００９】Ｆ／Ｃ接続構造における半導体素子やバン
プ電極の破損を防止する方法が種々検討されている。特
許第２０９５２１０号公報には、所定のヤング率を有す
るシリコンゲルを用いて封止する方法が開示されてい
る。しかし、半導体装置全体を容器中で封止するため、
ＭＣＭ（マルチ チップ モジュール）やＣＳＰ（チッ
プ サイズ パッケージ）等のベアチップ実装には不向
きであった。Various methods have been studied for preventing damage to semiconductor elements and bump electrodes in the F / C connection structure. Japanese Patent No. 2095210 discloses a method of sealing using silicon gel having a predetermined Young's modulus. However, since the entire semiconductor device is sealed in the container,
It is not suitable for bare chip mounting such as MCM (multi-chip module) and CSP (chip size package).

【００１０】特開平７−６６３２６号公報には、Ｆ／Ｃ
接続部の応力緩和層として充填する樹脂層のフィレット
形状等を規定する方法が開示されている。しかし、ＣＳ
Ｐのように半導体素子と配線基板の寸法が略同等の場合
には、所定のフィレット形状を形成する余地がないため
適用が不可能な場合がある。Japanese Patent Application Laid-Open No. 7-66326 discloses an F / C
A method of defining a fillet shape and the like of a resin layer to be filled as a stress relaxation layer of a connection portion is disclosed. But CS
When the dimensions of the semiconductor element and the wiring board are substantially the same as in P, there is no room to form a predetermined fillet shape, so that application may not be possible.

【００１１】特開平８−５５９３８号公報には、Ｆ／Ｃ
接続部にヤング率の異なる２種類の樹脂を充填する方法
が開示されている。しかし、半導体素子の中央部と外周
部とで異なる種類の樹脂を所定の範囲に充填し分ける必
要があるため、前述したような種々のＦ／Ｃ接続構造を
選択する自由度が得られない問題があった。Japanese Patent Application Laid-Open No. 8-55938 discloses an F / C
A method is disclosed in which two types of resins having different Young's moduli are filled in a connection portion. However, since it is necessary to separately fill different types of resin in a predetermined range between the central portion and the outer peripheral portion of the semiconductor element, the above-described degree of freedom for selecting various F / C connection structures cannot be obtained. was there.

【００１２】[0012]

【発明が解決しようとする課題】本発明の目的は、Ｆ／
Ｃ接続構造を具備する半導体装置において、半導体素子
と配線基板との熱膨張係数の差による半導体素子のエッ
ジ部近傍の欠損部への応力集中に起因するチップクラッ
クを防ぎ、信頼性を向上した半導体装置及びその製造方
法を提供することである。An object of the present invention is to provide an F /
In a semiconductor device having a C-connection structure, a semiconductor device having improved reliability by preventing chip cracks due to stress concentration on a defective portion near an edge portion of a semiconductor element due to a difference in thermal expansion coefficient between the semiconductor element and a wiring board. It is to provide an apparatus and a method for manufacturing the same.

【００１３】[0013]

【課題を解決するための手段】請求項１は、Ｆ／Ｃ接続
構造を有する半導体装置において、半導体素子と配線基
板の間に充填された第１の樹脂層と、半導体素子の実装
面と対向する上面側のエッジ部を被覆するように形成さ
れた、見かけヤング率が８ＧＰａ以上である、第１の樹
脂層と同一の樹脂からなる第２の樹脂層とを有すること
を要旨とする。ここにいう「エッジ部を被覆する」と
は、半導体素子上面のエッジ部の全周を樹脂で被覆する
構造のみならず、必要な部位のみを選択的に被覆する構
造をも含む概念である。すなわち、半導体素子上面のエ
ッジ部近傍への応力集中を緩和してチップクラックを防
止できる箇所を被覆する構造であれば、本発明の目的は
達成される。この概念は、請求項２乃至請求項４におい
ても共通する概念である。例えば、応力集中の比較的少
ない半導体素子の角部のエッジ部を除いた四辺部のみを
樹脂で被覆する構造であってもよい。また、半導体素子
が長方形の場合には、応力の高い長辺側のエッジ部のみ
を樹脂で被覆する構造であってもよい。尚、樹脂被覆を
必要とする部位の決定は、実際のサンプルでの破壊部位
の観察やＦＥＭ等の応力解析結果に基づいて行う。According to a first aspect of the present invention, in a semiconductor device having an F / C connection structure, a first resin layer filled between a semiconductor element and a wiring board faces a mounting surface of the semiconductor element. First tree formed so as to cover the edge portion on the upper surface side, and having an apparent Young's modulus of 8 GPa or more.
The gist of the present invention is to have a resin layer and a second resin layer made of the same resin . The term "covering the edge portion" as used herein is a concept including not only a structure in which the entire periphery of the edge portion on the upper surface of the semiconductor element is covered with resin, but also a structure in which only necessary portions are selectively covered. That is, the object of the present invention is achieved by a structure that covers a portion where the chip crack can be prevented by relaxing the stress concentration near the edge of the upper surface of the semiconductor element. This concept is a common concept also in claims 2 to 4. For example, a structure may be adopted in which only the four sides excluding the edges of the corners of the semiconductor element where the stress concentration is relatively low are covered with the resin. In the case where the semiconductor element is rectangular, a structure may be employed in which only the edge portion on the long side with high stress is covered with resin. The determination of the portion that requires resin coating is made based on the observation of a broken portion in an actual sample and the result of stress analysis such as FEM.

【００１４】図１乃至図４は、本発明の基本的構成を例
示した説明図である。図１は、Ｃ４法への応用例であ
る。ここで、「半導体素子と配線基板の間に充填」され
た第１の樹脂層とは、例えば図１における樹脂層６を示
す。また、「半導体素子の実装面と対向する上面側のエ
ッジ部を被覆するように形成」された、第１の樹脂層と
同一の樹脂からなる第２の樹脂層とは、例えば図１にお
ける樹脂層６６を示す。図２は、導電性接着剤を用いた
方法への応用例である。図３は、異方性導電シートを用
いた方法への応用例である。図４は、光硬化性樹脂を用
いた方法への応用例である。FIGS. 1 to 4 are explanatory views illustrating the basic configuration of the present invention. FIG. 1 shows an example of application to the C4 method. Here, the first resin layer “filled between the semiconductor element and the wiring board” refers to, for example, the resin layer 6 in FIG. In addition, the first resin layer formed so as to cover an edge portion on the upper surface side opposite to the mounting surface of the semiconductor element,
The second resin layer made of the same resin refers to, for example, the resin layer 66 in FIG. FIG. 2 shows an example of application to a method using a conductive adhesive. FIG. 3 shows an example of application to a method using an anisotropic conductive sheet. FIG. 4 shows an example of application to a method using a photocurable resin.

【００１５】半導体素子２において、引張り応力のかか
る上面側エッジ部近傍を樹脂層６６で被覆する構造を取
ることで、半導体素子のダイシング（切り出し）時に前
記エッジ部近傍に生じた欠損部にかかる応力集中を緩和
し、チップクラックを防止することができる。尚、ここ
では図１及び図２の樹脂層６と樹脂層６６に用いる樹脂
は同じ樹脂を使用しているため、当該半導体装置の断面
を観察しても、樹脂層６と樹脂層６６の境界面は殆ど区
別することはできない。これは、図３の樹脂層９と樹脂
層９９、図４の樹脂層１１と樹脂層１１１においても同
様である。The semiconductor element 2 has a structure in which the resin layer 66 covers the vicinity of the upper edge on which a tensile stress is applied, so that the stress applied to the defective portion generated near the edge during dicing (cutting) of the semiconductor element. Concentration can be reduced and chip cracks can be prevented. Since the same resin is used for the resin layer 6 and the resin layer 66 in FIGS. 1 and 2 here, even if the cross section of the semiconductor device is observed, the boundary between the resin layer 6 and the resin layer 66 can be obtained. Surfaces can hardly be distinguished. The same applies to the resin layers 9 and 99 in FIG. 3 and the resin layers 11 and 111 in FIG.

【００１６】請求項２は、Ｆ／Ｃ接続構造を有する半導
体装置において、半導体素子と配線基板の間に充填され
た第１の樹脂層と、半導体素子の実装面と対向する上面
側のエッジ部を被覆するように形成された、見かけヤン
グ率が９ＧＰａ以上である、第２の樹脂層とを有するこ
とを要旨とする。According to a second aspect of the present invention, in the semiconductor device having the F / C connection structure, the first resin layer filled between the semiconductor element and the wiring board, and the upper surface facing the semiconductor element mounting surface.
Apparent yan formed to cover side edge
The gist is to have a second resin layer having a rate of 9 GPa or more .

【００１７】図５乃至図８は、第１の樹脂層と第２の樹
脂層に異なる種類の樹脂を用いた場合の基本的構成を例
示した説明図である。図５は、Ｃ４法において、第１の
樹脂層６と第２の樹脂層６６に異なる種類の樹脂を用い
た例である。図６は、導電性接着剤を用いた方法におい
て、第１の樹脂層６と第２の樹脂層６６に異なる種類の
樹脂を用いた例である。図７は、第１の樹脂層に異方性
導電シート９を用いた後、第２の樹脂層６６で半導体素
子のエッジ部近傍を被覆した例である。図８は、第１の
樹脂層に光硬化性樹脂１１を用いた後、第２の樹脂層６
６で半導体素子のエッジ部近傍を被覆した例である。以
上のように、Ｆ／Ｃ接続部に充填する樹脂と半導体素子
上面のエッジ部を被覆する樹脂の種類を使い分けること
によって、バンプの接続信頼性とチップクラックの２つ
の問題を効果的に解消することができる。FIGS. 5 to 8 are explanatory views exemplifying a basic structure in which different kinds of resins are used for the first resin layer and the second resin layer. FIG. 5 shows an example in which different types of resins are used for the first resin layer 6 and the second resin layer 66 in the C4 method. FIG. 6 shows an example in which different types of resins are used for the first resin layer 6 and the second resin layer 66 in the method using a conductive adhesive. FIG. 7 shows an example in which after the anisotropic conductive sheet 9 is used for the first resin layer, the vicinity of the edge of the semiconductor element is covered with the second resin layer 66. FIG. 8 shows that after the photocurable resin 11 is used for the first resin layer, the second resin layer 6 is formed.
6 is an example in which the vicinity of the edge of the semiconductor element is covered. As described above, the two problems of the connection reliability of the bump and the chip crack can be effectively solved by selectively using the type of the resin filling the F / C connection portion and the type of the resin coating the edge portion of the upper surface of the semiconductor element. be able to.

【００１８】本発明の半導体装置及びその製造方法は、
半導体素子の実装面と対向する上面側のエッジ部を被覆
する樹脂層の物性値を規定することを要旨とする。ここ
にいう「ヤング率」とは、樹脂の硬化体に超微小硬度計
を用いて測定される見かけヤング率をいう。所定のヤン
グ率を有する樹脂を用いて半導体素子の実装面と対向す
る上面側のエッジ部を被覆することで、該エッジ部に存
在するチッピングやマイクロクラック等の欠損部にかか
る引張り応力に基づく応力集中を効果的に緩和できる。 The semiconductor device and the method of manufacturing the same according to the present invention
The gist is to specify the physical property value of the resin layer covering the edge portion on the upper surface side facing the mounting surface of the semiconductor element. The term "Young's modulus" as used herein refers to an apparent Young's modulus measured on a cured body of a resin using an ultra-micro hardness meter. Use resin having a predetermined Young's modulus to face the mounting surface of the semiconductor element .
By covering the edge portion on the upper surface side, the stress concentration based on the tensile stress applied to the defective portion such as chipping or micro crack existing in the edge portion can be effectively reduced.

【００１９】請求項３は、請求項１又は２に記載の半導
体装置の製造方法を例示したものである。具体例によれ
ば、図１、図２、図５、図６にかかる半導体装置の製造
方法が該当する。以下、図５にかかる半導体装置の製造
方法を例に説明する。A third aspect exemplifies a method of manufacturing a semiconductor device according to the first or second aspect . According to a specific example, the method of manufacturing a semiconductor device according to FIGS. 1, 2, 5, and 6 corresponds to the method. Hereinafter, a method for manufacturing the semiconductor device according to FIG. 5 will be described as an example.

【００２０】図９乃至図１１は、図５に係る半導体装置
の製造方法の説明図である。はんだバンプを有する半導
体素子２を配線基板１上の電極４にはんだリフローによ
りＦ／Ｃ接続を行う（図示せず）。次いで、図９に示す
ように半導体素子２と配線基板１の間にディスペンサー
１３を用いて樹脂を充填し、図１０に示すように第１の
樹脂層６の形成を完了する。さらに、図１１に示すよう
にディスペンサー１３を用いて半導体素子上面のエッジ
部近傍を第２の樹脂で被覆する。その後、１５０℃に加
熱して各樹脂層を熱硬化させて（図示せず）、図５に示
す半導体装置を完成する。FIGS. 9 to 11 are views for explaining a method of manufacturing the semiconductor device shown in FIG. The semiconductor element 2 having the solder bump is connected to the electrode 4 on the wiring board 1 by F / C connection by solder reflow (not shown). Next, a resin is filled between the semiconductor element 2 and the wiring board 1 using a dispenser 13 as shown in FIG. 9, and the formation of the first resin layer 6 is completed as shown in FIG. Further, as shown in FIG. 11, the vicinity of the edge of the upper surface of the semiconductor element is covered with a second resin using a dispenser 13. Thereafter, the resin layers are heated to 150 ° C. to thermally cure the respective resin layers (not shown), thereby completing the semiconductor device shown in FIG.

【００２１】半導体素子と配線基板とをあらかじめＦ／
Ｃ接続した後に応力緩和用の樹脂を充填する工程を含む
タイプであれば、上記の具体例に挙げたＦ／Ｃ接続構造
に限定されずに適用可能である。The semiconductor element and the wiring board are
As long as the type includes a step of filling a resin for stress relaxation after the C connection, the invention is applicable without being limited to the F / C connection structure described in the above specific example.

【００２２】請求項４は、請求項３と同様に、請求項１
又は２に記載の半導体装置の製造方法を例示したもので
ある。具体例によれば、図３、図４、図７、図８にかか
る半導体装置の製造方法が該当する。本発明は、異方性
導電シートや導電性を有する光硬化性樹脂を用いたＦ／
Ｃ接続方法に代表されるように、導電性を有する第１の
樹脂層を介して半導体素子のバンプ電極を、配線基板上
の電極パッド群に接続した時にＦ／Ｃ接続構造が成立す
るタイプであれば、上記の具体例に挙げたＦ／Ｃ接続構
造に限定されずに適用可能である。Claim 4 is similar to Claim 3 and is similar to Claim 1.
Or a method for manufacturing a semiconductor device according to item 2 . According to a specific example, the method of manufacturing a semiconductor device according to FIGS. 3, 4, 7, and 8 corresponds to the method. The present invention provides an F / F using an anisotropic conductive sheet or a photocurable resin having conductivity.
As represented by C connection, the first bump electrode of the semiconductor element via the resin layer having conductivity, the wiring substrate
As long as the F / C connection structure is established when the F / C connection structure is established when the F / C connection structure is connected to the above electrode pad group , the present invention is not limited to the F / C connection structure described in the above specific example, and is applicable.

【００２３】以上の本発明に係る半導体装置に用いる配
線基板としては、例えばＰＴＦＥ系複合樹脂、ＢＴ（ビ
スマレイミド−トリアジン）或いはＦＲ−４等のエポキ
シ系の耐熱樹脂を主成分として用いたあらゆるプラスチ
ック製配線基板が使用可能である。これらのプラスチッ
ク材料は、シリコン等の半導体素子よりも熱膨張係数が
高いため、チップクラックが発生しやすい。しかし、本
発明の実装構造及び製造方法を用いれば、係る熱膨張係
数のミスマッチに起因するチップクラックを効果的に防
止可能である。As the wiring board used in the semiconductor device according to the present invention described above, for example, any plastic using as a main component an epoxy heat-resistant resin such as PTFE-based composite resin, BT (bismaleimide-triazine) or FR-4 can be used. A wiring board made of a metal can be used. Since these plastic materials have a higher thermal expansion coefficient than semiconductor elements such as silicon, chip cracks are likely to occur. However, by using the mounting structure and the manufacturing method of the present invention, it is possible to effectively prevent chip cracks caused by the mismatch of the thermal expansion coefficients.

【００２４】また、本発明は、Ｆ／Ｃ実装構造を有する
半導体装置であれば前記プラスチック製配線基板を用い
た半導体装置に限定されない。アルミナ、窒化アルミニ
ウム等からなるセラミックパッケージを用いた半導体装
置にも適用可能である。これらのセラミック材料の熱膨
張係数は、前記プラスチック材料の熱膨張係数よりも半
導体素子の熱膨張係数に近い。したがって、本発明の実
装構造及び製造方法を用いれば、半導体装置の薄型化や
大型化が進んだ場合においても、チップクラックを効果
的に防止可能である。The present invention is not limited to a semiconductor device using the plastic wiring board as long as the semiconductor device has an F / C mounting structure. The present invention is also applicable to a semiconductor device using a ceramic package made of alumina, aluminum nitride, or the like. The coefficient of thermal expansion of these ceramic materials is closer to the coefficient of thermal expansion of the semiconductor device than the coefficient of thermal expansion of the plastic material. Therefore, with the use of the mounting structure and the manufacturing method of the present invention, chip cracks can be effectively prevented even when the semiconductor device becomes thinner and larger.

【００２５】また、ホウケイ酸鉛系ガラス、ホウケイ酸
系結晶化ガラス、ホウケイ酸リチウム系結晶化ガラス等
のガラス成分にアルミナ、シリカ等のフィラー成分を複
合化させた複合材料からなるガラスセラミックパッケー
ジを用いた半導体装置にも適用可能である。この場合、
熱膨張係数がシリコン等の半導体素子よりも大きい複合
材料からなるガラスセラミックパッケージ（いわゆる高
膨張率ガラスセラミックパッケージ）を用いた半導体装
置に特に有用である。Further, a glass ceramic package made of a composite material in which a filler component such as alumina or silica is compounded with a glass component such as lead borosilicate glass, borosilicate crystallized glass, lithium borosilicate crystallized glass, or the like. The present invention is also applicable to the used semiconductor device. in this case,
The present invention is particularly useful for a semiconductor device using a glass ceramic package (a so-called high expansion coefficient glass ceramic package) made of a composite material having a thermal expansion coefficient larger than that of a semiconductor element such as silicon.

【００２６】[0026]

【実施例】以下、具体例を持って本発明を説明するが、
本発明は以下に示す具体的な実施の形態のみに限定され
るものではない。The present invention will be described below with reference to specific examples.
The present invention is not limited only to the specific embodiments described below.

【００２７】（実施例１）実施例１は、実体形状を用い
て耐チップクラック性を評価したものである。Example 1 In Example 1, the chip crack resistance was evaluated using the actual shape.

【００２８】（１）半導体装置の製造 半導体素子は、□１１．３３ｍｍ×厚み０．６３５ｍｍ
のシリコン製を使用した。該半導体素子の実装面の周縁
には、外径１２５μmのはんだパンプが２５０μmピッチ
で配置されている。(1) Manufacture of semiconductor device A semiconductor element is 11.33 mm square and 0.635 mm thick.
Was used. On the periphery of the mounting surface of the semiconductor element, solder pumps having an outer diameter of 125 μm are arranged at a pitch of 250 μm.

【００２９】配線基板は、□４２．５ｍｍ×厚み０．８
ｍｍのＰＴＦＥ（ポリテトラフルオロエチレン）を主成
分とする樹脂製のものを使用した。該配線基板には、銅
配線が形成されている。銅配線の半導体素子を実装する
部分には、ニッケルメッキ及び金メッキが施されてい
る。該配線基板の半導体素子の実装面には、スティフナ
と称される□４２．５ｍｍ×厚み０．７ｍｍの銅製の補
強板（図１７及び図１８に示す１４）が接着されてい
る。該スティフナのほぼ中央部には、半導体素子を実装
するための開口部（□２２．５ｍｍ）が設けられてい
る。The wiring board is □ 42.5 mm × thickness 0.8
mm of PTFE (polytetrafluoroethylene) as a main component was used. Copper wiring is formed on the wiring board. Nickel plating and gold plating are applied to portions where copper wiring semiconductor elements are mounted. A copper reinforcing plate (14 shown in FIGS. 17 and 18) having a square of 42.5 mm and a thickness of 0.7 mm, called a stiffener, is adhered to the mounting surface of the semiconductor element of the wiring board. An opening (□ 22.5 mm) for mounting a semiconductor element is provided substantially at the center of the stiffener.

【００３０】前記半導体素子を前記配線基板上の実装用
電極に配置し、最高保持温度２６０℃×５秒の条件では
んだリフロー炉を通して半導体素子実装基板を作製し
た。The semiconductor element was placed on the mounting electrode on the wiring board, and a semiconductor element mounting board was manufactured through a solder reflow furnace at a maximum holding temperature of 260 ° C. × 5 seconds.

【００３１】試験に用いた樹脂は、表１に示した４種類
とした。表１に示す各樹脂の「ヤング率」とは、各樹脂
の硬化体に超微小硬度計（Ｆｉｓｃｈｅｒ社製 フィッ
シャースコープ Ｈ−１００）を用いて測定される見か
けヤング率｛Ｅ／（１−ν2）｝（単位；ＧＰａ）をい
う。ここで、Ｅはヤング率（単位；ＧＰａ）、νはポア
ソン比である。測定方法はＤＩＮ５０３５９−１に準じ
て行った。充填層用樹脂及び被覆層用樹脂の組み合わせ
は、表２に示した１０種類とした。The resins used in the test were the four types shown in Table 1. The “Young's modulus” of each resin shown in Table 1 means an apparent Young's modulus ΔE / (1-−) measured on a cured body of each resin using an ultra-micro hardness tester (Fischer scope H-100 manufactured by Fischer). ν2)｝ (unit: GPa). Here, E is Young's modulus (unit: GPa), and ν is Poisson's ratio. The measuring method was carried out according to DIN50359-1. The combinations of the resin for the filling layer and the resin for the coating layer were 10 types shown in Table 2.

【００３２】まず、前記半導体素子実装基板のＦ／Ｃ接
続部に各充填層用樹脂をディスペンサーを用いて毛細管
現象を利用して充填した。次いで、半導体素子の上面エ
ッジ部近傍をディスペンサーを用いて各被覆層用樹脂に
て被覆した。First, the filling layer resin was filled into the F / C connection portion of the semiconductor element mounting board by utilizing a capillary phenomenon using a dispenser. Next, the vicinity of the upper edge of the semiconductor element was covered with a resin for each covering layer using a dispenser.

【００３３】その後、加熱炉を用い大気中にて１２０℃
×１５分〜１５０℃×３０分の加熱処理を行って充填層
用樹脂及び被覆層用樹脂を熱硬化させて、各半導体装置
の製造を完了した。図１７は実施例の形態を示す説明図
である。図１８は、比較例の形態を示す説明図である。Then, at 120 ° C. in the air using a heating furnace.
A heat treatment was performed for 15 minutes to 150 ° C. for 30 minutes to thermally cure the resin for the filling layer and the resin for the coating layer, thereby completing the manufacture of each semiconductor device. FIG. 17 is an explanatory diagram showing an embodiment. FIG. 18 is an explanatory diagram illustrating a form of a comparative example.

【００３４】（２）耐チップクラック試験 前記（１）で作製した各半導体装置を、耐チップクラッ
ク加速試験として各２０個ずつ最高保持温度２６０℃×
５秒の条件ではんだリフロー炉を６回連続で通した。室
温に戻るまで室温で放置した後、蛍光探傷液を用いてチ
ップクラックが発生しているか否かを目視及び倍率２０
倍の拡大鏡を用いて検査した。チップクラックが一切発
生しなかったものを合格とした。その合格率を「リフロ
ー合格率」として、結果を表２に示した。(2) Chip Crack Resistance Test Each of the semiconductor devices manufactured in the above (1) was subjected to a chip crack resistance acceleration test by a maximum of 20 ° C. × 260 ° C. ×
The solder reflow furnace was passed six times continuously for 5 seconds. After leaving at room temperature until the temperature returns to room temperature, it was visually inspected using a fluorescent test solution to determine whether or not chip cracks had occurred.
The examination was performed using a magnifying glass. A sample in which no chip crack occurred was regarded as a pass. The results were shown in Table 2 with the pass rate as “reflow pass rate”.

【００３５】[0035]

【表１】 [Table 1]

【００３６】[0036]

【表２】 [Table 2]

【００３７】表２の試料番号１乃至試料番号４は、充填
層と被覆層に同一の樹脂を用いた実施例である。試料番
号５乃至試料番号８は、半導体素子上面のエッジ部を被
覆しなかった比較例である。試料番号本発明の実施例で
ある試料番号２乃至試料番号４、試料番号９及び試料番
号１０は、リフロー合格率が９０〜１００％と良好な耐
チップクラック性を示した。Sample Nos. 1 to 4 in Table 2 are examples in which the same resin was used for the filling layer and the coating layer. Sample Nos. 5 to 8 are comparative examples in which the edge of the upper surface of the semiconductor element was not covered. Sample No. Sample Nos. 2 to 4, Sample No. 9 and Sample No. 10, which are examples of the present invention, showed good chip cracking resistance with a reflow pass rate of 90 to 100%.

【００３８】一方、半導体素子上面のエッジ部を被覆し
なかった比較例である試料番号５乃至試料番号８は、リ
フロー合格率が６０〜８４％という結果であった。ま
た、半導体素子上面のエッジ部を被覆する樹脂のヤング
率が５ＧＰａ未満の比較例である試料番号１及び試料番
号１１は、リフロー合格率がそれぞれ７５％及び８２％
という結果であった。On the other hand, Sample Nos. 5 to 8, which are comparative examples in which the edge of the upper surface of the semiconductor element was not covered, had a reflow pass rate of 60 to 84%. Sample Nos. 1 and 11, which are comparative examples in which the Young's modulus of the resin coating the edge portion of the upper surface of the semiconductor element is less than 5 GPa, have reflow pass rates of 75% and 82%, respectively.
Was the result.

【００３９】表２における試料番号９乃至試料番号１１
は、充填層と被覆層の樹脂のヤング率を変化させた例で
ある。半導体素子上面のエッジ部を被覆する樹脂のヤン
グ率が５ＧＰａ以上の実施例である試料番号９及び試料
番号１０は、リフロー合格率がそれぞれ１００％と良好
な耐チップクラック性を示した。一方、半導体素子上面
のエッジ部を被覆する樹脂のヤング率が５ＧＰａ未満の
実施例である試料番号１１は、８２％という結果であっ
た。Sample Nos. 9 to 11 in Table 2
Is an example in which the Young's modulus of the resin of the filling layer and the coating layer is changed. Sample No. 9 and Sample No. 10, which are examples in which the Young's modulus of the resin coating the edge portion of the upper surface of the semiconductor element is 5 GPa or more, showed a reflow pass rate of 100%, respectively, indicating good chip crack resistance. On the other hand, Sample No. 11, which is an example in which the Young's modulus of the resin coating the edge portion of the upper surface of the semiconductor element is less than 5 GPa, was 82%.

【００４０】以上の結果より、半導体素子上面のエッジ
部を樹脂で被覆する構造をとれば、耐チップクラック性
を向上させる効果が得られることが分かる。特には、所
定のヤング率を有する樹脂を用いて被覆層を形成するこ
とで、耐チップクラック性をより一層向上できる。被覆
層を形成する樹脂の好ましいヤング率は５ＧＰａ以上で
ある。より好ましくは７．５ＧＰａ以上である。被覆層
を形成する樹脂のヤング率を７．５ＧＰａ以上にするこ
とで、リフロー合格率を９０％以上に高めることができ
る。更に好ましくは９．０ＧＰａ以上である。被覆層を
形成する樹脂のヤング率を９．０ＧＰａ以上にすること
で、リフロー合格率をほぼ１００％に高めることができ
る。From the above results, it can be understood that the effect of improving the chip crack resistance can be obtained by adopting a structure in which the edge of the upper surface of the semiconductor element is covered with the resin. In particular, by forming the coating layer using a resin having a predetermined Young's modulus, the chip crack resistance can be further improved. The preferred Young's modulus of the resin forming the coating layer is 5 GPa or more. More preferably, it is 7.5 GPa or more. By setting the Young's modulus of the resin forming the coating layer to 7.5 GPa or more, the reflow pass rate can be increased to 90% or more. More preferably, it is 9.0 GPa or more. By setting the Young's modulus of the resin forming the coating layer to 9.0 GPa or more, the reflow acceptance rate can be increased to almost 100%.

【００４１】以上の実施例１では、シングルチップ実装
型の半導体装置を例に説明したが、本発明の半導体装置
は当該形態に限定されるものではない。本発明の半導体
装置は、ＣＳＰ、ＭＣＭ或いはチップオンボード等の様
々な形態に適用可能である。In the first embodiment, the semiconductor device of the single-chip mounting type has been described as an example. However, the semiconductor device of the present invention is not limited to this embodiment. The semiconductor device of the present invention is applicable to various forms such as a CSP, an MCM, or a chip-on-board.

【００４２】（実施例２）実施例２は、切り出し試験片
形状の４点曲げ強度測定して、耐チップクラック性を評
価したものである。Example 2 In Example 2, the chip crack resistance was evaluated by measuring the four-point bending strength of a cut test piece shape.

【００４３】（１）評価サンプルの作製 評価サンプルは、シリコンウエハからダイシングソーを
用いて切り出したものを使用した。評価サンプルのエッ
ジ部は、基本的にはダイヤモンドやすりを用いて切り出
し時に生じたチッピングを除去し、評価上必要とされる
部位についてはチッピングをそのまま残した。(1) Production of Evaluation Sample An evaluation sample cut out from a silicon wafer using a dicing saw was used. At the edge of the evaluation sample, chipping generated at the time of cutting was basically removed by using a diamond file, and chipping was left as it is at a site required for evaluation.

【００４４】評価サンプルの寸法は、長さ３５ｍｍ×幅
４ｍｍ×厚み０．７３ｍｍの板状とした。評価サンプル
には、半導体素子のエッジ部に存在する欠損部を想定し
て、あらかじめ２種類の欠陥を設けた。一つは、評価サ
ンプルの引っ張り応力がかかる面側のエッジ部に、効果
を明確にするため実際の半導体素子に見られるものより
大きめのチッピングを設けた。これを以下、「チッピン
グ品」と称する。他方は、評価サンプルの略中央部にビ
ッカースの圧子で１Ｎの荷重をかけて、図１９に示すよ
うな欠陥部を設けた。これを以下、「予備欠陥品」と称
する。The dimensions of the evaluation sample were a plate having a length of 35 mm × a width of 4 mm × a thickness of 0.73 mm. In the evaluation sample, two types of defects were provided in advance, assuming a defect existing at the edge of the semiconductor element. One is to provide a larger chipping than that seen in an actual semiconductor device at the edge of the evaluation sample on the side where the tensile stress is applied to clarify the effect. This is hereinafter referred to as “chipping product”. On the other hand, a defective portion as shown in FIG. 19 was provided by applying a load of 1 N to a substantially central portion of the evaluation sample with a Vickers indenter. This is hereinafter referred to as "preliminarily defective product".

【００４５】評価サンプルの形態は以下の計１０種類と
した。 ．チッピング品 ．チッピング被覆品４種類（チッピング品のエッジ部
を表１の４種類の樹脂でそれぞれ被覆したもの。） ．予備欠陥品 ．予備欠陥被覆品４種類（予備欠陥品の欠陥部エッジ
部を表１の４種類の樹脂でそれぞれ被覆したもの。）The forms of the evaluation samples were a total of 10 types as follows. . Chipping products. 4 types of chipping-coated products (the edge of the chipping product is coated with each of the four resins shown in Table 1). Spare defects. Preliminary defect coated products 4 types (the defective edge portions of the preliminarily defective products are coated with four types of resins shown in Table 1, respectively).

【００４６】（２）４点曲げ強度の測定 前記（１）で作製した１０種類の評価サンプルについ
て、４点曲げ強度を測定した。試験方法は、ＪＩＳ Ｒ
１６０１に準じて行った。結果を表３に示した。(2) Measurement of Four-Point Bending Strength The four-point bending strength was measured for the ten types of evaluation samples prepared in the above (1). The test method is JIS R
1601. The results are shown in Table 3.

【００４７】[0047]

【表３】 [Table 3]

【００４８】表３に示すように、本発明の実施例である
試料番号１４乃至試料番号１６、試料番号１９及び試料
番号２１は、１０８〜１４０ＭＰａの良好な４点曲げ強
度を示した。被覆樹脂のヤング率が上昇するにつれて、
４点曲げ強度も上昇していくことがわかる。As shown in Table 3, Sample Nos. 14 to 16, Sample No. 19 and Sample No. 21, which are Examples of the present invention, exhibited good four-point bending strengths of 108 to 140 MPa. As the Young's modulus of the coating resin increases,
It can be seen that the four-point bending strength also increases.

【００４９】一方、被覆層を有しない比較例である試料
番号１２及び試料番号１７は、４点曲げ強度がそれぞれ
９５ＭＰａ及び８９ＭＰａという結果となった。また、
被覆層のヤング率が５ＧＰａ未満の比較例である試料番
号１３及び試料番号１８は、４点曲げ強度がそれぞれ１
０３ＭＰａ及び９３ＭＰａという結果となった。On the other hand, Sample No. 12 and Sample No. 17, which are comparative examples having no coating layer, resulted in four-point bending strengths of 95 MPa and 89 MPa, respectively. Also,
Sample No. 13 and Sample No. 18, which are comparative examples in which the Young's modulus of the coating layer is less than 5 GPa, each has a four-point bending strength of 1
The results were 03 MPa and 93 MPa.

【００５０】以上の結果より、実施例２における評価サ
ンプルでの４点曲げ強度の結果は、実施例１で実体形態
で評価した耐チップクラック性の結果とほぼ相関関係が
あるといえる。よって、半導体素子上面のエッジ部を所
定の樹脂層で被覆すれば、半導体素子にかかる引っ張り
応力に基づく応力集中を効果的に緩和することができる
ことがわかる。From the above results, it can be said that the results of the four-point bending strength of the evaluation sample in Example 2 are substantially correlated with the results of the chip crack resistance evaluated in the actual form in Example 1. Therefore, it is understood that if the edge portion on the upper surface of the semiconductor element is covered with the predetermined resin layer, stress concentration based on the tensile stress applied to the semiconductor element can be effectively reduced.

【００５１】尚、実施例1及び実施例２の結果より、被
覆樹脂層のヤング率の上限値としては、少なくとも１
１．０ＧＰａまでは適用可能であることが確認されてい
る。半導体装置上面に作用する引っ張り応力に基づくエ
ッジ部近傍への応力集中を緩和するという本発明の目的
から判断すれば、１１．０ＧＰａ以上の樹脂を用いても
当該応力緩和の効果を奏することが可能である。From the results of Example 1 and Example 2, the upper limit of the Young's modulus of the coating resin layer was at least 1
It has been confirmed that application is possible up to 1.0 GPa. Judging from the object of the present invention that the concentration of stress in the vicinity of the edge portion due to the tensile stress acting on the upper surface of the semiconductor device is alleviated, the effect of the stress relaxation can be exerted even if a resin of 11.0 GPa or more is used. It is.

【００５２】[0052]

【発明の効果】本発明によれば、Ｆ／Ｃ接続構造を具備
する半導体装置において、半導体素子と配線基板との熱
膨張係数の差による半導体素子のエッジ部近傍の欠損部
への応力集中に起因するチップクラックを防ぎ、信頼性
を向上した半導体装置及びその製造方法を提供すること
ができる。According to the present invention, in a semiconductor device having an F / C connection structure, stress concentration on a defect near an edge portion of a semiconductor element due to a difference in thermal expansion coefficient between the semiconductor element and a wiring board is reduced. It is possible to provide a semiconductor device and a method for manufacturing the same, which can prevent chip cracks due to the problem and have improved reliability.

【図面の簡単な説明】[Brief description of the drawings]

【図１】請求項１に係る発明のＣ４法への応用例の説明
図。FIG. 1 is an explanatory diagram of an application example of the invention according to claim 1 to a C4 method.

【図２】請求項１に係る発明のＳＳＢ法への応用例の説
明図。FIG. 2 is an explanatory diagram of an application example of the invention according to claim 1 to the SSB method.

【図３】請求項１に係る発明のＡＣＦ法への応用例の説
明図。FIG. 3 is an explanatory diagram of an application example of the invention according to claim 1 to an ACF method.

【図４】請求項１に係る発明のＭＢＢ法への応用例の説
明図。FIG. 4 is an explanatory diagram of an application example of the invention according to claim 1 to the MBB method.

【図５】請求項２に係る発明のＣ４法への応用例の説明
図。FIG. 5 is an explanatory diagram of an application example of the invention according to claim 2 to the C4 method.

【図６】請求項２に係る発明のＳＳＢ法への応用例の説
明図。FIG. 6 is an explanatory diagram of an application example of the invention according to claim 2 to the SSB method.

【図７】請求項２に係る発明のＡＣＦ法への応用例の説
明図。FIG. 7 is an explanatory diagram of an application example of the invention according to claim 2 to an ACF method.

【図８】請求項２に係る発明のＭＢＢ法への応用例の説
明図。FIG. 8 is an explanatory diagram of an application example of the invention according to claim 2 to the MBB method.

【図９】請求項３又は請求項４に係る半導体装置の製造
方法の説明図。FIG. 9 is an explanatory diagram of a method for manufacturing a semiconductor device according to claim 3 or 4;

【図１０】請求項３又は請求項４に係る半導体装置の製
造方法の説明図。FIG. 10 is an explanatory diagram of a method for manufacturing a semiconductor device according to claim 3 or 4;

【図１１】請求項３又は請求項４に係る半導体装置の製
造方法の説明図。FIG. 11 is an explanatory view of a method for manufacturing a semiconductor device according to claim 3 or 4;

【図１２】従来のＣ４法を用いた半導体装置の説明図。FIG. 12 is an explanatory diagram of a semiconductor device using a conventional C4 method.

【図１３】従来のＳＳＢ法を用いた半導体装置の説明
図。FIG. 13 is an explanatory diagram of a semiconductor device using a conventional SSB method.

【図１４】従来のＡＣＦ法を用いた半導体装置の説明
図。FIG. 14 is an explanatory diagram of a semiconductor device using a conventional ACF method.

【図１５】従来のＭＢＢ法を用いた半導体装置の説明
図。FIG. 15 is an explanatory diagram of a semiconductor device using a conventional MBB method.

【図１６】「チップクラック」の発生メカニズムの概念
図。FIG. 16 is a conceptual diagram of an occurrence mechanism of “chip crack”.

【図１７】実施例１の実施例に係る形態を示す説明図。FIG. 17 is an explanatory view showing a form according to the example of Example 1.

【図１８】実施例１の比較例に係る形態を示す説明図。FIG. 18 is an explanatory diagram showing an embodiment according to a comparative example of Example 1.

【図１９】実施例２に係る予備欠陥の形態を示す説明
図。FIG. 19 is an explanatory diagram showing a form of a preliminary defect according to the second embodiment.

【符号の説明】[Explanation of symbols]

１ 配線基板 ２ 半導体素子 ３ 半導体素子側の電極 ４ 配線基板側の電極 ５ はんだバンプ ６ 充填層 ６６ 被覆層 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Semiconductor element 3 Electrode on semiconductor element side 4 Electrode on wiring board side 5 Solder bump 6 Filling layer 66 Coating layer

フロントページの続き (56)参考文献 特開 平６−349893（ＪＰ，Ａ) 特開 平７−66326（ＪＰ，Ａ) 特開 平11−31762（ＪＰ，Ａ) 特開 平６−232208（ＪＰ，Ａ) 特開 平８−153830（ＪＰ，Ａ) 特開 平９−246321（ＪＰ，Ａ) 特開 平10−92875（ＪＰ，Ａ) 特開2000−40776（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/56 H01L 21/60 311 Continuation of the front page (56) References JP-A-6-349893 (JP, A) JP-A-7-66326 (JP, A) JP-A-11-31762 (JP, A) JP-A-6-232208 (JP) JP-A-8-153830 (JP, A) JP-A-9-246321 (JP, A) JP-A-10-92875 (JP, A) JP-A-2000-40776 (JP, A) (58) Field (Int.Cl. 7 , DB name) H01L 21/56 H01L 21/60 311

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 一主面にバンプ電極が形成された半導体
素子と、 前記バンプ電極を接続するための電極パッド群を有し、
該電極パッド群上に前記バンプ電極とが実質的に固定さ
れるようにして前記半導体素子が搭載された配線基板
と、 前記半導体素子と前記配線基板の間に充填された第１の
樹脂層と、 前記半導体素子の実装面と対向する上面側のエッジ部を
被覆するように形成された、見かけヤング率が９ＧＰａ
以上である、第１の樹脂層と同一の樹脂からなる第２の
樹脂層とを有する半導体装置。1. A semiconductor device having a bump electrode formed on one main surface, and an electrode pad group for connecting the bump electrode,
A wiring board on which the semiconductor element is mounted such that the bump electrode is substantially fixed on the electrode pad group; and a first filler filled between the semiconductor element and the wiring board .
An apparent Young's modulus of 9 GPa is formed so as to cover the resin layer and the edge on the upper surface side facing the mounting surface of the semiconductor element.
The semiconductor device having the first resin layer and the second resin layer made of the same resin as described above . 【請求項２】 一主面にバンプ電極が形成された半導体
素子と、 前記バンプ電極を接続するための電極パッド群を有し、
該電極パッド群上に前記バンプ電極とが実質的に固定さ
れるようにして前記半導体素子が搭載された配線基板
と、 前記半導体素子と前記配線基板の間に充填された第１の
樹脂層と、 前記半導体素子の実装面と対向する上面側のエッジ部を
被覆するように形成された、見かけヤング率が９ＧＰａ
以上である、第２の樹脂層とを有する半導体装置。2. A semiconductor device having a bump electrode formed on one main surface, and an electrode pad group for connecting the bump electrode,
A wiring board on which the semiconductor element is mounted such that the bump electrode is substantially fixed on the electrode pad group; and a first resin layer filled between the semiconductor element and the wiring board. An apparent Young's modulus of 9 GPa formed so as to cover an edge portion on the upper surface side facing the mounting surface of the semiconductor element;
The above is the semiconductor device having the second resin layer. 【請求項３】 前記半導体素子のバンプ電極を前記配線
基板上の電極パッド群に接続する工程と、 前記半導体素子と前記配線基板の間に第１の樹脂層を充
填する工程と、 前記半導体素子の実装面と対向する上面側のエッジ部
を、見かけヤング率が９ＧＰａ以上となる、第２の樹脂
で被覆する工程とを具備する請求項１又は２に記載の半
導体装置の製造方法。A step of connecting a bump electrode of the semiconductor element to an electrode pad group on the wiring board; a step of filling a first resin layer between the semiconductor element and the wiring board; 3. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: covering an edge portion on the upper surface side facing the mounting surface with a second resin having an apparent Young's modulus of 9 GPa or more. 【請求項４】 前記半導体素子のバンプ電極を、導電性
を有する第１の樹脂層を介して前記配線基板上の電極パ
ッド群に接続する工程と、 前記半導体素子の実装面と対向する上面側のエッジ部
を、見かけヤング率が９ＧＰａ以上となる、第２の樹脂
で被覆する工程とを具備する請求項１又は２に記載の半
導体装置の製造方法。4. A step of connecting a bump electrode of the semiconductor element to an electrode pad group on the wiring substrate via a first resin layer having conductivity, and an upper surface side facing a mounting surface of the semiconductor element. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising: coating the edge portion with a second resin having an apparent Young's modulus of 9 GPa or more.
JP33884398A 1998-11-30 1998-11-30 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3303162B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33884398A JP3303162B2 (en) 1998-11-30 1998-11-30 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33884398A JP3303162B2 (en) 1998-11-30 1998-11-30 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2000164610A JP2000164610A (en) 2000-06-16
JP3303162B2 true JP3303162B2 (en) 2002-07-15

Family

ID=18321954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33884398A Expired - Fee Related JP3303162B2 (en) 1998-11-30 1998-11-30 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3303162B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4547079B2 (en) * 2000-09-29 2010-09-22 トッパン・フォームズ株式会社 IC chip protection part and method of forming the same
JP3835556B2 (en) 2003-10-27 2006-10-18 セイコーエプソン株式会社 Semiconductor device manufacturing method and semiconductor device manufacturing apparatus
JP2007059767A (en) 2005-08-26 2007-03-08 Shinko Electric Ind Co Ltd Substrate with electronic component mounted thereon employing underfill material and its manufacturing method
JP2009260302A (en) * 2008-03-28 2009-11-05 Toppan Printing Co Ltd Semiconductor package
JP6065135B2 (en) * 2015-04-02 2017-01-25 日亜化学工業株式会社 Light emitting device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2820147B2 (en) * 1988-04-20 1998-11-05 セイコーエプソン株式会社 Semiconductor device
JPH06232208A (en) * 1993-01-29 1994-08-19 Matsushita Electric Ind Co Ltd Method for sealing semiconductor device, and sealing structure
JPH06349893A (en) * 1993-06-02 1994-12-22 Citizen Watch Co Ltd Flip chip connection semiconductor package
JPH0766326A (en) * 1993-08-30 1995-03-10 Nippondenso Co Ltd Semiconductor device
JPH08153830A (en) * 1994-11-29 1996-06-11 Toshiba Corp Semiconductor device and manufacture thereof
JP3409957B2 (en) * 1996-03-06 2003-05-26 松下電器産業株式会社 Semiconductor unit and method of forming the same
JP3235520B2 (en) * 1997-07-10 2001-12-04 松下電器産業株式会社 Method for manufacturing semiconductor device
JP3563603B2 (en) * 1998-07-24 2004-09-08 京セラ株式会社 Semiconductor element mounting structure

Also Published As

Publication number Publication date
JP2000164610A (en) 2000-06-16

Similar Documents

Publication Publication Date Title
TW392318B (en) Semiconductor device, and manufacturing method of the same
JP3648277B2 (en) Semiconductor device
US5773896A (en) Semiconductor device having offsetchips
US20020098620A1 (en) Chip scale package and manufacturing method thereof
EP0239315B1 (en) Semiconductor device having an encapsulating package
US10490515B2 (en) Semiconductor substrate having stress-absorbing surface layer
JP3702877B2 (en) Resin-sealed semiconductor device, die-bonding material and sealing material used therefor
JP3303162B2 (en) Semiconductor device and manufacturing method thereof
JPH1050770A (en) Semiconductor device and its manufacture
JP2607877B2 (en) Method for manufacturing resin-reinforced LSI mounting structure
JP2675003B2 (en) LSI packaging structure
JP2009188392A (en) Semiconductor device and method of manufacturing semiconductor device
JP3566680B2 (en) Method for manufacturing semiconductor device
JP3243988B2 (en) Method for manufacturing semiconductor device
JPH0639563B2 (en) Manufacturing method of semiconductor device
KR100968008B1 (en) A Semiconductor device and a method of manufacturing the same
JP2000036506A (en) Manufacture of semiconductor device
JPH09260433A (en) Manufacture of semiconductor device and semiconductor device provided thereby
JP4366971B2 (en) Method for designing liquid sealing resin composition and method for manufacturing semiconductor device
US11270971B2 (en) Semiconductor device and method of manufacturing the same
JP3741670B2 (en) Manufacturing method of semiconductor device
TW502344B (en) Chip scale package structure and its manufacturing method
JP2004134821A (en) Semiconductor apparatus
JPS6124255A (en) Structure for semiconductor package
TW466719B (en) Multi chip module packaging method by mixing chip and package

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees