TW502344B - Chip scale package structure and its manufacturing method - Google Patents

Chip scale package structure and its manufacturing method Download PDF

Info

Publication number
TW502344B
TW502344B TW89126322A TW89126322A TW502344B TW 502344 B TW502344 B TW 502344B TW 89126322 A TW89126322 A TW 89126322A TW 89126322 A TW89126322 A TW 89126322A TW 502344 B TW502344 B TW 502344B
Authority
TW
Taiwan
Prior art keywords
substrate
wafer
patent application
anisotropic conductive
adhesive layer
Prior art date
Application number
TW89126322A
Other languages
Chinese (zh)
Inventor
Yi-Chuan Ding
Xin-Hui Lee
Kun-Ching Chen
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW89126322A priority Critical patent/TW502344B/en
Application granted granted Critical
Publication of TW502344B publication Critical patent/TW502344B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body

Abstract

A chip scale package structure comprises a substrate arranged on the positive face of a semiconductor chip by using an anisotropic conductive film (ACF). A plurality of solder pads are formed on the upper surface of the substrate. A plurality of contact pads are formed on the lower surface of the substrate for electrically connecting to the corresponding solder pads. A plurality of metal bumps are formed on the contact pads on the lower surface of the substrate. The semiconductor chip has a plurality of die pads formed on its positive face. The metal bumps on the substrate are electrically connected to the corresponding die pads by ACF. The substrate and the side of the ACF are sealed by an encapsulant. The present invention also provides a method for manufacturing a chip scale package structure in a wafer level, which is characterized in sequentially adhering a plurality of substrates the chips of a wafer, so as to minimize the influence of CTE mismatch between the wafer and substrate, thereby greatly increasing the product yield.

Description

502344 五、發明說明（1) 【發明領域】 本發明係有關於一種晶片尺寸級封裝構造（ch ip sca ie Package， CSP)。本發明特別有關於一種在晶圓層次， (waf er 1 eve 1 )製造複數個晶片尺寸級封裝構造的方法。 【先前技術】 ik著更輕更複雜電子裝置需求的曰趨強烈，晶片的速度 及複雜性相對越來越高，因此需要更高之封裝效率 (packaging efficiency)。微型化（miniaturizati〇n)是 使用先進封裝技術（例如晶片尺寸級封裝（chip scale package)以及覆晶（f 1 ip Ch ip))的主要驅動力。相較於 球格陣列封裝或薄小輪廓封裝（thin small outline package，TSOP)而言’晶片尺寸級封裝以及覆晶這兩種技 術均大幅增加封裝效率，藉此減少所需之基板空間。一般 而言，晶片尺寸級封裝之大小與晶片本身大小相當或稍大 於晶片本身（最多約百分之二十）。此外，晶片尺寸級封裝 可直接促成良好晶片（known good die，KGD)測試及老化 (burn - in)測試。再者，晶片尺寸級封裝亦可結合表面黏g 著技術（surface mount technology，SMT)之標準化及可 在加工性等優點，與覆晶技術之低阻抗，高I /〇接腳數及 直接散熱路徑等優點，而提升晶片尺寸級封裝之效能。 然而’與球袼陣列（ba 1 1 grid array)封裝或薄小輪廓 封裝（thin small outline package，TS0P)相比較，晶片 尺寸級封裝具有較高製造成本之缺點。若能將晶片尺寸級 封裝以大量生產方式製造，前述高製造成本之缺點將可被502344 V. Description of the invention (1) [Field of the invention] The present invention relates to a chip size package structure (ch ip sca ie package, CSP). The present invention particularly relates to a method for manufacturing a plurality of wafer-scale package structures at a wafer level. [Previous technology] The demand for lighter and more complex electronic devices is increasing. The speed and complexity of chips are relatively higher and higher, so higher packaging efficiency is required. Miniaturization is the main driving force for the use of advanced packaging technologies such as chip scale packages and f 1 ip Ch ip. Compared with the ball grid array package or thin small outline package (TSOP), the two technologies of wafer-level package and flip chip have greatly increased the packaging efficiency, thereby reducing the required substrate space. In general, the size of a chip-size package is equal to or slightly larger than the chip itself (up to about 20%). In addition, chip-scale packaging can directly contribute to known good die (KGD) testing and burn-in testing. In addition, the chip size package can also combine the advantages of surface mount technology (SMT) standardization and processability, and the low impedance of the flip chip technology, high I / 0 pin count and direct heat dissipation. Path and other advantages, and improve the performance of chip-scale packaging. However, compared with a ba 1 1 grid array package or a thin small outline package (TS0P), the chip size package has the disadvantage of higher manufacturing cost. If the chip-scale package can be manufactured in a mass production manner, the aforementioned disadvantages of high manufacturing costs will be overcome.

P00~150.ptd 第5頁 五、發明說明（2) 克，。因此’封裝業者嘗試開發晶圓層次（waf er 1 eve 1) 封裝技術，以能大量生產晶片尺寸半導體封裝構造，如美 ^專利第5, 977，624及美國專利第6, 〇〇4, 867號。該晶圓層 次封裂技術的製造步驟，大體上皆包括將一基板直接貼合 至—晶圓（wa f er )上，其中該半導體晶圓係尚未切割成個 別晶片。該基板係與整片晶圓之尺寸大致相同，並且包含 複數個單元對應於晶圓上的複數個晶片。 由於該晶圓與基板熱膨脹係數差異相當大（晶圓之熱膨P00 ~ 150.ptd Page 5 5. Description of the Invention (2) grams. Therefore, the packaging industry has tried to develop wafer-level (wafer er 1 eve 1) packaging technology to enable mass production of wafer-size semiconductor packaging structures, such as US Patent No. 5,977,624 and US Patent No. 6,004,867 number. The manufacturing steps of the wafer level cracking technology generally include directly attaching a substrate to a wafer, wherein the semiconductor wafer has not been cut into individual wafers. The substrate is approximately the same size as the entire wafer and includes a plurality of cells corresponding to a plurality of wafers on the wafer. Because the difference between the thermal expansion coefficient of the wafer and the substrate is quite large (the thermal expansion of the wafer

脹係數（coefficient of thermal expansion，CTE)約為 3-5ppm°C—1，基板之熱膨脹係數（CTE)約為M — goppfc-i )’因此晶圓與基板會隨溫度變化而產生不同的膨脹或收 縮里。這會该晶圓與基板之介面產生切變（s h e a r )應力或 彎曲（bend)應力。而由於基板係與整片晶圓之尺寸大致相 同，因此該破壞性應力會累積而更擴大其所導致的可靠性 問題。 一般至少會有數個在測試 chip)。因此，在前述習 基板單元就浪費掉了。同樣 亦有可能包含不良品。因 此外，晶圓上的複數個晶片 判定為不良品晶片（defective 技術中’貼在不良品晶片上的 的’基板上的複物個基板單元The coefficient of thermal expansion (CTE) is about 3-5ppm ° C-1, and the coefficient of thermal expansion (CTE) of the substrate is about M — goppfc-i) '. Therefore, the wafer and the substrate will have different expansions with temperature changes. Or shrink inside. This will generate a shear stress or bend stress on the interface between the wafer and the substrate. Since the substrate is approximately the same size as the entire wafer, the destructive stress will accumulate and expand the reliability issues caused by it. There are usually at least several chips under test). Therefore, the substrate unit is wasted in the foregoing practice. It is also possible to include defective products. In addition, a plurality of wafers on the wafer were judged to be defective wafers (a plurality of substrate units on a substrate that is affixed to a defective wafer in a defective technology).

此，在前述習用技術中，對應於不良品基板單元的晶片也 同樣是.浪費掉。 _ 因此，有必要尋求一種在晶圓層次（wafer level)製造 複數個晶片尺寸級封裝構造的方法，其可解決前述券i 術的問題。Therefore, in the aforementioned conventional technology, the wafer corresponding to the defective substrate unit is also wasted. _ Therefore, it is necessary to find a method for manufacturing a plurality of wafer-scale package structures at a wafer level, which can solve the problem of the aforementioned coupon technique.

P00-150.ptd 第6頁 502344 五、發明說明（3) ' 一 【發明概要】 因此，本發明之主要目的係提供一種在晶圓層次製造的 晶片尺寸級封裝構造，其可解決前述先前技術的問題。 本發明之次要目的係提供一種在晶圓層次（wafer levei) 製造複數個晶片尺寸級封裝構造的方法，苴可大幅提 裝良率。 根據本發明之晶片尺寸級封裝構造，其主要包含一基板 利用一異方性導電膠層（ACF)設於一半導體晶片之正面。P00-150.ptd Page 6 502344 V. Description of the invention (3) '1 [Summary of the invention] Therefore, the main purpose of the present invention is to provide a wafer-size package structure manufactured at the wafer level, which can solve the aforementioned prior art The problem. A secondary object of the present invention is to provide a method for manufacturing a plurality of wafer-size package structures at a wafer level, which can greatly improve the yield of the package. According to the wafer-size package structure of the present invention, it mainly includes a substrate provided on the front side of a semiconductor wafer by using an anisotropic conductive adhesive layer (ACF).

該基板之上表面設有複數個錫·球銲墊（s〇lder pad)，該 基板之下表面設有複數個接,（c〇ntact pad)電性連接至 相對應的錫球銲墊。複數個金屬突塊（metal bump)設於該 f板下表面之接墊。該半導體晶片具有複數個晶片銲墊設 於其正面。該基板上之金屬突塊係利用異方性導電膠層電 性連接至相對應之晶片銲墊。該基板以及異方性導電膠層 之側邊係為一封膠體密封。 根據本發明之晶片尺寸級封裝構造製造方法，其包含 列步驟：（a)提供一基板條（substrate strip)，其包^A plurality of solder pads are provided on the upper surface of the substrate, and a plurality of solder pads are provided on the lower surface of the substrate to be electrically connected to the corresponding solder ball pads. A plurality of metal bumps are provided on the pads on the lower surface of the f-plate. The semiconductor wafer has a plurality of wafer pads provided on its front surface. The metal bumps on the substrate are electrically connected to the corresponding wafer pads by using an anisotropic conductive adhesive layer. The substrate and the side of the anisotropic conductive adhesive layer are sealed by a gel. The method for manufacturing a wafer-scale package structure according to the present invention includes the following steps: (a) providing a substrate strip, which includes:

複數個基板；（b )形成複數個金屬凸塊於該每一基板下表 面之複數個接塾上；（c)將一異方性導電膠層（ACF )貼至 該基板條之下表面而形成一異方膠/基板條複合體；（d) 副該異方膠/基板條複合體成複數個下表面具有異方性 導電膠層之基板；（e)將該複數個基板藉由設於其上之異 方性導電膠層接合至一晶圓上的複數個晶片，使得該每_ 基板上之金屬突塊電性連接至相對應之晶片銲墊；（f)形A plurality of substrates; (b) forming a plurality of metal bumps on a plurality of contacts on the lower surface of each substrate; (c) attaching an anisotropic conductive adhesive layer (ACF) to the lower surface of the substrate strip and Forming an anisotropic rubber / substrate strip composite; (d) forming the anisotropic rubber / substrate strip composite into a plurality of substrates having an anisotropic conductive adhesive layer on the lower surface; (e) placing the plurality of substrates by setting The anisotropic conductive adhesive layer thereon is bonded to a plurality of wafers on a wafer, so that the metal bumps on each substrate are electrically connected to corresponding wafer pads; (f) shape

P00-150.ptdP00-150.ptd

第7頁 502344 五、發明說明（4) 成溝槽對應於該複數個晶片之邊界區域；（g)密封該溝 槽；（h )切割該晶圓以及密封溝槽而製得該複數個晶片尺 寸級封裝構造。 ^根據本發明之CSP製造方法，其特徵在於該複數個基板 係逐片貼至該晶圓上之晶片，藉此將晶圓與基板熱膨脹係 數不配合（CTE mismatch)的影響減至最小，因而大幅增加 產品良率。此外，由於可選擇只將測試後可接受之基板貼 至晶圓，因此可避免浪費晶圓上完好之晶片。 為了讓本發明之上述和其他目的、特徵、和優點能更明 顯，下文特舉本發明較佳實施例，並配合所附圖示，作詳 細說明如下。 【發明說明】 第十四圖揭示根據本發明較佳實施例之晶片尺寸級封裝 構造100，其主要包含一基板11()利用一異方性導電膠層 (anisotropic conductive adhesive film (ACF))120 設 於一半導體晶片130之正面。該基板11〇之下表面設有_ 個接墊（contact pad) ll〇a。複數個金屬突塊（〇161；31 @ bu!np)l 40設於該接墊1 1 〇a，其中該金屬突塊14〇較佳為利 用習知的打線技術（wire bonding technique)形成之柱狀 突塊（stud bump)。該半導體晶片13〇具有複數個晶片銲墊 130a設於其正面。該基板上之金屬突塊14〇係利用異方性 導電膠層1 2 0電性連接至相對應之晶片銲墊丨3 〇 a，用以將 晶片傳出之訊號經由基板Π 0傳送至外界。該基板丨丨〇以及 異方性導電膠層1 2 0之側邊係為一封膠體丨5 〇密封。已知適 502344 五、發明說明（5) 合用以形成該異方性導電膠層1 2 〇的異方性膠為一「z轴異 方性膠」，其係被填入低濃度之導電粒子丨2〇a，並且使得 其在xy平面不會彼此接觸。因此，在z方向壓縮該物質將 建立一導電路徑。 、 根據本發明之基板1 1 0，其上表面設有複數個錫球銲墊 (solder pad)(未示於圖中），用以供複數個錫球設於其 上。該基板1 1 0下表面之複數個接墊11 〇 a係利用一導電電 路（未示於圖中）電性連接至相對應的錫球銲墊。用於本 發明之基板可包含任何層數之導電電路。較佳地，該基板 係為以利用任一種增層法（build-up)製程技術形成之球 格陣列（B G A)基板。該基板可由玻璃纖維強化b τ (bismaleimide-triazine)樹脂，或FR-4玻璃纖維強化環 氧樹脂（fiberglass reinforced epoxy resin)形成。該 基板亦可以是一多層陶瓷基板（multi - layer ceramic substrate)或是一聚醯亞胺薄片基板（p〇lyimide fi lm substrate 弟 圖至弟十二圖係用以祝明根據本發明較佳實施例』 晶片尺寸級封裝構造製造方法。 、 參K?、弟一圖，在大量生產時，一般係將複數個基板η 〇 正a在起形成一條狀物（一般稱為基板條（s u b s t r a t e strip) 20 0 )，其較佳在基板間設有切割道（street nne 2 0 0 a以供切割之用。 第二圖揭示複數個金屬突塊1 4 〇形成在該基板條2 〇 〇上。 遠金屬突塊1 4 0係設於每一個基板11 〇的複數個接墊11 〇 aPage 7 502344 V. Description of the invention (4) The grooves correspond to the boundary area of the plurality of wafers; (g) the grooves are sealed; (h) the wafers are cut and the grooves are sealed to obtain the plurality of wafers Size-level package construction. ^ The CSP manufacturing method according to the present invention is characterized in that the plurality of substrates are wafers attached to the wafer one by one, thereby minimizing the influence of the CTE mismatch between the wafer and the substrate, so that Significantly increase product yield. In addition, because you can choose to attach only acceptable substrates to the wafer after the test, you can avoid wasting intact wafers on the wafer. In order to make the above and other objects, features, and advantages of the present invention more apparent, the following describes the preferred embodiments of the present invention and the accompanying drawings in detail, as follows. [Explanation of the Invention] The fourteenth figure discloses a wafer-scale package structure 100 according to a preferred embodiment of the present invention, which mainly includes a substrate 11 () using an anisotropic conductive adhesive film (ACF) 120 It is disposed on the front surface of a semiconductor wafer 130. A contact pad 110a is provided on the lower surface of the substrate 110. A plurality of metal bumps (〇161; 31 @ bu! Np) l40 are provided on the pad 1 1 〇a, wherein the metal bump 14 is preferably formed by using a conventional wire bonding technique. Stud bump. This semiconductor wafer 130 has a plurality of wafer pads 130a provided on its front surface. The metal bumps 14 on the substrate are electrically connected to the corresponding wafer pads 320 using the anisotropic conductive adhesive layer 120, which is used to transmit the signal transmitted from the wafer to the outside through the substrate Π0. . The substrate and the side of the anisotropic conductive adhesive layer 120 are sealed with a gel. Known for 502344 V. Description of the invention (5) The anisotropic adhesive used to form the anisotropic conductive adhesive layer 1 2 0 is a "z-axis anisotropic adhesive", which is filled with low-concentration conductive particles 2a, and make it not contact each other in the xy plane. Therefore, compressing the substance in the z direction will establish a conductive path. According to the substrate 110 of the present invention, a plurality of solder pads (not shown in the figure) are provided on an upper surface of the substrate 1 10 for the plurality of solder balls to be disposed thereon. The plurality of pads 110a on the lower surface of the substrate 110 are electrically connected to corresponding solder ball pads by using a conductive circuit (not shown). The substrate used in the present invention may include any number of layers of conductive circuits. Preferably, the substrate is a ball grid array (B G A) substrate formed by using any build-up process technology. The substrate may be formed of glass fiber reinforced b τ (bismaleimide-triazine) resin or FR-4 fiberglass reinforced epoxy resin. The substrate may also be a multi-layer ceramic substrate or a polyimide thin film substrate (polyimide fi lm substrate). Example "Manufacturing method of a wafer-size package structure. Please refer to Fig. 1 and Fig. 1. In mass production, a plurality of substrates η 〇 are generally formed into a strip (commonly referred to as a substrate strip) ) 20 0), which is preferably provided with cutting lanes (street nne 2 0 a) for cutting between the substrates. The second figure reveals that a plurality of metal bumps 1 400 are formed on the substrate strip 2000. The far metal bump 1 40 is a plurality of pads 11 〇 a provided on each substrate 11 〇 a

P00-150.ptd 第9頁 502344 五、發明說明（6) 上。該金屬突塊1 4 0較佳為利用習知的打線技術（w i re bonding technique)形成之柱狀突塊（stud bump)。此 外’該金屬突塊1 4 0可利用習知的植球技術（b u m p i n g technology)形成，其包含步驟（Α)在基板的複數個接墊上 开> 成一突塊下金屬層（under bump metallurgy，UBM)，例 如以無電鍍鎳/金（electroless Ni/Au)形成UBM ;以及（B) 在U B Μ上形成金屬突塊’植球的方式則有蒸鐘、電鑛 (electroplating)、印刷（printing)等方法。 第五圖揭示一異方性導電膠層12〇以及其下表面之離型 層一起貼至一具黏性薄片（adhesive sheet)210。一般而 言’異方性導電膠層出廠時，其上表面以及下表面係各為 一離型層（Re lease Fi lm)保護。首先，將該異方性導電膠 層以及其表面之離型層一起貼至一具黏性薄片（adhesi ve sheet) 210，使得其下表面之離型層i2〇b係面向該具黏性 薄片。然後，移除該異方性導電膠層上表面之離型層。較 佳地，該具黏性薄片2 1 0係為一用於晶圓切割的藍膠 (blue tape)，並且係為一環形框架22〇支撐。 參照第五圖以及第六圖，將設有金屬凸塊丨4 〇之基板條 200下表面貼到該異方性導電膠層12〇上而形成一異方膠/ 基板條複合體。 參照第七圖，切割該異方膠/基板條複合體成為複數個 個別單兀。值得注意的是，切割之深度係大於基板丨丨〇以 及異方性導電膠層120之厚度，但小於基板11〇、異方性導 電膠層120以及其下表面離型層i2〇b之厚度。由於膠層120P00-150.ptd Page 9 502344 V. Description of Invention (6). The metal bump 1 40 is preferably a stud bump formed using a conventional wi re bonding technique. In addition, the metal bump 1 40 can be formed by using a conventional bumping technology, which includes a step (A) of opening on a plurality of pads of the substrate to form an under bump metallurgy (under bump metallurgy, (UBM), for example, UBM is formed by electroless Ni / Au; and (B) Metal bumps are formed on the UB ′, such as steaming bells, electroplating, and printing. ) And other methods. The fifth figure reveals that an anisotropic conductive adhesive layer 120 and a release layer on the lower surface thereof are attached to an adhesive sheet 210 together. Generally speaking, when the anisotropic conductive adhesive layer is shipped from the factory, its upper surface and lower surface are protected by a release layer (Re lease Fi lm). First, the anisotropic conductive adhesive layer and the release layer on the surface thereof are affixed to an adhesive sheet 210 such that the release layer i2b on the lower surface thereof faces the adhesive sheet. . Then, the release layer on the upper surface of the anisotropic conductive adhesive layer is removed. Preferably, the adhesive sheet 2 10 is a blue tape for wafer cutting, and is supported by a ring frame 22. Referring to the fifth and sixth figures, the lower surface of the substrate strip 200 provided with the metal bumps 400 is attached to the anisotropic conductive adhesive layer 120 to form an anisotropic adhesive / substrate strip composite. Referring to the seventh figure, the anisotropic rubber / substrate strip composite is cut into a plurality of individual units. It is worth noting that the depth of the cut is greater than the thickness of the substrate 丨 丨 and the anisotropic conductive adhesive layer 120, but smaller than the thickness of the substrate 110, the anisotropic conductive adhesive layer 120 and the lower surface release layer i20b . Since the glue layer 120

P00-150. ptd 第10頁 502344 五、發明說明（7) 及離型層120b間之附著力遠小離型層120b與具黏性薄片 2 1 0間之附著力，因此個別之基板1 1 〇及其下之異方性導電 膠層1 2 0可輕易地被切開的（s a w e d - a p a r t)異方膠/基板條 複合體中移出。 參照第八圖，一自動化選取及安放的機器2 3 0，將個別 之基板11 0及異方性導電膠層1 2 0精確置放在晶圓24 0上之 預先設定位置（參見第九圖）。一般而言，基板條2 〇 〇上 的不良品基板（defective substrate)會被塗上白墨以便 與其他正常品基板區別。因此，該自動化選取及安放的機 器2 3 0可藉由辨識白墨而選取正常品基板。由於可選擇只 將正常品基板及異方性導電膠層貼至晶圓，因此可避免浪 費晶圓上完好之晶片。此外，晶圓上的不良品晶片係以虛 基板（dummy substrate) 235利用普通之膠層例如環氧膠貼 上’因此可避免浪費完好之基板及異方性導電膠層。該虛 基板的材質係與基板大致相同。該虛基板不需要佈線，藉 此降低成本。 接著，進行熱壓合製程（thermoc⑽pressi⑽b⑽di_ 後’使得基板1 1 0藉由設於其上之異方性導電膠層丨 至晶圓240上之晶片130，並且使得該基板丨1〇上之金屬突 塊140藉由導電粒子12〇3電性連接至相對應之晶片銲墊 130a (參照第十圖）。可以理解的是異方性導電膠層可以 是熱塑性或熱固性。熱塑性異方轉係先被加熱軟化使用 後再冷卻固化。熱固性異方性膠則需加熱1〇〇_3〇〇。〇，數 分鐘至一小時或以上使其固化。P00-150. Ptd Page 10 502344 V. Description of the invention (7) The adhesion between the release layer 120b and the release layer 120b is very small. The adhesion between the release layer 120b and the adhesive sheet 2 1 0, so the individual substrate 1 1 〇 and the anisotropic conductive adhesive layer 1 2 0 can be easily removed from the sawed-apart anisotropic adhesive / substrate strip composite. Referring to the eighth figure, an automatic selection and placement machine 2 3 0 accurately places individual substrates 11 0 and anisotropic conductive adhesive layers 1 2 0 on a predetermined position on a wafer 24 0 (see FIG. 9 ). Generally speaking, defective substrates on the substrate strip 2000 are coated with white ink to distinguish them from other normal substrates. Therefore, the automatic selection and placement machine 230 can select a normal substrate by recognizing the white ink. Because you can choose to stick only the normal substrate and the anisotropic conductive adhesive layer to the wafer, you can avoid wasting the intact wafer on the wafer. In addition, the defective wafer on the wafer is affixed with a dummy substrate 235 using a common adhesive layer such as epoxy adhesive, so that the intact substrate and the anisotropic conductive adhesive layer can be avoided. The material of the dummy substrate is substantially the same as that of the substrate. The dummy substrate does not require wiring, thereby reducing costs. Next, a thermocompression bonding process (thermoc⑽pressi⑽b⑽di_ 'is performed to make the substrate 1 10 pass through the anisotropic conductive adhesive layer provided thereon to the wafer 130 on the wafer 240, and make the metal protrusion on the substrate 10 The block 140 is electrically connected to the corresponding wafer pad 130a (refer to the tenth figure) through the conductive particles 1203. It can be understood that the anisotropic conductive adhesive layer can be thermoplastic or thermosetting. The thermoplastic anisotropic conversion is first After heating and softening, it will be cooled and solidified. The thermosetting anisotropic adhesive needs to be heated for 100-300 °, which can be cured for several minutes to one hour or more.

^U2J44 五、發明說明（8) " - -- 參照第十一圖，利用一切割刀具（dicing Made)25〇在 =應=該複數個晶片13〇之邊界區域形成溝槽254。值得注 二的疋’該溝槽2 5 4之深度係大於基板丨丨〇以及異方性導電 .=1。20之厚度，但小於基板丨1()、異方性導電膠層12〇以 及阳圓2 4 0之厚度。較佳地，該溝槽2 5 4之深度大致等於基 板110以及異方性導電膠層12〇之厚度。 參照第十二圖’利用一自動化點膠系統（aut〇mated underfill dispense system)將填膠材料（underfill material)點在溝槽254中，然後移至一固化爐（curing oven)内’固化該填膠材料而形成封膠體ί5〇。 根據本發明之晶片尺寸級封裝構造製造方法，其較佳另 包含將複數個錫球設於該基板錫球銲墊之步驟（未示於圖 中）。其較佳係在填膠材料固化製程完成後，將該複數個 錫球利用錫球放置法（s〇lder —baU placement)或模板印 刷技#(、ftenci 1 print丨ng)形成於該基板上表面之錫球銲 墊。忒複數個錫球係做為根據本發明之晶片尺寸級封冓 造=外部輸入輪出電極（I/〇 electr〇de)。 最後，麥照第十三圖，利用另一切割刀具（dicing blade) 252切割該晶圓以及密封之溝槽而製得如第十四圖 所示之晶片尺寸級封裝構造100。值得注意的是，該刀具 252之厚度係比形成溝槽之刀具2 5〇小。藉此使得該異方性 導電膠層120之側邊有封膠體15Q密封，而防止外界之水氣 以及雜質經由該異方性導電膠層丨2〇入侵至封裝構造丨〇 〇 内。^ U2J44 V. Description of the Invention (8) "--Referring to the eleventh figure, a groove 254 is formed in a boundary region of the plurality of wafers 13 by using a dicing Made 25. It is worth noting that the depth of the groove 2 5 4 is larger than the substrate 丨 丨 and anisotropic conductivity. = 1.20 thickness, but smaller than the substrate 丨 1 (), the anisotropic conductive adhesive layer 12 〇 and The thickness of the sun is 2 4 0. Preferably, the depth of the trenches 2 54 is substantially equal to the thickness of the substrate 110 and the anisotropic conductive adhesive layer 120. Refer to Figure 12 'Using an automated underfill dispense system to spot the underfill material in the trench 254 and then move it into a curing oven' to cure the underfill Glue material to form a sealing gel ί50. According to the method for manufacturing a wafer-size package structure according to the present invention, it preferably further includes a step of placing a plurality of solder balls on the substrate solder ball pad (not shown in the figure). Preferably, after the curing process of the filling material is completed, the plurality of solder balls are formed on the substrate by a solder ball placement method (solder-baU placement) or stencil printing technique # (, ftenci 1 print). Surface solder pads.忒 A plurality of solder balls are used as the wafer-size-level package according to the present invention = external input wheel output electrode (I / 〇 electrode). Finally, according to the thirteenth figure, Mai uses another dicing blade 252 to cut the wafer and the sealed trench to obtain a wafer-size package structure 100 as shown in the fourteenth figure. It is worth noting that the thickness of the cutter 252 is smaller than that of the cutter 250 which forms the groove. As a result, the side of the anisotropic conductive adhesive layer 120 is sealed with a sealing compound 15Q, so as to prevent external moisture and impurities from invading into the packaging structure through the anisotropic conductive adhesive layer 丨 20.

P00-150. ptd 第12頁 502344 五、發明說明（9) 根據本發明之CSP製造方法，其特徵在於該複數個基板 係逐片貼至該晶圓上之晶片，藉此將晶圓與基板熱膨脹係 數不配合（C 丁 E m i s m a t c h )的影響減至最小，因而大幅增加 產品良率。 雖然本發明已以前述較佳實施例揭示，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作各種之更動與修改。因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。P00-150. Ptd Page 12 502344 V. Description of the invention (9) The CSP manufacturing method according to the present invention is characterized in that the plurality of substrates are wafers attached to the wafer one by one, whereby the wafer and the substrate The influence of the thermal expansion coefficient mismatch (C but E mismatch) is minimized, thus greatly increasing the product yield. Although the present invention has been disclosed with the aforementioned preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

P00-150.ptd 第13頁 502344 圖式簡單說明 【圖示說明】 第1圖至第1 3圖：其係用以說明根據本發明較佳實施例 之晶片尺寸級封裝構造製造方法；及 第1 4圖：根據本發明較佳實施例之晶片尺寸級封裝構造 之剖面圖。 【圖號說明】 100 晶 片 尺 寸 級 封 裝 構 造 110 基 板 110a 接 墊 120 異 方 性 導 電 膠 層 120a 導 電 粒 子 120b 離 型 層 130 半 導 體 晶片 130a 晶 片 銲 墊 140 金 屬 突 塊 150 封 膠 體 200 基 板 條 2 0 0a 切 割 道 210 具 黏 性 薄 片 220 環 形 框 架 230 .自 動 化 選 取 及 安 放 的機器 240 晶 圓 250 刀 具 252 刀 具 254 溝 槽P00-150.ptd Page 13 502344 Brief description of the drawings [Illustration] Figures 1 to 13: These are used to explain the manufacturing method of the chip size package structure according to the preferred embodiment of the present invention; and 14: A cross-sectional view of a wafer-scale package structure according to a preferred embodiment of the present invention. [Illustration of the drawing number] 100 chip size package structure 110 substrate 110a pad 120 anisotropic conductive adhesive layer 120a conductive particles 120b release layer 130 semiconductor wafer 130a wafer pad 140 metal bump 150 sealing compound 200 substrate strip 2 0 0a Cutting line 210 Adhesive sheet 220 Ring frame 230. Machine for automatic selection and placement 240 Wafer 250 Tool 252 Tool 254 Groove

P00-150.ptd 第14頁P00-150.ptd Page 14

Claims (1)

JUZJ44JUZJ44 案號 89126322 1 丨丨丨 I I 六、申請專利範圍 1、一種晶片尺寸級封裝構造，其包含： 心基Ϊ’具有一上表面以及-下表面，該基板之上表面 個錫球銲塾（SQlder pad)，該基板之下表面設有 ^數個接塾（contact pad)電性連接至相對應的錫球銲 I 複數個金屬突塊（metal bump)設於該基板之接墊； 二半導體晶片，其具有複數個晶片銲墊設於其正面； 該基板係利用一異方性導電膠層（ACF)設於該晶片之正 面使得°玄基板上之金屬突塊電性連接至相對應之晶片銲 墊；及 封膝體後封該基板以及異方性導電膠層之侧邊。 Μ 實 % 容 § 2、 依申請專利範圍第1項之晶片尺寸級封裝構造，其中該 基板係為一球格陣列（BGΑ)基板。 3、 依申請專利範圍第1項之晶片尺寸級封裝構造，其中該 封膠體係由填膠材料（underfiH material)形成。 4、 依申請專利範圍第1項之晶片尺寸級封裝構造，其另包 含複數個錫球（solder bal 1)設於該基板之錫球銲墊。 5、 依申請專利範圍第1項之晶片尺寸級封裝構造，其中該 金屬突塊係為利用習知的打線技術形成之柱狀突塊（stud bump) 〇Case number 89126322 1 丨 丨 丨 II VI. Patent application scope 1. A chip-size package structure, which includes: a core substrate with an upper surface and a lower surface, and a solder ball on the upper surface of the substrate (SQlder) pad), the bottom surface of the substrate is provided with a plurality of contact pads which are electrically connected to corresponding solder balls. A plurality of metal bumps are provided on the substrate; two semiconductor wafers; The substrate is provided with a plurality of wafer pads on its front surface; the substrate is provided with an anisotropic conductive adhesive layer (ACF) on the front surface of the wafer so that the metal bumps on the substrate are electrically connected to the corresponding wafer A solder pad; and sealing the side of the substrate and the anisotropic conductive adhesive layer after sealing the knee body. Μ Real% capacity § 2. According to the wafer size package structure of the first patent application scope, the substrate is a ball grid array (BGA) substrate. 3. The chip-size package structure according to item 1 of the patent application scope, wherein the sealing system is formed of an underfiH material. 4. The chip-size package structure according to item 1 of the scope of patent application, which additionally includes a plurality of solder balls (solder bal 1) solder balls provided on the substrate. 5. The chip-size package structure according to item 1 of the patent application scope, wherein the metal bump is a stud bump formed by a conventional wire bonding technology. P00-150.ptc 第15頁 502344P00-150.ptc Page 15 502344 b、一種在晶圓層次（wafer level)製造複數個晶片尺寸級 封裝構造的方法，其包含下列步驟： 、 提供一基板條（substrate strip)，其包含複數個基 板，該每一基板上表面設有複數個錫球銲墊，該每一&基板 之下表面設有複數個接墊電性連接至相對應的錫球銲^ 形成複數個金屬凸塊於該每一基板之複數個接墊上·’ 將一異方性導電膠層（ACF)貼至該基板條之下表面而形 成一異方膠/基板條複合體； y 切割該異方膠/基板條複合體成複數個下表 性導電膠層之基板； 卸/、有異方 提供一晶圓包含複數個晶片，其中該晶片具有 片銲墊設於其正面；b. A method for manufacturing a plurality of wafer-size package structures at a wafer level, comprising the following steps: 1. A substrate strip is provided, which includes a plurality of substrates, and the upper surface of each substrate is provided with a substrate strip. There are a plurality of solder ball pads, and a plurality of pads are provided on the lower surface of each & substrate to be electrically connected to the corresponding solder ball ^ to form a plurality of metal bumps on the plurality of pads of each substrate · 'An anisotropic conductive adhesive layer (ACF) is attached to the lower surface of the substrate strip to form an anisotropic adhesive / substrate strip composite; y cutting the anisotropic adhesive / substrate strip composite into a plurality of A substrate with a conductive adhesive layer; unloading, providing a wafer including a plurality of wafers, wherein the wafer has a pad on the front surface; 將該複數個基板藉由設於其上之異方性導電膠層接人 该晶圓之複數個晶片，使得該每一基板上之金屬突塊 連接至相對應之晶片銲墊； ’’ 形成溝槽對應於該複數個晶片之邊界區域； 密封該溝槽； 切割該晶圓以及密封溝槽而製得該複數個晶片尺 裝構造。 封 7、依申請專利範圍第6項之晶片尺寸級封裝構造製造方 法，其中該溝槽之深度係大於基板以及異方性導電膠層之 厚度，但小於基板、異方性導電膠層以及晶圓之厚度:The plurality of substrates are connected to the plurality of wafers of the wafer through an anisotropic conductive adhesive layer provided thereon, so that the metal bumps on each substrate are connected to corresponding wafer pads; The trenches correspond to the boundary regions of the plurality of wafers; sealing the trenches; cutting the wafer and sealing the trenches to obtain the plurality of wafer ruled structures. Seal 7. The method for manufacturing a wafer-size package structure according to item 6 of the patent application scope, wherein the depth of the groove is greater than the thickness of the substrate and the anisotropic conductive adhesive layer, but smaller than the thickness of the substrate, the anisotropic conductive adhesive layer, and Circle thickness: 修正 、依申請專利範圍第6項 之晶片尺寸級封裝構造製造方 ;厚；：該溝槽之深度大致等於基板以及異方 膠層 、依申請專利範圍第6項 之晶片尺寸級封裝構造製造方 法，其中該溝槽之形命总心4〜—丨丹也农逭万 澧槽之切塞…一係利用第一刀具，該晶圓以及密封 溝槽之切割係利用第二刀具， 具小 該第二刀具之厚度比第一刀 1二利範圍第6項之晶片尺寸級封震構造製造方 '八^ 土板係為—球格陣列（BGA)基板。 、 11、 依申請專利範圍第β s 法，其中該溝槽之= 封裝構造製造， w心在封係利用一填膠材料。 < I 12、 依申請專利範圍第6項之晶片尺寸級封 法，其另包含將複數個錫球設於該基板錫球銲二製二方 13、 依中請專利範圍第6項之晶片尺寸級封 的打線技術形成之柱 法，其中該金屬突塊係為利用習知:每衣造方 狀 突塊（stud bump) 1 4、一種在晶圓層次（wafer 1 I造複數個 曰曰 片尺寸 P〇〇-150.ptc 第17頁 3U2344 -----盡里89126322 __年月日 條正 &'申請專繼目 " -—- 級封裝構造的方法，其包含下列步驟： 提供基板條（substrate strip)，其包令複數個基 反，該每一基板上表面設有複數個錫球銲墊，該每一其板 之下表面設有複數個接墊電性連接至相對應的錫球銲g ; 形成複數個金屬凸塊於該每一基板之複數個接墊上. 提供一異方性導電膠層，其上表面以及下表面各為丄離 型層（Release Film)保護； 4異方性導電膠層以及其表面之離型層貼至一具黏性薄 片（adhesive sheet)，像得其下表面之離型層係面向該具 黏性薄片； 移除該異方性導電膠層上表面之離型層； 將設有金屬凸塊之基板條下表面貼到該異方性導電膠層 上而形成一異方膠/基板條複合體； 切割該異方膠/基板條複合體成複數個下表面具有異| 性導電膠層之基板； 〜 提供一晶圓包含複數個晶片，其中該晶片具有複數個晶 片銲墊設於其正面； 將该複數個基板藉由設於其上之異方性導電膠層接合至 該晶圓之複數個晶片，使得該每一基板上之金屬突塊電性 連接至相對應之晶片銲墊； 形成溝槽對應於該複數個晶片之邊界區域； 密封該溝槽； 切割該晶圓以及密封溝槽而製得該複數個晶片尺寸級封 裝構造。Revised, according to the wafer size packaging structure manufacturing method according to item 6 of the patent application scope; Thick ;: The depth of the groove is approximately equal to the substrate and the anisotropic adhesive layer, and the wafer size packaging structure manufacturing method according to item 6 of the patent application scope Among them, the shape of the groove is 4 ~~ 丨 The cutting plug of Dan Ye Nong Nong Wan Wan groove ... One uses the first tool, and the wafer and the sealed groove are cut by the second tool. The thickness of the second cutter is larger than that of the first cutter in the 6th range of the wafer size-grade seismic isolation structure manufacturing method. The earth plate system is a ball grid array (BGA) substrate. 11. According to the β s method of the scope of the patent application, where the groove = is manufactured by the packaging structure, and a sealing material is used in the sealing system. < I 12. The wafer size-level sealing method according to item 6 of the patent application scope, which further includes a plurality of solder balls set on the substrate, solder ball two-party two-party 13, wafers according to the patent application item 6 The pillar method formed by the wire bonding technology of the size-level sealing, wherein the metal bump is a conventional method: a stud bump 1 is made per garment, a kind of wafer 1 (wafer 1) Chip size P〇〇-150.ptc Page 17 3U2344 ----- as far as possible 89126322 __ year month day article is positive & 'application for special purpose "---class packaging structure method, which includes the following steps : A substrate strip is provided, which includes a plurality of substrates. Each substrate has a plurality of solder ball pads on its upper surface, and a plurality of pads on its lower surface are electrically connected to the substrate. Corresponding solder ball g; forming a plurality of metal bumps on the plurality of pads of each substrate. An anisotropic conductive adhesive layer is provided, the upper surface and the lower surface of which are each a release film (Release Film) Protection; 4 anisotropic conductive adhesive layer and the release layer on the surface is stuck to a sticky Adhesive sheet, the release layer on the lower surface is facing the adhesive sheet; the release layer on the upper surface of the anisotropic conductive adhesive layer is removed; the lower surface of the substrate strip provided with metal bumps Paste on the anisotropic conductive adhesive layer to form an anisotropic adhesive / substrate strip composite; cut the anisotropic adhesive / substrate strip composite into a plurality of substrates with an anisotropic conductive adhesive layer on the lower surface; ~ provide a The wafer includes a plurality of wafers, wherein the wafer has a plurality of wafer pads provided on the front surface thereof; the plurality of substrates are bonded to the plurality of wafers of the wafer through an anisotropic conductive adhesive layer provided thereon, so that The metal bumps on each substrate are electrically connected to corresponding wafer pads; forming grooves corresponding to the boundary areas of the plurality of wafers; sealing the grooves; cutting the wafer and sealing the grooves to obtain the A plurality of wafer-scale package structures. P00-150.ptc 第18頁 502344 __案號 89126322 六、申請專利範圍 月 曰 1 5、依申請專利範圍第1 4項之晶片尺寸級封裝構造製造方 法’其中该溝槽之深度係大於基板以及異方性導電勝廣 厚度，但小於基板、異方性導電膠層以及晶圓之摩度。 1 6、依申請專利範圍第1 4項之晶片尺寸級封裝構造製造万 法，其中該溝槽之深度大致等於基板以及異方性導電膠廣 之厚度。 1 7、依申請專利範圍第1 4項之晶片尺寸級封裂構造製造方 法，其中該溝槽之形成係利用第一刀具，該晶圓以及密封 溝槽之切割係利用第二刀具，該第二刀具之厚度比第/刀 =:依申請專利範圍第14項之晶片尺寸級封裴構造製造方 > ，其中該基板係為一硃格陣列（BGA)基板。 L 19〜 法，P00-150.ptc Page 18 502344 __Case No. 89126322 VI. Scope of Patent Application Month 1 and 5. Manufacturing Method of Wafer Size Package Structure According to Item 14 of Patent Application Scope 'where the depth of the trench is greater than the substrate And the thickness of anisotropic conductive is wider, but smaller than the friction of substrate, anisotropic conductive adhesive layer and wafer. 16. According to the method for manufacturing a wafer-size package structure according to item 14 of the scope of patent application, the depth of the trench is approximately equal to the thickness of the substrate and the anisotropic conductive adhesive. 17. According to the method for manufacturing a wafer size-level cracking structure according to item 14 of the scope of the patent application, the formation of the grooves uses a first tool, and the cutting of the wafer and the sealed grooves uses a second tool. The thickness ratio of the two knives / knife =: According to the wafer size-class sealing and manufacturing method of the patent application No. 14 >, wherein the substrate is a Zhuge Array (BGA) substrate. L 19 ~ Law, 八中該溝槽之密封係利用 依申請專利範圍第1 4項之 晶片尺寸級封裝構造製造方 一填膠材料。 20〜 法， i之晶片 其另包含將複數個錫球設於 依申請專利範圍第20項之晶 片尺寸級封裝構造製造方 該基板錫球銲墊之少雜。 片尺寸級封裝構造製达方 502344 _案號89126322_年月曰 修正_ 六、申請專利範圍 法，該錫球設£步驟係在溝槽密封後、晶圓以及密封溝槽 切割前進行。 ， 22、 依申請專利範圍第1 4項之晶片尺寸級封裝構造製造方 法，其中該金屬突塊係為利用習知的打線技術形成之柱狀 突塊（stud bump)。 23、 依申請專利範圍第1 4項之晶片尺寸級封裝構造製造方 法，其中該具黏性薄片係為一用於晶圓切割的藍膠帶 (blue tape) 〇 24、 依申請專利範圍第1項之晶片尺寸封裝構造，其中該 異方性導電膠層係大致覆蓋於該基板之整個下表面。The sealing of the trench in No. 8 is made by using a wafer-size package structure manufactured by the patent application No. 14 and a filler material. 20 ~ method, i wafer It also includes a plurality of solder balls in the wafer size package structure manufacturing method according to the scope of the patent application No. 20 Manufacturing method of the substrate solder ball pads. Chip size-level package structure manufacturing method 502344 _Case No. 89126322_ year month amendment _ 6, the scope of the patent application method, the solder ball set step is performed after the trench sealing, wafer and sealed trench cutting. 22. The manufacturing method of the chip-size package structure according to item 14 of the scope of patent application, wherein the metal bump is a stud bump formed by a conventional wire bonding technology. 23. The method for manufacturing a wafer-scale package structure according to item 14 of the scope of patent application, wherein the adhesive sheet is a blue tape for wafer cutting. 〇24, according to item 1 of the scope of patent application The chip size package structure, wherein the anisotropic conductive adhesive layer covers substantially the entire lower surface of the substrate. P00-150.ptc 第20頁P00-150.ptc Page 20
TW89126322A 2000-12-07 2000-12-07 Chip scale package structure and its manufacturing method TW502344B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW89126322A TW502344B (en) 2000-12-07 2000-12-07 Chip scale package structure and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW89126322A TW502344B (en) 2000-12-07 2000-12-07 Chip scale package structure and its manufacturing method

Publications (1)

Publication Number Publication Date
TW502344B true TW502344B (en) 2002-09-11

Family

ID=21662267

Family Applications (1)

Application Number Title Priority Date Filing Date
TW89126322A TW502344B (en) 2000-12-07 2000-12-07 Chip scale package structure and its manufacturing method

Country Status (1)

Country Link
TW (1) TW502344B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI425583B (en) * 2007-05-04 2014-02-01 Stats Chippac Ltd Extended redistribution layers bumped wafer
TWI665944B (en) * 2014-06-19 2019-07-11 Samsung Electro-Mechanics Co., Ltd. Substrate strip, substrate panel, and manufacturing method of substrate strip

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI425583B (en) * 2007-05-04 2014-02-01 Stats Chippac Ltd Extended redistribution layers bumped wafer
US8716853B2 (en) 2007-05-04 2014-05-06 Stats Chippac, Ltd. Extended redistribution layers bumped wafer
US9406647B2 (en) 2007-05-04 2016-08-02 STATS ChipPAC Pte. Ltd. Extended redistribution layers bumped wafer
TWI665944B (en) * 2014-06-19 2019-07-11 Samsung Electro-Mechanics Co., Ltd. Substrate strip, substrate panel, and manufacturing method of substrate strip

Similar Documents

Publication Publication Date Title
US6737300B2 (en) Chip scale package and manufacturing method
JP3597754B2 (en) Semiconductor device and manufacturing method thereof
JP4705748B2 (en) Manufacturing method of semiconductor device
US7413925B2 (en) Method for fabricating semiconductor package
TW423120B (en) Semiconductor device having a sub-chip-scale package structure and method for forming same
KR100424058B1 (en) Semiconductor device and method of manufacturing same
US6372549B2 (en) Semiconductor package and semiconductor package fabrication method
US9698072B2 (en) Low-stress dual underfill packaging
JP2003332521A (en) Semiconductor device and manufacturing method therefor
US9425177B2 (en) Method of manufacturing semiconductor device including grinding semiconductor wafer
TWI236747B (en) Manufacturing process and structure for a flip-chip package
US6911737B2 (en) Semiconductor device package and method
US20110147905A1 (en) Semiconductor device and method of manufacturing the same
JP2012009655A (en) Semiconductor package and method of manufacturing the semiconductor package
JP3547303B2 (en) Method for manufacturing semiconductor device
JP2006222470A (en) Semiconductor device and manufacturing method thereof
US10854576B2 (en) Semiconductor device and manufacturing method thereof
TW502344B (en) Chip scale package structure and its manufacturing method
CN110634880A (en) Semiconductor device and method for manufacturing the same
TWI813942B (en) Semiconductor device
JP3243988B2 (en) Method for manufacturing semiconductor device
TWI394240B (en) Flip chip package eliminating bump and its interposer
TWI425580B (en) Process for manufacturing semiconductor chip packaging module
WO2024082532A1 (en) 2.5d module structure with six-side protection and manufacturing method therefor
JPH11204556A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent