TW466719B - Multi chip module packaging method by mixing chip and package - Google Patents

Abstract

The present invention provides a multi chip module packaging method by mixing chip and package. Conventionally, in order to increase the package density and operating speed, most of the bare and know-good dies (KGDs), such as processors or memory, are first installed on the substrate and then packaged. However, in the conventional multi chip module packaging process, there is encountered a problem in that the cost of known-good die is too high. If the KGD procedure is neglected, a problem is encountered in that the yield of the multi chip module packaging process is not high. The present invention discloses a multi chip module packaging method having the advantages of low cost and high reliability. The tested thin and small package is used as a KGD to be integrated into the ball grid array package process, so that the multi chip module packaging process can meet the requirements of low cost and high reliability.

Description

_ «89109556_year θ fl Rev. π: __ V. Description of the Invention (1) Field of the Invention The present invention relates to a method for multi-chip module package (MCM Package) of a hybrid chip and a package, traditionally ' In order to improve the density and speed of mounting on the substrate in semiconductor manufacturing processes, most known qualified chips (KGD), such as processors or memories, that are not yet packaged (Bare) are mounted on the substrate before proceeding. Encapsulation works. However, in the traditional multi-chip module packaging process, there is still a question that must be solved, then the problem of the high cost of known qualified chips (KD-Known Good Die), because if the known qualified chips are discarded [ The CD process, the whole multi-chip module packaging process will have a problem of low yield. BACKGROUND OF THE INVENTION After the wafers (Wafer) manufactured by the previous process are cut into chips, they are fixed on a metal frame. (Frame) and then use gold (au) and other metal wires to connect the tiny electrodes on the chip with the lead frame of the lead frame (L ead Frame). 'Finally covered with plastic to protect the internal semiconductor components (Dev ices), and finally it is electrically connected to the external motherboard. This technology of connecting the chip to the lead frame and covering it is called packaging.

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Mu Ke's advanced packages, such as chip scale packages, have become lighter and lighter than traditional packages, such as QFp (Quad nat pack) or SOKmali 〇utline Package. Thin and short, in order to reduce costs, packaging technology has also progressed from ceramic packaging technology to plastic packaging technology. It is also because of the multilayer interconnect structure in the front-through process, the protective layer process technology, and plastic packaging. Quality, and improve product reliability. However, if the cost of packaging can be reduced further, it will be more widely used in various electronic products. The technology not only strives for light, thin, short, small, and chip-scale packages (Chip Scab Packages) or wafer-level packaging (Wafer Level csp), but also to develop diversified packaging technologies in order to achieve higher density Sound installed. For this reason, the multi-chip module package has become another one: Known qualified wafer KGD refers to a wafer that can meet the specifications and has been tested and qualified. 'In order to improve the qualification rate of polycrystalline silicon in the semiconductor process, It is necessary to install KGD, which is a known qualified wafer. 、; MCM = Knowing that qualified wafers KGD are in the manufacturing process, and there are high costs: Q. Purpose of the invention

In view of this, the present invention integrates the thin and small scratches that have been tested as a known qualified wafer KGD into a ball grid array package, case number 89109556 V. Description of the invention (3) (Ball Gnd Array) process Because the package test has a test capacity point compared with the known qualified chip KGD, the method disclosed in the present invention is similar to J. It is a low-cost and highly reliable user. The cost is greatly reduced. According to the present invention, the present invention provides a rare-type package structure and method for achieving the above-mentioned objectives, including a multi-chip module package of cost and high reliability; a plurality of electrical components, a substrate, and one or more wafers. The substrate, wafer, and chip package connection pins, and a packaging material cover the J package. The schematic diagram is simple. Figure 5] Schematic diagram of the structure of the polar crystal square size package. Figure 5 Knows the crystal square size package with the central pad B. The square size CSP (Wafer Level CSP). Figure 1 (A) is Conventional map one (β) is a conventional flip chip bonding diagram. Figure two (A) is a conventional wire bonding chart. Figure two is a conventional flip chip bonding. Figure two (C) is another conventional flip chip. (D) is a conventional flip chip. Schematic diagram of multi-chip module package structure Schematic diagram of multi-chip module package structure

Page 7_Case No. 89109556_Year_Month_i ± i-_ V. Description of the invention (4) Figure 3 (A) is the first of the crystal size of wire bonding and flip chip bonding of the present invention. Schematic diagram of the package structure of a polycrystalline module according to an embodiment FIG. 3 (B) is a schematic diagram of the package structure of a multi-chip module of the second embodiment of a crystal-size package with chip bonding and a central pad of the present invention Three (C) is a schematic diagram of a multi-chip module package structure of the third embodiment of a wire-bonded wafer and a flip-chip-bonded chip-size package of the present invention. Figure three (D) is a multi-chip mold of the third embodiment of the present invention. The perspective of the package is not intended. Figure 3 (E) is a schematic diagram of the multi-chip module package structure of the fourth embodiment of the flip-chip bonded wafer and wire-bonded crystal-square package of the present invention. Figure 3 (F) is the wire bonding of the present invention. Multi-chip module package structure of the fifth embodiment of the wafer and the central pad of the cube-shaped package. Schematic diagram of the component symbols. 11,21,31 Substrate 12,22. The surface of the wafer 121,221 is facing up. Wafer 1 2 2, 2 2 2 Face down wafer 1 3, 23, 33 ball solder 1 4, 24, 34 Encapsulated Molding Resin 1 5, 2 5, 3 5 Wire 16, 26 Solder Ball Bump 27 Solder Pad

Case No. 8910 跖 5ft Month Five, Description of the Invention (5) Amend 321 322 371 372 373 Wire-bonded wafer flip-chip bonding Wafer wire-bonded crystal square-sized package Chip-bonded crystal square-sized package Central fresh Detailed description of the invention of the square-sized package (1) The ball diagram is a conventional multi-chip module package structure. There are more than one chip in a package, and the internal connection (Interc〇nnecti〇n) is a wire bond. (Wire Bonding) or FHp Chip Bonding. FIG. 1 (a) is a schematic diagram of a wire bonding package structure, which includes a substrate 11 and a plurality of wafers, a solder 13 located below the substrate u, and a connecting surface facing up the wafer 121 and the lead 15 of the substrate ^ , And packaging resin 14; Figure 1 (B) is a schematic diagram of a flip-chip bonding package structure 'including-substrate 11, a plurality of wafers 12, the spherical tin 13 on the substrate ur side, the connection surface is facing down 122 and the solder ball resin 14 of the substrate. Because these chips in the package have not undergone burn-in test (Burn ίη) and functional test (ρ / τ, 7: ^ =, order, so it is impossible to determine these crystals in the package. The yield of the agricultural body cannot be improved. 4 i. If there are four crystals in a package, the average F / T yield is 99%.

(99%) χ (99%) χ (99%) x (99%) = 96% Therefore, after multi-chip module packaging, the F / T yield of the entire multi-chip module package is reduced to 96%, and The more wafers to be packaged, the lower the yield. This will adversely affect the development of multi-chip module packaging in the future. Traditional know-how provides a way to avoid this effect, which is to know the qualified wafer KGD (KnWn-Good Die). In order to avoid the failure of the chip to determine its yield, which leads to a reduction in the F / T yield of the package, the wafer in the packaging process must undergo Burn In and Function Test. This process is called It is known as GKGi) (Known-Good Die). However, the implementation of the known qualified wafer KGD process is a high-cost process because the wafer size is small and it is not easy to fix in the process of performing old tests and functional tests, so the detailed description of the XS Rji ^ invention cannot be completely solved ( (2) The first disclosure of the present invention uses a chip packaging method. At present, a CSP (Chip Scale package) in a polycrystalline square size package is shown in the market. As shown in FIG. 2 (D), the chip size package csp (chip Scaie packag two package) The size of the device is slightly larger than the size of the chip—points, and the height is very low (about ^ its 1 · 00〇_ below). Figure two (A) ~ (D) are the conventional crystal size package

Page 10 466719 Λ__month correction ^ S__M〇9556 Five 'invention description (7) =, of which Figure 2 (A) is a schematic diagram of the wire-bonded crystal-size package structure 2 ((: Figure 2 (β) is a flip-chip bonding Schematic diagram of the crystal size package structure, Figure 2 (D is the structure schematic diagram of the crystal size package of the central pad, this figure is the conventional wafer-level crystal size CSP (Wafer Level CSP). These two, the size structure The csp is not only light, thin, short, and small, but it has also been tested by Laoliang ^ and functional tests. Therefore, there is no problem in constructing a CSP with this crystal size. Etc. The more important issue is to use this after aging tests and functions. The test cost is 'far lower than the known qualified KGD process. Another feature is short' using these cube sizes to construct the csp has no yield problems, and is light, thin, and a 'small' so it can easily replace the existing It is known that the qualified chip KGD is integrated into the multi-chip module package MCM Package process. Therefore, the thin and small CSP chip package or wafer level package size CSP (Wafer Level CSP) package that has been tested is known as Qualified Wafer (KGD), of which Of course, the chip may also include a bare chip, and the unpackaged chip may be bonded to the substrate by wire bonding or nip chip bonding. The package is integrated into the process of the ball grid array package (BGA Package) to 'make the multi-chip module packaging process' truly meet the requirements of low cost and high reliability. The following is a detailed description of the embodiment of the present invention: Examples

Three (A) is a schematic diagram of the multi-chip module package structure of the first embodiment of the wire-bonding and flip-chip bonding crystalline square-size package, which is the use of CSP for the present invention

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No. 89109FiM Amendment V. Description of the invention (8) In the multi-chip module packaging process, a ball-shaped cymbal // middle ditch substrate 31 under a substrate 31 is connected to a paddle die resin 34 ′ An embodiment of sealing the substrate with a square-shaped package 371 and a flip chip bonded to the square size of the substrate: (B) is the second size of the flip-chip bonded crystal and the central pad :: the second implementation Example: Multi-chip module sealing structure diagram inch: soil plate 31, spherical solder 33 below the substrate 31, sealing pei ^^: middle, the crystal size of the flip-chip bonding above the substrate 31 == 中央 中心 # 塾The crystal-square-size package 373, wherein the crystal square ruler 373, is electrically connected to the substrate with a wire 35. The third embodiment of the assembly FIG. 3 (C) is a schematic diagram of a multi-chip module package structure of a third embodiment of a wire-bonded wafer and a flip-chip-bonded crystal cube of the third embodiment. The lower ball-shaped solder 33, the package stamper 34, and the chip-size package θ and the wire 35 bonded to the flip-chip bonding 321 above the substrate 31 are bonded to the wafer 321. " __ Fourth Embodiment FIG. 3 (E) is a schematic diagram of a multi-chip module package structure of a fourth embodiment of a flip-chip-bonded wafer and a wire-bonded crystal-square package, including a substrate 31 on the substrate 31 The lower solder joint 33 and the molding resin 34 are encapsulated.

Page 12 466719 a Case No. 89109556 V. Description of the invention (9) __ Bonded to the wire above the substrate 31, a crystal bonded wafer 3 2 2. 3, 71 and the fifth embodiment Figure 3 (F) is a wire-bonded wafer and a central pad ^ The multi-chip module sealing structure of the fifth embodiment is shown in 3 ^ inch package The substrate 31, a ball-shaped solder under the substrate 31, "Feng Zhuang ^ includes a 3 4 ′ and a crystal square of the central material above the substrate 3 i, a wafer 321 bonded to the resin and the wire 35, wherein the crystal square The size seal ^ piece 373 wire 35 'is electrically conductively connected to the substrate. It is described in section 373 to sum up the above-mentioned' when it is known that the present invention has industrial applicability, natural, and progressive properties' and the present invention is not Seen in any publication, it should comply with the provisions of the Patent Law. However, the above are only the preferred embodiments of the present invention, and each can limit the scope of the implementation of the present invention. All equal changes and modifications should be covered by this creation ^.

4 6 6 7 1 9 _Case No. 89109556_Year Month Date__ Brief Description of Drawings Brief Description of Drawings Figure 1 (A) is a schematic diagram of the package structure of a conventional multi-chip module with wire bonding. Figure 1 (B) is a conventional Flip-chip bonding multi-chip module package structure diagram Figure 2 (A) is the structure schematic diagram of the conventional wire-bonded crystal-size package Figure 2 (B) is the structure schematic diagram of the conventional flip-chip-bonded crystal size package Figure 2 (C) is a schematic diagram of another conventional crystal-size package with a central pad. Figure 2 (D) is a conventional wafer polar size CSP (Wafer Level CSP). Figure 3 (A) is a wire of the present invention Schematic diagram of the multi-chip module package structure of the first embodiment of the bonded crystal square size and flip-chip bonded crystal square size package Figure 3 (B) is the flip-chip bonded crystal square size and the central pad of the present invention Schematic diagram of the multi-chip module package structure of the second embodiment of the size package Figure 3 (C) is a schematic diagram of the multi-chip module package structure of the third embodiment of the wire-bonded wafer and flip-chip-bonded chip-size package of the present invention Figure 3 (D) shows the third embodiment of the present invention Perspective view of the multi-chip module package of the example. Figure 3 U) is a schematic diagram of the multi-chip module package structure of the fourth embodiment of the flip-chip bonding wafer and wire bonding package of the present invention.

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Claims (1)

Case number 89109556 范围 Application scope 1. Multi-chip module substrate of mixed chips and packages' The substrate is provided with a plurality of electrical connection structures, including an electrical connection point, a plurality of electrical connection pins and : Ten = and J: body, and the chip package, the electrical connection ^, Japanese and Japanese packaging materials are covered. 4 U and the recording board are covered by the seal 2. If the package structure of the patent application item No. 丨, and the grandfather is a package that encapsulates csp or wafer level (CSP) at the crystal size. Tapping size CSP (Wafer 3 · If the scope of the patent application is the first item or Dai? Seal package, $, 丨, fly the second package structure, including the chip package. Alpha, Wire Bonding) Size package. Five seals were made in February, and the seal structure of item 1 or item 2 of the criminal garden, in which the wafer was sealed, at least one of them was a crystal-size package with a center material. 6 · If the package structure of the scope of application (item or item 2), where the chip Page 16 Λ. The package is a seal that has been tested for aging (hnCt 10n Test ^ = π-Ιη) and functional test. 7. If the connection pin of the first scope of the patent application is a ball solder. . ,,, structure, where the plurality of electrical properties 8. If the sealing connection point of item i in the scope of the patent application is a ball solder or gold wire factory, "a plurality of electrical properties 9 #-a hybrid chip and The package of the multi-chip module package of the package, — a plurality of electrical connection chip packages and bases are arranged on the U substrate: electrical connection points, a plurality of electrical connection pins and a packaging material. The characteristics are: configuration At least one chip and one or more chip packages on the substrate, and the chip, the chip package, the electrical connection point, and the substrate are covered by the packaging material. 1. If the scope of patent application The package structure of item 9, wherein the chip is-an unpackaged (Bare) chip. 11 · For the package structure of the scope of application for item 10, wherein the unpackaged (Bare) chip is at least one wire-bonded ( (Wire Bonding) or Flip chip bonding on the substrate. 1 2. The package structure according to item 9 of the patent application scope, wherein the chip package 466719-Case-No. __Year month __ amendment_ VI. The scope of patent application is for package of csp or wafer level package size CSp (Wafer Level CSP). 1 3 * If the package structure of item 9 or item 12 of the scope of the patent application, at least one of the chip package 'is a wire-bonded (W 丨 rebondng) crystalline square-size package. 1 4 · If the package structure of item 9 or item 12 of the scope of patent application, at least one of the chip package is a chip-size package with flip chip bonding. 1 5. The package structure according to item 9 or item 12 of the scope of patent application, wherein at least one of the chip package is a crystal-size package with a central pad. 16. If the package structure of item 9 or item 12 of the scope of patent application, the wafer package ’is a package that has been tested by Burn In and Function Test. . For example, the package structure in the scope of the patent application item 9, wherein the plurality of electrical pins are spherical solders. 18 · In the package structure, the scope of the patent application item 9, the plurality of electrical reverse contacts may be spherical. Solder or gold wire. Page 18 6 6 7 t 9 Six applications for patent scope 1 9-multiple kinds of mixed total chips and packages, including a plurality of chip adhesion-substrate, chip module packaging method, including electrically connecting the chip assembly and the substrate J, the substrate is provided with a plurality of connection pins and a plurality of connection points formed by a packaging material, and a plurality of electrical properties lies in the use of one or more: a chip package package body, which features a chip 'electricity The package is physically connected to the substrate, as a known assembly. Electrical connection points to form the book 20, such as the 19th application for the scope of patent application can form a plurality of electrical connection pins ,,, /, where the upper surface of the body. Cover the body with an encapsulation material 21. The encapsulation pin according to item 20 of the patent application is a ball solder. The method of mounting the method 22. Among them, the method of mounting μ + in the scope of the patent application No.9, wherein the chip packaging system is a package of crystal size package (csp or wafer level CSP). Human T UP (Wafe 23. If the method of encapsulating the 19th or 22nd patent scope of the patent application applies directly to the chip package, at least one is a crystalline package with wire bonding (Wlre Bonding). 24. Such as The method of applying for the encapsulation of item 9 or item 22 of the patent scope, in which Page 19, 18 6 7 19 _Case No. 89109556_Year Month Amendment _ Six 'Patent Application Scope The chip package, at least one of which is a chip-size package of FI ip Chip Bonging. 2 5. The method of packaging according to item 19 or item 22 of the patent application scope, wherein at least one of the chip package is a crystal-size package with a central pad. 2 6. The method of packaging according to item 19 or item 22 of the scope of patent application, wherein the chip package may be a package that has been tested for burn-in and function test (F uncti ο η T est) body. 2 7. The method of packaging according to item 19 of the scope of patent application, wherein the height of the chip package is lower than 1.0 mm. 2 8. The method of encapsulation according to item 19 of the scope of patent application, wherein the electrical connection points of the chip package can be ball solder or gold wires. Page 20