TWI236744B - Method for manufacturing stacked multi-chip package - Google Patents

Method for manufacturing stacked multi-chip package Download PDF

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Publication number
TWI236744B
TWI236744B TW093118578A TW93118578A TWI236744B TW I236744 B TWI236744 B TW I236744B TW 093118578 A TW093118578 A TW 093118578A TW 93118578 A TW93118578 A TW 93118578A TW I236744 B TWI236744 B TW I236744B
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Taiwan
Prior art keywords
chip
wafer
item
pad
scope
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TW093118578A
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Chinese (zh)
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TW200601511A (en
Inventor
Yung-Li Lu
Shih-Chang Lee
Gwo-Liang Weng
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Advanced Semiconductor Eng
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Priority to TW093118578A priority Critical patent/TWI236744B/en
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Publication of TWI236744B publication Critical patent/TWI236744B/en
Publication of TW200601511A publication Critical patent/TW200601511A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A method for manufacturing stacked multi-chip package is disclosed. At first, a first chip is disposed on a substrate, the first chip has a plurality of first bonding pads and at least a second bonding pad on its active surface. A plurality of first bonding wires connect the first bonding pads of the first chip to the substrate. A mold compound having an opening is formed by a molding tool to seal the first bonding pads of the first chip and the first bonding wires without covering the second bonding pad. After removing the molding tool, the second bonding pad is exposed from the opening of the mold compound. A second chip is disposed on the exposed active surface of the first chip and electrically connects to the second bonding pad so that the first chip and the second chip can transmit signal each other.

Description

1236744 五、發明說明（1) 【發明所屬之技術領域 本發明係有關於—福各曰Η 法，特別係有關於―種電二;^疊封裂構造之製造方 之間之多晶片堆疊封裝；===行在多封膠體形成 【先前技術】 & ° 隨者微小化與向運作球唐愛七 ^ ^ ^ ^ Β,, ； ：h,；p, ；soc) ^ ^^ 门糸統封裝（system in pac age，SI P ，其中系統晶片係將類比、記憶體和邏輯 電路整合為一，但其製程複雜製作不易，而習知之多晶片 堆疊封裝構造，如美國專利公告第5, 923, 〇9〇號「微電子 ，裝及其製造方法」所揭示者，其係包含一基板、一第一 晶片:一第二晶片及一封膠體，該第一晶片係貼設於該基 板，該第一晶片之一主動面係具有複數個周邊銲墊與複數 個中央銲墊，該些周邊銲墊係以複數個銲線與該基板電性 連接’該第二晶片係以複數個凸塊接合於該第一晶片之第 二銲墊，該封膠體係於該第二晶片覆晶接合於該第一晶片 之後，才形成於該基板上，以密封該第一晶片與該第二晶 片’因此，如果該第一晶片或該第二晶片在製程中受靜電 或外力所影響，而造成功能不良，必須在完成該多晶片堆< 叠封裝構造之後，進行產品測試（final test)，才可得知 結果，無法在形成該封膠體之前得知，造成成本浪費與降 低良率。 【發明内容】1236744 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to the -Fukushima method, and more particularly to-a kind of electric two; ^ multi-chip stacking package between the manufacturers of the stacking and cracking structure ; === Rows of colloids are formed. [Previous technique] & ° Follower miniaturization and operation ball Tang Aiqi ^ ^ ^ ^ Β ,,;: h ,; p,; soc) ^ ^^ ^ System package (system in pac age, SIP), where the system chip integrates analog, memory, and logic circuits into one, but its complex process is not easy to manufacture, and the conventional multi-chip stacked package structure, such as US Patent Bulletin No. 5, As disclosed in No. 923, "Microelectronics, Packaging and Manufacturing Method", it includes a substrate, a first wafer: a second wafer, and a colloid. The first wafer is attached to the substrate. An active surface of one of the first wafers has a plurality of peripheral pads and a plurality of central pads. The peripheral pads are electrically connected to the substrate by a plurality of bonding wires. The second wafer is a plurality of protrusions. The second bonding pad is bonded to the first wafer, and the sealing system is The wafer is bonded to the first wafer and then formed on the substrate to seal the first wafer and the second wafer. Therefore, if the first wafer or the second wafer is subjected to static electricity or external forces during the manufacturing process, Impact, resulting in poor function, the final test must be performed after the multi-chip stack < stacked package structure is completed, the results can not be known, which can not be known before the formation of the sealant, resulting in cost waste and reduction Yield [Inventive Content]

1236744 五、發明說明（3) 供一 Ϊ本發明之多晶片堆疊封裝構造之製造方法，包含提 ;動該第一晶片係具有一主動面及-背面，該 數個第一銲塾與至少-第二銲塾，之後 一 $/$ Μ ϋ片於一基板，並以複數個第一銲線連接該第 口：篦ί 一銲墊與該基板’再以一模具形成-具有-開 二日：？膠體’該第—封膠體係密封該第-晶片之該些 f '墊與該些第一銲線，接著移除該模具，使得該第一 日曰A ^ °亥第一知塾顯4於该第—封膠體之開口，之後設置 第二曰曰片於该第一晶片之主動面上並電性連接該第二晶 至D亥第sa片之s亥第二銲塾，較佳地，可再形成一第二 封膠體於該第一晶片之主動面上，以密封該第二晶片。 【實施方式】 參閱所附圖式，本發明將列舉以下之實施例說明。 依本發明之第一具體實施例，一種多晶片堆疊封裝構 造之製造方法，請參閱第1A圖，提供一第一晶片11〇，該 第一/晶片110係具有一主動面lu及一背面112，該主動面 111係形成有複數個第一銲墊丨13與至少一第二銲墊i 14 ; 請再參閱第1 B圖，利用一黏晶層丨20將該第一晶片i丨〇設置 於一基板130，該基板13 0係具有一上表面131及一下表面 1 3 2 ’该上表面1 31係形成有複數個連接塾1 3 3，該下表面 1 3 2形成有複數個接球墊1 3 4，再以複數個第一銲線14 〇連 接該第一晶片11 〇之該些第一銲墊1丨3與該基板丨3 〇之該些 連接墊1 3 3 ;請再參閱第1 C圖，以一模具2 〇 〇形成一第γ封 膠體1 5 0 ’該第一封膠體1 5 0係密封該第一晶片1 1 〇之該些1236744 V. Description of the invention (3) A method for manufacturing a multi-chip stacked package structure according to the present invention, including the step of moving the first chip to have an active surface and a -back surface, the plurality of first solder pads and at least- The second welding pad, followed by a $ / $ Μ wafer on a substrate, and the first port is connected with a plurality of first bonding wires: a solder pad and the substrate are formed again with a mold-have-open for two days :? The colloid 'the first-sealing system seals the f' pads of the first wafer and the first bonding wires, and then removes the mold, so that the first day is called A ^ ° ° The first-sealing colloid is opened, and then a second wafer is set on the active surface of the first wafer and electrically connects the second crystal to the second solder joint of the first wafer, preferably, A second sealant can be formed on the active surface of the first wafer to seal the second wafer. [Embodiment] With reference to the drawings, the present invention will be described by the following embodiments. According to a first embodiment of the present invention, a method for manufacturing a multi-chip stacked package structure is provided in FIG. 1A. A first chip 110 is provided. The first / chip 110 has an active surface lu and a back surface 112. The active surface 111 is formed with a plurality of first bonding pads 13 and at least one second bonding pad i 14; please refer to FIG. 1B again, and use a sticky crystal layer 20 to set the first wafer i 1. On a substrate 130, the substrate 130 has an upper surface 131 and a lower surface 1 3 2 'The upper surface 1 31 is formed with a plurality of connections 塾 1 3 3, and the lower surface 1 3 2 is formed with a plurality of catch balls Pads 1 3 4 and then a plurality of first bonding wires 14 〇 to connect the first bonding pads 1 丨 3 of the first wafer 11 〇 and the connection pads 1 3 3 of the substrate 丨 3; please refer to again In FIG. 1C, a first sealing compound 150 is formed with a mold 200. The first sealing compound 150 is used to seal the first wafer 1 1 0.

睡 第11頁 1236744 、發明說明（4) 第麵*墊11 3與該些第一録線1 3 0，而不覆蓋該第一晶片 11 〇之該第二銲墊丨丨4，較佳地，在本實施例中，係以一離 形膜210形成在該模具2〇〇與該第一晶片11〇之主動面111之 間’以覆蓋該第二銲墊1 14，該離形膜210係可使該模具 2〇〇在形成該第一封膠體15〇後容易脫模與防止該模具2〇() 壓傷該第一晶片1丨〇之主動面i丨i ;請再參閱第丨D圖，移除 該模具200與該離形膜21〇，使得該第一封膠體15〇係具有 一開口151，且該第一晶片110之該第二銲墊114顯露於該 第一封膠體1 50之該開口 151 ;請再參閱第ιέ圖，利用一測 試裝置300接觸該基板130之該些接球墊134，以測試該第 一晶片11 0 ,其係確認該第一晶片i i 〇在經過上述之製程 後，疋否為良品，如為良品則繼續下列步驟；請再參閱第 1F圖’堆疊設置一第二晶片16〇於該第一晶片u〇之主動面 111上’並以至少一第二銲線1 7 〇電性連接該第二晶片1 6 〇 至該第一晶片110之該第二銲墊114 ;請再參閱第1G圖，形 成一第一封膠體180於該第一晶片11〇之主動面hi上，以 密封該第二晶片1 60與該第二銲線1 70，該第二封膠體1 80 係可覆蓋至該第一封膠體15〇之上；請再參閱第丨^圖，植 接複數個銲球1 9 0於該基板1 3 0之該些接球墊1 3 4，以完成 該多晶片堆疊封裝構造。 因此’本發明係利用該模具2〇〇形成該具有該開口 151 之第一封膠體1 50，再移除該模具2 〇〇與該離形膜21〇之 後’使得該第一晶片11 〇之第二銲墊丨丨4顯露於該第一封膠 體1 50之該開口 1 51，且在堆疊設置該第二晶片1 6〇後，電Sleep on page 111236744, description of the invention (4) the first surface * pad 11 3 and the first recording wires 1 3 0, without covering the second pad 丨 4 of the first wafer 11 〇, preferably In this embodiment, a release film 210 is formed between the mold 200 and the active surface 111 of the first wafer 110 to cover the second pads 14 and the release film 210. It can make the mold 200 easy to demold after forming the first sealant 150 and prevent the mold 200 () from crushing the active surface i 丨 i of the first wafer 1 丨 i; please refer to section 丨 again Figure D, the mold 200 and the release film 21 are removed, so that the first sealant 150 has an opening 151, and the second pad 114 of the first wafer 110 is exposed in the first sealant The opening 151 of 1 50; please refer to the figure again, using a test device 300 to contact the ball receiving pads 134 of the substrate 130 to test the first wafer 11 0, which confirms that the first wafer ii 〇 After the above process, whether it is a good product, if it is a good product, continue with the following steps; please refer to FIG. 1F again to set a second chip 16 on the first chip u. On the active surface 111 and electrically connect the second wafer 160 to the second pad 114 of the first wafer 110 with at least one second bonding wire 170; please refer to FIG. 1G again to form a first A piece of colloid 180 is on the active surface hi of the first wafer 11 to seal the second wafer 1 60 and the second bonding wire 1 70. The second sealing colloid 1 80 can cover the first sealing colloid. Above 150; please refer to FIG. ^^ again, a plurality of solder balls 190 are implanted on the substrates 130 and the ball receiving pads 134 to complete the multi-chip stacked package structure. Therefore, 'the present invention uses the mold 200 to form the first sealant 150 having the opening 151, and then removes the mold 2000 and the release film 21' to make the first wafer 11 The second pad 丨 丨 4 is exposed in the opening 151 of the first sealant 150, and after the second wafer 160 is stacked, the

第12頁 1236744 五、發明說明 =連接該第二晶片16〇與該第一晶片110之該第二銲塾 疊嘹二達笛到多晶片二疊封裝之功效，此外，本發明在堆 义》置该第二晶片160於該第一晶片U〇之主動面m ^係先測試該第一晶片11 G，確認經過該第—封腺_ j ζ Λ 局部封桊夕赞 B y 1 1 η 4 封膠體150 設置於ϊΐ 良品’才將該第二晶片16〇堆疊 片160;Λ 晶片110之主動面111 ’並電性連接該第二晶 片堆義H一晶片110之第二輝塾114，以達到提昇多晶 月堆疊封裝構造之良率。 造之ΐΐ::之實施例，一種多晶片堆疊封裝構 =方法，睛參閱第2Α圖，提供一第一晶片41〇，該 第一晶片410係具有一主動面411及一背面412，該主動面 4^1係形成有複數個第一銲墊413與複數個第二銲墊414 ·， 請再參閱第2B圖，設置該第一晶片410於一基板42〇，再以 複數個第一銲線43 0連接該第一晶片41〇之第一銲墊413與 該基板420 ;請再參閱第2C圖，形成一第一封膠體440，該 第一封膠體4 4 0係密封該第一晶片4 1 〇之該些第一銲墊4 14 與該些第一銲線43 0，該第一封膠體440係具有一開口 4 41 ’以顯露該第一晶片41 0之該些第二桿墊41 4 ;請再參 閱第2D圖，堆疊設置一第二晶片450於該第一晶片410之主 動面41 1上並電性連接該第二晶片45〇至該第一晶片41〇之 該第二銲墊4 1 4，在本實施例中，該第二晶片450之一主動 面451係形成有複數個凸塊452，該第二晶片450係以該些 凸塊4 5 2覆晶接合於該第一晶片4 1 〇之該些第二銲墊414 ; 請再參閱第2E圖，形成〆第二封膠體4 60於該第一晶片410Page 121236744 V. Description of the invention = the effect of connecting the second solder pad stack of the second chip 160 to the first wafer 110 to the multi-chip two-stack package. In addition, the present invention Placing the second wafer 160 on the active surface m ^ of the first wafer U 0 first tests the first wafer 11 G to confirm that it passes through the first-gland _ j ζ Λ partly sealed Xi Zan B y 1 1 η 4 The sealing compound 150 is set on the “good product” before stacking the second wafer 160, and the active surface 111 of the wafer 110 is electrically connected to the second wafer 114 of the second wafer stack H and the wafer 110. To improve the yield of polycrystalline moon stacked package structure. Ϊ́ΐ 之 :: An embodiment, a multi-chip stacked package structure method, referring to FIG. 2A, providing a first chip 410, the first chip 410 has an active surface 411 and a back surface 412, the active The surface 4 ^ 1 is formed with a plurality of first pads 413 and a plurality of second pads 414. Please refer to FIG. 2B again, set the first wafer 410 on a substrate 42, and then use a plurality of first pads. The line 43 0 connects the first pad 413 of the first wafer 4 10 and the substrate 420; please refer to FIG. 2C again to form a first sealant 440. The first sealant 4 4 0 seals the first wafer. The first bonding pads 4 14 and the first bonding wires 43 0, the first sealing body 440 has an opening 4 41 ′ to expose the second rod pads of the first wafer 41 0. 41 4; Please refer to FIG. 2D again. A second chip 450 is stacked on the active surface 41 1 of the first chip 410 and is electrically connected to the second chip 450 and the second chip 450. Pads 4 1 4. In this embodiment, a plurality of bumps 452 are formed on one of the active surfaces 451 of the second wafer 450. The second wafer 450 uses the bumps 4. 5 2 flip-chips are bonded to the second pads 414 of the first wafer 4 1 0; please refer to FIG. 2E again to form a second sealant 4 60 on the first wafer 410

第13頁 1236744_ 五、發明說明（6) 之主動面411上，以密封該第二晶片450之主動面451及該 些凸塊452。 本發明之保護範圍當視後附之申請專利範圍所界定者 為準，任何熟知此項技藝者，在不脫離本發明之精神和範 圍内所作之任何變化與修改，均屬於本發明之保護範圍。Page 13 1236744_ 5. The active surface 411 of the invention description (6) seals the active surface 451 of the second wafer 450 and the bumps 452. The protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. .

第14頁 1236744 圖式簡單說明 【圖式簡單說明】 第1 A至1Η圖：依本發明之第一實施一夕 裝構造之製造方法，一第一曰M i… 種夕晶片堆疊封 圖；及 “曰片在製造過程中之截面示意 第2A至2E圖：依本發明之第二實 一 裝構造之製造方法，一第一曰片 種夕日曰片 圖。 元件符號簡單說明 . 110 第一晶片 111 主動面 113 第一銲墊 114 第二銲墊 120 黏晶層 130 基板 131 上表面 133 連接墊 134 接球墊 140 第一銲線 150 第一封膠體 151 開口 160 第二晶片 170 第二銲線 180 第二封膠體 190 鲜球 200 模具 210 離形膜 300 測試裝置 410 第一晶片 411 主動面 413 第一銲墊 414 第二銲墊 堆疊封 112背面 132下表面 41 2背面 <1Page 14 1267444 Brief description of the drawings [Simplified description of the drawings] Figures 1 A to 1: The manufacturing method of the first embodiment of the invention according to the first embodiment of the present invention. And "The cross-section of the Japanese film in the manufacturing process is schematically shown in Figures 2A to 2E: according to the manufacturing method of the second real assembly structure of the present invention, a first-day film and a Japanese-style film chart. Element symbols are simply explained. 110 first Wafer 111 Active surface 113 First solder pad 114 Second solder pad 120 Cryptolayer 130 Substrate 131 Upper surface 133 Connection pad 134 Ball contact pad 140 First bonding wire 150 First gel 151 Opening 160 Second wafer 170 Second solder Line 180 Second sealant 190 Fresh ball 200 Mold 210 Release film 300 Test device 410 First wafer 411 Active surface 413 First pad 414 Second pad stack seal 112 Back surface 132 Lower surface 41 2 Back surface < 1

第15頁 1236744 圖式簡單說明 420 基板 430 第一銲線 440 第一封膠體 441 開口 450 第二晶片 451 主動面 4 5 2 凸塊 460 第二封膠體 « Φ _臓 第16頁Page 15 1236744 Brief description of the drawing 420 Substrate 430 First bonding wire 440 First colloid 441 Opening 450 Second wafer 451 Active surface 4 5 2 Bump 460 Second encapsulation «Φ _ 臓 Page 16

Claims (1)

1236744 六、申請專利範圍 【申睛專利範圍 1、 一種多晶 提供一第 面，該主動面 墊； 設置該第 該第一晶片之 以一模具 第一晶片之該 係形成在該模 二銲墊； 移除該模 口以顯露該第 設置一第 该第二晶片至 2、 如申請專 製造方法，在 步驟之前，其 3、 如申請專 製造方法，其 第一晶片之該 ，> 4、 如申請專利範圍第3項所述之多晶 製造方法，其另包含：形成一第二封膠體於^裝 主動面上，用以密封該第二晶片與該第二銲線。曰曰月 二，f封巢構造之製造方法，包含： ,曰片 °亥第一晶片係具有一主動面及 係形成有複數個第一銲墊與至少 背 第二鲜 一晶片於一基板，並以複數個 該些第一銲墊與該基板； -第-封膠體，該第一封膠體係密封該 些第一銲墊與該些第一銲線，其中一離形膜 具與該第-晶片之主動面之間’卩覆蓋該第 具與該離形膜，以使該襄、二封膠 二銲墊；及 : 〃 $ 间 2片Π第一晶片之主動面上並電性連接 该第一晶片之該第二銲墊。 利範圍第1項所述之多晶片堆疊封 之 设置該第二晶片於該第一晶片之 另包含：測試該第一晶片。 面上 第1項所述之多晶片堆疊封裝構造之 :該第二晶片係以至少一第二】 第二銲墊。 &任玉 銲線連接1236744 6. Scope of patent application [Scope of Shenyan patent 1. A polycrystal provides a first surface and the active surface pad; the first wafer is provided with a mold and the first wafer is formed on the second solder pad of the mold ; Remove the die to reveal the first set of the second wafer to 2. If applying for a special manufacturing method, before step 3, if applying for a special manufacturing method, the first wafer, > 4, The method for manufacturing polycrystalline silicon according to item 3 of the scope of patent application, further comprising: forming a second sealing gel on the mounting active surface for sealing the second wafer and the second bonding wire. The manufacturing method of the f-sealing structure includes: The first wafer has an active surface and is formed with a plurality of first pads and at least a second wafer on a substrate. And a plurality of the first bonding pads and the substrate;-a first sealing compound, the first sealing system seals the first bonding pads and the first bonding wires, wherein a release film is connected with the first bonding pads; -Between the active surfaces of the chip '卩 cover the first device and the release film, so that the two sealing pads and two bonding pads are; and The second pad of the first wafer. The multi-wafer stacked package described in item 1 of the present invention. Setting the second wafer on the first wafer further includes: testing the first wafer. The multi-chip stacked package structure described in item 1 above: The second chip is at least one second] second bonding pad. & Ren Yu Wire Bonding 12367441236744 六、申請專利範圍 5、 如申請專利範圍第4項所述之多晶 製造方法，其中該第二封膠體係覆蓋 湩/裝構造之 上。 亥第一封膠體之 6、 如申請專利範圍第1項所述之多晶 製造方法’其中該第二晶片係覆晶接合於封f構造之 第二銲墊。 么°亥弟—晶片之該 7、 如申請專利範圍第6項所述之多晶片 製造方法，其另包含：形成―第二封膠_。: 主動面上與該第二晶片之間。 日日片之 8、 一種多晶片堆疊封裝構造之製造方法，勺人· 提供-第-晶片’該第一晶片係具有面 面，該主動面係形成有複數個第一銲墊 者 墊； 、土/ 弟二知 * ·; 片之 a曰 设置该第一晶片於一基板，並電性 該些第-銲墊與該基板； 以壓模形成一第一封膠體於該基板上，該第— 係=封該第-晶片之該些第一銲塾，該第一封膠真 一開口，以顯露該第二銲墊；及 係，、有 ^設置一第二晶片於該第一晶片之主動面上並電性連接 该第一晶片至該第一晶片之該第二銲墊。 二Ϊ:請ί利範圍第8項所述之多晶片堆疊封裝構造之 製以方法，其另包含：形成一第二封膠體於該第一晶片之 主動面上，用以密封該第二晶片。 10、如申請專利範圍第g項所述之多晶片堆疊封裝構邊之6. Scope of patent application 5. The polycrystalline silicon manufacturing method as described in item 4 of the scope of patent application, wherein the second sealant system covers the top / mount structure. 6. The polycrystalline silicon manufacturing method according to item 1 of the scope of the patent application, wherein the second wafer is a flip-chip bonded to a second bonding pad having a sealed structure. Mo Haidi—the wafer 7. The multi-wafer manufacturing method as described in item 6 of the scope of patent application, which further includes: forming a “second sealant”. : Between the active surface and the second chip. No. 8 of Japan and Japan 8. A manufacturing method of a multi-chip stacked package structure, a person providing-a-chip-the first chip has a surface, and the active surface is formed with a plurality of first pads; Soil / Di Erzhi * ·; a means of setting the first wafer on a substrate, and electrically connecting the first pad and the substrate; forming a first sealant on the substrate by a stamper, the first — Is the first solder pads sealing the first wafer, the first sealant is really open to expose the second pad; and, there is an initiative to set a second wafer on the first wafer The first pad is electrically connected to the second pad of the first wafer on the surface. Second: Please refer to the method for manufacturing the multi-chip stacked package structure described in Item 8 and further includes: forming a second sealing gel on the active surface of the first chip to seal the second chip . 10. The edge of the multi-chip stacked package as described in item g of the patent application. 第18頁 1236744 六、申請專利範圍 製造方法，其中該第 上。 ’ u、如申請專利範圍 製造方法，在設置該 步驟之前，其另包含 I2、如申請專利範圍 製造方法，其中該第 第二鮮塾 〇 1 3、如申請專利範圍 之製造方法，其另包 之主動面上與該第二 14、一種多晶片堆疊Page 18 1236744 6. Scope of Patent Application Manufacturing method, of which the first. 'u. If a manufacturing method for a patented scope is applied, before this step is set, it additionally includes I2, such as a manufacturing method for a patented scope, where the second fresh 塾 03, such as a manufacturing method for a patented scope, which includes another package. The active surface is stacked with the second 14, a multi-chip 第 曰曰 片，其 係形成有複數個第 一基板，係供設 之该些第一鮮塾； 一以壓模形成之 该些第一銲墊，該第 一鲜塾；及 二封膠體係覆蓋至該第一封膠體之 第8項所述之多晶片堆疊封裝構造么 第二晶片於該第一晶片之主動面上！ :測試該第一晶片。 第8項所述之多晶片堆疊封裝構造之 二晶片係覆晶接合於該第—晶片之該 第1 2項所述之多晶片堆疊封裝構造 含：形成一第二封膠體於該第〜曰 晶片之間。 μ # 封裝構造，包含： 係具有一主動面及一背面，該主動面 銲墊與至少一第二銲墊； 置該第一晶片並電性連接該第—曰 ^ 日日/ΐ 第一封膠體，其係密封該第一晶片之 一封勝體係具有一開口，以顯露該第 第一晶片，其係設置於該第一晶片之主動面上 1 性連接至該第一晶片之該第二銲墊。 1=、如申請專利範圍第丨4項所述之多晶片堆疊封裝構 造，其中該第二晶片係以至少一第二銲線連接至該第一曰 ! < 曰曰 片之$玄第二鲜墊。The first film is formed with a plurality of first substrates for the first fresh rafters; one of the first solder pads formed by a stamper, the first fresh rafters; and two sealant systems Cover the multi-chip stacked package structure described in item 8 of the first sealant with the second chip on the active surface of the first chip! : Test the first wafer. The second chip of the multi-chip stacked package structure described in item 8 is a flip-chip bonded to the first chip. The multi-chip stacked package structure described in item 12 includes: forming a second sealing gel on the first ~ Between the wafers. μ # Package structure, which includes: an active surface and a back surface, the active surface pad and at least one second pad; the first chip is placed and electrically connected to the first — ^ 日 日 / ΐ first A colloid, which seals a first system of the first chip, has an opening to expose the first chip, which is disposed on the active surface of the first chip and is connected to the second chip of the first chip. Pads. 1 = The multi-chip stacked package structure as described in item 4 of the patent application scope, wherein the second chip is connected to the first with at least a second bonding wire! ≪ Fresh pad. 第19頁 1236744 六、申請專利範圍 1 6、如申請專利範圍第1 5 項所述之多晶片堆疊封裝構 造，其另包含有一第二封膠體，其係形成於該第一晶片之 主動面上，用以密封該第二晶片與該第二銲線。 1 7、如申請專利範圍第1 6 項所述之多晶片堆疊封裝構 造，其中該第二封膠體係覆蓋至該第一封膠體之上。 1 8、如申請專利範圍第1 4項所述之多晶片堆疊封裝構 造，其中該第二晶片係以覆晶接合於該第一晶片之該第二 銲塾。 1 9、如申請專利範圍第1 8項所述之多晶片堆疊封裝構 造，其另包含有一第二封膠體，其係形成於該第一晶片之 主動面上與該第二晶片之間。 2 0、如申請專利範圍第1 4項所述之多晶片堆疊封裝構 造，其另包含有複數個銲球，其係植接於該基板。Page 19, 1237644 VI. Patent application range 16 6. The multi-chip stacked package structure described in item 15 of the patent application range, which further includes a second sealing gel formed on the active surface of the first wafer To seal the second chip and the second bonding wire. 17. The multi-chip stacked package structure as described in item 16 of the scope of patent application, wherein the second sealant system covers the first sealant. 18. The multi-chip stacked package structure as described in item 14 of the scope of the patent application, wherein the second wafer is flip-chip bonded to the second solder pad of the first wafer. 19. The multi-chip stacked package structure described in item 18 of the scope of patent application, further comprising a second sealant formed between the active surface of the first chip and the second chip. 20. The multi-chip stacked package structure described in item 14 of the scope of patent application, further comprising a plurality of solder balls, which are implanted on the substrate. 第20頁Page 20
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US8110928B2 (en) 2007-10-05 2012-02-07 Advanced Semiconductor Engineering, Inc. Stacked-type chip package structure and method of fabricating the same
TWI383509B (en) * 2007-01-05 2013-01-21 Univ Chang Gung A method of stacking solar cells
TWI394236B (en) * 2006-12-28 2013-04-21 Stats Chippac Ltd Mountable integrated circuit package-in-package system with adhesive spacing structures
US10431513B2 (en) 2005-08-19 2019-10-01 Micron Technology, Inc. Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
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US10431513B2 (en) 2005-08-19 2019-10-01 Micron Technology, Inc. Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US11239128B2 (en) 2005-08-19 2022-02-01 Micron Technology, Inc. Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US10861824B2 (en) 2005-08-26 2020-12-08 Micron Technology, Inc. Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
TWI394236B (en) * 2006-12-28 2013-04-21 Stats Chippac Ltd Mountable integrated circuit package-in-package system with adhesive spacing structures
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US8110928B2 (en) 2007-10-05 2012-02-07 Advanced Semiconductor Engineering, Inc. Stacked-type chip package structure and method of fabricating the same

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