TWI250597B - Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips - Google Patents

Abstract

A method for multi-chip package is disclosed. A first chip is disposed on a chip carrier. A first chip adhesive layer is formed on an active surface of the first chip and exposes pads on the first chip. Then, a wire-bonding step is processed to electrically connect the pads on the first chip to the chip carrier through a plurality of first bonding wires. At least a second chip is provided with a second chip adhesive layer formed on backside of the second chip in wafer form. Utilizing picking and placing, the second chip is stacked on the first chip adhesive layer, and the second chip adhesive layer is combined with the first chip adhesive layer to seal portions of the first bonding wires above the active surface of the first chip. It could package a plurality of central pads chip and protect the first bonding wires.

Description

1250597

[Technical Field of the Invention] - A multi-chip package method, in particular, a central pad type multi-chip package method for a die bond layer. [Prior Art] A multi-chip package is a trend in integrated circuit packages in which a plurality of integrated circuit chips are stacked to increase the functionality of the package structure.

As shown in FIG. 1 , a conventional peripheral pad type multi-chip package structure includes a wafer carrier 1 , a first wafer 2 , a second wafer 30 , a plurality of bonding wires 4 , and a The first wafer 20 is disposed on one upper surface 11 of the wafer carrier 1 by an adhesive layer 7 , and the active surface 21 of the first wafer 20 is attached to the upper surface 11 of the wafer carrier 1 . An interposer 8 having a plurality of pads 22, such as a dummy wafer, a metal piece, etc., is formed on the active surface 21 of the first wafer 20 and the solder pads 2 2 are exposed. The second wafer 30 is disposed on the medium 8 ,, and the second wafer 3 includes a plurality of fresh slabs 3 2 formed on the periphery of the active surface 31 of the 4th wafer 310. The bonding wires 40 are the same The pads 22 of a wafer 20 and the pads 32 of the second wafer 30 are electrically connected to the wafer carrier 1 , respectively, and the encapsulant 50 is formed on the wafer carrier 10 to seal the first The wafer 20, the second wafer 3, and the bonding wires 40, the solder balls 60 are disposed on the lower surface of the wafer carrier 1 12 12 ° In the chip package structure, in order to prevent the bonding wires 40 connecting the first wafer 20 and the wafer carrier 10 from contacting the first wafer 2

Page 8 1250597 V. Inventive Note (2) or the second wafer 3 is damaged, the t dielectric 80 is disposed on the first wafer 2, and the supporting force is insufficient and the multi-chip package is caused. The package method described above cannot be applied to the wafer of the central pad, so the crystal to be stacked must be packaged, but the square of the crystal back is only limited to two layers, so the package structure is increased. Limitation. SUMMARY OF THE INVENTION The main object of the present invention is to provide a multi-chip package method for bonding wires, which is provided with a carrier, and then a first adhesive layer is formed at =, and a wire bonding step is performed to obtain a plurality of wires. a first wafer to the wafer carrier, and then taking a second wafer of the second adhesive layer to a portion of the first adhesive layer and the second adhesive layer; a portion of the active surface of the wafer; Avoid = to the first wafer or the first wafer can be damaged by the day, the type of wafer. The second wafer 3 of the 5th layer is thicker than that provided by the dielectric material 80. Therefore, if the wafer is stacked in the crystal back to the crystal back, the number of stacks of the wafer is functional. There is also a method of bonding a first wafer to a wafer of the first wafer and a back bonding layer on the first wafer, and actively bonding the first bonding wires to the first bonding wire. There is a first layer in the first contact layer to stack a plurality of central solder pads. The second object of the present invention is a multi-chip package structure of a bonding wire, and a fE body of the wafer stack, a The first chip system of the charm 曰m is set in a crystal > 骽 黏 黏 日 日 胶 胶 形成 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 第一 第一 第一 第一 第一 第一 ^ ^ ^ ^ ^ ^ ^ ^ a second wafer is disposed on the plurality of sorghums of the second 曰 塾 塾 塾 Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ

1250597 ------------- V. Description of the Invention (3) · - : The glue is formed on the back surface of the second wafer, wherein the first adhesive bond and the second adhesive The crystal glue layer jointly covers the portions of the first bonding wires on the active surface of the first crystal to reduce the overall thickness of the wafer stack, and the purpose of the wafer assembly. According to the present invention, a multi-chip package for bonding a bonding wire between wafer stacks includes a first wafer to a wafer carrier, and the first wafer surface is formed with a plurality of pads to form a first The adhesive layer is on the active surface of the ruthenium sheet, and the first adhesive layer reveals the solder dies, and the wire bonding step is electrically connected to the δ of the first wafer by a plurality of first bonding wires. Soldering the wafer carrier to the wafer carrier, providing at least one second wafer, the active surface of the first wafer is formed with a plurality of soldering pads, and the back surface of the second wafer is formed with a second adhesive layer. A second wafer is taken onto the first adhesive layer, and the first adhesive layer and the first bonding wire are coated on the active surface (2) of the first wafer. The first adhesive layer and the second adhesive layer protect the first bonding wires to prevent. The first solder wire is short-circuited due to contact with the first wafer or the second wafer. [Embodiment] Referring to the drawings, the present invention will be described by way of the following examples. According to a first embodiment of the present invention, a multi-chip packaging method, please refer to FIG. 2, firstly, a wafer carrier 11 is provided, which has an upper surface 111 and a lower surface 11 2, and the wafer carrier 110 is For a lead frame or a circuit substrate, in the embodiment, the wafer carrier 11 is a circuit substrate. Next, a first wafer 120 is disposed on the wafer carrier 11

1250597 V. Inventive Description (4) The upper surface 111, wherein the first wafer 120 is adhered to the wafer carrier 11 by a die bond 113, the first wafer 120 has an active surface 1 21 and The plurality of pads 122 formed on the active surface 121 are included in the center of the active surface 121 of the first wafer 120 in the present embodiment.

Referring to FIG. 2B, a first adhesive layer 130 is formed on the active surface 121 of the first wafer 120. The first adhesive layer 130 exposes the pads 122 of the first wafer 120. Preferably, the first adhesive layer 130 is selected from one of a low modulus of elasticity adhesive film or a B-stage cured adhesive. Then, a plurality of first bonding wires 40 are electrically connected to the pads 122 of the first wafer 12 to the wafer carrier 110 by a plurality of first bonding wires 40.

Referring to FIG. 2C, at least one second wafer 150 is provided, which has an active surface 151 and a back surface 152 and includes a plurality of pads 153 formed on the active surface 151. Preferably, the second wafer 15〇 The first wafer 12 is the same size as the first wafer 12, and the first wafer i 2 and the second wafer 15 can be a memory wafer. In the embodiment, the solder pads 153 of the second wafer i 50 are located at the center of the active surface 151 of the second wafer 150. A second adhesive layer 160 is formed on the back surface 152 of the second wafer 15. In the embodiment, the second adhesive layer 160 is formed on the second wafer cassette 50, preferably The second adhesive layer 丨 60 series may be a low modulus of elasticity adhesive film or a β-stage curing adhesive and formed on the wafer level second wafer 丨5〇. A second wafer 150 is taken onto the first adhesive layer 130, and a predetermined downward pressure is applied to the second wafer 150, so that the first adhesive layer 丨3〇 and the second adhesive layer

Page 11 1250597

The crystal layer 160 is closely adhered to and partially covers the portion of the first bonding wire HQ above the active surface 121 of the first wafer 120. In this embodiment, the back surface of the second three wafers 150 2 is not contacted by the first bonding wires 140 due to the barrier of the second adhesive. μ, please refer to FIG. 2D. In this embodiment, a wire bonding step is further performed to electrically connect the pads 153 of the second wafer 15 to the wafer by a plurality of second bonding wires 170. Vector i 10. Preferably, in the method of multi-chip packaging, an identical second wafer (not shown) can be taken onto the active surface 151 of the second wafer 150 to achieve an appropriate number. Wafer stacking, in this embodiment, after performing the wire bonding step, forming a colloid 180 to seal the first wafer 120, the second wafer 15 5, the first bonding wires 140, and The second bonding wires 170, in addition, after forming the sealing body 180, a plurality of solder balls 190 are disposed on a lower surface 11 2 of the wafer carrier 11 to form a multi-chip package structure! 0 〇. Referring to FIG. 3 , in the embodiment, when the second adhesive layer 1 60 is formed, the back surface of the wafer composed of the plurality of second wafers 150 is turned up to 1 ' The template 21 is disposed on the two sides of the back surface 152 to form a groove 211 at the back surface 152, and then fill the groove 21 1 with the squeegee 220, that is, Forming the second adhesive layer 160 by printing, and finally, singulating the wafer to form the second wafers 150. Further, refer to FIGS. 4 and 5, the first die bond The adhesive layer 13 is formed by attaching the active surface 1 21 of the first wafer 1 2 or the active surface 121 ′ of the first wafer 2 2 as a film. The way of the second chip (as shown in Figure 3), and finally,

Page 12 1250597 V. Description of the Invention (6) The second wafer 150 including the right process and the germanium-silicone layer 160 is disposed at the end of the process, and the second step is On the first wafer 120 (the upper portion V as shown in FIG. 2C can be ~ the second to the second line 14: the cladding and protection of the first wafer 1 60 and the first adhesive layer 1 30 and the second bonded crystal In the method of the multi-chip package described above, when the second wafer is attached to the second wafer, the first bonding wires 140 are coated by the second bonding layer. The adhesive layer 130 is coated with the second adhesive layer 16 , and the adhesive layer 13 is bonded to the second adhesive layer 16 , and the second wafer 15 is applied. With a little pressure, the first bonding wires 14 can be closely attached to each other without damaging the first bonding wires "Ο, the mouth, the wafer with the central bonding pad and preventing the first bonding wires 14 from contacting The first wafer 1 20 or the second wafer 15 〇. Further, at the exposed portion of the pads 122 of the first wafer i 2 , the second adhesive layer 16a 〇 a may be depressed Squeeze, and down And fixing the joints of the first bonding wires 14 and the pads 122 of the first die 120 to prevent the first and second wires 14 from being affected by the first adhesive layer 130 and The second adhesive layer 16 is extruded and removed. Please refer to FIG. 2D, which is formed by one of the above manufacturing methods.

The chip package structure 1 〇0, a first wafer 12 is disposed on an upper surface ill of a wafer carrier 110, the first wafer 120 has a "main" surface 121 and includes a plurality of forms formed on the active The solder pad 122 of the surface 121 is formed on the active surface 121 of the first die 120, and the first adhesive layer 130 exposes the first wafer 120. The pads 122, plural

Page 13 1250597____ V. Description of the Invention (7) The first bonding wire 140 is electrically connected to the pads 122 of the first wafer 120 and the wafer carrier 110. At least one second wafer 150 is disposed on the first adhesive layer 130. The second wafer 150 has an active surface 151 and a back surface 152 corresponding to the active surface 151. The second wafer 150 includes a plurality of pads 1 formed on the active surface 151. A second adhesive layer 160 is formed on the back surface 152 of the second wafer 150. The first adhesive layer 130 Cooperating with the second adhesive layer 16 6 to cover the portion of the first bonding wire 1 40 above the active surface 1 2 1 of the first wafer 110, in the embodiment, the multi-chip The package structure 100 includes a plurality of second bonding wires 170, a glue body 180, and a plurality of solder balls 190. The second bonding wires 170 are electrically connected to the pads 1 5 3 of the second wafer 150. To the wafer carrier 1 1 , the encapsulant 18 is formed on the wafer carrier 110 to seal the first wafer 120 ′ the first fresh line 140 , the second wafer 150 , and the second bonding wires 17〇, the solder balls are disposed on a lower surface 11 2 of the wafer carrier 11 to mount the multi-chip package structure 100 on other electronic devices. In the multi-chip package structure 100, a plurality of second wafers may be separately disposed on the second wafer 15 5 to enhance the functionality of the multi-chip package structure, and the first adhesive The layer 130 and the second adhesive layer 16 can not only fix the first bonding wires 14 but also have an insulating effect, thereby preventing the occurrence of electrical interference, and using the elastic one. A layer of adhesive layer 130 and the second layer of adhesive layer 16 are inter-wafers, which can reduce the volume of the multi-chip package 100 to obtain a larger package package product with smaller size. The scope of the present invention is defined by the scope of the appended claims, which is incorporated herein by reference. Any changes and modifications are within the scope of the invention. 1250597_ \® Simple Description '1' &"^ ' 1 I Schematic Description 1 The i-th circle · Conventional multi-chip package edge t-plane schematic circle; 2A to 2D diagram · According to the invention An embodiment, a cross-sectional view of a multi-chip package structure for bonding a bonding wire between wafer stacks in a manufacturing process, FIG. 3: According to an embodiment of the present invention, the second adhesive layer is formed during formation FIG. 4 is a cross-sectional view showing a process of forming one of the first adhesive layers; and FIG. 5: the first die is formed according to an embodiment of the present invention. A schematic cross-sectional view of another formation process of the glue layer. Brief description of component symbols: 10 wafer carrier 11 20 first wafer 21 30 second wafer 31 40 front 50 70 adhesive 80 100 multi-chip package structure 110 wafer carrier 111 113 adhesive 120 first wafer 121 130 first die Adhesive layer 140 first bonding wire 150 second wafer 151 upper surface 12 lower surface active surface 22 soldering active surface 32 pad sealing body 60 solder ball interposer upper surface 112 lower surface active surface 122 pad active surface 152 back

Page 16 1250597_ Brief description of the diagram 153 Pad 220 Scraper 160 Second adhesive layer 170 Second wire 180 Sealant 1 9 0 Solder ball 210 template

Claims (1)

1250597 Scope of application for patents [Scope of application for patent application] 1. A multi-chip package method comprising: disposing a first wafer to a wafer carrier, wherein an active surface of the first wafer is formed with a plurality of pads; forming a first paste a layer of the adhesive layer on the active surface of the first wafer, the first adhesive layer revealing the solder pads; performing a wire bonding step of electrically connecting the first wafer by a plurality of first bonding wires a pad to the wafer carrier; providing at least one second wafer, the active surface of the second wafer is formed with a plurality of pads, and a second adhesive layer is formed on the back surface of the second wafer; a second wafer is disposed on the first adhesive layer, and the first adhesive layer and the second adhesive layer jointly cover the portions of the first zinc lines above the active surface of the first wafer . The third, the fourth, the central. The multi-chip packaging method of claim 1, wherein the two adhesive layer is formed on the second wafer by a wafer level. The multi-chip packaging method of claim 1, wherein the pads of a wafer are located in the center of the active surface of the first wafer. The multi-chip packaging method according to claim 1 or 3, wherein the pads of the second wafer are located in the active surface of the second wafer, such as: the multi-wafer described in the item of the patent of the month The package method, a wafer and the second wafer are of the same size. The multi-chip packaging method according to claim 1, wherein Page 18 1250597 The first wafer and the second wafer are memory chips. 7. The multi-chip packaging method of claim 1, comprising: repeatedly picking up another second wafer to the active surface of the second wafer to package an appropriate number of wafer stacks. 8. The multi-chip packaging method according to claim 1, wherein the back surface of the second wafer does not touch the first bonding wires. 9. The multi-chip encapsulation method as described in claim 1, wherein the first adhesive layer is selected from one of a low modulus of elasticity adhesive phase stage curing adhesive. /犋 and B-stage (B-10, multi-chip sealing as described in claim 1 or 9) wherein the second adhesive layer is selected from a low elastic modulus (three) mounting method, One of the B-stage curing adhesives. 11. The multi-chip package according to claim 1, wherein the first adhesive layer is formed by printing. The multi-wafer sealing of the first adhesive layer is attached to the first crystal t, wherein t is a multi-chip package as described in claim i. The method for forming the first adhesive layer is a printing process. / /, wherein the polycrystalline 1 : J crystal layer is as attached to the ' ί: The first-to-second wafer to 4 ί;::= method is taken, and the first-line step is performed, and after the plurality of second strips are replaced by 4, the pads are applied to the wafer carrier. Connected to the second chip Page 19 VI. Application for Patent Range 1 6. If the application specifically includes: The first line. 17. If included: another 18, such as the wafer 19, such as the wafer 20, one in the set of wafers, the application is dedicated to forming the surface. The application for the special carrier is the application of the carrier. The second wafer is the second wafer. The second wafer is in the range of the first 16 gel. The first range is the one of the lead frame. After the line, forming a colloid, and further sealing, the first bonding wires and the multi-chip packaging method described in the second item, setting a plurality of solder balls to the multi-wafer described in the wafer carrier item a packaging method, wherein: a circuit substrate: the multi-chip package method, wherein a multi-chip package constructs a wafer carrier; a first wafer having an active surface and comprising a plurality of first adhesive layers The plurality of first bonding wires exposing the first wafer are padded to the wafer carrier; eight, comprising: being disposed on the wafer carrier, the first wafer being a solder fillet formed on the active surface; Forming on the active surface of the first wafer and soldering; electrically connecting the solder pads of the first wafer to the first wafer; the first surface is disposed on the first surface; the active surface and the active surface -Back,;: 曰曰二匕3 a plurality of solder pads formed on the active surface; and an I bismuth adhesive layer formed on the back surface of the second wafer, wherein a viscous adhesive layer and the second viscous adhesive layer are co-coated The first 1250597 s. Patent application: a multi-chip package structure as described in the second aspect of the first wafer, wherein the second adhesive layer is a wafer. A stage is formed on the second wafer. The multi-chip package structure of claim 2, wherein the pads of the first wafer are located on the active surface of the first wafer. The multi-chip package structure of the present invention, wherein the pads of the first first die are located on the main surface of the second wafer, and the other of them is 24, as claimed in the patent application. The first wafer and the second wafer are of the same size in the multi-wafer package described in the above item, wherein: 25: the first wafer of the multi-wafer package according to the second aspect of the patent application and the first wafer The second wafer is a memory wafer. 2 is set in the multi-chip package structure described in claim 20 of the Patent Application No. 20, and another second surface is disposed on the active surface of the first wafer of 5 hai. Pick up the right number of wafer stacks. 1 In the multi-chip package structure described in Item 2 of the second paragraph, the first day of the film is not pressed against a 2 28, as described in claim 20 of the patent scope. . The smectic layer is selected from the group consisting of a low $ a bismuth sheet and a f-type structure of a 3 (B-stage) cured glue. The coefficient of the adhesive b 曰 film and the B-order 4 29, as in the scope of the patent application No. 2 or 28 5, wherein the first - 曰瞅 曰瞅 、 、 斤 斤 斤 日 日 日 日 日 封装 ( ( ( ( ( ( ( Phase) of the two-dimensional elastic modulus of the cured adhesive 1250597 Patent Application No. 30, as claimed in the second section, includes a plurality of second bonding wires, 苴# described in a multi-chip package structure,; _ 塾The blush 31 electrically connected to the wafer carrier 、 /, the second wafer, as in the third aspect of the patent application, includes a sealant, which is used to seal the multi-chip package structure of the employee, two pieces You are in the first chip, the first wire and the second wire. The film 32 is a wire carrier as described in the second paragraph of the patent application. The f-package test of the multi-chip package described in claim 2 is a circuit substrate. 34. The multi-chip package structure as described in claim 3rd. A plurality of solder balls are included, which are disposed on the other surface of the wafer carrier and have another 22nd page