200532873 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於一種包含有晶圓切割之多晶片堆疊封 裝製程’特別係有關於一種多晶片同尺寸堆疊之封裝製 程0 【先前技術】 習知多晶片堆疊封裝係將複數個相同尺寸之半導體晶 片逐一往上堆疊在一基板上，並且該些半導體晶片之主動 面係朝上’以利打線，而以打線形成之銲線係電性連接該 些晶片至該基板，如美國專利第5, 323, 〇6〇號所揭示之技 f ’為了防止該些銲線被上方堆疊之晶片壓迫，在晶片與 晶片之間應提供有一間隔材料（spacer)，該間隔材料之高 度係需高於同一層銲線之弧高，此一間隔材料習知地可以 是聚亞醯胺膠帶（PI tape)、虛晶片（du_y chip)、金屬 plate)等等，在打線之前該間隔材料係預先黏 在下方晶片之主動面，但此一間隔材料之尺寸係必須小 :下方晶片之主動面，以顯露於下方晶片之銲墊，方可使 線形成，但因此係造成該間隔材料對於上方晶片 J其周邊之打線支撐力不足，且上方晶片的厚度亦無法薄 U此該多晶片堆疊封裝具有相當厚度之晶片與間隔材 Π = = 手段，故在一預定封裝厚度内可供堆疊 <晶片數量為有限。 睛參閱第1圖’目前常用的多晶Ηπ . π〜r A 夕日日片同尺寸堆疊封裝構 在一預疋封裝厚度内係包含有一第一晶 、一 晶片20及一基板30，該第一晶片j 〇之— 仫 一 序面1 2係黏貼在該 200532873 五、發明說明（2) 基板30之一上表面31，該第一 θΚΐη 形成有複數個銲塾13，一如卢曰—主動面11周邊係 兮第一曰η 1 η夕士 ι 如虛日日片之間隔材料5〇係貼設於 4第 曰曰片1 0之主動面1 1而不覆蓋兮此# * ! 9 個打線形成之銲線40連接該第墊13 ’再以複數 Qn夕ρ主二w ^ ^ ^曰日片10之鋒塾23至該基板 30之上表面31 ’该間隔材料5()係高於該些銲㈣ 咼，且在該間隔材料50係形成有—黏著層Η，以該 一晶片1 0與該第二晶片2 〇，此夕卜，— ^ ^ 丄山，， 日日乃z u，此外，母一銲線40係具有一紝 球鈿41及一線尾端42，習知該些結球端“係形 : 片10之該些銲墊13上，哕此魂厘媸B〆 ’、7成；第 曰曰 ,.^Q1 » "二線尾鳊42係形成於該基板30之 上表面31，该間隔材料5〇係具有相當之 該些銲線40之弧高；該第-晶片？n夕 ^ 便具间於 弟一日日片20之一背面22係黏貼於該 間隔材料50，習知該第二晶片2〇之複數個鲜塾⑴系鱼第一 曰y 10相同地形成在該主動面21之周&，並以複數個鲜線 60連接该些銲墊23至該基板3〇之上表面“，由於該第二晶 片20在孩些銲墊23之形成區域未能得到該間隔材料5〇之充 伤支撐因此，戎第二晶片2 0係具有相當之厚度，以避免 在打線形成該些銲線60時造成該第二晶片2〇斷折，以防止 打線連接失敗之問題，該第一晶片j 〇與該第二晶片2 〇在堆 疊與電性連接之後習知地其係以一封膠體3 〇密封，故在一 預定封裝厚度内可供堆疊之晶片數量為有限。 我國專利公告第563900號「通用晶片規格之晶片堆疊 封裝」揭露有另一種習知之多晶片堆疊封裝構造，其係以 一第一晶片堆疊在一基板上與並以銲線連接，一間隔層係 完全覆蓋於該第一晶片之主動面固定該銲線之一端（結球200532873 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a multi-chip stacked packaging process including wafer dicing, and particularly to a multi-chip stacked packaging process of the same size. 0 [Previous technology The conventional multi-chip stacked package is a method of stacking a plurality of semiconductor wafers of the same size on a substrate one by one, and the active side of the semiconductor wafers is facing up to facilitate wiring, and the bonding wires formed by wiring are electrically conductive. To connect the wafers to the substrate, as disclosed in U.S. Patent No. 5,323,060, f 'In order to prevent the bonding wires from being pressed by the wafers stacked above, a spacer material should be provided between the wafers and the wafers. (Spacer), the height of the spacer material needs to be higher than the arc height of the welding wire of the same layer. This spacer material can be conventionally made of PI tape, du_y chip, and metal plate. Wait, the spacer material is pre-adhered to the active surface of the lower wafer before wiring, but the size of this spacer material must be small: the active surface of the lower wafer to be exposed to the lower The bonding pads of the wafers can form the wires, but this causes the spacing material to support the upper wafer J and its surroundings with insufficient wire support, and the thickness of the upper wafers cannot be thin. The multi-chip stacked package has a relatively thick wafer. With the spacer Π == means, the number of wafers available for stacking within a predetermined package thickness is limited. Please refer to Figure 1 for the currently used polycrystalline Ηπ. Π ~ r A The same size stacked package of the sun and the sun is packaged in a pre-packaged package thickness including a first crystal, a wafer 20 and a substrate 30. The first The wafer j 〇 之 — the first sequence surface 12 is adhered to the 200532873. V. Description of the invention (2) One of the upper surfaces 31 of the substrate 30. The first θΚΐη is formed with a plurality of solder pads 13, as in Lu Yue—active surface 11 The surrounding area is the first η 1 η Xi Shi I The spacer material such as the virtual sun and the daily film 50 is attached to the active surface 1 of the 4th day film 1 0 without covering the XI # *! 9 lines The formed bonding wire 40 is connected to the first pad 13 ', and then the plurality of Qn and the main two w ^^^^ is the front edge 23 of the solar panel 10 to the upper surface 31 of the substrate 30. The spacer material 5 () is higher than the These welding pads 咼, and an adhesive layer 形成 are formed on the spacer material 50, with the one wafer 10 and the second wafer 20, and then, ^ ^ 丄 山, 日 日 乃 zu, and The mother-bond wire 40 has a ball ball 41 and a wire tail end 42. It is known that the ball-end ends are "shaped: on the pads 13 of the sheet 10," B 魂 ', 7 ^ Q1 »^ Q1» " Two-line tail fins 42 are formed on the upper surface 31 of the substrate 30, the spacer material 50 is equivalent to the arc height of the bonding wires 40; the first-wafer? On the evening, one of the two pieces of the one-day piece 20 of the toilet is adhered to the spacer material 50, and it is known that a plurality of fresh sturgeon fishes of the second wafer 20 are formed in the same manner as y 10. The periphery of the active surface 21 is connected to the upper surface of the substrate 30 with a plurality of fresh wires 60. Because the second chip 20 cannot be obtained in the area where the pads 23 are formed, The filling support of the spacer material 50 is therefore, the second wafer 20 has a considerable thickness to avoid breaking the second wafer 20 when the bonding wires 60 are formed by wire bonding, so as to prevent the connection failure of the wire bonding. Problem, the first wafer j 〇 and the second wafer 20 are conventionally sealed with a gel 30 after stacking and electrical connection, so the number of wafers that can be stacked within a predetermined package thickness is limited . China Patent Bulletin No. 563900 "Universal Chip Specification Chip Stack Package" discloses another conventional multi-chip stack package structure, which is a first chip stacked on a substrate and connected by bonding wires, and a spacer layer system Completely covers the active surface of the first chip and fixes one end of the bonding wire (knot ball
第8頁 200532873^ 五、發明說明（3) ^ )以減少發生沖線，習知銲線之結球端具有較強之結合 1度以為間隔層包覆該些銲線之結球端仍有可能由該些 銲線之線尾端發生沖線，此外，由於在每一次黏晶與打線 ^後，，要以印刷或塗佈方式重覆形成該間隔層，其係增 ^ ^疊晶步驟，且該間隔層之平坦度與厚度無法均勻控 " 並且在固化後該間隔層不具有黏性，必須在該間隔層 夕f表面額外黏貼一膠帶以供一第二晶片疊設，當堆疊越 ^曰曰片時，打線連接之銲墊位置與水平度越不容易被控 方此外，在已打線完成之晶片之主動面上以印刷或塗佈 二形^該間隔層，其形成該間隔層之治具（如網板）要避 主=些銲線，並且要形成該適當面積之間隔層於該晶片之 動面，有實施上之困難與不可被利用性。 【發明内容】 本發明之 之封裝製程， 晶片之背面， 形成有該半固 之—主動面， 之鐸塾，以降 而包覆該些銲 面’以取代習 料’故在預定 片’並且增進 依本發明 主要目的係在於提 脂係形 一半固化樹 在一晶圓切 供一種多晶片同 成於複數個在晶 尺寸堆疊 圓等級之 化樹脂之第 並且複數個 低之銲線弧 線之線尾端 知需要多道 封裝厚度内 該些銲線之 之多晶片同 割成複數個晶片之後，以其中一 晶片黏接一基板或一第二晶片 該些晶片 受熱熔融 成於該第一晶片之主動 間隔材 數量之晶 銲線之 高，且 ，而形 製程方 可簡化 線尾端 尺寸堆 線尾端係連接於 該半固化樹脂係 能形成之大厚度 步驟地堆叠更多 固定力。 疊之封裝製程， 主要包含 200532873 五、發明說明（4) 有：提供一半導體晶圓， 之晶片區域 樹脂於該晶 該主動面 形成一半固化 面 以形成同尺寸 一晶片之背面 之至少一第 與該第二晶 脂；接著，以該第一晶片 之上表面； 與該基板， ，該些結球 背面至一基板 接該第一晶片 端及一線尾端 線尾端係設於 晶片之半固化 主動面，其中 線之線尾端； 片與該基板， 端，該些結球 於該第二晶片 加熱熔融該半 與該第二晶片 其係具有多晶 之功效。 【實施方式】 參閱所附 依據本發 第2 A圖，首先 該第一晶片 該晶圓 内係形 圓之背 一晶片 片之背 之半固 接著， 其中每 端係設 之該些 樹脂黏接該第二晶 該半固化樹脂係受 接著，以複數個第 其中每一第二銲線 端係設於該基板之 之該些銲墊上，在 固化樹脂之後，以 ’以構成一多晶片 片堆疊、固定銲線 係具有一主動面及 <一背 成有複數個銲墊；接著， 面；接著，切割該晶圓， 與至少一第二晶片，該第 面分別形成有該半固化樹 化樹脂黏接該第一晶片之 以複數個第一銲線電性連 一第一銲線係具有一結球 於該基板之上表面，該些 録墊上；接著，以該第二 片之背面至該第一晶片之 熱熔融而包覆該些第一鲜 ，銲線電性連接該第二晶 係具有一結球端及一線尾 上表面，該些線尾端係設 重覆地打線、堆疊晶片與 一封膠體密封該第一晶片 同尺寸堆疊之封裝構造， 之線尾端與減少疊晶步驟 本發明將列舉以下之實施例說明。 明；多晶片同尺寸堆養之封裝製帛，請參閱 ^供-半導體晶smo，該晶圓UG係具有Page 8 200532873 ^ V. Description of the invention (3) ^) In order to reduce the occurrence of punching lines, it is known that the nodular ends of the welding wire have a strong combination of 1 degree, so it is still possible to cover the nodular ends of these welding wires as a spacer layer. Punching occurs at the end of the wire of these bonding wires. In addition, since the spacer layer is repeatedly formed by printing or coating after each sticking and wire bonding ^, it is an additional step of ^^ superimposed crystals, and The flatness and thickness of the spacer layer cannot be controlled uniformly. "After curing, the spacer layer does not have adhesiveness. An additional tape must be pasted on the surface of the spacer layer f for a second wafer to be stacked. In the case of filming, the more difficult it is to control the position and level of the soldered pads. In addition, the active surface of the wafer that has been wired is printed or coated with a two-shaped spacer layer, which forms the spacer layer. Fixtures (such as stencils) should avoid main wires, and it is necessary to form a spacer of the appropriate area on the moving surface of the wafer, which is difficult to implement and cannot be used. [Summary of the invention] In the packaging process of the present invention, the semi-solid-active surface is formed on the back of the chip, so as to cover the soldering surfaces to replace the conventional materials, so it is planned to be improved. The main purpose according to the present invention is to cut fat-cured half-cured trees on a wafer to provide a multi-wafer that is formed from the first and the plurality of low welding wire arc ends of a plurality of round resins stacked in crystal size. Knowing that multiple wafers of the bonding wires within multiple package thicknesses are cut into multiple wafers at the same time, one of the wafers is bonded to a substrate or a second wafer, and the wafers are heated and fused to the first wafer. The number of spacers is higher than that of the crystal bonding wire, and the forming process can simplify the size of the end of the wire. The end of the wire is connected to the semi-cured resin with a large thickness to form a stack of more fixing force. The package packaging process mainly includes 200532873. V. Description of the invention (4) There are: a semiconductor wafer is provided, and the wafer area resin forms a half-cured surface on the active surface of the wafer to form at least a first and a back surface of a wafer of the same size. The second crystal grease; then, the upper surface of the first wafer; and the substrate, the back of the nodule to a substrate connected to the first wafer end and a line tail end line tail end is provided on the semi-cured active of the wafer Surface, the end of the line of the line; the sheet and the substrate, the ends, the balls are heated and melted on the second wafer, the half and the second wafer are polycrystalline. [Embodiment] Referring to the attached figure 2A according to the present disclosure, firstly, the first wafer and the back of a wafer in the wafer are semi-fixed, and each end is attached with the resins. The second crystal and the semi-cured resin are received, and a plurality of each of the second bonding wire ends are arranged on the pads of the substrate. After the resin is cured, a 'to form a multi-chip chip stack is formed. The fixed bonding wire has an active surface and < a plurality of bonding pads formed on the back; then, a surface; then, the wafer is cut, and at least a second wafer, the first surface is respectively formed with the semi-cured tree A plurality of first bonding wires are electrically connected to the first wafer by resin, and a first bonding wire has a knot on the upper surface of the substrate and the recording pads. Then, the back of the second chip is connected to the first wafer. The first wafer is thermally melted to cover the first fresh wires, and the bonding wire is electrically connected to the second crystal system with a knot end and a wire tail upper surface. The wire tail ends are repeatedly wired, stacked wafers and a Sealing gel seals the first wafer with the same size stack The package structure, the wire tail end and the step of reducing the superposition of the chip. The present invention will be illustrated by the following examples. Ming; the packaging system of multi-chip stacking with the same size, please refer to ^ supply-semiconductor crystal smo, the wafer UG has
200532873 五、發明說明（5) 一主動面111及一背面112，該主動面1U之晶片區域内係 形成有複數個積體電路元件（圖未繪出）以及複數個銲螯 113 ’其中δ玄晶圓110之主動面ill係朝下放置於一晶圓載 台2 1 0，請參閱第2 Β圖，以一晶背研磨工具2 2 〇研磨該晶圓 11 0之背面11 2，可以使該晶圓11 〇之厚度例如到達6〜丄5 m i 1 (密耳，1 m i 1約等於2 5 · 4微米）之間。 接著’請參閱第2 C與2 D圖，形成一半固化樹脂丨2 2於 遠晶圓11 0之背面1 1 2，首先以旋塗（Sp i n c〇at丨ng)或印刷 方式藉由一塗膠工具230將一液態或膠稠態之未固化樹脂 121，如B-Stage樹脂，塗施在該晶圓11〇之背面丨12，請再· 參閱第2 D圖，在一烘烤裝置2 4 0或照射裝置之作用下，將 該未固化樹脂1 2 1部分聚合反應為一半固化樹脂1 2 2，該半 固化樹脂1 22在不同溫度下將呈現半固態膠片與黏稠糊 狀，該半固化樹脂1 2 2之厚度係以介於3〜8 m i 1為較佳。 接著，請參閱第2E圖，在該晶圓11 〇之背面11 2以一切 割膠帶250黏貼該半固化樹脂1 22，再進行切割該晶圓 110，請參閱第2F圖，以一切割刀具260切割該晶圓110， 以形成同尺寸之至少一第一晶片11 4與至少一第二晶片 11 5，在本實施例中，該晶圓11 〇係以切割成一第一晶片 114、一第二晶片1 1 5、一第三晶片1 1 6及一第四晶片11 7例· 舉之，而每一晶片之背面（包含該第一晶片11 4之背面1 1 2a 與該第二晶片11 5之背面11 2b)分別形成有該半固化樹脂 122a與122b，而每一晶片之主動面（包含該第一晶片114之 主動面11 la與該第二晶片11 5之主動面11 lb)分別形成有複200532873 V. Description of the invention (5) An active surface 111 and a back surface 112. A plurality of integrated circuit elements (not shown in the figure) and a plurality of soldering stubs 113 'are formed in the chip area of the active surface 1U. The active side ill of the wafer 110 is placed on a wafer stage 2 1 0 downward, please refer to FIG. 2B. A wafer back grinding tool 2 2 0 is used to grind the back surface 11 2 of the wafer 11 0. The thickness of the wafer 110 is, for example, 6 to 丄 5 mi 1 (mil, 1 mi 1 is approximately equal to 2 5 · 4 microns). Next, please refer to Figures 2C and 2D to form a semi-cured resin 丨 2 2 on the backside of the far wafer 1 1 1 1 2 and firstly apply it by spin coating (Sp inc〇at 丨 ng) or printing. The glue tool 230 applies a liquid or glue-like uncured resin 121, such as B-Stage resin, to the back surface of the wafer 11 and 12. Please refer to FIG. 2D again, in a baking device 2 Under the effect of 40 or irradiation device, the uncured resin 1 2 1 is partially polymerized into a half-cured resin 1 2 2. The semi-cured resin 1 22 will present a semi-solid film and a thick paste at different temperatures. The thickness of the cured resin 1 2 2 is preferably between 3 and 8 mi 1. Next, please refer to FIG. 2E. On the back surface 11 2 of the wafer 11 0, a dicing tape 250 is used to stick the semi-cured resin 1 22, and then the wafer 110 is cut. Please refer to FIG. 2F and a cutting tool 260. The wafer 110 is cut to form at least one first wafer 114 and at least one second wafer 115 of the same size. In this embodiment, the wafer 110 is cut into a first wafer 114 and a second wafer. Wafer 1 15, a third wafer 1 16 and a fourth wafer 11 7 · For example, the back of each wafer (including the back 1 1 2a of the first wafer 11 4 and the second wafer 11 5 The back surface 11 2b) is formed with the semi-cured resins 122a and 122b, respectively, and the active surfaces of each wafer (including the active surface 11a of the first wafer 114 and the active surface 11lb of the second wafer 115) are formed separately. You Fu
第11頁 200532873 五、發明說明（6) 數個銲墊1 1 3a與1 1 3b。當然在不同實施例中，一第一晶片 1 1 4及一第二晶片丨丨5亦可被分割自兩種不同之晶圓，而每 ή:曰曰Λ之背曰面係形成有該半固化樹脂。其中，第-晶片 …、第一 ΒΒ片115之尺寸大致相等，或第一晶片1 1 4略大 (小）於第二晶片1 1 5。 接著，請參閱第2G圖，以在該第一晶片114下方之 固化樹脂122a將該第一晶片114之背面U2a黏接至一基板 130之上表面131，該基板13〇係可為陶瓷、玻璃纖維^化 樹脂、聚亞醯胺材質之電路板，在本實施例中，該基板 130係為一種球格陣列封裝基板，在該基板13〇之上表面 131與下表面分別形成有連接墊132與接球墊（圖未繪出）， 此外，亦可以習知之黏膠或膠帶將該第一晶片丨14黏著設 置於該基板1 30。 接著，進行第一晶片114與該基板13〇之打線連接，在 本實施例中，在打線形成複數個第一銲線14〇之前，請參 閱第2H圖，在該第一晶片114之該些銲墊U3a上係形成有 複數個結線凸塊143(stud bump)，以利接合該些第一銲線 140之線尾端142 ;接著，請參閱第21圖，以該些第一銲線 1 4 0電性連接垓第一晶片丨丨4與該基板1 3 〇，其中該些第一Page 11 200532873 V. Description of the invention (6) Several pads 1 1 3a and 1 1 3b. Of course, in different embodiments, a first wafer 1 4 and a second wafer 5 can also be divided from two different wafers, and the price: the back surface of the Λ is formed with the half Cured resin. Among them, the size of the first wafer…, the first BB wafer 115 is approximately the same, or the first wafer 1 1 4 is slightly larger (smaller) than the second wafer 1 1 5. Next, referring to FIG. 2G, the back surface U2a of the first wafer 114 is adhered to the upper surface 131 of a substrate 130 by a curing resin 122a under the first wafer 114. The substrate 13 may be ceramic or glass. In the present embodiment, the substrate 130 is a ball grid array package substrate, and a connection pad 132 is formed on the upper surface 131 and the lower surface of the substrate 130. And the ball receiving pad (not shown in the figure), in addition, the first wafer 14 can be adhered to the substrate 1 30 by conventional adhesive or tape. Next, the first wafer 114 is wire-connected to the substrate 130. In this embodiment, before the wires are formed to form a plurality of first bonding wires 14o, please refer to FIG. 2H. A plurality of stud bumps 143 (stud bumps) are formed on the bonding pad U3a to facilitate joining the wire ends 142 of the first bonding wires 140; then, referring to FIG. 21, the first bonding wires 1 4 0 is electrically connected to the first chip 丨 4 and the substrate 1 3 〇, where the first
銲線140係具有一打線開始時形成之結球端141以及一打線 截斷時形成之線尾端丨42，該些結球端141係設於該基板 iy〇之上表面131，該些線尾端142係設於該第一晶片114之 銲墊11 3 a上，忒些第一銲線1 4 〇係為逆打形成而具有較低 之狐高。The bonding wire 140 has a ball end 141 formed at the beginning of a wire and a tail end 42 formed at the time of a wire cut. The ball ends 141 are provided on the upper surface 131 of the substrate iy〇, and the wire ends 142 The first bonding wires 114 are provided on the bonding pads 11 3 a of the first wafer 114, and the first bonding wires 1 4 0 are formed by reverse punching and have a lower fox height.
第12頁 200532873 五、發明說明（7) 接著，請參閱第2 J圖，以在該第二晶片1 1 5下方之半 固化樹脂122b黏接該第二晶片11 5之背面112b至該第一晶 片114之主動面1 1 la，其中該半固化樹脂122b係受熱熔融 而包復該些第一銲線1 /1 〇之線尾端1 4 2，在本實施例中，該Page 12 200532873 V. Description of the invention (7) Next, referring to FIG. 2J, the semi-cured resin 122b under the second wafer 1 1 5 is used to adhere the back 112b of the second wafer 11 5 to the first The active surface 1 1 1a of the wafer 114, wherein the semi-cured resin 122b is melted by heat to cover the wire ends 1 4 2 of the first bonding wires 1/1/10. In this embodiment, the
半固化樹脂122b受熱熔融之溫度係介於11〇〜150 °c，故在 單一疊晶步驟中，僅需要適當加熱，該半固化樹脂1 22b將 黏著該第一晶片114之主動面111a並包覆該些第一銲線140 之線尾端1 4 2，省卻習知在晶片堆疊與打線後之間隔材料 形成步驟，此外，該半固化樹脂丨22b係覆蓋該第一晶片 114之該些銲墊ii3a，且可全面覆蓋該第一晶片114之主動 面11 la，以對該第二晶片丨丨5提供良好之打線支撐，故第 二晶片11 5可具有較薄的厚度（例如可以薄到6〜1 5 m丨丨）。 較佳地，該半固化樹脂丨22b亦可以相當的薄，在本實施例 中’至少一該些第一銲線丨4 〇係可接觸至該第二晶片丨丨5之 背面112b。接著，請參閱第2K圖，以複數個第二銲線15〇 電性連接該第二晶片11 5與該基板1 3 〇，在該第二晶片1 1 5 之鲜塾11 3b亦可同樣地形成複數個結球凸塊丨53，以利該 些第二銲線150之線尾端152接合，而該些第二銲線150之 結球端151亦形成於該基板丨30之上表面131上；請參閱第3 圖’在重覆地打線、堆疊晶片與加熱熔融該半固化樹脂 122a與I22_b之後，以本實施例之封裝厚度，可以快速地再 堆疊上第二晶片11 6，以第三銲線i 6 〇連接該第三晶片i丄6 與該基板130，並可再堆疊上第四晶片117，以第四銲線 1 7 〇連接忒第四晶片11 7與該基板1 3 〇，最後，以一封膠體 200532873 五、發明說明（8) 1 8 0密封該第一晶片1 1 4、該第二晶片1 1 5、該第三晶片 1 16、該第四晶片1 17與該些第一銲線140、該些第二銲線 150、該些第三銲線160與該些第四銲線170，並使該些半 固化樹脂122a、122b同時固化成為個別之完全固化樹脂 1 23，以構成一多晶片同尺寸堆疊之封裝構造，達到堆疊 多數量之晶片、固定銲線之線尾端與減少疊晶步驟之功 效0 此外’本發明用以連接第一晶片丨丨4與該基板丨3〇之第 一銲線140，其可採用前述之逆打線法，亦可採用 Kulicke&Soffa 之前折式打線製程（F〇rward F〇lded L〇〇pThe temperature at which the semi-cured resin 122b is heated and melted is between 110 and 150 ° c. Therefore, in a single stacking step, only the appropriate heating is required. The semi-cured resin 1 22b will adhere to the active surface 111a of the first wafer 114 and wrap The wire ends 1 4 2 of the first bonding wires 140 are covered, eliminating the conventional step of forming spacer materials after the wafer stacking and wire bonding. In addition, the semi-cured resin 22b covers the bonding wires of the first wafer 114. Pad ii3a, and can fully cover the active surface 11 la of the first chip 114 to provide good wire support for the second chip 丨 5, so the second chip 11 5 can have a thinner thickness (for example, it can be as thin as 6 ~ 1 5 m 丨 丨). Preferably, the semi-cured resin 22b may also be relatively thin. In this embodiment, at least one of the first bonding wires 4o may be in contact with the back surface 112b of the second wafer 5b. Next, referring to FIG. 2K, the second wafer 115 and the substrate 13 are electrically connected by a plurality of second bonding wires 150. The same can be said for the fresh wafer 11 3b of the second wafer 1 15 Forming a plurality of nodular bumps 53 to facilitate the bonding of the tail ends 152 of the second bonding wires 150, and the nodular ends 151 of the second bonding wires 150 are also formed on the upper surface 131 of the substrate; Please refer to FIG. 3 'After repeatedly wiring, stacking the wafers and heating and melting the semi-cured resins 122a and I22_b, the second wafer 11 16 can be quickly stacked again with the package thickness of this embodiment, and the third soldering Line i 6 〇 connects the third wafer i 丄 6 and the substrate 130, and a fourth wafer 117 can be stacked on top of it, and a fourth bonding wire 1 7 0 connects the fourth wafer 11 7 and the substrate 1 3 0, and finally A colloid 200532873 V. Description of the invention (8) 1 8 0 Seal the first wafer 1 1 4, the second wafer 1 1 5, the third wafer 1 16, the fourth wafer 1 17 and the first wafers. A bonding wire 140, the second bonding wires 150, the third bonding wires 160, and the fourth bonding wires 170, and the semi-cured resins 122a and 122b are the same. It can be cured into individual fully cured resins 1 to 23 to form a multi-chip stacked package structure of the same size, to achieve the effect of stacking a large number of wafers, fixing the end of the wire and reducing the step of stacking. The first bonding wire 140 connecting the first chip 丨 4 and the substrate 丨 30 can use the aforementioned reverse wire bonding method, or it can also use Kulicke & Soffa's previous folding wire bonding process (Folder F〇lded L. 〇p
Bonding Process，F2 bonding process)。該種打線方式 ί7線ΐ一接合點位於晶片銲墊上，而第二接合點位於基 ，刚折式打線製程具有低弧高（1〇w 1〇〇ρ)之優點，以 週用於本發明之多晶片堆疊之封裝製程。 本發明，保護範圍當視後附^申請專利範圍所界定者 圍内所=何熟知此項技藝者，在不脫離本發明之精神和範 圍内所作之任何變化與修改’均屬於本發明之保護範圍。 200532873 圖式簡單說明 、———_ 【圖式簡單說明】 第1 圖··習知多晶片同尺寸堆疊之封麥 意圖； 、攝造之截面 第2A至2K圖：依據本發明之多晶片同尺寸堆晶 程，一晶圓或其切割後晶片在製程中燮之封裝製 第3圖：依據本發明之多 意圖；及 ::所製造之多…尺寸堆疊之封裝=== 元件符號簡單說明： 第一晶片 銲墊 第二晶片 銲墊 銲線 間隔材料 封膠體 晶圓 11 主動面 12 背面 21 主動面 22 背面 30 基板 31 上表面 41 結球端 42 線尾蠕 51 111 黏著層 主動面 60 銲線 主動面 主動面 112a 第一晶片 之主動面 背面 113a 第一晶片 之銲墊 |〇 ί晶2同尺寸堆疊封裝構造 13 20 23 40 50 70 110 a 112 背面 112b 第二 113 銲墊Bonding Process, F2 bonding process). In this wire bonding method, one bonding point is located on the wafer pad and the second bonding point is located on the base. The rigid folding wire bonding process has the advantage of low arc height (10w 100p) and is used in the present invention. Multi-chip stack packaging process. The scope of protection of the present invention shall be deemed to be attached within the scope defined by the scope of the patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention belong to the protection of the present invention. range. 200532873 Schematic illustration, ———_ [Schematic description of the drawing] Fig. 1 · Knowing the intention of multi-chip stacking with the same size; Figure 2A to 2K of the photographed section: The multi-chip according to the present invention is the same Dimension stacking process, packaging of a wafer or its diced wafer in the manufacturing process Figure 3: According to the many intentions of the present invention; and: as many as manufactured ... Packages with dimensional stacking === Simple description of component symbols : First wafer pad Second wafer pad Welding wire spacer material Sealing colloidal wafer 11 Active surface 12 Back surface 21 Active surface 22 Back surface 30 Substrate 31 Upper surface 41 Ball end 42 Line tail creep 51 111 Adhesive layer active surface 60 Welding wire Active face Active face 112a Active face of the first wafer 113a Back pad of the first wafer | 〇2 Crystal 2 same size stacked package structure 13 20 23 40 50 70 110 a 112 Back 112b Second 113 pad
第15頁 200532873_ 圖式簡單說明 113b 第二晶片之銲墊 114 第一晶片 115 苐二晶片 116 第三晶片 117 第四晶片 121 未固化樹脂 122 半固化樹脂 122a 第一晶片下之半固 化樹脂 122b 第二晶片下之半固 化樹脂 123 全固化樹脂 130 基板 131 上表面 132 連接墊 140 第一銲線 141 結球端 142 線尾端 143 結球凸塊 150 第二焊線 151 結球端 152 線尾端 153 結球凸塊 160 第三銲線 170 第四鮮線 180 封膠體 210 晶圓載台 220 研磨工具 230 塗膠工具 240 烘烤裝置 250 切割膠帶 260 切割刀具Page 15 200532873_ Brief description of the diagram 113b Pads for the second wafer 114 First wafer 115 Second wafer 116 Third wafer 117 Fourth wafer 121 Uncured resin 122 Semi-cured resin 122a Semi-cured resin 122b under the first wafer Semi-cured resin under two wafers 123 Fully cured resin 130 Substrate 131 Upper surface 132 Connection pad 140 First bonding wire 141 Ball end 142 Line end 143 Ball bump 150 Second welding line 151 Ball end 152 Line end 153 Ball end Block 160 Third welding line 170 Fourth fresh line 180 Sealing compound 210 Wafer stage 220 Grinding tool 230 Gluing tool 240 Baking device 250 Cutting tape 260 Cutting tool
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