1331390 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種多晶片封裝構造，特別 於一種妥善利用基板黏晶區之多晶片封裝構造。 【先前技術】 多晶片封裝構造是越來越受到重視的半導趙 品，這是因為可以增加一封裝趙内積體電路的密 中以晶片在晶片上（Chip-On-Chip)的堆整方式不 封裳表面接合面積’更優於晶片並為 (side-by_side)。若是直接將所有需要的積體電路 單一晶片内，會有不良率提高的問題，且晶片的 變大’導致封裝體之表面接合面積擴大。 请參閱第1圖所示’一種習知的多晶片封裝賴 主要包含一基板110、複數個表面黏著型被 120、一第一晶片130、一第二晶片14〇、複數 15 1與152以及一封膠體16〇。該第二晶片14〇 上係大於該第一晶片130，並設置於該基板11〇 面ill。該第二晶片140係具有一主動面141、 之背面142以及複數個形成於該主動面141之第 143。利用複數個銲線152電性連接該第二晶片 銲墊143至該基板U心該些表面黏著型被動元> 又可稱之為晶片型被動元件，例如電容、電感、 積層陶究電容（MLCC)，其係設置於該基板n〇 面111在黏晶區之外的其餘部位。在有限的基 係有關 封裝產 度，其 會增加 t方式 整合於 尺寸會 ^ 造 100 動元件 個銲線 在尺寸 之一表 /相對 二桿墊 140之 f牛 1 2 0， 電阻或 之該表 板面積 6 1331390 内，並同時預留有第二晶片140與該些表面黏著型被動 元件120的設置面積，故第二晶片丨4〇之尺寸受到限 制，目前而言無法擴大到晶片尺寸封裝（chip Size Package，簡稱CSP)等級。當更小尺寸的第一晶片 貼設在該第二晶片1 40之主動面1 4丨之邊緣，但會影響 其它晶片堆整與模流平衡。此外，第一晶片130之銲塾 131可利用複數個銲線151電性連接至該基板11〇。通 常該多晶片封裝構造1 00係為一種數位保全記憶卡 (Micro SD card)，該第一晶片13〇係可為一控制器晶 片，該第二晶片140係可為一快閃記憶體晶片。該封膠 體i60係形成於該基板110之該表面m，並密封該第 一晶片uo、該第二晶片140、該些鲜線i5i與152。 當記憶體或積體電路的密度擴大，該第二晶片"Ο之尺 寸亦會變大，相對使得可設置哕 直该些表面黏著型被動元件 120的面積縮小。 【發明内容】 本發明之主要目的係在 3¾ ^ ^ ^ a ^ 杈供一種妥善利用基板黏 匕之多b日片封裝構造，較大 且不會減少月的尺寸可進一步擴大 會减 > 表面黏著型被動元件 小被阵麄Β ΰ # 町叹置面積，並減少較 规隱減曰曰片對於晶片堆疊與模 利影響》 、'_平衡所能產生的不 本發明之次一目的係在於提供一 晶區之多晶片封裝椹.告叮 、種妥善利用基板黏 於被隱藏較小晶片以及坍# 1 方堆疊較大晶片對 日日月以及對於下方承费 $之表面黏著型被 7 1331390 動元件的電性短路。1331390 IX. Description of the Invention: [Technical Field] The present invention relates to a multi-chip package structure, and more particularly to a multi-chip package structure that utilizes a substrate die-bonding region. [Prior Art] The multi-chip package structure is a semi-conductor product that is receiving more and more attention because it can increase the density of a chip-on-chip (Chip-On-Chip) in a package. The unbonded surface joint area is better than the wafer and is (side-by-side). If all of the required integrated circuits are directly placed in a single wafer, there is a problem that the defective rate is increased, and the wafer becomes larger, resulting in an increase in the surface joint area of the package. Referring to FIG. 1 , a conventional multi-chip package mainly includes a substrate 110 , a plurality of surface mount patterns 120 , a first wafer 130 , a second wafer 14 , a plurality of 15 1 and 152 , and a Sealant 16 〇. The second wafer 14 is larger than the first wafer 130 and disposed on the substrate 11 ill. The second wafer 140 has an active surface 141, a back surface 142, and a plurality of 143 formed on the active surface 141. The plurality of bonding wires 152 are electrically connected to the second die pad 143 to the substrate U. The surface-adhesive passive elements are also referred to as wafer-type passive components, such as capacitors, inductors, and laminated ceramic capacitors ( MLCC) is disposed on the remaining portion of the substrate n-plane 111 outside the die-bonding region. In a limited base system related to package yield, it will increase the t-mode integration in size. It will make 100 moving elements in one wire in the size of the table / relative to the two-bar pad 140 f 1 2 0, resistance or the table The board area is 6 1331390, and at the same time, the second wafer 140 and the surface area of the surface-adhesive passive components 120 are reserved, so that the size of the second wafer 受到4〇 is limited, and currently cannot be expanded to the wafer size package ( Chip Size Package, referred to as CSP). When the smaller size of the first wafer is attached to the edge of the active surface of the second wafer 140, it affects other wafer stacking and mold flow balance. In addition, the pad 131 of the first wafer 130 can be electrically connected to the substrate 11 by a plurality of bonding wires 151. Typically, the multi-chip package structure 100 is a digital SD card, the first chip 13 can be a controller wafer, and the second wafer 140 can be a flash memory chip. The encapsulant i60 is formed on the surface m of the substrate 110, and seals the first wafer uo, the second wafer 140, and the fresh lines i5i and 152. When the density of the memory or integrated circuit is increased, the size of the second wafer is also increased, so that the area of the surface-adhesive passive component 120 can be reduced. SUMMARY OF THE INVENTION The main object of the present invention is to provide a multi-b-day package structure for properly utilizing substrate adhesion, which is large and does not reduce the size of the moon and can be further enlarged and reduced. Adhesive passive components are small 麄Β ΰ # 町 叹 置 , , , , , , , , , , , , , , , , , , , , , 町 町 町 町 町 町 町 町 町 町 町 町 町 町 町 町 町 町 町 町 町Provide a multi-chip package of a crystal region. Advise, properly use the substrate to adhere to the hidden smaller wafers, and stack the larger wafers to the sun and the moon and the surface adhesion type for the lower cost of $1313390 Electrical short circuit of the moving element.
本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種妥善利用基板黏晶區之 多晶片封裝構造主要包含一基板、複數個表面黏著型被 動元件、一第一晶片以及一第二晶片。該基板之一表面 係界定有一黏晶區。該些表面黏著型被動元件係設置於 該黏晶區之角隅或邊緣並電性連接至該基板。該第一晶 片係設置於該黏晶區之一相對中央位置並電性連接至 該基板。該第二晶片係設置於該些表面黏著型被動元件 上並電性連接至該基板，且該第二晶片之覆蓋面積係對 應於該黏晶區。另揭示該多晶片封裝構造之應用及其使 用之基板。 本發明&目的及解決其技術問題還可採用卩下技術 措施進一步實現。 在前述的多晶片封裝構邊φ ^衣得造中，該些表面黏著型被動 元件係可具有一間隔維持离痄 子阿度以避免該第二晶片壓觸 該第·一晶片。 在前述的多晶片封裝槿垆巾 稱把中’可另包含複數個第一 銲線’其係位於該黏晶區内 ^ 以電性連接該第一晶片與 該基板，並且該些第一短Λώ . _ . 輝線之弧馬係不超過該間隔維持 高度9 ^ J刀巴言複思：個弟一 銲線’其係電性連接該第-曰 弟一晶片與該基板。 在前述的多晶片封裝構造 干 該第一晶片係可設有 8 1331390 複數個凸塊’以覆晶接合至該基板，其中該第一晶片之 背面係不超過該間隔維持高度。 在前述的多晶片封裝構造中，該第二晶片之背面係 可被覆有一絕緣層’其係貼觸於該些表面黏著型被動元 件之表面電極上，以避免該些表面黏著型被動元件之短 路。 在前述的多晶片封裝構造中，該黏晶區係可不小於 該基板之表面面積百分之七十，以構成晶片尺寸封裝。 在前述的多晶片封裝構造中，該基板於該表面係可 设有複數個第一内接墊、複數個第二内接墊與複數個表 面黏著塾’以供該第一晶片、該第二晶片與該些表面黏 著型被動元件之電性連接，其中該些第一内接墊與該些 表面黏著墊係位於該黏晶區内，並且該些表面黏著墊相 對較鄰近於該黏晶區之邊緣或角隅。 在前述的多晶片封裝構造中，該多晶片封裝構造係 可為一種數位保全記憶卡（Micro SDcard)，其中該第一 晶片係為一控制器晶片、該第二晶片係為一快閃記憶體 晶片。 在前述的多晶片封裝構造中，可另包含有至少一第 三晶片’其係疊設於該第二晶片上，該第三晶片係為一 快閃記憶體晶片且尺寸實質相同於該第二晶片。 在前述的多晶片封裝構造中，可另包含有至少一第 三晶片，其係疊設於該第二晶片上。 在前述的多晶片封裝構造中，可另包含有一封膠 9 1331390 體’其係密封該第二晶片。 在前述的多晶片封裝構造中，可另包含有一黏晶物 質’其係黏接該第二晶片並密封該第一晶片與該些表面 黏著型被動元件。 【實施方式】 依據本發明之第一具體實施例，揭示—種妥善利用 基板黏晶區之多晶片封裝構造。第2圖係為該多晶片封 裝構造之截面示意圖。第3圖係為該多晶片封裝構造透 視封膠體之基板表面示意圖。第4圖係為該多晶片封裝 構造多晶片封裝構造之另一截面示意圖《第5圖係為該 多晶片封裝構造之基板表面示意圖。 請參閱第2圖所示，一種妥善利用基板黏晶區之多 晶片封裝構造200主要包含一基板210、複數個表面黏 著型被動元件220、一第一晶片230以及一第二晶片 240。該基板210係可為一印刷電路板、一陶瓷電路板 或一電路薄膜，其係具有一上表面211與一下表面 212。請參閱第3圖並配合第5圖所示，該基板210之 上表面2 1 1係界定有一黏晶區2 1 3，其尺寸大小對應於 該第二晶片240。此外，該上表面211係可設有複數個 第一内接墊214、複數個第二内接墊215與複數個表面 黏著墊216，以分別可供該第一晶片23 0、該第二晶片 240與該些表面黏著型被動元件220之電性連接，其中 該些第一内接墊214與該些表面黏著墊216係位於該黏 晶區213内，該些第二内接墊215係位於該黏晶區213之 1331390 外，並且該些表面黏著墊216相對於該些第一内接塾 214較鄰近於該黏晶區213之邊緣或角隅。在本實施例 中’該黏晶區213係可不小於該基板210之該上表面 211面積百分之七十，即該第二晶片240之主動面尺寸 可接近該基板210之上表面211，以構成晶片尺寸封 裝。請參閱第4圖所示，該基板210更可包含有複數個 外接墊217，其係形成於該基板210之下表面212。 該些表面黏著型被動元件220係設置於該黏晶區 213之角隅或邊緣並電性連接至該基板210之該些表面 黏著墊216。該些表面黏著型被動元件220或可稱為晶 片型被動元件，其外形係為條塊狀小顆粒，如〇2〇 1或 0402等被動元件規格，可利用表面黏著（SMT)技術焊設 於該基板210之該些表面黏著墊216。較佳地，該些表 面黏著型被動元件220係可具有一間隔維持高度hi， 以避免該第二晶片240壓觸該第一晶片230。如第2及 3圖所示’不受局限地，部分之表面黏著型被動元件220 係可設置於該黏晶區213之外。 請參閱第2、3及4圖所示，該第一晶片230之尺寸 係小於該第二晶片240。該第一晶片230係設置於該黏 晶區213之一相對中央位置並電性連接至該基板21〇。 在本實施例中，該第一晶片230係具有複數個第一銲塾 231，在晶片設置之後，該些第一銲墊231係為朝上。 複數個第一銲線251係形成於該黏晶區213内，以電性 連接該些第一銲墊23 1與該朞板210之該些第一内接塾 1331390 214。請參閱第4圖所示’較佳地，該些第一銲 之弧高H2以及該第一晶片23 〇皆不超過該間隔 度Η1 ’以使該第一晶片23 0隱藏在該第二晶片 該基板210之間且不會有電性短路的問題。 該第二晶片240係具有一主動面241及一相 面242，其中該主動面241係形成有複數個第 243。请參閱第2及4圖，該第二晶片24〇係設 些表面黏著型被動元件220上並利用複數個第 252電性連接該些第二銲墊243與該基板21〇之 一内接塾215(如第3圖所示），並且如上述這般 一晶片240之覆蓋面積係對應於該黏晶區2 i 3 地，該第二晶片24〇之背面242係可被覆有一 244’其係貼觸於該些表面黏著型被動元件220 電極上’以避免作為晶片間隔控制的該些表面黏 動元件220在表面電極與表面電極之間產生電怕 具體而言，該多晶片封裝構造2 〇〇可另包含 膠體2 60，其係形成於該基板210之該上表面2 密封該第一晶片230、該第二晶片240、該些表 型被動元件220、該些第一銲線251與該些第 252。在本實施例中，該多晶片封裝構造200係 種數位保全記憶卡（Micro SD card)，其中該第 230係為一控制器晶片、該第二晶片24〇係為一 憶艘晶片。 因此，在上述的多晶片封裝構造20〇中’較 線25 1 維持高 240與 對之背 二銲墊 置於該 二銲線 該些第 ，該第 。較佳 絕緣層 之表面 著型被 .短路》 有一封 1 1，以 面黏著 二銲線 可為一 一晶片 快閃記 大的第 12 1331390 二晶片240的尺寸可進一步擴大且不會減少表面 型被動元件220的設置面積，特別是第二晶片24〇 動面241面積可達到接近該基板21〇之上表面211 構成晶片尺寸封裝。此外，並能減少較小被隱藏的 晶片230對於晶片堆疊與模流平衡所能產生的不 響。本發明之另一顯著功效為，不需要隨著表面黏 被動元件220的設置數量增加而被迫縮小第二晶片 的尺寸’相反地’表面黏著型被動元件22〇的設置 增加更可以增加第二晶片240的打線支撐，以提高 良率。 在本發明之第二具體實施例，揭示另一種妥善 基板黏晶區之多晶片封裝構造。請參閱第6圖所示 多晶片封裝構造300主要包含一基板310、複數個 黏著型被動元件320、一第一晶片330以及一第二 340〇該基板310之一上表面311係界定有一黏晶 對應於該第二晶片340。該基板310更具有複數個 墊313，其係形成於該基板310之一下表面312。 該些表面黏著型被動元件320係設置於該黏晶 角隅或邊緣並以錫膏電性連接至該基板310。該第 片330係設置於該黏晶區之一相對中央位置並電 接至該基板310»在本實施例中，該第一晶片330 為一覆晶晶片，其係設有複數個凸塊3 3 1，以覆晶 至該基板310，其中該第一晶片330之背面332係 過該間隔維持高度H3。因此，該些表面黏著型被 黏著 之主 ，以 第一 利影 著型 240 數量 製程 利用 ，該 表面 晶片 區， 外接 區之 一晶 性連 係可 接合 不超 動元 13 •1331390 件3 20係能提供一間隔維持高度h3，以避免該第二晶 片340壓觸該第一晶片33〇。 該第二晶片340係設置於該些表面黏著型被動元件 320上並電性連接至該基板310，且該第二晶片340之 覆蓋面積係對應於該黏晶區。該第二晶片3 40係具有一 主動面341 ’該主動面341係設有複數個銲墊343。利 用複數個銲線351電性連接該第二晶片340之銲墊343 至該基板3 1 0。 較佳地，該第二晶片34〇之背面342係可被覆有一 絕緣層344 ’以避免該些表面黏著型被動元件320之短 路°在本實施例中，該多晶片封裝構造300可另包含有 一點晶物質370，其係黏接該第二晶片340並密封該第 一晶片330與該些表面黏著型被動元件32〇。 該多晶片封裝構造300可另包含有一封膝體360’ 其係密封該第二晶片34〇。當該封膠體360形成之後’ 可製成一卡片狀。具體而言，該多晶片封裝構造3 00係 "T為一種數位保全記憶卡（MicroSDcard)，其中該第一 晶片330係為一控制器晶片、該第二晶片34〇係為一快 閃記憶體晶片。 該多晶片封裝構造3 00可另包含有至少一第三晶片 380 ’其係疊設於該第二晶片340上，該第三晶片380 係為一快閃記憶體晶片且尺寸實質相同於該第二晶片 340 »該第三晶片38〇係疊設於該第二晶片34〇上，並 使該第三晶片380之複數個銲墊381係位於其朝上之主 14 1331390 動面，可藉由複數個鮮線352電性連接該些銲塾381至 該基板310。該第二晶片340與該第三晶片380之間係 設有一間隔片390，以提供該第三晶片38〇在正向堆疊 時之打線間隔，並可避免該第三晶片38〇壓觸至相對下 方之該些銲線351。 因此，該多晶片封裝構造3〇〇係可將一較小尺寸之 第一晶片330與該些表面黏著型被動元件32〇隱藏在同 一層之黏晶間隙’不會影響較大尺寸之第二晶片34〇與 第二晶片3 8 0的縱向堆疊而導致堆疊厚度增加。此外， 不需要縮小較大尺寸之第二晶片34〇而能設置更多數 量的表面黏著型被動元件320，具有實用性。 以上所述’僅是本發明的較佳實施例而已’並非對 本發明作任何形式上的限制’雖然本發明已以較佳實施 例揭露如上’然而並非用以限定本發明，任何熟悉本專 業的技術人員’在不脫離本發明技術方案範圍内，當可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容’依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖·一種習知多晶片封裝構造之截面示意圖。 第2圖：依據本發明之第一具體實施例，一種妥善利用 基板黏晶區之多晶片封裝構造之截面示意圖。 15 1331390 第3圖：依據本發明之第一具體實施例，該多晶片封裝 構造透視封膠體之基板表面示意圖。 第4圖：依據本發明之第一具體實施例，該多晶片封裝 構造多晶片封裝構造之另一截面示意圖。 第5圖：依據本發明之第一具體實施例，該多晶片封裝 構造之基板表面示意圖。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a multi-chip package structure for properly utilizing a die attach region of a substrate mainly comprises a substrate, a plurality of surface-adhesive driven elements, a first wafer, and a second wafer. One surface of the substrate defines a die-bonding region. The surface-adhesive passive components are disposed at the corners or edges of the die-bonding region and are electrically connected to the substrate. The first wafer is disposed at a center of the one of the die bonding regions and electrically connected to the substrate. The second wafer is disposed on the surface-adhesive passive component and electrically connected to the substrate, and the coverage area of the second wafer corresponds to the die-bonding region. The application of the multi-chip package construction and the substrate used therewith are also disclosed. The object of the present invention and the solution of the technical problems thereof can be further realized by the following technical measures. In the foregoing multi-chip package fabrication, the surface-adhesive passive components may have a spacing maintained from the dies to prevent the second wafer from pressing against the first wafer. In the foregoing multi-chip package squeegee, a plurality of first bonding wires may be further included in the die bonding region to electrically connect the first wafer and the substrate, and the first short Λώ . _ . The arc line of the ray line does not exceed the interval to maintain the height of 9 ^ J. The reckless thinking: a younger wire is connected to the wafer and the substrate. In the foregoing multi-chip package structure, the first wafer system may be provided with 8 1331390 plurality of bumps 'to be flip-chip bonded to the substrate, wherein the back surface of the first wafer does not exceed the interval maintaining height. In the foregoing multi-chip package structure, the back surface of the second wafer may be covered with an insulating layer that is in contact with the surface electrodes of the surface-adhesive passive components to avoid short-circuiting the surface-adhesive passive components. . In the above multi-wafer package construction, the die bond region may be no less than seventy percent of the surface area of the substrate to constitute a wafer size package. In the above multi-chip package structure, the substrate may be provided with a plurality of first inner pads, a plurality of second inner pads and a plurality of surface adhesives for the first wafer, the second Electrically connecting the wafer to the surface-adhesive passive components, wherein the first inner pads and the surface adhesive pads are located in the die-bonding region, and the surface-adhesive pads are relatively adjacent to the die-bonding region The edge or corner. In the above multi-chip package structure, the multi-chip package structure may be a digital SD card, wherein the first chip is a controller chip, and the second chip is a flash memory. Wafer. In the foregoing multi-chip package structure, at least one third wafer is additionally disposed on the second wafer, the third wafer is a flash memory chip and the size is substantially the same as the second Wafer. In the foregoing multi-chip package construction, at least one third wafer may be further included on the second wafer. In the foregoing multi-chip package construction, an adhesive 9 1331390 body may be additionally included which seals the second wafer. In the foregoing multi-chip package construction, a die-bonding material may be further included which adheres to the second wafer and seals the first wafer and the surface-adhesive passive components. [Embodiment] According to a first embodiment of the present invention, a multi-chip package structure in which a substrate die-bonding region is properly utilized is disclosed. Figure 2 is a schematic cross-sectional view of the multi-wafer package construction. Figure 3 is a schematic view of the surface of the substrate of the multi-chip package structure through the encapsulant. Fig. 4 is another schematic cross-sectional view showing the multi-chip package structure of the multi-chip package structure. Fig. 5 is a schematic view showing the surface of the substrate of the multi-chip package structure. Referring to FIG. 2, a multi-chip package structure 200 for properly utilizing a die attach region of a substrate mainly includes a substrate 210, a plurality of surface-adhesive passive components 220, a first wafer 230, and a second wafer 240. The substrate 210 can be a printed circuit board, a ceramic circuit board or a circuit film having an upper surface 211 and a lower surface 212. Referring to FIG. 3 and in conjunction with FIG. 5, the upper surface 211 of the substrate 210 defines a die-bonding region 213 having a size corresponding to the second wafer 240. In addition, the upper surface 211 can be provided with a plurality of first inner pads 214, a plurality of second inner pads 215 and a plurality of surface adhesive pads 216 for respectively providing the first wafer 230 and the second wafer. The second inner pad 214 and the surface adhesive pad 216 are located in the die bonding area 213, and the second inner pad 215 is located. The surface of the die attach region 213 is outside the 1331390, and the surface adhesive pads 216 are adjacent to the edges or corners of the die attach region 213 relative to the first interconnect pads 214. In the present embodiment, the area of the adhesive layer 213 is not less than 70% of the area of the upper surface 211 of the substrate 210, that is, the active surface of the second wafer 240 is close to the upper surface 211 of the substrate 210. Form a wafer size package. Referring to FIG. 4, the substrate 210 further includes a plurality of external pads 217 formed on the lower surface 212 of the substrate 210. The surface-adhesive passive components 220 are disposed at the corners or edges of the die-bonding region 213 and are electrically connected to the surface-adhesive pads 216 of the substrate 210. The surface-adhesive passive component 220 may be referred to as a wafer-type passive component, and its shape is a small block-shaped small particle, such as a passive component specification such as 〇2〇1 or 0402, which can be soldered by surface adhesion (SMT) technology. The surfaces of the substrate 210 are adhered to the pads 216. Preferably, the surface-adhesive passive components 220 can have a spacing maintaining height hi to prevent the second wafer 240 from pressing against the first wafer 230. As shown in Figures 2 and 3, a portion of the surface-adhesive passive component 220 can be disposed outside of the die-bonding region 213 without limitation. Referring to Figures 2, 3 and 4, the first wafer 230 is smaller in size than the second wafer 240. The first wafer 230 is disposed at a central position of the one of the bonding regions 213 and is electrically connected to the substrate 21A. In this embodiment, the first wafer 230 has a plurality of first solder pads 231, and the first pads 231 are facing upward after the wafer is disposed. A plurality of first bonding wires 251 are formed in the die bonding region 213 to electrically connect the first bonding pads 23 1 and the first interconnecting pads 1331390 214 of the period plate 210. Referring to FIG. 4, preferably, the first welding arc height H2 and the first wafer 23 不 do not exceed the spacing Η1′ to hide the first wafer 230 from the second wafer. There is no problem of electrical short between the substrates 210. The second wafer 240 has an active surface 241 and a surface 242, wherein the active surface 241 is formed with a plurality of 243th portions. Referring to FIGS. 2 and 4, the second wafer 24 is affixed to the surface-adhesive passive component 220 and electrically connected to the substrate 21 by a plurality of 252th electrodes 243. 215 (as shown in FIG. 3), and as described above, a coverage area of the wafer 240 corresponds to the die bonding region 2 i 3 , and the back surface 242 of the second wafer 24 can be covered with a 244 ′ Applying to the surface-adhesive passive component 220 electrodes to avoid the surface-gearing elements 220 as wafer spacing control from generating electrical interference between the surface electrodes and the surface electrodes. Specifically, the multi-chip package structure 2 〇 The first surface of the substrate 210 is sealed on the upper surface 2 of the substrate 210 to seal the first wafer 230, the second wafer 240, the phenotype passive components 220, the first bonding wires 251 and the Something 252. In this embodiment, the multi-chip package structure 200 is a micro SD card, wherein the 230th is a controller chip, and the second chip 24 is a memory wafer. Therefore, in the above-described multi-chip package structure 20', the line 25 1 is maintained at a height of 240 and the back of the second pad is placed on the second wire, the first, the first. The surface of the preferred insulating layer is shaped by a short circuit. There is a 1,1 surface-to-surface adhesion of the second bonding wire. The 12th 1331390 of the wafer can be flashed. The size of the wafer 240 can be further expanded without reducing the surface type. The set area of the component 220, particularly the area of the second wafer 24 lands 241, can be close to the top surface 211 of the substrate 21 to form a wafer size package. In addition, it can reduce the impact of the smaller hidden wafer 230 on wafer stack and mold flow balance. Another significant effect of the present invention is that it is not required to reduce the size of the second wafer as the number of surface-adhesive passive elements 220 is increased. [Inversely, the increase in the setting of the surface-adhesive passive element 22 can increase the second. The wire 240 is wire-supported to increase the yield. In a second embodiment of the present invention, another multi-chip package construction of a proper substrate die-bonding region is disclosed. The multi-chip package structure 300 shown in FIG. 6 mainly includes a substrate 310, a plurality of adhesive passive elements 320, a first wafer 330, and a second 340. The upper surface 311 of the substrate 310 defines a die bond. Corresponding to the second wafer 340. The substrate 310 further has a plurality of pads 313 formed on a lower surface 312 of the substrate 310. The surface-adhesive passive elements 320 are disposed on the die corners or edges and are electrically connected to the substrate 310 by solder paste. The first piece 330 is disposed on the opposite side of the die bond region and electrically connected to the substrate 310. In the embodiment, the first wafer 330 is a flip chip, and the plurality of bumps 3 are disposed. 3 1, to crystallize to the substrate 310, wherein the back surface 332 of the first wafer 330 is maintained at the height H3. Therefore, the surface-adhesive type is adhered to, and the first type of wafer is used in the number 240 process. The surface wafer area, one of the external areas can be bonded to the non-translating element 13 • 1331390 pieces 3 20 series energy An interval maintaining height h3 is provided to prevent the second wafer 340 from pressing against the first wafer 33. The second wafer 340 is disposed on the surface-adhesive passive component 320 and electrically connected to the substrate 310, and the coverage area of the second wafer 340 corresponds to the die-bonding region. The second wafer 340 has an active surface 341'. The active surface 341 is provided with a plurality of pads 343. A plurality of bonding wires 351 are used to electrically connect the pads 343 of the second wafer 340 to the substrate 310. Preferably, the back surface 342 of the second wafer 34 is covered with an insulating layer 344 ′ to avoid short circuit of the surface-adhesive passive components 320. In this embodiment, the multi-chip package structure 300 may further include A layer of crystalline material 370 adheres to the second wafer 340 and seals the first wafer 330 and the surface-adhesive passive elements 32A. The multi-chip package construction 300 can further include a knee body 360' that seals the second wafer 34A. When the sealant 360 is formed, a card shape can be formed. Specifically, the multi-chip package structure 300 is a digital memory card (MicroSDcard), wherein the first chip 330 is a controller chip, and the second chip 34 is a flash memory. Body wafer. The multi-chip package structure 300 may further include at least one third wafer 380' stacked on the second wafer 340. The third wafer 380 is a flash memory chip and has substantially the same size as the first The second wafer 340 is stacked on the second wafer 34, and the plurality of pads 381 of the third wafer 380 are located on the upper surface of the main 14 1331390. A plurality of fresh wires 352 electrically connect the solder pads 381 to the substrate 310. A spacer 390 is disposed between the second wafer 340 and the third wafer 380 to provide a wire spacing of the third wafer 38 when stacked in the forward direction, and the third wafer 38 is prevented from being pressed against the relative The bonding wires 351 below. Therefore, the multi-chip package structure 3 can hide a small-sized first wafer 330 and the surface-adhesive passive elements 32 〇 in the same layer of the die-gap gap 'does not affect the second of the larger size. The longitudinal stacking of the wafer 34A with the second wafer 380 causes the stack thickness to increase. Further, it is not necessary to reduce the size of the second wafer 34 of a larger size, and a larger number of surface-adhesive passive elements 320 can be provided, which is practical. The above description is only a preferred embodiment of the present invention and is not intended to limit the invention in any way. The present invention has been described above by way of a preferred embodiment. A person skilled in the art can make some modifications or modifications to equivalent embodiments, which can be made without departing from the technical scope of the present invention, without departing from the technical scope of the present invention. It is still within the scope of the technical solution of the present invention to make any simple modifications, equivalent changes and modifications to the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional multi-chip package structure. Fig. 2 is a schematic cross-sectional view showing a multi-chip package structure for properly utilizing a die attach region of a substrate in accordance with a first embodiment of the present invention. 15 1331390 FIG. 3 is a schematic view showing the surface of a substrate of a see-through encapsulant in accordance with a first embodiment of the present invention. Figure 4 is another cross-sectional view of the multi-chip package construction multi-chip package construction in accordance with a first embodiment of the present invention. Figure 5 is a schematic view showing the surface of a substrate of the multi-chip package structure in accordance with a first embodiment of the present invention.
第6圖：依據本發明之第二具體實施例，另一種妥善利 用基板黏晶區之多晶片封裝構造之截面示意 圖。 【主要元件符號說明】 100多晶片封裝構造Fig. 6 is a cross-sectional view showing another multi-chip package structure in which a substrate die-bonding region is suitably used in accordance with a second embodiment of the present invention. [Main component symbol description] 100 multi-chip package structure
110 基板 111 表面 120 表面黏著型被動元件 130 第一晶片 131 銲墊 140 第二晶片 141 主動面 142 背 面 143 銲墊 151 銲線 152 銲線 160 封膠體 200 多晶片封裝構造 210 基板 211 上表面 212 下表面 213 黏晶區 214 第一内接墊 215 第 二内 216 表面黏著墊 217 外接墊 220 表面黏著型被動元件 230 第一晶片 231 第一銲墊 240 第二晶片 241 主動面 242 背 面 16 1331390110 substrate 111 surface 120 surface-adhesive passive component 130 first wafer 131 solder pad 140 second wafer 141 active surface 142 back surface 143 pad 151 bonding wire 152 bonding wire 160 sealing body 200 multi-chip package structure 210 substrate 211 upper surface 212 Surface 213 die bonding region 214 first inner pad 215 second inner surface 216 surface adhesive pad 217 external pad 220 surface adhesive type passive component 230 first wafer 231 first bonding pad 240 second wafer 241 active surface 242 back surface 16 1331390
243 第二銲墊 244 絕緣層 251 第一銲線 252 第二銲線 260 封膠體 300 多晶片封裝構造 310 基板 311 上表面 313 外接墊 320 表面黏著型被動元件 330 第一晶片 331 凸塊 340 第二晶片 341 主動面 343 銲墊 344 絕緣層 351 銲線 352 銲線 360 封膠體 370 黏晶物質 381 銲墊 390 間隔片 H1 間隔維持兩度 H2 弧·南 H3 間隔維持南度 312下表面 332背面 342背面 380第三晶片243 second bonding pad 244 insulating layer 251 first bonding wire 252 second bonding wire 260 sealing body 300 multi-chip package structure 310 substrate 311 upper surface 313 external pad 320 surface-adhesive passive component 330 first wafer 331 bump 340 second Wafer 341 active surface 343 solder pad 344 insulating layer 351 bonding wire 352 bonding wire 360 sealing body 370 adhesive material 381 pad 390 spacer H1 interval maintained twice degrees H2 arc · south H3 interval maintenance south 312 lower surface 332 back 342 back 380 third chip
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