TWI245393B - Multi-chip stacked package - Google Patents

Abstract

A multi-chip stacked package mainly comprises a substrate, a first chip, a dummy chip and a second chip. The substrate has a top surface. The first chip and the second chip are disposed on the top surface of the substrate with active surfaces. The dummy die is disposed between the first chip and the second chip. The dummy die has a ground layer. At least one ground device connects the ground layer for reducing the electromagnetic interference between the two chips.

Description

1245393 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a multi-chip stacked package structure, and more particularly, to a multi-chip stacked package structure that prevents electromagnetic interference between two adjacent stacked wafers. [Previous technology] There are many known types of multi-chip package structures. In order to achieve a small surface bonding area, a plurality of wafers are generally stacked on a substrate in a stacking manner. When the chips are electrically connected by wire bonding, With the substrate 4, the active faces of the wafers are stacked upward to facilitate the connection of a plurality of bonding wires. A conventional multi-wafer stacked packaging structure is a dummy wafer placed between two adjacent wafers, or, A paste adhesive or film is used to space two adjacent wafers to provide a sufficient arc height of the bonding wires. Chinese Patent Bulletin No. 455967 "Manufacturing Method of Stacked Chip Package Structure" discloses a conventional chip stack package structure in which a dummy chip is placed between two adjacent chips. Please refer to FIG. 1, the multi-chip The stacked package structure 100 includes a substrate 110, a first wafer 120, a dummy wafer 130, a second wafer 140, a plurality of first bonding wires 150, and a plurality of second bonding wires 160. The substrate 1 1 〇 It has an upper surface, and includes a plurality of connection pads formed on the upper surface! 12. The first wafer 120 and the second wafer 140 are disposed on the substrate with the active side facing upward. The first wafer 120 has a first active surface 121 and includes a plurality of The first bonding pad 123 of the first active surface 121 is used to bond the first chip 120 to the upper surface Π1 of the substrate 110 with an adhesive layer 122. The first bonding wires 150 are connected to the first chip 120. The first pads 123 correspond to the substrate 11

1245393 V. Description of the invention (2) The connection pad 1 1 2 and an adhesive layer 1 2 4 are used to bond the dummy chip 1 30 to the first active surface 21 of the first chip 120. The dummy chip 1 30 has A film adhesive 1 3 1 on its surface. When the film adhesive 1 3 1 is heated to have viscosity, the second wafer 1 40 can be set on the dummy wafer i 30, and the second wafer 1 40. It has a second active surface 141 and includes a plurality of second bonding pads 142 formed on the second active surface 141. The second bonding wires are connected to the second bonding pads of the second chip 14 by the second bonding wires 60. The pads 1 2 2 and the substrate 1 1 0 correspond to some connection pads 1 2, a knee 1 70 is to seal the first wafer 1 2 0, the dummy wafer 1 3 0, the second wafer 140, The first bonding wires 15 and the second bonding wires 160, wherein the dummy chip 130 can provide a space for connecting / connecting the first chip 120 and the substrate 110 The first bonding wire 15 has a sufficient arc height. However, the stacking system of the first chip 120 and the second chip 14o will cause inter-chip communication, interference, and noise, especially when above or below. Either wafer when the wafer is a high frequency or radio frequency chip, corresponding to the crystal stack of the other - the degree of interference-sheet even more serious. [Summary of the Invention] The main object of the present invention is to provide a multi-chip stacked package structure including-substrate,-first-chip,-dummy chip,-second and subsequent; a grounding device, the first chip and The second wafer is disposed on the substrate in a stacked manner, and the winning wafer is disposed between the first wafer and the second wafer, and the virtual wafer is referred to as > 〇 ラa _ is a grounding layer, and the grounding device is used to connect one of the connection pads of the substrate or the grounding pad of the first chip, which is a problem of mutual electromagnetic interference between the plates, preferably , The ground λ is not less than the area of a second active surface of one of the second chips, and

1245393 V. Description of the invention (3) Adding the ground layer to the second chip &&;; r ~ 一日 day and month (I and separated), thereby preventing interference to a signal, providing better noise suppression The effect is that the first chip and a dummy board are stacked in a multi-chip package according to the present invention, which includes a second chip and a plurality of solder joints.

B ^ 1 ▼ f I | ΙΞ | j _, — »wire, a plurality of second bonding wires, and at least one grounding device, the substrate is provided with an upper surface and includes a plurality of connection pads formed on the upper surface, the first A wafer has a first active surface and includes a plurality of first pads formed on the first main body. The first wafer is disposed on the upper surface of the board with the first active surface facing upward. The virtual chip is disposed on the first chip, the virtual crystal = has a ground layer, the grounding device is connected to the ground layer, and the first S-chip has a second active surface and includes a plurality of formations. The second bonding pad on the first active surface, the second chip is disposed on the dummy wafer with the second active surface facing up, and the first bonding wires and the second bonding wires are respectively used. The first bonding pads of the first chip and the second bonding pads of the second chip and corresponding connection pads of the substrate are connected. [Embodiment] With reference to the drawings, the present invention will be described by the following embodiments. According to a first embodiment of the present invention, please refer to FIG. 2. A multi-chip stacked package structure 200 mainly includes a substrate 210, a first wafer 220, a dummy wafer 230, and a second wafer 240. , A plurality of first bonding wires 250, a plurality of second bonding wires 26, and at least one grounding device 27, the substrate 210 has an upper surface 2Π and includes a plurality of connections formed on the upper surface 2] ^ connection 塾 21 2. The first chip 220 has a first active surface 221 and includes a plurality of

Page 8 1245393 V. Description of the invention (4) The first pad 222 formed on the first active surface 221, and the first active surface 22 1 of the first wafer 220 can be set up or down. On the upper surface 2 11 of the substrate 2 1 0, in this embodiment, the first active surface 22 1 of the first wafer 2 2 is facing upward, and a glue 223 is used to bond the first wafer. The back side of 2 2 0 is on the top surface 2 11 of the substrate 2 1 0. The first bonding wires 250 are connected to the first pads 222 of the first wafer 22 0 and correspond to the substrate 2 10. Connection pad 212. Alternatively, the first wafer 220 may be flip-chip bonded to the upper surface 211 (not shown) of the substrate 21 0 so that the first active surface 2 2 1 is disposed downward toward the substrate 2 1 0. The dummy wafer 230 is bonded with an adhesive 233 to be disposed on the first wafer 220. In this embodiment, the size of the dummy wafer " o is smaller than the first wafer 220 to expose the first wafer 220. The first bonding pads 222 of a wafer 22, «Xuanxu said that the chip 230 has a ground layer 232. In this embodiment, the grounding layer 232 is a sputter i ng The copper layer formed is formed on one surface 2 31 of the edge virtual chip 230. Preferably, the ground layer 232 completely covers the surface 231 of the virtual chip 230, and the area of the ground layer 232 is It is larger than a second active surface 241 of the second chip 240 to provide better ability to suppress electromagnetic interference. The grounding device 270 is connected to the grounding layer 232. In this embodiment, the grounding device 2 70 is a grounding wire, which is connected to the grounding layer 23 2 to β 丨 one of the connection pads of the substrate 2 1 0 2 丨 2; In addition, please refer to FIG. 3. In the second embodiment, one substrate 21, a first wafer 220, a dummy wafer 230, a second wafer 240, and a plurality of substrates of the multi-chip stacked package structure are provided. The first bonding wires 250 are the same as the first embodiment, in which the first

Page 9 1245393 V. Description of the invention (5) The first active surface 221 of a wafer 22 0 is further formed with at least one ground pad 224, and the dummy wafer 230 is provided on the first wafer 22 0 of the first The active surface 221 and the grounding device 2 70 connect the grounding layer 232 to the grounding pad 224 of the first chip 220 to suppress the problem of mutual electromagnetic interference between the two chips. In the above two embodiments, the size of the dummy wafer 23 is larger than that of the second wafer 240, and the second wafer 240 is disposed on the dummy wafer 230 with the second active surface 241 facing up. An adhesive material 234 bonds the second chip 240 and the dummy chip 2 30. A plurality of second pads 242 are formed on the second active surface 241. Preferably, the second chip 24 () is an RFID (Radi 〇Frequency Identification (radio frequency identification) chip, the 丨 second bonding wires 260 are connected to the second pads 242 and the substrate 2 are connected to each other, a sealant seals the first chip 220 1 virtual chip 230. The second chip 240, the first bonding wires 25, the second bonding wires 260, and the grounding device 270. The substrate 21 may be a ball grid array (ball grid array, BGA), a plurality of solder balls 213 may be disposed on a lower surface 214 of the substrate 210 to constitute the multi-chip stacked package structure 2000. In the above-mentioned multi-chip stacked package structure 2000, the dummy chip 23 The ground layer 23 is located between the first wafer 220 and the second wafer 240, and the dummy wafer 23 The 2 series can suppress the mutual electromagnetic interference between the first chip 22 and the second chip 240 to reduce noise, wherein the area of the ground layer 2 3 2 of the virtual chip 2 30 is larger than that of the second chip 240. Two wafers 2 4 0, which can provide better shielding effect. "

Page 1245393 5. Description of the invention (6) According to the third embodiment of the present invention, please refer to FIG. 4. A multi-chip stacked package structure 3 0 0 series mainly includes a substrate 3 J 〇, a first wafer 3 20. A dummy wafer 3 30, a second wafer 340, a plurality of first bonding wires 350, a plurality of second recording wires 36, and a plurality of grounding devices 370. The substrate 310 has an upper surface 311 and includes a plurality of A connection pad 312 is formed on the upper surface 311. One of the first active surfaces 3 2 1 of the first wafer 3 2 0 faces upward, and is bonded with an adhesive 324 or the first wafer 320 on the upper surface 311 of the substrate 310. The first active surface 3 21 is A plurality of first bonding pads 322 and a plurality of ground bonding pads 323 are formed, and the first bonding wires 3 5 0 are used to connect the _ first bonding pads 322 and the substrate 3 0 0 Corresponding to the connection pads 3 1 2, in this embodiment, the first chip 320 has a size-inch that is slightly the same as that of the dummy chip 33. The dummy wafer 3 3 0 is disposed on the first wafer 3 2 0, and the dummy wafer 330 has a ground layer 332 (ground layer) formed on one of the surfaces of the dummy wafer 3 3 0 3 3 1. In this embodiment, the ground layer μ 2 completely covers the surface 331 of §Xuanxu wafer 330, and the size of the virtual wafer 330 is slightly equal to that of the second wafer 340, so the area of the ground layer 332 is Slightly specializes in the area of one of the second active surfaces 341 of the first chip 340 of the Hai Hai. In this embodiment, the ground layer 3 3 2 is a copper layer. The grounding devices 370 are disposed on the grounding layer 332. In this embodiment, the grounding devices 3 7 0 are grounding bumps, which are corresponding to the grounding layer 32 and the first chip 320. These ground pads 3 23, an underfill 3 3 3 is filled in the dummy wafer 3 3 0 and the first wafer 3 2 0.

Himr Page 11 1245393 V. Description of the invention (7) A gap between the active surfaces 3 2 1 and seals the grounding devices 3 7 0. The 5th first βθ sheet 3 4 0 is disposed on the dummy wafer 330 with the first active surface 341 facing upward, and a second material 34 0 and the dummy wafer 330 are bonded with an adhesive 334 ′. A plurality of second pads 342 are formed on the second active surface 341. Preferably, the second chip 340 is an RFID (Radio

Frequency Ident if icat ion (radio frequency identification) chip, the first bonding wires 360 are connected to the second bonding pads 342 and the substrate 3 1 〇 corresponding to the connection pads 3 12, a gel 380 is sealed The first wafer 32, the virtual wafer 330, the second wafer 340, the first bonding wires 350, and the second bonding wires 360. In this embodiment, the substrate 31 may be a Ball grid array (BGA), a plurality of solder balls 313 can be set on the lower surface of one of 4 substrates 3 1 0 3 1 4 to form the multi-chip stacked package structure 300 〇 In the above-mentioned multi-chip stacked package In the structure 300, the dummy wafer 33 is disposed between the first wafer 32 and the second wafer 340, and the ground pads 323 of the first wafer 32 are connected with the grounding devices 370. In order to suppress the phenomenon of mutual electromagnetic interference between the first chip 320 and the second chip 340 to reduce noise. According to a fourth specific embodiment of the present invention, please refer to FIG. 5. A multi-chip stacked package structure 400 series mainly includes a substrate 41, a first chip 42, a virtual chip 430, and a second chip 440. , A plurality of fresh wires 45 and a plurality of grounding devices 460, the substrate 4 10 has an upper surface 4 u and includes a plurality of first connection pads 412, a second connection pad 413, and a ground bond formed on the upper surface 411 Pad 414. 1245393 V. Description of the invention (8) The first wafer 420 has a first active surface 421 and a back surface 422 and includes a plurality of first welding pads 4 2 3 formed on the first active surface 4 2 1. A wafer 4 2 0 is flip-chip bonded to the upper surface 411 of the substrate 410 with the first active surface 4 2 1 facing downward, wherein a plurality of bumps 424 are disposed on the substrate 4 1 0 and the first Between the first active surface 4 2 1 of the wafer 4 2 0, and the bumps 424 are electrically connected to the first connections 塾 41 2 of the substrate 41 and the first connection 420 of the first wafer 420. A welding pad 423 and an underfill 425 fill the gap between the upper surface 411 of the substrate 410 and the first active surface 421 of the first wafer 420 and seal the bumps 424. In this embodiment, The first chip 4 2 0 may be smaller than the dummy chip 4 3 0. The dummy wafer 430 is disposed on the first wafer 420. The dummy wafer 430 has an upper surface 431 and includes a ground layer 432 formed on the upper surface 431. In this embodiment, the ground layer 432 is formed away from the back surface 422 of the first chip 420 and is formed on the upper surface 431 of the dummy chip 43. The back surface 422 of a wafer 420, the ground layer 432 completely covers the upper surface 4 31 of the dummy wafer 4 3 0, and the size of the dummy wafer 4 3 0 is larger than that of the second wafer 44 0. In the embodiment, the ground layer 43 2 is a copper layer. One end of the grounding devices 460 is connected to the grounding layer 432. In this embodiment, the grounding devices 46 are ground bonding wires, which are connected to the grounding layer 4 3 2 to the substrate 4 1. This corresponds to some ground pads 414. The first wafer 4 4 0 is placed on the dummy wafer 430 with the second active surface 4 41 facing upward, and the back of the second wafer 440 is bonded with an adhesive 434.

1245393 on page 13 Brief description of the drawings [Schematic representation of the month 1st figure: Know more: μ Recognition field 2nd figure: Schematic cross-section diagram of the package structure according to the present invention = ★ 隹 f In a specific embodiment, a multi-wafer stacking, multi-wafer stacking, multi-wafer stacking, multi-wafer stacking, and multi-wafer stacking are shown in FIG. 3 according to the present invention. Schematic sectional view of the structure of the third specific embodiment; and FIG. 5 • Schematic cross-section of the fourth specific embodiment of the structure la according to the date of the issue + beginning " even, "哉 t. Simple explanation of the component symbols: 100-chip stacked package structure 110 substrate 120 first wafer 1 2 3 first fresh wafer 1 3 0 dummy wafer 140 second wafer 150 first bonding wire 1 6 0 second bonding wire 170 sealing compound 2 〇 0 Multi-chip stacked package structure 210 Upper surface of substrate 211 Fresh surface 214 Lower surface 111 Upper surface 121 First active surface 124 Adhesive layer 1 31 Thin film adhesive 141 Second active surface 11 2 Connection pad 122 Adhesive layer 142 Second solder pad 2 1 2 Connection pad

1245393 Brief description of the drawing 2 2 ◦ First wafer 2 2 3 Adhesive glue 2 3 0 Virtual wafer 233 Adhesive material 240 Second wafer 2 5 0 First 'fresh wire 260 Second welding wire 2 7 0 Grounding device 280 sealant 3 0 0 multi-chip stacking seal 31 0 substrate 31 3 solder ball 320 first wafer 3 2 3 ground pad 3 3 0 dummy wafer 3 3 3 underfill 3 4 0 second wafer 3 5 0 first bonding wire 380 seal Colloid 400 multi-chip stacking seal 410 substrate 413 second connection pad 420 first wafer 4 2 3 first fresh 221 first active surface 2 2 4 ground welding 231 surface 234 glue 241 second active surface mount structure 311 upper surface 314 lower surface 321 first active surface 324 crystal adhesive 331 surface 334 adhesive material 341 second active surface 360 second fresh wire mounting structure 411 upper surface 41 4 ground pad 421 first active surface 424 bump 2 2 2 first welding Pad 2 3 2 Ground layer 242 Second solder pad 3 1 2 Connection pad 322 First solder pad 332 Ground layer 342 Second solder pad 370 Grounding device 4 1 2 First connection pad 422 Back surface 425 Filler at the bottom «

Page 16 1245393 Brief description of the diagram Ί 3 0 dummy wafer 433 glue material 440 second wafer 450 welding wire 4 3 1 upper surface 434 glue material 441 second active surface 460 grounding device 4 3 2 ground layer 442 second pad 470 Sealing gel

Page 17

Claims (1)

O, W 1245393 ___ Case No. 93119549 VI. Patent application scope t = Month amendment [Patent application scope] 1 λ A multi-chip stack package structure including: a substrate having an upper surface and containing a plurality of formations A connecting pad on the surface; '~ previous first wafer' which has a first active surface and includes a plurality of first pads formed on the first active surface, and the first chip is based on the first main substrate; ^ The moving surface is set up on the upper surface of the substrate; a dummy die is set on the first chip, and the dummy chip has a ground iayer, which is A second wafer formed on the surface of the virtual wafer 9 has a second active surface and includes a plurality of second pads formed on the second active surface. The second wafer is based on the second active surface. Face-up manner is provided on the dummy wafer; a plurality of first bonding wires are connected to the first bonding pads of the first wafer and corresponding connection pads of the substrate; a plurality of second bonding wires are The second pads connected to the second chip Corresponding to the connection pads of the substrate; and at least one grounding means, which is connected to the ground-based layer. 2. The multi-chip stacked package structure described in item 1 of the scope of the patent application, wherein the grounding device is a ground bonding wire, and the grounding layer is formed on the -t surface of the dummy wafer. 3. The multi-chip stacked package structure described in item 2 of the scope of the patent application, wherein the ground bonding wire is used to connect the ground layer to one of the connection pads of the board. 1245393 ---- Case No. 93119549__ Year, Month, and Date Amendment VI. Patent application scope 4. Multi-chip stacked package structure as described in item 1 of the patent application scope, wherein the grounding device is a grounding bump and the grounding layer is Formed on the lower surface of the dummy wafer. i. The multi-chip stacked package structure according to item 2 or 4 of the scope of the patent application, wherein the grounding device is connected to the ground layer to at least one ground pad of the first chip.苴 The multi-chip stacked package structure described in item 4 of the scope of the patent application, which includes an underfill, which fills the gap between the virtual chip and the first active surface of the first chip and Seal these grounding devices. Gan 7 i is the multi-chip stacked package structure described in item 1 of the scope of the patent application, and the size of the dummy chip is not smaller than that of the second chip. The basin has a multi-chip stacked package structure as described in item 7 of the scope of the patent application, and the ground layer has an area of the second active rhyme of not less than the second chip. Among them, the multi-chip stacked package structure 10 described in the first item of the scope, and the M-layer = layer system completely covers the surface of the virtual chip. The multi-chip stacked package structure described in Item 1 of the Fu Zhong P. Patent. The ground layer is a copper layer. In addition, the multi-wafer stacking and sealing structure described in item 1 of the patent scope has a piece of colloid to seal the first wafer, the dummy wafer, and the first bonding wires and the second bonding wires. Welding wire. 1 3 ~ 1 多 The multi-chip stacked package structure described in item 1 of the patent scope c. Sealing gel, which seals the grounding device. Multi-chip stacked package structure as described in Shenyan Patent Scope Item 丨 1245393 — case number 931195 cents 6. Scope of patent application TH The second chip is-RFID (_i0 Frequency Identihcatwn, radio frequency identification) chip. 1 4. If the scope of patent application is the first! Industrial Mv M: Φ ^ ^ +, the chip stack package packaging structure described by the staff member, and the substrate is a ball grid array substrate (bau d BGA). ay, 15. A multi-chip stacked structure, comprising: a substrate having an upper surface and including a plurality of connection pads formed on the upper surface; and a first piece, which is provided on the upper surface of the substrate, The first wafer has a first active surface and includes a plurality of first pads formed on the first active surface; a dummy die is disposed on the first wafer, and the dummy wafer It has a ground iayer, which is formed on a surface of the virtual chip; a second chip, which has a second active surface and includes a plurality of second pads formed on the second active surface The second chip is disposed on the dummy chip with the second active surface facing up; and at least one grounding device connected to the ground layer. 16. The multi-wafer stacked structure according to item 5 of the scope of the patent application, wherein the first wafer is disposed on the upper surface of the substrate with the active side facing upward. 17. The multi-chip stacked structure according to item 16 of the scope of patent application, wherein the ground layer faces the active surface of the first chip. 18. The multi-chip stacked structure as described in item 16 of the scope of patent application, wherein Page 20 1245393 93119549 bump, the ground layer is formed on the dummy wafer electrically connects the ground layer to the multi-chip stack structure described in item 18 of the first wafer, and it is also filled in The dummy chip is spaced from the first chip and the ground devices are to be sealed. The multi-chip stacked structure according to item 15, wherein the moving surface is arranged on the top surface of the substrate. 6. Scope of patent application The grounding device is a grounded lower surface, and the grounding device has at least one grounding pad. 19. If the scope of patent application includes an underfill between the first active surface 20, if the scope of patent application includes the first wafer, the multi-chip stacking structure described in item 20 of the main surface 0 is provided on the main surface The substrate and the bumps of the first wafer are electrically connected to the substrate and the first, and the other one of the first and second crystals. 1. If the scope of the patent application includes a plurality of bumps between the active surfaces, and the first The multi-wafer stacked structure according to item 21, further comprising filling the substrate and the first wafer with the sealed bumps. The multi-wafer stacked structure according to item 20, wherein one of the wafers has a back side. Among them, among them, 〇 Among them 22, if the scope of patent application includes an underfill, the gap of the first active surface is 2 3, if the scope of patent application, the ground layer is away from the 24th, such as the scope of patent application 1 5 The multi-chip stack structure described in the item, the grounding device is a ground wire, and the ground layer is formed on the virtual upper surface. 25. According to the multi-chip stack structure described in item 24 of the patent application scope, the ground bonding wire is one of the connections connecting the ground layer to the substrate. 26. Multi-chip stack described in item 15 of the patent application scope. structure, Page 21 1245393 — — Case No. 9311QFUQ__Year Month Day__Amendment__ 6. The scope of the patent application, the grounding device is at least one ground pad that connects the ground layer to the first chip. 27. The multi-wafer stacked structure described in item 5 of the patent application scope, wherein the size of the dummy wafer is not smaller than that of the second wafer. 28. The multi-chip stacked structure described in item 27 of the scope of the patent application, wherein the ground layer has a second active area that is not less than the second chip. 29. The multi-chip stacked structure described in item 5 of the scope of the patent application, wherein the ground layer completely covers the surface of the virtual chip. 30. The multi-chip stacked structure as described in item 15 of the scope of the patent application. The ground layer is a copper metal. Langzhong 31. The multi-wafer stacked structure as described in item 15 of the scope of the patent application, further comprising a colloid to seal the first wafer, the dummy wafer, and the second wafer. 32. The multi-chip stacked structure as described in item 15 of the scope of the patent application, which further includes a colloid, which seals the grounding device. 33. The multi-chip stack structure described in item 15 of the scope of patent application, wherein the first day of the film is an RFID (Radio Frequency Identification (radio frequency identification) chip. 34. The multi-wafer stacked structure described in item 15 of the scope of the patent application, wherein the -Hai substrate is a ball grid array substrate (BGA). Page 22