TWI313924B - High frequency ic package for uniforming bump-bonding height and method for fabricating the same - Google Patents

Description

1313924 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a high-frequency integrated circuit packaging technology, and more particularly to a high-frequency integrated circuit package with uniform bump bonding height. Structure 1 [Prior Art]

Integral circuit packaging technology is expected to protect higher frequency, faster computing integrated circuit wafers with a more simplified process and lower package cost. However, the current packaging method is to use a wire bonding or flip chip bonding technology in the electrical connection between the wafer and the substrate. The wire connection has electricity = transmission distance, and cannot be used for the high frequency integrated circuit, and the flip chip bonding needs to be covered. The surface of the crystal wafer forms a Redistribution Uyer (RDL) to make the bumps required for the flip chip are arranged in a matrix, but the cost is high, especially for a memory package of a lower pitch. Referring to FIG. 1 , a conventional integrated circuit package structure mainly includes a substrate 1 10 , a wafer 1 20 , a die layer 1 30 , a plurality of bonding wires 1 40 , and a colloid 丨 5 . 〇 and a plurality of external terminals 丄. The first surface 1 1 1 of the substrate 10 serves as a die-bonding surface, and the second surface U2 of the substrate 1 1 作为 serves as a spherical surface. Typically, the substrate 1 10 is a rigid printed circuit board and has a slot 13 for wire passing. The adhesive layer 13 is formed on the active surface i 2 of the wafer 120 to adhere to the active surface 121 of the wafer 120. The active surface 1 2 1 of the wafer 12 is formed with a plurality of pads 1 22 . The bonding wire 52 2 313924% is electrically connected to the wafer 12 2 and the substrate 〇 and the sealing film 150 is sealed with the sealing material 150 and the bonding wires 40. The solder ball external terminals 16 are bonded to the second surface 112 of the substrate η , to be externally bonded (s ΜΤ) to an external printed circuit board. However, the length of these bonding wires is not conducive to the transmission of high frequency ic signals. In addition, it is desired to be thinner and lighter in high-frequency integrated circuit package products. Φ [Summary of the Invention] The main object of the present invention is to provide a southwest-integrated circuit package structure and a method for fabricating the same bumps and sigma, which can be flip-chip bonded by a low-cost wafer in which non-matrix arrays are arranged. , to reduce the complexity of the process and increase the mass production speed 'and has a short electrical path, to prevent punching and packaging thinning effect. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a high-frequency integrated circuit package structure in which a uniform bump is bonded to a high φ degree mainly comprises a substrate, a multi-stage adhesive layer, a wafer, and a plurality of external terminals. The substrate has a first surface and a second surface, wherein a plurality of bump pads are formed on the first surface. The multi-stage adhesive layer is formed on the first surface of the substrate. The wafer has an active surface and a plurality of bumps on the active surface. The wafer is flip-chip mounted on the first surface of the substrate to bond the bumps to the bumps. a pad, and the multi-stage adhesive layer adheres to the active surface of the wafer. The external terminals are disposed on the second surface of the substrate. The object of the present invention and solving the technical problems thereof can also adopt the following techniques: 6 1313924

The technical measures are further realized. In the above-mentioned prior art, a wide circuit package structure, each bump pad has a recessed area ′ to increase m #^ s plus the bonding area of the bumps. In the aforementioned south-frequency integrated package structure, the bumps are tin-lead bumps and the bump pads are formed with a nickel-gold layer. In the above two-frequency integrated circuit structure, the bumps are gold bumps, and the bump pads are opened to form a fresh layer to facilitate soldering of the bumps. -

In the above-described high-frequency integrated circuit package structure, solder balls are included. In the aforementioned high-frequency integrated circuit package structure, a DDR3 memory chip. In the aforementioned high-frequency integrated circuit, the circuit film is in the % & package structure. The external terminals ’ the wafer is the substrate

The wafer size in the aforementioned high-frequency integrated circuit package structure. [Embodiment] The substrate is close to the second embodiment of the present invention. In the first embodiment, the uniform bump bonding height mainly includes a substrate 210, and a two-frequency integrated circuit package. A multi-stage adhesive layer 2 2 0, 2 3 0 and a plurality of external terminals 2 4 Q are constructed. The substrate 210 has a dew-surface 21 1 and 212, wherein the first surface has a sheet 2 1 3 . The substrate 210 can be printed with a plurality of bump pads or a circuit film formed on the second surface. Better 7 1313924 / 押乙月日修 ( <) 正^^ 换页 '1_____

The substrate 210 is a circuit film such as a COF flexible film, which is advantageous for thinning, weight reduction, and thermal resistance reduction. Further, in the present embodiment, the substrate 210 is accessible to the wafer size. The second surface 212 of the substrate 210 is formed with a plurality of ball pads 215. The substrate 210 further includes a circuit layer 217 on the first surface 211 and a plurality of electrical vias 2 1 6 ′ extending through the substrate 211 to electrically connect the bump pads 2 1 3 of the substrate 2 1 0 and the pads Ball pad 2 1 5. In addition, the first surface 211 of the substrate 210 may be formed with a solder resist layer (not shown) to partially cover the circuit layer 217 of the substrate 210. The multi-stage adhesive layer 220 is formed on the first surface 21 of the substrate 210. The multi-stage adhesive layer 220 comprises a multi-stage cured resin. For example, the multi-stage adhesive layer 220 can be printed on the substrate 210 in the A-stage, and the substrate 2 10 is baked to be partially Curing the multi-stage adhesive layer 220 to the B-stage, which has a viscosity

The crystal characteristic is attached to the substrate 210 in a film type, and the multi-stage adhesive layer 220 will be fully cured to the C-stage when the final product is shipped. In addition, in various embodiment variations, the multi-staged polycrystalline layer 220 of the B-stage can be further subdivided into more localized ripening states, such as B1, B2, B3, and the like. The wafer 230 has an active surface 231 and has a plurality of bumps 233 on the active surface 23 1 . The wafer 230 is overlying the first surface 211 of the substrate 210 such that the bumps 233 are metal bonded to the bump pads 2 1 3 , and the multi-stage adhesive layer 220 is adhered. The active surface 23 1 of the wafer 230 is connected. Utilize the multi-stage 8 '1313924

The bonding layer 220 maintains the flip-chip bonding gap and the bonding wafer. The wafer 230 may not need to be fabricated with a reconfigured wiring layer (RDL). The bumps 233 may be directly disposed above the original plurality of pads 232 of the wafer 230. Located at the center or periphery of the active surface 231. In this embodiment, the bumps 233 are gold bumps, and the bump pads 213 are formed with a solder layer 2 1 4 to solder the bumps 23 3 to achieve flip chip bonding. Electrical connection. Therefore, the electrical connection path between the δ sinusoidal wafer 230 and the substrate 210 is short, and the bonding height of the bumps 233 is uniform, and the gold wire formed by the wire can be omitted, and the reconfigured circuit layer of the conventional flip chip is omitted. (RDL) for low cost south frequency packages. Preferably, the wafer 306 is a DDR3 memory chip having a frequency of more than 500 MHz. In addition, the back surface of the wafer 230 is preferably exposed or otherwise provided with a heat sink (not shown) to increase the heat dissipation effect. The external terminals 240 are disposed on the second surface 2 1 2 ' of the substrate 2 for external bonding. In this embodiment, the external terminals 240 comprise solder balls disposed on the ball pads 215. In various embodiments, the solder terminals may be replaced by solder paste, metal balls, metal plugs or ACF conductive paste to form the external terminals 240. By the multi-stage adhesion layer 220 around the bumps 23 3 , when the bumps 2 3 3 are metal-bonded to the bump pads 2 1 3 , the wafers 2 3 0 are not easily tilted to maintain The joint height of the bumps 2 3 3 is uniform, and it is not necessary to refill the underfill material. In addition, the electrical connection between the wafer 230 and the substrate 210 is omitted from the conventional wiring electrical connection step, and the process is simplified. 9 • 1313924 :· In conjunction with Figures 3A to 3 C, the fabrication process of the high-frequency integrated circuit package structure 200 is disclosed. First, as shown in FIG. 3A, a substrate 2 1 0 ' is first provided with a plurality of bump blocks 2丨3 formed on the first surface 2 11 and a plurality of second surfaces 2 1 2 formed thereon. Ball pad 2 1 5. The bump pads 2丨3 and the ball pads 215 are electrically connected to the electrical vias 21, 6 and the electrical vias 21, 6 . Then, as shown in Fig. 3B, a multi-stage adhesive layer 220 can be formed on the first surface 211 of the substrate 210 by using a steel plate, and pre-baked into a B-stage before the bonding, to achieve an appropriate supporting effect. Then, as shown in FIG. 3C, the flip chip is disposed on the first surface 211 of the substrate 210, and the bumps 233 of the wafer 230 are bonded to the bump pads 2 1 3 , and The multi-stage adhesive layer 220 is bonded to the active surface 23 1 of the wafer 230. Finally, the external terminals 240 are placed on the 'ball pads 215, and the multi-stage die layer 220 is cured, and the high-frequency integrated circuit package structure 2 shown in FIG. 2 can be fabricated. Referring to FIG. 4, in a second embodiment of the present invention, a high-frequency integrated circuit package structure 300 of a uniform bump bump height is disclosed, which mainly includes a substrate 3 1 , a multi-stage The die layer 32 is, a wafer 3 30 and a plurality of external terminals 3 4 〇. The substrate 3 has a first surface 311 and a second surface 312. The first surface 31 is formed with a plurality of bump pads 3 1 3 , and the second substrate 3 1 0 The surface 3 1 2 is formed with a plurality of ball pads 3 16 . The substrate 3 1 〇 further includes a plurality of electrical vias 3 丨 7 and at least one wiring layer 3 1 8 to electrically connect the bump pads 3 丨 3 and the ball pads 3 丨 6 . In this embodiment, the substrate 310 can be a printed circuit board or a circuit 10 • 1313924 *· film </ RTI> to facilitate thinning and weight reduction of the package. The multi-stage adhesive layer 3 2 is formed on the first surface 3 of the substrate 3 1 . The wafer 3 3 has an active surface 331 and a plurality of bumps 3 3 3 ′ on the active surface 331. The wafer 3 3 is laminated on the first surface 311 of the substrate 310 . Preferably, the bumps 333 are bonded to the bump pads 3 1 3 ′ and the multi-stage adhesive layer 3 2 is bonded to the active surface 3 3 1 该 of the wafer 3 3 较佳 preferably, The bumps 333 are disposed over the fresh plastic 1 332 of the wafer 330 to omit the reconfigured wiring layer of the conventional flip chip. The external terminals 340 are disposed on the second surface of the substrate, and the circumscribing amps 340 can include a solder ball. Preferably, as shown in FIG. 5, each bump pad 3丨3 has a recessed portion 3 1 4 ′ to increase the joint area of the bumps 3 3 3 and prevent the bumps from being covered. 3 3 3 collapsed. In this embodiment, the bumps 3 3 3 are tin bumps and the bump pads 3 1 3 are formed with a nickel gold layer 3 1 5 ' to achieve metal bonding by reflow. Since in the present embodiment %, the wafer 303 is replaced by thermal recompression by reflow to achieve a flip chip bonding operation, 'the supply amount of the multi-stage viscous layer 3 2 0 fails to seal the bumps 333'. The memory package structure 3 can further include a glue 350' formed on the first surface 311 of the substrate 31 and can seal the wafer 330, and can be filled in the space below the wafer 33 'To prevent the occurrence of popcorn (p〇pc〇rn) phenomenon. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, although the present invention has been described above by way of a preferred embodiment.

And all of the simple modifications, equivalent changes, and modifications made by the present invention are within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a conventional integrated circuit package structure. FIG. 2 is a view showing a high-frequency integrated circuit package structure of a uniform bump bonding height according to a first embodiment of the present invention. Schematic diagram. 3A to 3C: In accordance with a first embodiment of the present invention, the integrator circuit package is constructed with a substrate cross-section in the process. Fig. 4 is a cross-sectional view showing another high-frequency integrated circuit package structure of a bump-joining height according to a second embodiment of the present invention. Figure 5 is a partially enlarged cross-sectional view showing one of the bumps of the high frequency product circuit package structure in accordance with a second embodiment of the present invention. [Main component symbol description] The apparent cross section shows the decent surface 100 integrated circuit package structure 110 substrate 111 113th slot 120 wafer 121 main 130 adhesive layer 140 solder 160 external terminal one surface 112 second surface dynamic surface 122 solder Pad line 150 sealant 12 1313924

200 high frequency integrated circuit package structure 2 1 0 substrate 2 1 3 bump pad 2 1 6 electrical via 211 first surface 214 solder layer 217 circuit layer 212 second surface 2 1 5 ball pad 220 multi-stage die Layer 230 wafer 233 bump 231 active surface 232 pad

240 external terminal 3 00 high frequency integrated circuit package structure

3 10 substrate 3 13 bump pad 3 16 ball pad 320 multi-stage adhesive layer 330 wafer 333 bump 3 40 external terminal 3 11 苐 a surface 3 14 recessed area 3 1 7 electrical via 33 1 active surface 3 5 0 sealant 3 12 second surface 3 1 5 gold layer 3 1 8 circuit layer 3 3 2 fresh 塾 13

Claims (1)

• 1313924 X. Patent Application Range: 1. A high-frequency integrated circuit package structure with uniform bump bonding height, comprising: a substrate having a first surface and a second surface, wherein the first surface The upper system is formed with a plurality of bump pads; a multi-stage adhesive layer formed on the first surface of the substrate; a wafer having an active surface and a plurality of bumps on the active surface, the wafer is flip-chip disposed on the substrate On the first surface, the bumps are bonded to the bump pads, and the multi-stage adhesive layer is bonded to the active surface of the wafer; and a plurality of external terminals are disposed on the first surface The second surface of the substrate; wherein each bump pad has a recessed region. 2. The high frequency integrated circuit sealing structure of the uniform bump height according to claim 1, wherein the bumps are tin-lead bumps and the bump pads are formed Nickel gold layer. 3. The high-frequency integrated circuit package structure of the uniform bump-bonding height according to claim 1, wherein the bumps are gold bumps, and the bump pads are formed with a solder layer. . 4. The high frequency integrated circuit sealing structure of the uniformized bump joint height as described in the scope of the patent application, wherein the external terminals comprise fresh balls. 5, such as the scope of patent application! The high-frequency integrated circuit package structure of the uniformized bump bonding height described in the item, wherein the substrate is a circuit film. 6. The 14 1313924 high-frequency integrated circuit package structure of the uniform bump bonding height as described in the patent application scope, wherein the substrate is a printed circuit board 0 ^, and a uniform bump bonding height is high. The method of packaging a capacitor circuit includes: providing a substrate having a first surface and a second surface, wherein the first surface is formed with a plurality of bump pads; forming a multi-stage adhesive layer On the first surface of the substrate; The flip chip is provided with a wafer on the first surface of the substrate, the wafer has an active surface and a plurality of bumps on the active surface, the bumps are bonded to the 4b &amp; :i 4f 〇 » ^ —Bumping pads, and 5H multi-stage bonding layer bonding. a g Hai active surface of the sunday film; and a plurality of external terminals are disposed on the second surface of the substrate. ^The method of encapsulating a height of a two-integrated body circuit according to the seventh aspect of the patent application, wherein each bump pad has - 9. If the application of the patent range is the same as that of the unification of the bumps, the inter-frequency block circuit is sealed, and the H-mounting method is that the bumps are tin-lead convex two? The bump pads are formed with a gold layer. 10, such as the application of the δ month patent range of the high-frequency integrated circuit package, the height of the bumps and the bumps (4) f, wherein the bumps are gold bumps, &quot;, Such as the scope of patent application;: "solder layer. The high-frequency integrated circuit package side, the uniformized bump bonding height ball. The method of the external terminal includes welding 15 1313924 12 , such as the patent application model, the 笫 笫 7 纠 、, +, — ^ ^ 固 7 7 item of the uniform bump ancient high-frequency integrated circuit sealing square mouth An inter-package method in which the substrate is a high-frequency integrated circuit package method of a height of a bump of a bumper bump, as described in the patent application, 笫7, ,,,,,,,,, A, the substrate is a printed circuit board. 14. The high-frequency integrated circuit package structure of the block bonding height, comprising: a bungee π W π π — π back surface is formed with a plurality of bump pads; -= stage viscous layer ' is formed on the surface of the substrate [a surface; a wafer's system, with - active surface and plural a bump on the active surface, the wafer is flip-chip disposed on the first surface of the substrate, such that the bumps are bonded to the bump pads, and the multi-stage adhesive layer is Bonding the W active surface; and a plurality of external terminals disposed on the second surface of the substrate; wherein a solder layer is formed on the two bump pads to solder the bumps. (1) A high-frequency integrated circuit package structure of a uniform bump bonding height as described in claim 14, wherein the external terminals are packaged with solder balls. Η 尚 Η Η Η Η Η Η Η 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致 一致17. The high frequency integrated circuit package structure of the uniform bump bonding height as described in claim 14, wherein the substrate is a printed circuit 16 '1313924 Λ *· board. 18. A high frequency integrated circuit package structure having a uniform bump bond height as described in claim 14 wherein the bumps are gold bumps. 17 1313924 VII. Designated representative map: (1) The representative representative of the case is: (2). (2) Brief description of the components of the representative figure: 200 high-frequency integrated circuit package structure 212 second surface 215 ball pad 232 pad 210 substrate 211 first surface 213 bump pad 214 solder layer 2 1 6 electrical conduction Hole 21 7 circuit layer 220 multi-stage adhesive layer 230 wafer 231 active surface 233 bump 240 external terminal 8. If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention: