1321349 ¥ 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種打線型態之多晶片堆疊封 造’特別係有關於一種可將複數個同尺寸晶片主動 上堆疊之多晶片堆疊封裝構造。 【先前技術】 在多晶片堆疊封裝構造領域中，複數個晶片係 主動面朝向同一方向地由一基板往上縱向堆疊並 連接至該基板’可有效縮小封裝構造之表面接合 (footprint) ’以避免多晶片堆疊封裝構造之尺寸過 通常在晶片與晶片之間通常會設置一中央間 (central spacer)，以墊高晶片間距，防止上層晶片 下方銲線。然而，該中央間隔物係需小於該下層晶 不能播到該下層晶片之銲塾，以供打線接合，使得 央間隔物遠小於該下層晶片，因此造成該中央間隔 於上層晶片在其周邊之打線支樓力不足，故打線在 晶片之打線接合壓力會導致上層晶片斷裂。 請參閱第1圖所示，一種習知的多晶片堆疊封 造100主要包含一基板11()、一第一晶片12〇、一 晶片1 3 0、複數個第一銲線1 4 1、複數個第二銲線 以及一中央間隔物150。該基板110係具有一上表δ 以及一下表面112，其中複數個打線接指113係形 該上表面111’複數個接觸墊U4或外接端子係可 於該基板110之該下表面112。該第一晶片120之 裝構 面朝 以其 電性 面積 大。 隔物 觸壓 片且 該中 物對 上層 裝構 第二 142 illl 成於 形成 一第 6 1321349 一背面122係黏貼於該基板n〇之該上表面i 一晶片120係具有複數個第一銲墊123，其係 第一晶片120之—第一主動面121上。利用打 該些第一銲線141電性連接該些第一銲墊123 1 1 0之該些打線接指Η 3。該第二晶片1 3 0係 一晶片120上。請再參閱第1圖所示，該中 1 50之尺寸係小於該第一晶片i 20與該第二晶 尺寸’該中央間隔物1 5 〇係黏設於該第一晶片 第一主動面121，並顯露該些第一銲墊123, 間隔物1 5 0係位於該第一晶片i 2 0與該第二晶 間。該第二晶片1 3 0之一第二背面1 3 2係設置 間隔物1 5 0上，且該第二晶片i 3 0之該第二背 不與該些第一銲線141直接接觸。通常該中 150係可為一膠片、一虛晶片或一金屬片等等 晶片取放（pick and pi ace)方式設置於該第一晶 該第一主動面121上。該第二晶片130係具有 二銲墊133，其係形成於該第二晶片130之一 面131上。該些第二銲線142係以打線方式連 二銲墊133至該基板110。通常可另以一模封 密封該第一晶片120、該第二晶片130、該些 Ml與該些第二銲線142 » 請再參閱第1圖所示，當該第二晶片130 中央間隔物150上時，由於該中央間隔物150 第二晶片1 3 0，使得該第二晶片1 3 0之周邊無 11。該第 形成於該 線形成之 至該基板 設於該第 央間隔物 片130之 1 20之該 且該中央 片130之 於該中央 面132係 央間隔物 ，以如同 片120之 複數個第 第二主動 接該些第 膠體160 第一銲線 設置於該 係小於該 法獲得來 7 1321349 自該中央間…50之支擇而成懸空部分，故在該第二 晶片13G於打線作料，打線接切針㈣合在設有該 些第二鲜塾133之該第-戶ΰ ηΛΛ> , 一晶片1 3 0之位置無法受到該中 央間隔物150之有效±擔，而於士地， 叉得而於支撐點引發斷裂1 3 4， 進而造成結構損壞。 【發明内容】 本發明之主要目的係在於提供一種多晶片堆疊封裝 構造，可在不需要在晶片堆疊之間設置中央間隔物之條 件下，堆疊上層晶片且不會壓觸至下方銲線的問題另 能在上層晶片設有銲墊之位置提供足夠打線支撐，避免 上層晶片由支撐點斷裂之問題，藉以提高產品之良率。 本發明之次一目的係在於提供一種多晶片堆疊封裝 構造，利用一邊緣間隔膠體預先包覆複數個銲線，當壓 模形成一模封膠體時，不會有因沖線導致銲線短路或/ 與線斷裂造成斷路之問題。 本發明之再一目的係在於提供一種多晶片堆疊封裝 構造’可避免因晶片堆疊不正或傾斜之現象導致銲線觸 碰上層晶片背面。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種多晶片堆疊封裝構造主 要包含一基板、一第一晶片、複數個第一銲線、一第一 邊緣間隔膠體（peripherally stand-off encapsulant)、一 第二晶片以及複數個第二銲線。該第一晶片係設置於該 基板上並具有一第一主動面。該些第一銲線係電性連接 :.-¾ 8 1321349 該第一晶片與該基板。該第一邊緣間隔膠體係形成於該 第一晶片之第一主動面之一邊緣、該第一晶片之側面輿 該基板上並且高出於該第一主動面，以至少密封該些第 一銲線之一部位。該第二晶片係設置於該第一邊緣間隔 膠體上並具有一第二主動面。該些第二銲線係電性連接 該第二晶片與該基板。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的多晶片堆疊封裝構造中，該第一邊緣間隔 膠體係可具有倒L形截面。 在前述的多晶片堆疊封裝構造中，該第一邊緣間隔 膠體係可高於該些第一銲線之弧高。 在前述的多晶片堆疊封裝構造中，該第一邊緣間隔 膠體係可完全密封該些第一銲線。 在前述的多晶片堆疊封裝構造中，可另包含有一模 封膠體，其係密封該第一晶片、該第二晶片與該第一邊 緣間隔膠體。 在前述的多晶片堆疊封裝構造中，該模封膠體可更 填充於該第一晶片與該第二晶片之中央間隙。 在前述的多晶片堆疊封裝構造中，可另包含有一第 二邊緣間隔膠體，其係形成於該第二晶片之第二主動面 之一邊緣、該第二晶片之側面與該第一邊緣間隔膠體上 並且高出於該第二主動面，以至少密封該些第二銲線之 一部位。 ·'· .5=¾ 9 1321349 在前述的多晶片堆疊封裝構造中，該第二晶片係可 更具有一第二背面，該第二背面係形成有一晶背保護 c«〇a 膠。 在前述的多晶片堆疊封裝構造中，該第二晶片係可更 具有一第二背面，該邊緣間隔膠體係直接黏著該第二晶 片之該第二背面。 【實施方式】 依據本發明之第一具體實施例，揭示一種多晶片堆 疊封裝構造。第2圖係為該多晶片堆疊封裝構造之截面 示意圖。第3圖係為該多晶片堆疊封裝構造在製程中形 成一邊緣間隔膠體之立體示意圖。第4A至4C圖係為 該多晶片堆疊封裝構造於製程中一基板之截面示意圖。 請參閱第2圖所示，一種多晶片堆疊封裝構造200 主要包含一基板210、一第一晶片 220、一第二晶片 230、複數個第一銲線241、複數個第二銲線242以及 至少一邊緣間隔膠體250。該基板2 1 0係具有一上表面 211以及一下表面212，其中該上表面211係形成有複 數個打線接指2 1 3，以供打線方式與晶片電性連接。該 基板210係可另具有複數個形成於該下表面212之接觸 墊214。依應用產品之不同變化，該基板210亦可為一 導線架。 該第一晶片220係具有一第一主動面221及一相對 之第一背面222，其中該第一主動面221係形成有複數 個第一銲墊2之3。該第一晶片220之該第一背面222係 10 220 1321349 黏貼於該基板210之該上表面211，使該第一晶片 係設置於該基板2 1 0上。在黏晶之後，利用打線形 些第一銲線241，以電性連接該些第一銲墊223與 板2 1 0之該些打線接指2 1 3，達到該第一晶片220 基板210之電性互連。 請參閱第2及3圖所示，該邊緣間隔膠體250 成於該第一晶片220之第一主動面221之一邊緣、 _ 一晶片220之側面與該基板210上並且高出於該第 動面22 1 ’以至少密封該些第一銲線241之一部位 本實施例中’該邊緣間隔膠體25 0係可具有倒L 面。因此，該邊緣間隔膠體250具有間隔維持、晶 • 緣打線支撐、預密封銲線以防止沖線之功效，更由 邊緣間隔膠體250形成於該第一晶片220之側面與 板210上，能對於該第一晶片22〇產生更加強的黏 定’此外能將打線時應力吸收或分散至該基板21〇 _ 請再參閱第2圖所示，該邊緣間隔膠體250係 於該些第一銲線24 1之弧高，以防止當該第二晶片 於打線作業時’因打線接合時對該第二晶片23〇施 應力過大而造成該第二晶片23〇之背面傾斜而壓 些第一銲線241。較佳地，該邊緣間隔膠體250係 全密封該些第一銲線241，以避免在後續壓模製程 沖線導致該些第一銲線241短路或/與線斷裂造成 之問題。請參閲第3圏所示，可利用點膠技術藉由 膠針頭10提供尚為液態或膠稠態之該邊緣間隔 π 成該 該基 與該 係形 該第 一主 。在 形戴 片邊 於該 該基 著固 〇 可高 230 加之 觸該 可完 中因 斷路 一點 膠體BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire-type multi-wafer stacking package, particularly relating to a multi-wafer stack package capable of actively stacking a plurality of wafers of the same size. structure. [Prior Art] In the field of multi-wafer stacked package construction, a plurality of wafer system active faces are stacked longitudinally from a substrate upwardly and connected to the substrate in the same direction to effectively reduce the surface footprint of the package structure to avoid The size of the multi-wafer stacked package structure is usually such that a central spacer is usually disposed between the wafer and the wafer to increase the wafer pitch and prevent the bonding wires under the upper wafer. However, the central spacer system needs to be smaller than the solder layer of the lower layer crystal which cannot be broadcast to the lower layer wafer for wire bonding, so that the central spacer is much smaller than the lower layer wafer, thereby causing the central interval to be lined at the periphery of the upper layer wafer. The strength of the support is insufficient, so the bonding force of the wire bonding on the wafer causes the upper wafer to break. Referring to FIG. 1 , a conventional multi-wafer stack package 100 mainly includes a substrate 11 ( ), a first wafer 12 , a wafer 1 30 , a plurality of first bonding wires 1 4 1 , and a plurality A second bond wire and a central spacer 150. The substrate 110 has an upper surface δ and a lower surface 112, wherein a plurality of wire bonding fingers 113 are formed on the upper surface 111. A plurality of contact pads U4 or external terminals are available on the lower surface 112 of the substrate 110. The first wafer 120 is mounted with a larger electrical area. The spacer touches the sheet and the intermediate layer is formed on the second layer 142 ill1 to form a sixth 1321349. The back surface 122 is adhered to the upper surface of the substrate n. The wafer 120 has a plurality of first pads. 123, which is on the first active surface 121 of the first wafer 120. The wire bonding fingers 3 are electrically connected to the first pads 123 1 1 0 by using the first bonding wires 141. The second wafer 130 is mounted on a wafer 120. Referring to FIG. 1 again, the size of the middle 150 is smaller than the first wafer i 20 and the second crystal size 'the central spacer 15 5 is adhered to the first active surface 121 of the first wafer. And exposing the first pads 123, and the spacers 150 are located between the first wafers i20 and the second intercrystals. The second back surface 1 3 2 of the second wafer 110 is disposed on the spacer 150, and the second back of the second wafer i 3 0 is not in direct contact with the first bonding wires 141. Generally, the medium 150 series may be a film, a dummy wafer or a metal piece, and the like, and a chip pick and pi ace is disposed on the first crystal first active surface 121. The second wafer 130 has a second pad 133 formed on one surface 131 of the second wafer 130. The second bonding wires 142 are connected to the substrate 110 by wire bonding 133. The first wafer 120, the second wafer 130, the M1 and the second bonding wires 142 are generally sealed by a mold. Please refer to FIG. 1 again, when the second wafer 130 is centered. At 150, the central wafer 150 has a second wafer 1 300, so that there is no 11 around the second wafer 130. The first portion formed on the line to which the substrate is disposed on the first spacer sheet 130 and the central sheet 130 is disposed on the central surface 132 to form a plurality of spacers Secondly, the first bonding wire is connected to the first bonding wire 160, and the first bonding wire is disposed in the system. The first bonding wire is smaller than the method obtained by the method. The first wafer 13 is selected from the central portion 50 to be a suspended portion. Therefore, the second wafer 13G is grounded and wired. The cutting needle (4) is integrated with the first ΰ ΛΛ ΛΛ 设有 设有 设有 设有 , , , , , , , , , 一 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片The fracture 1 3 4 is induced at the support point, which causes structural damage. SUMMARY OF THE INVENTION The main object of the present invention is to provide a multi-wafer stacked package structure in which an upper layer wafer can be stacked without pressing on the lower bonding wire without providing a central spacer between the wafer stacks. In addition, sufficient wire bonding support can be provided at the position where the upper wafer is provided with a bonding pad to avoid the problem that the upper wafer is broken by the supporting point, thereby improving the yield of the product. A second object of the present invention is to provide a multi-wafer stack package structure in which a plurality of bonding wires are pre-coated with an edge spacer colloid, and when the stamper forms a molding compound, there is no short circuit of the bonding wire due to the punching line or / Problem with the line break causing an open circuit. It is still another object of the present invention to provide a multi-wafer stacked package structure that avoids the solder wire from contacting the back side of the upper wafer due to a phenomenon in which the wafer stack is not aligned or tilted. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a multi-wafer stacked package structure mainly includes a substrate, a first wafer, a plurality of first bonding wires, a first edge-off encapsulant, a second wafer, and a plurality of second Welding wire. The first wafer is disposed on the substrate and has a first active surface. The first bonding wires are electrically connected: -3⁄4 8 1321349 the first wafer and the substrate. The first edge spacer gel system is formed on one edge of the first active surface of the first wafer, the side of the first wafer is on the substrate and is higher than the first active surface to seal at least the first solder One part of the line. The second wafer is disposed on the first edge spacer and has a second active surface. The second bonding wires are electrically connected to the second wafer and the substrate. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing multi-wafer stacked package construction, the first edge spacer system may have an inverted L-shaped cross section. In the foregoing multi-wafer stacked package construction, the first edge spacer system may be higher than the arc height of the first bonding lines. In the foregoing multi-wafer stacked package configuration, the first edge spacer system can completely seal the first bonding wires. In the foregoing multi-wafer stacked package configuration, a molding compound may be further included which seals the first wafer, the second wafer and the first edge spacer. In the foregoing multi-wafer stack package configuration, the mold sealant may be further filled in a central gap between the first wafer and the second wafer. In the foregoing multi-wafer stack package structure, a second edge spacer colloid may be further formed on one edge of the second active surface of the second wafer, the side of the second wafer and the first edge spacer colloid Up and up from the second active surface to seal at least one of the second bonding wires. In the foregoing multi-wafer stack package configuration, the second wafer system may further have a second back surface, and the second back surface is formed with a crystal back protection c«〇a glue. In the foregoing multi-wafer stack package configuration, the second wafer system may further have a second back surface, and the edge spacer rubber system directly adheres to the second back surface of the second wafer. [Embodiment] According to a first embodiment of the present invention, a multi-wafer stack package structure is disclosed. Figure 2 is a schematic cross-sectional view of the multi-wafer stacked package construction. Figure 3 is a perspective view of the multi-wafer stack package structure forming an edge spacer colloid in the process. 4A to 4C are schematic cross-sectional views showing a substrate of the multi-wafer stack package constructed in the process. Referring to FIG. 2 , a multi-wafer stacked package structure 200 mainly includes a substrate 210 , a first wafer 220 , a second wafer 230 , a plurality of first bonding wires 241 , a plurality of second bonding wires 242 , and at least An edge spacer colloid 250. The substrate 210 has an upper surface 211 and a lower surface 212. The upper surface 211 is formed with a plurality of wire bonding fingers 201 for electrically connecting to the wafer. The substrate 210 can have a plurality of contact pads 214 formed on the lower surface 212. The substrate 210 can also be a lead frame depending on the application. The first wafer 220 has a first active surface 221 and an opposite first back surface 222. The first active surface 221 is formed with a plurality of first pads 2 . The first back surface 222 of the first wafer 220 is adhered to the upper surface 211 of the substrate 210, so that the first wafer is disposed on the substrate 210. After the die bonding, the first bonding wires 241 are wire-shaped to electrically connect the first bonding pads 223 and the bonding wires 2 1 3 of the board 2 10 to reach the first wafer 220 substrate 210. Electrical interconnection. Referring to FIGS. 2 and 3, the edge spacer 150 is formed on one edge of the first active surface 221 of the first wafer 220, on the side of the wafer 220, and on the substrate 210, and is higher than the first motion. The face 22 1 ' is to seal at least one of the first bonding wires 241. In the embodiment, the edge spacer colloid 25 0 may have an inverted L surface. Therefore, the edge spacer colloid 250 has a gap maintaining, a crystal edge bonding support, and a pre-sealing bonding wire to prevent the effect of the punching. The edge spacer gel 250 is formed on the side of the first wafer 220 and the board 210. The first wafer 22 〇 produces a stronger adhesion ′, and the stress can be absorbed or dispersed to the substrate 21 打 during the wire bonding. 请 Referring to FIG. 2 , the edge spacer colloid 250 is attached to the first bonding wires. The arc of 24 1 is high to prevent the first wafer from being tilted when the second wafer 23 is excessively stressed due to excessive stress on the second wafer 23 when the wire is bonded. 241. Preferably, the edge spacers 250 completely seal the first bonding wires 241 to avoid problems caused by short-circuiting or/and wire breakage of the first bonding wires 241 in the subsequent molding process. Referring to Figure 3, the dispensing process can be utilized to provide the edge spacing π which is still in a liquid or gel state by the glue head 10 to form the base and the first primary. At the edge of the wearing piece, the base can be as high as 230, and the touch can be completed.
邊緣且Φ環氧樹脂(eP。”)，點塗在該第-晶, 其中該邊緣間隔膠體25〇係具有在加敎， :為不同實施例中，該邊緣間隔㈣ 刷戈鋼：固化膠趙能在A階(A_Stage)狀態^ 刷或鋼板印刷方式形成於 #· 日曰月 220之邊 :，Γ°上並可以包覆蓋些第一銲線241。场 :使邊:：隔穋體25。之後’可預㈣該邊緣間 50使其4Β階（B_stage)狀態，以維持較為平整 易變形之外形。 該一第二晶片230係具有一第二主動面231及 者面232，該第二晶片23〇之該第二主動 係：成有冑數個第二㈣233。纟適當之壓合壓 熱溫度下，使得該邊緣間隔膠體25〇具有黏著力 接該第二晶片230之該第二背面232,使該第二晶 係設置於該邊緣間隔膠體25〇上。或可利用另一 黏接該第二晶片23 0。另外，可利用該些第二銲 電性連接該些第二銲墊233與該基板21〇之該些 指213。在本實施例中，該第二晶片23〇之該第 232係形成有一晶背保護膠234。其中，該第二晶 之尺寸係可相同於該第一晶片220之尺寸。 具想而言，該多晶片堆疊封裝構造2〇〇可另 一模封膠體260，其係形成於該基板210之該 21 1 ’以密封該第一晶片22〇、該第二晶片23〇、 間隔膠體250與該些第二銲線242，使該多晶片 丨220之 可黏接 [250 係 網板印 緣與該 常在塗 隔膠體 且不容 一相對 面23 1 力與加 ，以黏 丨片230 黏晶膠 線242 打線接 二背面 片230 包含有 上表面 該邊緣 堆疊封 12 1^21349 裝構造200之内部元件與外部隔離，以避免受外界水氣 或污染物侵害。請再參閱第2圖所示，較佳地，該模封 膠體260可更填充於該第—晶片220與該第二晶片23〇 之中央間隙’以增加晶片包覆性逹到產品町靠性的提 昇。 因此’在該多晶片堆疊封裝構造2〇〇中，利用該邊 ]隔膠體250能在不需要在晶片堆疊之間設置中央 ^物之條件下堆疊該第二晶片23〇 ’而不會有上方堆 ^ '片壓觸下方銲線的問題，並得到較佳的打線支撐 進步在該第一晶片230設有該些第二銲墊233 ::置提供打線支撑，而能承受該第二晶片23〇與該基 之破之作用力’達到防止該第二晶片230 — 壞。此外，該邊緣間隔膠體250係私覆該些第 杆線 2 41，Edge and Φ epoxy (eP."), spotted on the first crystal, wherein the edge spacer colloid 25 has a twist, in different embodiments, the edge spacing (four) brush Ge steel: curing adhesive In the A-stage (A_Stage) state ^ brush or steel plate printing method is formed on the side of #·日曰月220:, Γ° and can cover some of the first bonding wires 241. Field: make the side:: barrier body After the second edge 230 has a second active surface 231 and a surface 232, the second wafer 230 has a second level (B_stage) state. The second active system of the second wafer 23 is formed with a plurality of second (four) 233. The appropriate spacing and pressing tempering temperature causes the edge spacer colloid 25 to have an adhesive force to the second of the second wafer 230. The second crystal system is disposed on the edge spacer 65 。, or the second wafer 230 can be bonded by another. The second soldering connection can be used to connect the second solders. The pad 233 and the substrate 21 are separated by the fingers 213. In this embodiment, the second chip 23 is formed by the second 232 system. The backing protective layer 234. The size of the second crystal may be the same as the size of the first wafer 220. The multi-wafer stacked package structure 2 may be another molding compound 260, The 21 1 ′ formed on the substrate 210 to seal the first wafer 22 , the second wafer 23 , the spacer colloid 250 and the second bonding wires 242 to bond the multi-chip wafer 220 [250] The printing edge of the stencil is opposite to the surface of the adhesive body and is not allowed to be opposed to the surface of the adhesive sheet 230. The adhesive sheet 230 is bonded to the adhesive line 242. The second back sheet 230 includes the upper surface of the edge stacking seal 12 1^ 21349 The internal components of the mounting structure 200 are isolated from the outside to avoid being exposed to external moisture or contaminants. Please refer to FIG. 2, preferably, the molding compound 260 can be further filled with the first wafer 220 and The central gap of the second wafer 23 is increased to increase the wafer coating property to the product. Therefore, in the multi-wafer stacked package structure 2, the spacer 250 can be used without using the edge. Stacking the same under the condition that a central object is placed between the wafer stacks The wafer 23〇' does not have the problem of the upper stacking layer's pressing the lower bonding wire, and the better wire bonding support is improved. The second wafer 230 is provided on the first wafer 230. And the force of the second wafer 23 and the breaking of the substrate can be prevented to prevent the second wafer 230 from being damaged. Further, the edge spacer colloid 250 is privately covered by the plurality of rod lines 2 41,
第一銲線 不會因壓模的壓力與模流逮度導致該些 問題。、’· 241因沖線造成短路或/與線斷裂造成斷路之 該多晶片±仓* 可應用在一 ^封裝構造200不僅適用於記憶卡，亦 (BGa)、平面般半導體封裝產品中’例如球格陣列封裝 等等。 陣列封裝（LGA)或薄小外型尺寸封裝（TSOP) 第4A至4 施例之該多曰C圖係用以說明根據本發明之第一具體實 請參閱第J片堆叠封裝構造2°°之製造方法。首先， 210,該第一曰圖所示，設置一第一晶片220於一基板 晶片220之第一背面2之2係黏貼於該基板 13 1321349 210’其中該第一晶片220係具有複數個第一銲塾223, 該些第一銲墊223係形成於該第一晶片220之第一主動 面221。該基板210係具有一上表面211及一下表面 212，該上表面211係形成有複數個打線接指213，該 基板210更具有複數個接觸墊214，該些接觸塾214係 形成於該下表面212。可利用打線技術形成之複數個第 一銲線241連接該些第一銲墊223與該些打線接指 2 1 3 ’以達到該第一晶片220與該基板2 1 0之間之電性 連接。 之後，請參閱第4B圖所示，以點塗、網板印刷或鋼 板印刷等方式形成一邊緣間隔膠體2 5 〇於該第一晶片 220上，使該邊緣間隔膠體250係形成於該第一晶片22〇 之第一主動面221之一邊緣、該第一晶片220之側面以 及該基板210上並且高出於該第一主動面221，以至少 密封該些第一銲線241之一部位，該邊緣間隔膠體250 係可選自於環氧樹脂（epoxy)與b階（B-stage)膠體之其 中之一。並經適當烘烤，以維持間隔特性。 最後，請參閱第4C圖所示，設置一第二晶片230 於該邊緣間隔膠鱧250上，該第二晶片230係具有一第 二主動面231及一相對之第二背面232。該第二主動面 231係形成有複數個第二銲墊233，該第二背面232更 形成有一晶背保護膠234 ^再以打線方式形成之複數個 第一知線242’其係電性連接該些第二銲整233至該基 板210之打線接指213。 14 1321349 因此，在上述多晶片堆疊封裝製程中，可在不需要 在晶片堆疊之間設置中央間隔物之條件下，堆疊該第二 晶片230時，該第二晶片230不會壓觸該些第一銲線 241，並且解決在打線形成該第二銲線242時由支撐邊 緣產生第二晶片230斷裂的問題。 在本發明之第二具體實施例，揭示另一種多晶片堆 疊封裝構造。請參閱第5圖所示，該多晶片堆疊封裝構 造300主要包含一基板310、一第一晶片320、一第二 晶片330、複數個第一銲線341、複數個第二銲線342 以及複數個邊緣間隔膠體351、352、353與354。 該基板310係具有一上表面311及一下表面312， 該上表面311係形成有複數個打線接指（圖中未繪出）。 該第一晶片320係具有一第一主動面321，該第一主動 面321係形成有複數個第一銲墊322。該第一晶片320 係設置於該基板310之該上表面311並且該第一晶片 320之該第一主動面321係為朝上。該些第一銲線341 係電性連接該些第一銲墊3 22至該基板310之打線接 指。 請再參閱5圖所示，該第一邊緣間隔膠體3 5 1係形 成於該第一晶片320之第一主動面321之一邊緣、該第 一晶片320之側面與該基板310上並且高出於該第一主 動面321，以至少密封該些第一銲線341之一部位。較 佳地，該第一邊緣間隔膠體3 5 1係可高於該些第一銲線 3 4 1之弧高，藉以避免在堆疊晶片時，該第二晶片3 3 0 / 15 1321349 壓觸該些第一銲線341。 該第二晶片330係具有一第二主動面331 形成於該第二主動面331之第二銲墊332。該 330係設置於該第一邊緣間隔膠體351上並使 銲墊332為朝上，以供該些第二銲線342電性 第—辉塾3 3 2至該基板3 1 0。在本實施例中， 堆疊封裝構造 300可另包含有一第二邊緣 3 52，其係形成於該第二晶片330之第二主動 一邊緣、該第二晶片3 3 0之侧面與該第一邊緣 351上並且高出於該第二主動面331，以至少 第二銲線342之一部位。 請再參閱第5圖所示，該多晶片堆疊封裝 可另包含一第三晶片370及一第四晶片38〇， 憶體容量。該第三晶片370係設置於該第二邊 體352上，並藉由複數個第三銲線343電性連 晶片370之複數個第三銲墊372,其中該些第：r ' 丨丨丨_ 係形成於該第三晶片370之一第三主動面371 實施例中，該多晶片堆疊封裝構造3 00可另包 三邊緣間隔膠體353’其係形成於該第三晶片 三主動面371之一邊緣、該第三晶片370之側 二邊緣間隔膠趙352上並且高出於該第三主動 以供堆疊該第四晶片380。其中該第三邊緣 353係至少密封該些第三銲線343之一部位。 該第四晶片3 8 0係堆疊於該第三邊緣間隔 及複數個 第二晶片 該些第二 連接該些 該多晶片 間隔膠體 面3 3 1之 間隔膠體 密封該些 構造300 以擴充記 緣間隔膠 接該第三 銲墊372 上。在本 含有一第 370之第 面與該第 面 371， 間隔膠體 膠體353 16 1321349 上’並藉由複數個第四銲線344電性連接該第四晶片 380之複數個第四銲墊382。在本實施例中，該多晶片 堆疊封裝構造3 00可另包含有一第四邊緣間隔膠體 354’其係形成於該第四晶片380之一第四主動面381 之一邊緣、該第四晶片3 80之側面與該第三邊緣間隔膠 體353上並且高出於該第四主動面381，以至少密封該 些第四鋒線344之一部位。 具體而言’該多晶片堆叠封裝構造3〇〇可另包含有 一模封膠體360，其係密封該第一晶片32〇、該第二晶 片33〇、該第三晶片37〇、該第四晶片38〇、該第一邊 緣間隔膠體351、該第二邊緣間隔膠逋352、該第三邊 緣間隔膠體3 5 3與該第四邊緣間隔膠體3 5 4。請再參閱 第5圖所示，所有的銲線341、342、343與344在模封 之前即被該些邊緣間隔膠體351、352、353與354預先 包覆達到防沖線的保護效果，使得該多晶片堆疊封裝構 造300的製造良率更為提高》 此外，上述之堆疊於第一晶片320之其餘晶片330 ' 370與3 80皆係分別疊設於該些邊緣間隔膠體351、352 與3 5 3上，故可省略習知之在晶片間設置一中央間隔 物，且不有位於上層之該些晶片330、370與380壓觸 該些下方銲線341、342與343之問題，亦可提供位於 上層之該些晶片330、370與380良好的打線支撐性， 避免位於上層之該些晶片330、370與380因受打線接 合力而崩裂損壞。 17 1321349 以上所述，僅是本發明的較佳實施例而已，並非對 本發月作任何形式上的限制，雖然本發明已以較佳實施 例揭露如上’然而並非用以限定本發明，任何熟悉本專 業的技術人員’在不脫離本發明技術方案範園内，當可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案 容’依據本發明的技術营暫抖w l虫“ 议何貫質對以上實施例所作的任 單修改、等同變化與修飾， 7簡 範圍内。 均仍屬於本發明技術方案的 【圖式簡單說明】 第1圖：一種習知多晶片金聶 第2圖 曰片堆疊封裝構造之截面示意圖。 依據本發明之第一具 ^具體實施例，一種多晶片Μ 疊封裝構造之截面示意圖。 第3圖：依據本發明之第一 ^具體實施例，該多晶片堆晶 封裝構造在製程中# ® 眾程中形成一邊緣間隔膠體 體示意圖。 正 第4Α至4C [依據本發明之第—具體實施例，該夕 晶片堆叠封裝構造於製程中-基板之戴面: 意圖》 不 第5圖：依據本發明之第二具體實施例，另一種多晶 堆疊封裝構造之截面示意圖。 曰9 【主要元件符號說明】 10 點膠針頭 100多晶片堆疊封裝構造 1321349The first bond line does not cause these problems due to the pressure of the stamper and the mold flow. '· 241 The multi-wafer ± bin* caused by a short circuit or/and a line break due to a line break can be applied to a package structure 200 not only for memory cards, but also for (BGa), planar semiconductor package products. Grid array package and more. Array Package (LGA) or Thin Outline Package (TSOP) The multi-layer C diagram of the 4A to 4th embodiment is used to illustrate the first embodiment of the present invention. Manufacturing method. First, 210, the first wafer 220 is attached to the substrate 13 1321349 210' of the first back surface 2 of a substrate wafer 220, wherein the first wafer 220 has a plurality of A first solder pad 223 is formed on the first active surface 221 of the first wafer 220. The substrate 210 has an upper surface 211 and a lower surface 212. The upper surface 211 is formed with a plurality of wire bonding fingers 213. The substrate 210 further has a plurality of contact pads 214, and the contact pads 214 are formed on the lower surface. 212. The plurality of first bonding wires 241 formed by the wire bonding technology may be connected to the first bonding pads 223 and the bonding wires 2 1 3 ′ to achieve electrical connection between the first wafer 220 and the substrate 2 10 . . Then, as shown in FIG. 4B, an edge spacer colloid 2 5 is formed on the first wafer 220 by dot coating, screen printing or steel plate printing, so that the edge spacer colloid 250 is formed on the first An edge of the first active surface 221 of the wafer 22, the side of the first wafer 220, and the substrate 210 and above the first active surface 221 to seal at least one of the first bonding wires 241, The edge spacer colloid 250 can be selected from one of an epoxy and a B-stage colloid. And properly baked to maintain the spacing characteristics. Finally, as shown in FIG. 4C, a second wafer 230 is disposed on the edge spacer capsule 250. The second wafer 230 has a second active surface 231 and an opposite second back surface 232. The second active surface 231 is formed with a plurality of second pads 233, and the second back surface 232 is further formed with a crystal back protective adhesive 234. The plurality of first lines 242' formed by wire bonding are electrically connected. The second soldering 233 is connected to the bonding wire 213 of the substrate 210. 14 1321349 Therefore, in the above multi-wafer stack packaging process, the second wafer 230 is not pressed against the second wafer 230 when the central spacers are not required to be disposed between the wafer stacks. A bonding wire 241 is disposed, and the problem that the second wafer 230 is broken by the supporting edge when the wire is formed to form the second bonding wire 242 is solved. In a second embodiment of the invention, another multi-wafer stack package construction is disclosed. As shown in FIG. 5 , the multi-wafer stacked package structure 300 mainly includes a substrate 310 , a first wafer 320 , a second wafer 330 , a plurality of first bonding wires 341 , a plurality of second bonding wires 342 , and a plurality of The edge spacers are 351, 352, 353 and 354. The substrate 310 has an upper surface 311 and a lower surface 312. The upper surface 311 is formed with a plurality of wire bonding fingers (not shown). The first wafer 320 has a first active surface 321 formed with a plurality of first pads 322. The first wafer 320 is disposed on the upper surface 311 of the substrate 310 and the first active surface 321 of the first wafer 320 is upward. The first bonding wires 341 electrically connect the first bonding pads 322 to the bonding wires of the substrate 310. Referring to FIG. 5 , the first edge spacer 35 1 1 is formed on one edge of the first active surface 321 of the first wafer 320 , the side of the first wafer 320 and the substrate 310 and is higher than the substrate 310 . The first active surface 321 is configured to seal at least one of the first bonding wires 341. Preferably, the first edge spacer 35 1 1 can be higher than the arc height of the first bonding wires 341 to avoid the second wafer 3 3 0 / 15 1321349 being pressed against the stacked wafer. Some first bonding wires 341. The second wafer 330 has a second active pad 331 formed on the second pad 332 of the second active surface 331 . The 330 is disposed on the first edge spacer 351 and the pad 332 is facing upward, so that the second bonding wires 342 are electrically connected to the substrate 3 10 . In this embodiment, the stacked package structure 300 may further include a second edge 352 formed on the second active edge of the second wafer 330, the side of the second wafer 305 and the first edge. 351 is above and above the second active surface 331 to at least one of the second bonding wires 342. Referring to FIG. 5 again, the multi-wafer stack package may further include a third wafer 370 and a fourth wafer 38, which have a memory capacity. The third wafer 370 is disposed on the second side body 352, and electrically connected to the plurality of third pads 372 of the wafer 370 by a plurality of third bonding wires 343, wherein the first: r ' 丨丨丨_ is formed in a third active surface 371 embodiment of the third wafer 370. The multi-wafer stacked package structure 300 may be further provided with a three-edge spacer colloid 353' formed on the third active surface 371 of the third wafer. An edge, the side edge of the third wafer 370 is spaced apart from the edge 352 and is higher than the third active for stacking the fourth wafer 380. The third edge 353 seals at least one of the third bonding wires 343. The fourth wafer 380 is stacked on the third edge interval and the plurality of second wafers. The second spacers are connected to the plurality of spacer spacers 353. The spacers are sealed to seal the structures 300 to expand the edge spacers. Connected to the third pad 372. A plurality of fourth pads 382 of the fourth wafer 380 are electrically connected to each other by a plurality of fourth bonding wires 344 on the first surface of the first 370 and the first surface 371, and on the spacer colloid 353 16 1321349. In this embodiment, the multi-wafer stack package structure 300 may further include a fourth edge spacer colloid 354' formed on one edge of one of the fourth active faces 381 of the fourth wafer 380, the fourth wafer 3. The side of the 80 is spaced apart from the third edge and is higher than the fourth active surface 381 to seal at least one of the fourth front lines 344. Specifically, the multi-wafer stacked package structure 3 can further include a molding compound 360 for sealing the first wafer 32, the second wafer 33, the third wafer 37, and the fourth wafer. 38〇, the first edge spacer colloid 351, the second edge spacer capsule 352, the third edge spacer colloid 3 53 and the fourth edge spacer colloid 3 5 4 . Referring to FIG. 5 again, all the bonding wires 341, 342, 343 and 344 are pre-coated by the edge spacers 351, 352, 353 and 354 to obtain the protection effect of the anti-shock line before the molding, so that The manufacturing yield of the multi-wafer stack package structure 300 is further improved. In addition, the remaining wafers 330 370 and 380 stacked on the first wafer 320 are respectively stacked on the edge spacers 351, 352 and 3 respectively. 5 3, so it can be omitted to provide a central spacer between the wafers, and there is no problem that the wafers 330, 370 and 380 located in the upper layer are pressed against the lower bonding wires 341, 342 and 343. The wafers 330, 370 and 380 located in the upper layer have good wire bonding support, and the wafers 330, 370 and 380 located in the upper layer are prevented from being cracked and damaged by the wire bonding force. 17 1321349 The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, although the present invention has been disclosed in the above preferred embodiments, however, it is not intended to limit the invention, A person skilled in the art can make some modifications or modifications to equivalent embodiments by using the above-disclosed technical contents without departing from the technical scope of the present invention. The technical battalion of the invention temporarily shakes wl worms. "What is the pertinence modification, equivalent change and modification of the above embodiment, 7 is within the scope of the present invention. All of them still belong to the technical scheme of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS A cross-sectional view of a multi-wafer stacked package structure in accordance with a first embodiment of the present invention. FIG. 3 is a cross-sectional view of a multi-wafer stacked package structure. In a first embodiment, the multi-wafer stacked crystal package structure forms a schematic diagram of an edge-spaced colloidal body in the process of the process. Α to 4C [In accordance with the first embodiment of the present invention, the wafer stack package is constructed in the process - the wearing surface of the substrate: Intent" Figure 5: According to the second embodiment of the present invention, another polycrystalline Schematic diagram of the stacked package structure. 曰9 [Main component symbol description] 10 dispensing needle 100 multi-chip stack package structure 1321349
110 基板 111 上表面 112 113 打線接指 114 接觸蟄 120 第一晶片 121 第一主動面 122 123 第一銲墊 130 第二晶片 131 第二主動面 132 133 第二銲墊 134 支撐斷裂點 141 第一銲線 142 第二銲線 150 中央間隔物 160 模封膠體 200 多晶片堆疊封裝構造 210 基板 211 上表面 212 213 打線接指 214 接觸墊 220 第一晶片 221 第一主動面 222 223 第一銲墊 230 第二晶片 231 第二主動面 232 233 第二銲墊 234 晶背保護膠 241 第一銲線 242 第二銲線 250 邊緣間隔膠體 260 模封膠體 300 多晶片堆疊封裝構造 310 基板 311 上表面 312 320 第一晶片 321 第一主動面 322 330 第二晶片 331 第二主動面 332 341 第一銲線 342 第二銲線 343 344 第四銲線 3 5 1第一邊緣間隔膠趙 下表面 第一背面 第二背面 下表面 第一背面 第二背面 下表面 第一銲塾 第二銲墊 第三銲線 19 1321349 352第二邊緣間隔膠體 353第三邊緣間隔膠體 3 54第四邊緣間隔膠體 360模封膠體 372第三銲墊 382第四銲墊 370第三晶片 371第三主動面 380第四晶片 381第四主動面110 substrate 111 upper surface 112 113 wire bonding finger 114 contact port 120 first wafer 121 first active surface 122 123 first pad 130 second wafer 131 second active surface 132 133 second pad 134 supporting break point 141 first Bonding wire 142 second bonding wire 150 central spacer 160 molding compound 200 multi-chip stacked package structure 210 substrate 211 upper surface 212 213 wire bonding finger 214 contact pad 220 first wafer 221 first active surface 222 223 first bonding pad 230 Second wafer 231 second active surface 232 233 second solder pad 234 crystal back protective rubber 241 first bonding wire 242 second bonding wire 250 edge spacer gel 260 molding compound 300 multi-chip stacked package structure 310 substrate 311 upper surface 312 320 First wafer 321 first active surface 322 330 second wafer 331 second active surface 332 341 first bonding wire 342 second bonding wire 343 344 fourth bonding wire 3 5 1 first edge spacer plastic Zhao lower surface first back Second back lower surface first back second back lower surface first solder second solder pad third bonding wire 19 1321349 352 second edge spacer colloid 3 53 third edge spacer colloid 3 54 fourth edge spacer colloid 360 mold sealing gel 372 third bonding pad 382 fourth bonding pad 370 third wafer 371 third active surface 380 fourth wafer 381 fourth active surface
2020