200836306 九、發明說明： 【發明所屬之技術領域] 本發明係有關於一種打線型態之多晶片堆疊封 造，特別係有關於一種可將複數個同尺寸晶片主動 上堆疊之多晶片堆疊封裝構造。 【先前技術】 在多晶片堆疊封裝構造領域中，複數個晶片係 主動面朝向同一方向地由一基板往上縱向堆疊並 連接至該基板，可有效縮小封裝構造之表面接合 (footprint)，以避免多晶片堆疊封裝構造之尺寸過 通常在晶片與晶片之間通常會設置一中央間 (central spacer)，以墊高晶片間距，防止上層晶片 下方銲線。然而’该中央間隔物係需小於該下層晶 不能檔到該下層晶片之銲墊，以供打線接合，使得 央間隔物遠小於該下層晶片，因此造成該中央間隔 U 於上層晶片在其周邊之打線支撐力不足，故打線在 晶片之打線接合壓力會導致上層晶片斷裂。 請參閱第1圖所示，一種習知的多晶片堆疊封 造100主要包含一基板110、一第一晶片120、一 晶片1 3 0、複數個第一銲線i 4 1、複數個第二銲線 以及一中央間隔物150。該基板11〇係具有一上表违 以及一下表面1 1 2，其中複數個打線接指1 1 3係形 該上表面111，複數個接觸墊114或外接端子係可 於該基板110之該下表面112。該第一晶片12〇之 裝構 面朝 以其 電性 面積 大。 隔物 觸壓 片且 該中 物對 上層 裝構 第二 142 « 111 成於 形成 一第 6 200836306 一背面1 22係黏貼於該基板11 0之該上表面] 一晶片120係具有複數個第一銲墊123，其係 弟一曰日片12〇之一^第一主動面121上。利用打 該些第一銲線141電性連接該些第一銲墊123 1 1 0之該些打線接指i i 3。該第二晶片i 3 〇係 一晶片120上。請再參閱第1圖所示，該中 150之尺寸係小於該第一晶片120與該第二晶 尺寸，該中央間隔物1 5 0係黏設於該第一晶片 第一主動面121，並顯露該些第一銲墊123, 間隔物1 5 0係位於該第一晶片1 2 〇與該第二晶 間。該第二晶片130之一第二背面132係設置 間隔物1 5 〇上，且該第二晶片1 3 0之該第二背 不與該些第一銲線141直接接觸。通常該中 150係可為一膠片、一虛晶片或一金屬片等等 晶片取放（pick and pi ace)方式設置於該第一晶 該第一主動面1 2 1上。該第二晶片1 3 0係具有 二銲墊1 3 3，其係形成於該第二晶片} 3 〇之一 面1 3 1上。$亥些第一鲜線1 4 2係以打線方式連 二銲墊133至該基板11〇。通常可另以一模封 密封該第一晶片1 20、該第二晶片i 3 〇、該些 141與該些第二銲線142。 請再參閱第1圖所示，當該第二晶片13〇 中央間隔物1 5 0上時，由於該中央間隔物丨5 〇 第二晶片130’使得該第二晶片13〇之周邊無 ί 1 1。該第 形成於該 線形成之 至該基板 設於該第 央間隔物 片130之 1 2 0之該 且該中央 片130之 於該中央 面1 3 2係 央間隔物 ，以如同 片120之 複數個第 第二主動 接該些第 膠體160 第一銲線 設置於該 係小於該 法獲得來 200836306 自該中央間隔物150之支撐而成懸空部分，故在該第二 晶片於打線作業時，打線接合銲針熱壓合在設有該 些第二銲墊133之該篦—曰ΰ 豕弟一日日片130之位置無法受到該中 央間隔物150之有效支撐，而於支撐點引發斷裂134， 進而造成結構損壞。 【發明内容】 Ο200836306 IX. Description of the Invention: [Technical Field] The present invention relates to a wire-type multi-wafer stacking package, and more particularly to a multi-wafer stack package structure capable of actively stacking a plurality of wafers of the same size . [Prior Art] In the field of multi-wafer stacked package structure, a plurality of wafer-based active faces are stacked longitudinally upward from a substrate and connected to the substrate in the same direction, which can effectively reduce the surface footprint of the package structure to avoid The size of the multi-wafer stacked package structure is usually such that a central spacer is usually disposed between the wafer and the wafer to increase the wafer pitch and prevent the bonding wires under the upper wafer. However, the central spacer system needs to be smaller than the underlying crystal can not be transferred to the pad of the underlying wafer for wire bonding, so that the central spacer is much smaller than the underlying wafer, thus causing the central spacer U to be on the periphery of the upper wafer. The wire holding force is insufficient, so the bonding force of the wire bonding on the wafer causes the upper wafer to break. Referring to FIG. 1 , a conventional multi-wafer stack package 100 mainly includes a substrate 110 , a first wafer 120 , a wafer 1 30 , a plurality of first bonding wires i 4 1 , and a plurality of second A wire bond and a central spacer 150. The substrate 11 has an upper surface and a lower surface 112, wherein a plurality of wire bonding fingers 1 1 3 form the upper surface 111, and a plurality of contact pads 114 or external terminals are disposed under the substrate 110. Surface 112. The first wafer 12 is mounted with a larger electrical area. The spacer touches the sheet and the middle object is mounted on the second layer 142 «111 to form a sixth 200836306. The back surface 1 22 is adhered to the upper surface of the substrate 110. A wafer 120 has a plurality of first The pad 123 is on the first active surface 121 of one of the 12 pieces of the Japanese film. The wire bonding fingers i i 3 are electrically connected to the first bonding pads 123 1 1 0 by using the first bonding wires 141. The second wafer i 3 is tied to a wafer 120. Referring to FIG. 1 again, the size of the middle 150 is smaller than the first wafer 120 and the second crystal size, and the central spacer 150 is adhered to the first active surface 121 of the first wafer, and The first pads 123 are exposed, and the spacers 150 are located between the first wafers 1 2 〇 and the second crystals. The second back surface 132 of the second wafer 130 is disposed on the spacer 15 5 , and the second back of the second wafer 1 300 is not in direct contact with the first bonding wires 141. Usually, the medium 150 series can be a film, a dummy wafer or a metal piece, and the like, and a chip pick and pi ace is disposed on the first crystal first active surface 112. The second wafer 130 has two pads 1 3 3 formed on one of the second wafers 1 3 1 . The first fresh wire of the haihe 1 4 2 is connected by wire bonding 133 to the substrate 11 以. The first wafer 120, the second wafer i3, the 141, and the second bonding wires 142 may be sealed by a single sealing. Referring to FIG. 1 again, when the second wafer 13 is on the central spacer 150, since the central spacer 〇5 〇 the second wafer 130' makes the periphery of the second wafer 13 无1 1. The first portion is formed on the line to which the substrate is disposed at 120 of the central spacer sheet 130 and the central sheet 130 is disposed on the central surface of the central portion 138 to form a plurality of sheets 120. The second first active wire is connected to the first colloids 160. The first bonding wire is disposed on the system less than the support obtained from the central spacer 150 by the method, so that the second wafer is wired during the wire bonding operation. The bonding pin is thermocompression-bonded at the position where the second pad 130 of the second pad 133 is provided, and is not supported by the central spacer 150, and the breakage 134 is induced at the support point. This causes structural damage. SUMMARY OF THE INVENTION Ο
本發明之主要目的係在於提供一種多晶片堆疊封裝 構造，可在不需要在晶片堆疊之間設置中央間隔物之條 件下，堆疊上層晶片且不會壓觸至下方銲線的問題，另 能在上層晶片設有銲墊之位置提供足夠打線支撐，避免 上層晶片由支撐點斷裂之問題，藉以提高產品之良率。 本發明之次一目的係在於提供一種多晶片堆疊封裝 構造，利用一邊緣間隔膠體預先包覆複數個銲線，當壓 模形成一模封膠體時，不會有因沖線導致銲線短路或/ 與線斷裂造成斷路之問題。 本發明之再一目的係在於提供一種多晶片堆疊封裝 構造，可避免因晶片堆疊不正或傾斜之現象導致銲線觸 碰上層晶片背面。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種多晶片堆疊封裝構造主 要包含一基板、一第一晶片、複數個第一銲線、一第一 邊緣間隔膠體（peripherally stand-off encapsulant)、一 第二晶片以及複數個第二銲線。該第一晶片係設置於該 基板上並具有一第一主動面。該些第一銲線係電性連接 8 200836306 該第一晶片與該基板。該第一邊緣間隔膠體係形成於該 第一晶片之第一主動面之一邊緣、該第一晶片之側面與 該基板上並且高出於該第一主動面，以至少密封該些第 一銲線之一部位。該第二晶片係設置於該第一邊緣間隔 膠體上並具有一第二主動面。該些第二銲線係電性連接 該苐二晶片與該基板。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 m 1 在前述的多晶片堆疊封裝構造中，該第一邊緣間隔 膠體係可具有倒L形截面。 在前述的多晶片堆疊封裝構造中，該第一邊緣間隔 膠體係可高於該些第一銲線之弧高。 在前述的多晶片堆疊封裝構造中，該第一邊緣間隔 膠體係可完全密封該些第一銲線。 在前述的多晶片堆疊封裝構造中，可另包含有一模 Q 封膠體，其係密封該第一晶片、該第二晶片與該第一邊 緣間隔膠體。 在前述的多晶片堆疊封裝構造中，該模封膠體可更 填充於該第一晶片與該第二晶片之中央間隙。 在前述的多晶片堆疊封裝構造中，可另包含有一第 二邊緣間隔膠體，其係形成於該第二晶片之第二主動面 之一邊緣、該第二晶片之侧面與該第一邊緣間隔膠體上 並且高出於該第二主動面，以至少密封該些第二銲線之 一部位。 9 200836306 在前述的多晶片堆疊封裝構造中，該第二晶片係可 更具有一第二背面 ，該第二背面係形成有一晶背保護The main object of the present invention is to provide a multi-wafer stack package structure which can stack the upper layer wafer without pressing the lower bonding wire without setting a central spacer between the wafer stacks, and can The position of the upper wafer with the solder pads provides sufficient wire support to avoid the problem that the upper wafer is broken by the support points, thereby improving the yield of the product. A second object of the present invention is to provide a multi-wafer stack package structure in which a plurality of bonding wires are pre-coated with an edge spacer colloid, and when the stamper forms a molding compound, there is no short circuit of the bonding wire due to the punching line or / Problem with the line break causing an open circuit. It is still another object of the present invention to provide a multi-wafer stacked package structure that avoids the solder wire from contacting the back side of the upper wafer due to a phenomenon in which the wafer stack is not aligned or tilted. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a multi-wafer stacked package structure mainly includes a substrate, a first wafer, a plurality of first bonding wires, a first edge-off encapsulant, a second wafer, and a plurality of second Welding wire. The first wafer is disposed on the substrate and has a first active surface. The first bonding wires are electrically connected to the first wafer and the substrate. The first edge spacer gel system is formed on one edge of the first active surface of the first wafer, the side of the first wafer and the substrate and is higher than the first active surface to at least seal the first solder One part of the line. The second wafer is disposed on the first edge spacer and has a second active surface. The second bonding wires are electrically connected to the second wafer and the substrate. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. m 1 In the aforementioned multi-wafer stacked package construction, the first edge spacer system may have an inverted L-shaped cross section. In the foregoing multi-wafer stacked package construction, the first edge spacer system may be higher than the arc height of the first bonding lines. In the foregoing multi-wafer stacked package configuration, the first edge spacer system can completely seal the first bonding wires. In the foregoing multi-wafer stacked package configuration, a die sealant may be further included which seals the first wafer, the second wafer and the first edge spacer. In the foregoing multi-wafer stack package configuration, the mold sealant may be further filled in a central gap between the first wafer and the second wafer. In the foregoing multi-wafer stack package structure, a second edge spacer colloid may be further formed on one edge of the second active surface of the second wafer, the side of the second wafer and the first edge spacer colloid Up and up from the second active surface to seal at least one of the second bonding wires. 9 200836306 In the foregoing multi-wafer stacked package structure, the second wafer system may further have a second back surface, and the second back surface is formed with a crystal back protection
在前述的多晶片堆疊封裝構造中，該第二晶片係可更 具有一第二背面，該邊緣間隔膠體係直接黏著該第二晶 片之該第二背面。 【實施方式】In the foregoing multi-wafer stack package configuration, the second wafer system may further have a second back surface, and the edge spacer rubber system directly adheres to the second back surface of the second wafer. [Embodiment]
依據本發明之第一具體實施例，揭示一種多晶片堆 疊封裝構造。第2圖係為該多晶片堆疊封裝構造之截面 示意圖。第3圖係為該多晶片堆疊封裝構造在製程中形 成一邊緣間隔膠體之立體示意圖。第4A至4C圖係為 該多晶片堆疊封裝構造於製程中—基板之載面示意圖。 請參閱第2圖所示，一種多晶片堆疊封裝構造2〇0 主要包含一基板210、一第一晶片220、一第二晶片 2 3 0、複數個第一銲線2 4 1、複數個第二銲線2 4 2以及 至少一邊緣間隔膠體250。該基板210係具有一上表面 211以及一下表面212，其中該上表面211係形成有複 數個打線接指2 1 3，以供打線方式與晶片電性連接。該 基板2 1 0係可另具有複數個形成於該下表面2丨2之接觸 墊214。依應用產品之不同變化，該基板21〇亦可為一 導線架。 相對 複數 係 該苐一晶片220係具有一第一主動面221及— 之第一背面222，其中該第一主動面221係形成有 個第一銲墊223。該第一晶片220之該第一背面 ^ ^ 222 10 200836306 黏貼於該基板210之該上表面211，使該第一晶片22〇 係設置於該基板2 1 0上。在黏晶之後，利用打線形成該 些弟一知線241’以電性連接該些第一銲墊223與該基 板210之該些打線接指213,達到該第一晶片22〇與該 基板2 1 0之電性互連。 請參閱第2及3圖所示，該邊緣間隔膠體25〇係形 成於該第一晶片220之第一主動面221之一邊緣 '該第 一晶片220之侧面與該基板2 i 〇上並且高出於該第一主 動面221 ’以至少密封該些第一銲線241之一部位。在 本實施例中，該邊緣間隔膠體25〇係可具有倒l形截 面。因此’該邊緣間隔膠體…具有間隔維持、晶片邊 緣打線支撐、預密封銲線以防止沖線之功效，更由於該 邊緣間隔膠體250形成於該第_晶片22()之側面與該基 $ 210上，此對於該第一晶片22〇產生更加強的黏著固 Ο 疋’此外能將打線時應力吸收或分散至該基板21〇。 於請再參閱第2圖所示，該邊緣間隔膠體250係可高 於該些第一銲線241夕抓古 於± . 之弧冋，以防止當該第二晶片230 ;打線作業時，因打線接合時 ^ 應力過大而造成該第-曰片23:第：…3〇施加之 些第一録、線241。較二^ 傾斜而壓觸該 全密封該些第-銲線24 ^緣間隔膠體⑽係可完 沖線導致該些第—銲二免在後續壓模製程中因 之卩。1 « •-夂_ ~ Λ 短路或/與線斷裂造成斷路 〜问喊。请參閱第3 — 膠針頭1〇提供尚二,利用點膠技術藉由-點 。為液悲或膠稠態之該邊緣間隔膠體 11 200836306 2 5 0例如環氧樹脂（e p 〇 χ y )，點塗在該第一晶片 邊緣’其中該邊緣間隔膠體250係具有在加熱下 晶片之能力。在不同實施例中，該邊緣間隔膠體 可為多階段固化膠體，能在A階（A-stage)狀態以 刷或鋼板印刷方式形成於該第一晶片220之邊 基板210上，並可以包覆蓋些第一銲線241。通 佈該邊緣間隔膠體250之後，可預烘烤該邊緣間 ζ\ 250使其為Β階（B-stage)狀態，以維持較為平整 易變形之外形。 ό亥第_晶片230係具有一第二主動面231及 之第二背面232，該第二晶片230之該第二主動 係形成有複數個第二録塾233。在適當之壓合壓 熱溫度下，使得該邊緣間隔膠體2 5 0具有黏著力 接該第二晶片230之該第二背面232,使該第二曰 係設置於該邊緣間隔膠體250上。或可利用另一 Ο 黏接該第二晶片230。另外，可利用該些第二鲜 電性連接該些第二銲墊233與該基板210之該些 指2 1 3。在本實施例中，該第二晶片2 3 0之該第 232係形成有一晶背保護膠234。其中，該第二曰 之尺寸係可相同於該第一晶片220之尺寸。 具體而言’該多晶片堆疊封裝構造2〇〇可另 一模封膠體2 6 0，其係形成於該基板2 1 〇之該 211，以密封該第一晶片220、該第二晶片23〇、 間隔膠體250與該些第二銲線242，使該多晶片 220之 可黏接 25 0係 網板印 緣與該 常在塗 隔膠體 且不容 一相對 面23 1 力與加 ’以黏 丨片230 黏晶膠 線242 打線接 二背面 片230 包含有 上表面 該邊緣 堆疊封 12 200836306 裝構造2 0 〇之内部元件與外部隔離，以避免受外界水氣 或污染物侵害。請再參閱第2圖所示，較佳地，該模封 膠體260可更填充於該第一晶片220與該第二晶片230 之中央間隙，以增加晶片包覆性達到產品可靠性的提 昇。 因此，在該多晶片堆疊封裝構造200中，利用該邊 緣間隔膠體2 5 〇能在不需要在晶片堆疊之間設置中央 間隔物之條件下堆疊該第二晶片230，而不會有上方堆 疊晶片壓觸下方銲線的問題，並得到較佳的打線支撐 性。可進一步在該第二晶片230設有該些第二銲墊233 之位置提供打線支撐，而能承受該第二晶片230與該基 板2 1 0打線接合時之作用力，達到防止該第二晶片2 3 0 之破裂損壞。此外，該邊緣間隔膠體2 5 0係包覆該些第 鲜線2 4 1，故不會因壓模的壓力與模流速度導致該些 第一銲線2 4 1因沖線造成短路或/與線斷裂造成斷路之 〇 問題。 該多晶片堆疊封裝構造200不僅適用於記憶卡，亦 可應用在一般半導體封裝產品中，例如球袼陣列封裝 (BGA)、平面陣列封裝（LGA)或薄小外型尺寸封裝（TSOP) 等等。 第4A至4C圖係用以說明根據本發明之第一具體實 施例之該多晶片堆疊封裝構造200之製造方法。首先， 請參閱第4A圖所示，設置一第一晶片220於一基板 210 ’該第一晶片220之第一背面222係黏貼於該基板 13 200836306 2 1 0，其中該第一晶片2 2 〇 1糸具有複數個第一銲墊2 2 3， 該些第一銲墊223係形成於兮 曰 、通弟一晶片220之第一主動 面221。該基板210係具右 L支工 ，、有~上表面211及一下表面 2 1 2 ’該上表面2 1 1择來屮& 係形成有複數個打線接指213，該 基板2 1 0更具有複數個接觸 、 喝塾2 1 4，該些接觸墊2 1 4係 形成於該下表面2 1 2 〇可刹田丄a 用打線技術形成之複數個第 一銲線241連接該些第— 一 一塾223與該些打線接指 213’以達到該第— 片220與該基板210之間之電性 連接。 之後，請參閱第4Β圖邮- 圖所不，以點塗、網板印刷或鋼 板印刷專方式形成^邊续鬥ΪΤ- 5» 風遭緣間隔膠體2 5 0於該第一晶片 2 2 0上’使該邊緣間隔膠辦？ J㈣膠篮250係形成於該第一晶片22〇 之第一主動面221之一邊绥斗始 α 遭緣、該第一晶片220之側面以 及該基板210上並且高屮^^ 儿且同®於该第一主動面221，以至少 密封該些第一辉線241夕 a 深Z4 1之一部位。該邊緣間隔膠體2 5 ΟIn accordance with a first embodiment of the present invention, a multi-wafer stack package construction is disclosed. Figure 2 is a schematic cross-sectional view of the multi-wafer stacked package construction. Figure 3 is a perspective view of the multi-wafer stack package structure forming an edge spacer colloid in the process. 4A to 4C are schematic views showing the carrier surface of the multi-wafer stack package in the process. Referring to FIG. 2, a multi-wafer stacked package structure 〇0 mainly includes a substrate 210, a first wafer 220, a second wafer 203, a plurality of first bonding wires 241, and a plurality of Two bonding wires 2 42 and at least one edge spacer colloid 250. The substrate 210 has an upper surface 211 and a lower surface 212. The upper surface 211 is formed with a plurality of wire bonding fingers 201 for electrically connecting to the wafer. The substrate 210 may additionally have a plurality of contact pads 214 formed on the lower surface 2丨2. The substrate 21 can also be a lead frame depending on the application. The first wafer 220 has a first active surface 221 and a first back surface 222. The first active surface 221 is formed with a first bonding pad 223. The first back surface ^ 222 10 200836306 of the first wafer 220 is adhered to the upper surface 211 of the substrate 210, so that the first wafer 22 is tethered on the substrate 210. After the die bonding, the wires 241 ′ are formed by wire bonding to electrically connect the first pads 223 and the wire bonding fingers 213 of the substrate 210 to reach the first wafer 22 and the substrate 2 . 10 electrical interconnection. Referring to FIGS. 2 and 3, the edge spacer 35 is formed on one edge of the first active surface 221 of the first wafer 220 and the side of the first wafer 220 is on the substrate 2 i and is high. For the first active surface 221 ′ to seal at least one of the first bonding wires 241 . In this embodiment, the edge spacer colloid 25 can have an inverted l-shaped cross section. Therefore, the edge spacer colloid has a gap maintaining, wafer edge bonding support, pre-sealing the bonding wire to prevent the effect of punching, and more since the edge spacer colloid 250 is formed on the side of the first wafer 22 () and the base $ 210 In this case, a stronger adhesive bond is generated for the first wafer 22, and the stress can be absorbed or dispersed to the substrate 21〇 during wire bonding. As shown in FIG. 2 again, the edge spacer colloid 250 can be higher than the arc of the first bonding wire 241 to prevent the second wafer 230 from being used during the wire bonding operation. When the wire is joined, the stress is too large to cause the first film line 241 to be applied to the first film 23: ...: 3〇. Pressing the full-sealing of the first-bonding wires 24 to complete the sealing of the colloids (10) can cause the first-welding to be eliminated in the subsequent molding process. 1 « •-夂_ ~ Λ Short circuit or / break with line breakage ~ Ask shout. Please refer to the 3rd - glue needle head 1 〇 provided by the second, using the dispensing technology by - point. The edge spacer colloid 11 200836306 2 5 0 such as an epoxy resin (ep 〇χ y ) is spot-coated on the edge of the first wafer, wherein the edge spacer colloid 250 has a wafer under heating ability. In various embodiments, the edge spacer colloid may be a multi-stage curing gel, which can be formed on the substrate 210 of the first wafer 220 by brush or steel plate printing in an A-stage state, and can be covered by a package. Some first bonding wires 241. After passing the edge spacer colloid 250, the inter-edge ζ\250 can be pre-baked to a B-stage state to maintain a relatively flat and easily deformable shape. The second embodiment 230 has a second active surface 231 and a second back surface 232. The second active portion of the second wafer 230 is formed with a plurality of second recording pads 233. The edge spacers 250 are adhesively attached to the second back side 232 of the second wafer 230 at a suitable press-fit temperature, such that the second tie is disposed on the edge spacers 250. Alternatively, the second wafer 230 may be bonded using another crucible. In addition, the second solder pads 233 and the fingers 2 1 3 of the substrate 210 may be electrically connected. In this embodiment, the second 232 of the second wafer 203 is formed with a crystal back protective paste 234. The size of the second crucible may be the same as the size of the first wafer 220. Specifically, the multi-wafer stacked package structure 2 can be another mold encapsulation 260, which is formed on the substrate 211 to seal the first wafer 220 and the second wafer 23 The spacer colloid 250 and the second bonding wires 242 enable the adhesive bond of the multi-chip 220 to be adhered to the adhesive body and the opposite surface 23 1 The sheet 230 is bonded to the second back sheet 230 and includes the upper surface. The edge stacking cover 12 200836306 The internal components of the structure 20 are separated from the outside to avoid being damaged by external moisture or pollutants. Referring to FIG. 2 again, preferably, the molding compound 260 can be further filled in the central gap between the first wafer 220 and the second wafer 230 to increase the wafer coating property to improve product reliability. Therefore, in the multi-wafer stack package structure 200, the edge spacer 65 can be used to stack the second wafer 230 without providing a central spacer between the wafer stacks, without stacking the wafers above. The problem of pressing the lower wire bond is obtained, and better wire support is obtained. The wire bonding support may be further provided at a position where the second pads 230 are disposed on the second wafer 230, and the force of the second wafer 230 and the substrate 210 may be withstood to prevent the second wafer from being prevented. 2 3 0 rupture damage. In addition, the edge spacer colloid 250 is coated with the first fresh line 241, so that the first bonding wire 241 is not short-circuited due to the punching line due to the pressure of the stamper and the mold flow speed. The problem of disconnection caused by wire breakage. The multi-wafer stack package structure 200 is applicable not only to memory cards, but also to general semiconductor package products such as ball grid array package (BGA), planar array package (LGA) or thin outline package (TSOP), etc. . 4A to 4C are views for explaining a method of manufacturing the multi-wafer stacked package structure 200 according to the first embodiment of the present invention. First, as shown in FIG. 4A, a first wafer 220 is disposed on a substrate 210'. The first back surface 222 of the first wafer 220 is adhered to the substrate 13 200836306 2 1 0, wherein the first wafer 2 2 〇 1糸 has a plurality of first pads 2 2 3 , and the first pads 223 are formed on the first active surface 221 of the wafer 220 of the crucible. The substrate 210 has a right L branch, and has an upper surface 211 and a lower surface 2 1 2 '. The upper surface 2 1 1 is selected and formed with a plurality of wire bonding fingers 213, and the substrate 2 1 0 is further Having a plurality of contacts, drinking 塾 2 1 4, the contact pads 2 1 4 are formed on the lower surface 2 1 2 〇 刹 刹 丄 用 a plurality of first bonding wires 241 formed by a wire bonding technique to connect the first- The wires 223 and the wire bonding fingers 213' are used to achieve electrical connection between the first plate 220 and the substrate 210. After that, please refer to the 4th image of the map - the map, the screen printing, screen printing or steel plate printing special way to form the edge of the bucket - 5» wind edge gap colloid 2 50 on the first wafer 2 2 0 On the 'make the edge gap glue? The J (four) plastic basket 250 is formed on one side of the first active surface 221 of the first wafer 22, the edge of the hopper, the side of the first wafer 220, and the substrate 210, and is high and the same The first active surface 221 is configured to seal at least one of the first bright lines 241 and the deep Z4 1 . The edge spacer colloid 2 5 Ο
係可選自於環氧樹脂（ep〇Xy)與Β階（B_stage)膠體之其 中之一。並經適當烘烤，以維持間隔特性。 最後’凊參閱第4C圖所示，設置一第二晶片23 〇 於該邊緣間隔膠體250上，該第二晶片23〇係具有一第 二主動面231及一相對之第二背面232。該第二主動面 231係形成有複數個第二銲墊233，該第二背面232更 形成有一晶背保護膠23 4。再以打線方式形成之複數個 第二鲜線242 ’其係電性連接該些第二銲墊233至該基 板2 1 0之打線接指2 1 3 14 200836306 因此’在上述多晶片堆疊封裝製程中，可在不 在晶片堆疊之間設置中央間隔物之條件下，堆疊該 晶片230時，該第二晶片23〇不會壓觸該些第一 2 4 1 ’並且解決在打線形成該第二銲線2 4 2時由支 緣產生第二晶片2 3 0斷裂的問題。 在本發明之第二具體實施例，揭示另一種多晶 燊封裝構造。請參閱第5圖所示，該多晶片堆疊封 造300主要包含一基板310、一第一晶片320、一 Ο 晶片3 3 0、複數個第一銲線3 4 1、複數個第二銲線 以及複數個邊緣間隔膠體351、352、353與354。 該基板310係具有一上表面311及一下表面3 該上表面3 1 1係形成有複數個打線接指（圖中未繪 该第一晶片320係具有一第一主動面321，該第一 面321係形成有複數個第一銲墊322。該第一晶片 係设置於該基板3丨〇之該上表面3丨丨並且該第一 ^ 3 2 0之该第一主動面3 2 1係為朝上。該些第一銲_ 德電性連接該些第一銲墊3 22至該基板3丨〇之打 指。 "月再參閱5圖所示，該第一邊緣間隔膠體351 成於該第一晶片320之第一主動面321之一邊緣、 〆日日片320之側面與該基板3丨〇上並且高出於該第 動面321 ’以至少密封該些第一銲線341之一部位 隹地，該第一邊緣間隔膠體351係可高於該些第一 341之弧高’藉以避免在堆疊晶片時，該第二晶片 需要 第二 鋅線 撐邊 片堆 裝構 第二 342 12， 出）° 主動 320 晶片 ：341 線接 係形 該第 一主 〇較 鲜線 330 15 200836306 壓觸該些第一銲線341。 該第二晶片330係具有一第二主動面331 形成於該第二主動面331之第二銲墊332。該 3 3 0係設置於該第一邊緣間隔膠體3 5 1上並使 銲墊3 3 2為朝上，以供該些第二銲線3 42電性 第二銲墊3 3 2至該基板3 1 0。在本實施例中， 堆疊封裝構造 300可另包含有一第二邊緣 3 5 2，其係形成於該第二晶片3 3 0之第二主動 〇 一邊緣、該第二晶片3 3 0之側面與該第一邊緣 351上並且高出於該第二主動面331，以至少 第二銲線342之一部位。 請再參閱第5圖所示，該多晶片堆疊封裝 可另包含一第三晶片3 70及一第四晶片3 80， 憶體容量。該第三晶片3 70係設置於該第二邊 體3 52上，並藉由複數個第三銲線343電性連 ^ . 晶片370之複數個第三銲墊3 72,其中該些第三 係形成於該第三晶片3 70之一第三主動面371 實施例中，該多晶片堆疊封裝構造3 00可另包 三邊緣間隔膠體3 53，其係形成於該第三晶片 三主動面3 7 1之一邊緣、該第三晶片3 70之側 二邊緣間隔膠體3 52上並且高出於該第三主動 以供堆疊該第四晶片 3 8 0。其中該第三邊緣 3 5 3係至少密封該些第三銲線3 43之一部位。 該第四晶片3 8 0係堆疊於該第三邊緣間隔 及複數個 弟二晶片 該些第二 連接該些 該多晶片 間隔膠體 面3 3 1之 間隔膠體 密封該些 構造 3 0 0 以擴充記 緣間隔膠 接該第三 .銲墊372 上。在本 含有一第 370之第 面與該第 面 371， 間隔膠體 膠體353 16 200836306 上’並藉由複數個第四銲線3 44電性連接該第四 380之複數個第四銲塾382。在本實施例中，該多 堆豐封裝構造300可另包含有一第四邊緣間隔 354’其係形成於該第四晶片380之_第四主動面 之一邊緣、該第四晶片3 80之側面與該第三邊緣間 體353上並且高出於該第四主動面381，以至少密 些第四銲線344之一部位。 ◎ 具體而言，該多晶片堆疊封裝構造3 00可另包 一模封膠體3 6 0，其係密封該第一晶片3 2 0、該第 片3 3 0、該第三晶片37〇、該第四晶片38〇、該第 緣間隔膠體3 5 1、該第二邊緣間隔膠體3 5 2、該第 緣間隔膠體3 53與該第四邊緣間隔膠體354。請再 第5圖所示，所有的銲線34 i、342、343與344在 之前即被該些邊緣間隔膠體351、352、353與354 包覆達到防沖線的保護效果，使得該多晶片堆疊封 (J 造3 00的製造良率更為提高。 此外，上述之堆疊於第一晶片320之其餘晶片 3 70與3 80皆係分別疊設於該些邊緣間隔膠體351 與3 5 3上，故可省略習知之在晶片間設置一中央 物，且不有位於上層之該些晶片330、37〇與380 該些下方銲線341、342與343之問題，亦可提供 上層之該些晶片330、370與380良好的打線支擇 避免位於上層之該些晶片330、370與380因受打 合力而崩裂損壞。 晶片 晶片 膠體 38 1 隔膠 封該 含有 二晶 一邊 三邊 參閱 模封 預先 裝構 33 0、 〜352 間隔 壓觸 位於 性， 線接 17 200836306 以上所述’僅是本發明的較佳實施例而已，並非 本發明作任何形式上的限 ,,,-^ , L 雎然本發明已以較佳實施 例揭路如上，然而並非用 酱从社a 本發明，任何熟悉本專 業的技術人員，在不脫離本發明技術方案範圍内，合可 利用上述揭示的技術内容作出些許更動或修飾為; 變化的等效實施例，但凡是未脫離本發明技術方宰的内 依據本發明的技術實質對以上實施例所作的任何簡It may be selected from one of epoxy (ep〇Xy) and B_stage colloids. And properly baked to maintain the spacing characteristics. Finally, referring to FIG. 4C, a second wafer 23 is disposed on the edge spacer colloid 250. The second wafer 23 has a second active surface 231 and an opposite second back surface 232. The second active surface 231 is formed with a plurality of second pads 233, and the second back surface 232 is further formed with a crystal back protective material 234. Then, a plurality of second fresh lines 242 ′ are formed by wire bonding, and the second bonding pads 233 are electrically connected to the bonding wires 2 1 3 14 200836306 of the substrate 2 1 0. Therefore, the above multi-wafer stack packaging process In the case that the central spacer is not disposed between the wafer stacks, when the wafer 230 is stacked, the second wafer 23 does not press the first 2 1 1 ' and solves the formation of the second solder in the wire bonding. The problem of the second wafer 203 breaking is caused by the rim at line 24.2. In a second embodiment of the invention, another polysilicon package construction is disclosed. Referring to FIG. 5, the multi-wafer stack sealing assembly 300 mainly includes a substrate 310, a first wafer 320, a silicon wafer 303, a plurality of first bonding wires 341, and a plurality of second bonding wires. And a plurality of edge spacers 351, 352, 353 and 354. The substrate 310 has an upper surface 311 and a lower surface 3. The upper surface 31 1 is formed with a plurality of wire bonding fingers (the first wafer 320 is not depicted as having a first active surface 321 , the first surface 321 is formed with a plurality of first pads 322. The first wafer is disposed on the upper surface 3 of the substrate 3 and the first active surface 3 2 1 of the first ^ 3 0 0 is Upward, the first edge _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ An edge of the first active surface 321 of the first wafer 320, a side surface of the next day 320, and the substrate 3 are raised and raised by the first moving surface 321 ' to at least seal the first bonding wires 341 The first edge spacer gel 351 can be higher than the arc heights of the first 341 to avoid the second wafer requiring the second zinc wire edge stacking structure 342 when the wafer is stacked. 12, out) ° active 320 wafer: 341 wire connection system, the first main line, fresh line 330 15 200836306 pressure on the first wire 3 41. The second wafer 330 has a second active pad 331 formed on the second pad 332 of the second active surface 331 . The 303 is disposed on the first edge spacer 35 1 1 and the pad 3 3 2 is facing upward, so that the second bonding wires 3 42 electrically elective the second pad 3 3 2 to the substrate 3 1 0. In this embodiment, the stacked package structure 300 may further include a second edge 315 formed on the second active edge of the second die 310, and the side of the second die 305. The first edge 351 is above and above the second active surface 331 to at least one of the second bonding wires 342. Referring to FIG. 5 again, the multi-wafer stack package may further include a third wafer 370 and a fourth wafer 380, which have a memory capacity. The third wafer 3 70 is disposed on the second side body 3 52 and electrically connected to the plurality of third bonding pads 3 72 of the wafer 370 by a plurality of third bonding wires 343, wherein the third Formed in the third active surface 371 embodiment of the third wafer 370, the multi-wafer stacked package structure 300 may be further provided with a three-edge spacer colloid 3, which is formed on the third active surface 3 of the third wafer. One of the edges of the third wafer 3 70 is disposed on the side edge of the third wafer 3 70 and is higher than the third active for stacking the fourth wafer 380. The third edge 353 further seals at least one of the third bonding wires 343. The fourth wafer 380 is stacked on the third edge and the plurality of second dies. The second spacers are connected to the spacers. The spacers are sealed to seal the structures 30,000 to expand the mark. The spacer is glued to the third. pad 372. In the first surface of the first 370 and the first surface 371, the spacer colloid 353 16 200836306 is electrically connected to the fourth 380 of the fourth 380 by a plurality of fourth bonding wires 3 44 . In this embodiment, the multi-package package structure 300 may further include a fourth edge spacer 354 ′ formed on one edge of the fourth active surface of the fourth wafer 380 and the side of the fourth wafer 380 . And the third edge body 353 is higher than the fourth active surface 381 to at least one of the fourth bonding wires 344. ◎ In particular, the multi-wafer stack package structure 300 may additionally include a mold seal body 360, which seals the first wafer 320, the third wafer 300, the third wafer 37, and the The fourth wafer 38〇, the edge spacer colloid 3 5 1 , the second edge spacer colloid 3 5 2, the edge spacer colloid 3 53 and the fourth edge spacer colloid 354. As shown in FIG. 5, all the bonding wires 34 i, 342, 343 and 344 are covered by the edge spacers 351, 352, 353 and 354 to achieve the protection effect of the anti-shock line, so that the multi-chip The manufacturing cost of the stacked package is further improved. In addition, the remaining wafers 3 70 and 380 stacked on the first wafer 320 are respectively stacked on the edge spacers 351 and 353. Therefore, it is possible to omit the conventional problem of providing a central object between the wafers, and there are no problems of the lower bonding wires 341, 342 and 343 of the wafers 330, 37A and 380 located in the upper layer, and the upper layers of the wafers can also be provided. The good wire bonding of 330, 370 and 380 avoids the chip 330, 370 and 380 located in the upper layer being broken and damaged due to the combined force. The wafer wafer colloid 38 1 is sealed with a double crystal and the three sides are pre-assembled. Structures 33 0, 352 are spaced by the pressure, and the line connection 17 200836306 is described above as a preferred embodiment of the present invention, and is not a limitation of any form of the present invention, -^, L 雎然The invention has been disclosed above in the preferred embodiment, however In the present invention, any person skilled in the art can make some modifications or modifications using the above-disclosed technical contents without departing from the technical scope of the present invention; Any simplification of the above embodiments in accordance with the technical essence of the present invention without departing from the technical scope of the present invention
單修改、等同變化與修飾，均仍屬於本發明技術方案二 範圍内。 【圖式簡單說明】 第1圖：一種習知多晶片堆疊封裝構造之截面示意圖。 第2圖：依據本發明之第一具體實施例，一種多晶片堆 疊封裝構造之截面示意圖。 第3圖：依據本發明之第一具體實施例，該多晶片堆疊 封裝構造在製程中形成一邊緣間隔膠體之立 體示意圖。 第4 A至4 C圖：依據本發明之第一具體實施例，該多 晶片堆疊封裝構造於製程中一基板之載面示 意圖。 第5圖：依據本發明之第二具體實施例，另一種多晶片 堆豐封裝構造之截面示意圖。 【主要元件符號說明】 10 點膠針頭 100多晶片堆疊封裝構造 18 200836306The single modification, the equivalent change and the modification are still within the scope of the technical solution 2 of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a conventional multi-wafer stacked package structure. Figure 2 is a cross-sectional view showing a multi-wafer stack package structure in accordance with a first embodiment of the present invention. Figure 3: A schematic view of a multi-wafer stack package structure forming an edge spacer colloid in a process in accordance with a first embodiment of the present invention. 4A through 4C: According to a first embodiment of the present invention, the multi-wafer stack package is constructed in accordance with a carrier surface of a substrate in a process. Figure 5 is a cross-sectional view showing another multi-wafer stack package structure in accordance with a second embodiment of the present invention. [Main component symbol description] 10 dispensing needle 100 multi-chip stacking package structure 18 200836306
Ο 110 基板 111 上表面 112 下表面 113 打線接指 114 接觸墊 120 第一晶片 121 第一主動面 122 第 一背面 123 第一銲墊 130 第二晶片 131 第二主動面 132 第 二背面 133 第二銲墊 134 支撐斷裂點 141 第一銲線 142 第二銲線 150 中央間隔物 160 模封膠體 200 多晶片堆疊封裝構造 210 基板 211 上表面 212 下表面 213 打線接指 214 接觸墊 220 第一晶片 221 第一主動面 222 第 一背面 223 第一銲墊 230 第二晶片 231 第二主動面 232 第 二背面 233 第二銲墊 234 晶背保護膠 241 第一銲線 242 第二銲線 250 邊緣間隔膠體 260 模封膠體 300 多晶片堆疊封裝構造 310 基板 311 上表面 312 下表面 320 第一晶片 321 第一主動面 322 第 一銲墊 330 第二晶片 331 第二主動面 332 第 二鲜塾 341 第一銲線 342 第二銲線 343 第 三鮮線 344第四銲線 351第一邊緣間隔膠體 19 200836306 352 第 二 邊 緣間1 隔膠體 353 第 三 邊 緣間1 隔膠體 354 第 四 邊 緣間1 隔膠體 360 模 封 膠 體 370 第 三 晶 片 371 第 三主動面 372 380 第 四 晶 片 381 第 四主動面 382 第三銲墊 第四銲墊Ο 110 substrate 111 upper surface 112 lower surface 113 wire bonding finger 114 contact pad 120 first wafer 121 first active surface 122 first back surface 123 first pad 130 second wafer 131 second active surface 132 second back surface 133 second Pad 134 Supporting Breaking Point 141 First Bonding Wire 142 Second Bonding Wire 150 Central Spacer 160 Molding Compound 200 Multi-Wafer Stacking Package Structure 210 Substrate 211 Upper Surface 212 Lower Surface 213 Wire Bonding Finger 214 Contact Pad 220 First Wafer 221 First active surface 222 first back surface 223 first solder pad 230 second wafer 231 second active surface 232 second back surface 233 second solder pad 234 crystal back protective rubber 241 first bonding wire 242 second bonding wire 250 edge spacer colloid 260 Molding Compound 300 Multi-Wafer Stack Package Structure 310 Substrate 311 Upper Surface 312 Lower Surface 320 First Wafer 321 First Active Surface 322 First Pad 330 Second Wafer 331 Second Active Surface 332 Second Fresh 塾 341 First Solder Line 342 second bonding wire 343 third fresh wire 344 fourth bonding wire 351 first edge spacer colloid 19 200836306 3 52 Second edge gap 1 Separator 353 Third edge gap 1 Separator 354 Fourth edge gap 1 Glue body 360 Molding compound 370 Third wafer 371 Third active surface 372 380 Fourth wafer 381 Fourth active surface 382 Third Pad fourth pad
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