200926389 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種背對背堆疊之多晶片封裝技 術，特別係有關於一種防止晶片上沖線與碰觸晶片邊緣 之背對背堆疊之多晶片封裝構造及其製造方法。 【先前技術】 在積體電路之多晶片封裝構造的領域中，複數個半 導體晶片可堆疊設置於一基板上，以達到高密度之封裝 並節省整個元件的表面接合面積。其中，依晶片主動面 朝向方向的不相同’晶片堆疊方式可進一步區別為背對 面之晶片主動面朝上堆疊、面對面之覆晶堆疊以及背對 背之晶片堆疊。 請參閱第1圖所示’習知背對背堆疊之多晶片封裝 構造100主要包含一基板110、背對背堆疊之一第一晶 片120與一第二晶片140、複數個銲線131與132、以 及一模封膠體160。該第一晶片12〇之第一主動面121 係貼附於該基板1 1 〇之上表面1 1 1，並使複數個位於該 第一主動面121之中央銲墊123對準於該基板11〇之打 線槽孔113内。該些第一銲線131通過該打線槽孔113 以電性連接該些中央銲墊123至該基板110。該第二晶 片140之第二背面142係貼附於該第一晶片12〇之第一 背面122 ’即背對背方式晶片堆疊。該第二晶片140之 第二主動面141係形成有複數個周邊銲墊143，可藉由 該些第二銲線132電性連接該些周邊銲墊143至該基板 5 200926389 11 ο。該模封膠體160係用以密封該第一晶片12〇、該 第二晶片ι4〇以及該些銲線131與m。複數個外接端 子170係設置於該基板110之下表面112。然而’該第 一晶片1 2 〇與該第二晶片1 4 0之銲墊配置位置並不相 同，方可滅少該些銲線1 3 2在該第二晶片1 4 0上的懸办 長度，故在製造時則必須製作不同種類之晶片，該第_ 晶片14 0在晶圓等級須另製作一層重分配線 • 将·層 Ο ❸ (Redistribution Layer，RDL)以將原在中央辉執 、 恐之位置 改變為周邊銲墊143,使得製造成本增加， 並因晶片種 類增加亦會造成物料較難以控管。 我國專利公告第407354號「一種雙晶片 造」，揭示一種以背對背晶片堆疊方式多晶之封裝構 造’其中上層晶片與下層晶片係具有配置片封裝構 央銲墊，故可減少晶片種類以降低製造成本。♦同之中 線電性連接上層晶片之中央_塾至基板時’ i f上層銲 上層晶片之主動面之懸空長度較長，在模I銲線在 封膠體之注膠沖擊力將使上層銲線產生時，由於模 外，上層晶片之中央銲塾與基板之打線接問題。此 面，上層銲線易接觸到上層晶片之在同-平 題。 或短路之問 【發明内容】 本發明之主要目的係在於提供一種背對 晶片封裝構造及其製造方法，可選用相堆叠之多 配置之上層晶片與下層晶片做背對背晶片±中央銲墊 B曰隹疊，藉以降 6200926389 IX. INSTRUCTIONS: TECHNICAL FIELD The present invention relates to a multi-chip package technology for back-to-back stacking, and more particularly to a multi-chip package structure for preventing back-to-back stacking of punched and touched wafer edges on a wafer. And its manufacturing method. [Prior Art] In the field of multi-chip package construction of integrated circuits, a plurality of semiconductor wafers can be stacked on a substrate to achieve high-density packaging and save surface joint area of the entire component. Among them, the different wafer stacking manner according to the direction of the active surface of the wafer can be further distinguished by the wafer facing active face-up stacking, the face-to-face flip chip stacking, and the back-to-back wafer stack. Referring to FIG. 1 , the multi-chip package structure 100 of the back-to-back stack includes a substrate 110 , a first wafer 120 and a second wafer 140 , a plurality of bonding wires 131 and 132 , and a die . Sealant 160. The first active surface 121 of the first wafer 12 is attached to the upper surface 112 of the substrate 1 1 , and a plurality of central pads 123 located on the first active surface 121 are aligned with the substrate 11 . Inside the wire slot 113. The first bonding wires 131 are electrically connected to the central pads 123 to the substrate 110 through the wire slot holes 113. The second back surface 142 of the second wafer 140 is attached to the first back surface 122' of the first wafer 12, that is, the back-to-back wafer stack. The second active surface 141 of the second wafer 140 is formed with a plurality of peripheral pads 143, and the second bonding wires 132 are electrically connected to the peripheral pads 143 to the substrate 5 200926389 11 . The molding compound 160 is used to seal the first wafer 12, the second wafer, and the bonding wires 131 and m. A plurality of external terminals 170 are disposed on the lower surface 112 of the substrate 110. However, the position of the pads of the first wafer 1 2 〇 and the second wafer 140 is not the same, so that the hanging length of the bonding wires 1 3 2 on the second wafer 1400 can be eliminated. Therefore, different types of wafers must be fabricated at the time of manufacture. The first wafer 104 must be made of another layer of redistribution lines at the wafer level. • The Redistribution Layer (RDL) will be used to The position of the fear is changed to the peripheral pad 143, so that the manufacturing cost is increased, and the increase in the type of the wafer also makes the material more difficult to control. China Patent Publication No. 407354 "a two-chip fabrication" discloses a package structure in which a back-to-back wafer stack is polycrystalline, in which an upper wafer and a lower wafer have a layout chip layout pad, thereby reducing the number of wafers to reduce manufacturing. cost. ♦When the center line is electrically connected to the center of the upper wafer _塾 to the substrate, the suspended surface length of the active surface of the upper layer of the upper layer is longer, and the impact of the injection of the mold wire in the sealing body will make the upper bonding wire When produced, due to the mold, the central soldering of the upper wafer is connected to the substrate. In this case, the upper bonding wire is easy to contact the same-level problem of the upper wafer. Or a short circuit [invention] The main object of the present invention is to provide a back-to-wafer package structure and a manufacturing method thereof, which can be used as a back-stacked wafer and a central pad of a multi-distribution upper layer wafer and a lower layer wafer. Stack, borrowing to drop 6
200926389 低晶片之製造成本與管理成本，並能解決長辉線在上 晶片上沖線以及碰觸晶片邊緣之問題。 本發明之次一目的係在於提供一種背對背堆巷之 晶片封裝構造及其製造方法，得有效界定所使用之線 結元件之形成區域。 本發明之另一目的係在於提供一種背對背堆昼之 晶片封裝構造及其製造方法，能修正並固定長鮮線在 層晶片上之形狀，以使長銲線在該上層晶片上為接近 平’並在該上層晶片之邊緣能為大幅度驚曲。 本發明之另一目的係在於提供一種背對背堆叠之 晶片封裝構造及其製造方法，能創造一種模擬下模流 道之上模流通道，以達上下模流平衡。 本發明的目的及解決其技術問題是採用以下技術 案來實現的。依據本發明之一種背對背堆疊之多晶片 裝構造主要包含一基板、一第一晶片、複數個第一 線、一第二晶片、複數個第二銲線、至少一線凍結元 以及一模封膠體》該第一晶片係設置於該基板上並具 複數個第一銲墊。該些第一銲線係電性連接該第一晶 之該些第一銲墊至該基板。該第二晶片係以背對背堆 方式設置於該第一晶片上並具有複數個第二銲墊。該 第二錄線係電性連接該第二晶片之該些第二銲墊至 基板。該線凍結元件係黏附至該第二晶片之一主動面 並包覆該些第二銲線之一局部線段。該模封膠體係密 該些第一銲線、該些第二銲線、該第一晶片、 層 多 凍 多 上 水 多 通 方 封 銲 件 有 片 疊 些 該 上 封 一第二晶 7 200926389 片以及該線凍結元件。其中，該些第一銲墊與該些第二 銲墊皆為中央型銲墊，以使該些第二銲線長於該些第一 銲線。此外，另揭示前述背對背堆疊之多晶片封裝構 造之製造方法。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的背對背堆疊之多晶片封裝構造中，該第一晶 片與該第二晶片係可為實質相同之晶片。 〇 在前述的背對背堆疊之多晶片封裝構造中，該線凍結 元件係可為液態塗佈之固化膠體。 在前述的背對背堆疊之多晶片封裝構造中，該線凍結 元件係可為複數條狀，並沿著該些第二銲墊之排列方向 黏附至該第二晶片之一主動面上。 在前述的背對背堆疊之多晶片封裝構造中，該基板係 可具有一打線槽孔，以供該些第一銲線之通過，並且該 _ 些線凍結元件係不覆蓋該些第二銲墊，以使該些線凍結 ❹ 元件在條與條之間係形成有一上模流通道。 在前述的背對背堆疊之多晶片封裝構造中，由該些條 狀線凍結元件形成之該上模流通道係可具有一間隙，其 係不小於該打線槽孔之寬度。 在前述的背對背堆疊之多晶片封裝構造中，該些線凍 結元件係可不覆蓋至該第一晶片與該第二晶片之側面 以及該基板之一上表面。 在前述的背對背堆疊之多晶片封裝構造中，該線凍結 8 200926389 元件係可包含有 位於該些第二録 —線墩以及一200926389 Low-wafer manufacturing cost and management cost, and can solve the problem that the long-light line is on the upper wafer and touches the edge of the wafer. A second object of the present invention is to provide a wafer package structure for a back-to-back stack and a method of fabricating the same that effectively define the formation regions of the wire bond components used. Another object of the present invention is to provide a back-to-back stacking chip package structure and a manufacturing method thereof, which can correct and fix the shape of the long fresh wire on the layer wafer so that the long bonding wire is close to flat on the upper wafer. And at the edge of the upper wafer can be a large shock. Another object of the present invention is to provide a back-to-back stacked wafer package structure and a method of fabricating the same that can create a simulated mold flow channel above the lower mold flow path for up-and-down mold flow balance. The object of the present invention and solving the technical problems thereof are achieved by the following techniques. A multi-chip package structure of a back-to-back stack according to the present invention mainly comprises a substrate, a first wafer, a plurality of first lines, a second wafer, a plurality of second bonding lines, at least one line of freezing elements, and a mold sealing body. The first wafer is disposed on the substrate and has a plurality of first pads. The first bonding wires are electrically connected to the first pads of the first crystal to the substrate. The second wafer is disposed on the first wafer in a back-to-back stack and has a plurality of second pads. The second recording line electrically connects the second pads of the second wafer to the substrate. The wire freezing component is adhered to one of the active faces of the second wafer and covers a partial line segment of the second bonding wires. The mold sealing system is dense with the first bonding wires, the second bonding wires, the first wafer, the layer multi-frozen multi-water multi-passing sealing member has a stack of the upper sealing and the second crystal 7 200926389 And the line freeze component. The first bonding pads and the second bonding pads are all central bonding pads, so that the second bonding wires are longer than the first bonding wires. Further, a manufacturing method of the above-described back-to-back stacked multi-wafer package structure is disclosed. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the multi-chip package construction of the back-to-back stack described above, the first wafer and the second wafer may be substantially identical wafers. 〇 In the aforementioned back-to-back stacked multi-chip package construction, the line freeze element can be a liquid coated solidified gel. In the foregoing multi-chip package structure of the back-to-back stack, the line freeze element may be in a plurality of strips and adhered to one of the active faces of the second wafer along the arrangement direction of the second pads. In the foregoing multi-chip package structure of the back-to-back stack, the substrate may have a wire slot for the first wire to pass, and the wire freeze components do not cover the second pads. In order for the lines to freeze, the element is formed with an upper mold flow path between the strips. In the foregoing multi-chip package construction of the back-to-back stack, the upper mold flow path formed by the strip line freezing elements may have a gap which is not less than the width of the wire slot. In the multi-chip package construction of the back-to-back stack described above, the wire-freezing components may not cover the sides of the first wafer and the second wafer and the upper surface of one of the substrates. In the foregoing multi-chip package construction of the back-to-back stack, the line freeze 8 200926389 component system may include the second record-line piers and one
在前述的背對背堆疊之多晶 質係可為液態環氧樹脂。 深敏以及一覆線物質，其中該線墩係 之下方’用以支撐該呰第二銲線並定 該覆線物質包覆之局部線段。 f堆疊之多晶片封裝構造中，該線墩係 n-Chip，引腳在晶片上型式）黏晶膠 之多晶片封裝構造中’該覆線物 在前述的背對背堆疊之多晶片封裝構造中，可另包含The polycrystalline system stacked back to back as described above may be a liquid epoxy resin. Deep sensitive and a covered material, wherein the underside of the wire pier is used to support the second wire of the crucible and to define a partial line covered by the covering material. In a multi-chip package structure of a f-stack, the line is n-Chip, the pin is in a wafer-on-type) multi-chip package structure of a die-adhesive, in the multi-chip package structure of the back-to-back stack described above, Can be included
有複數個LOC 點晶膠帶，以黏著該第/晶片之一主動 面至該基板。 在則述的背對背堆疊之多晶片封裝構造中’可另包含 有複數個外接端子，其係接合該基板之/下表面。 在前述的背對背堆疊之多晶片封裝構造中’該些外接 端子係可包含複數個銲球。 【實施方式】 依據本發明之第一具體實施例，具體揭示一種背對 背堆疊之多晶片封裝構造。請參閱第2澍所示’ 一種背 對背堆疊之多晶片封裝構造200主要包含一基板210、 一第一晶片220、複數個第一銲線231、一第二晶片 24〇、複數個第二銲線232、至少一線凍結元件250以 及一模封膠體260。 該基板210係具有一上表面211、乂下表面212以 及一打線槽孔2 1 3，該打線槽孔2 1 3係由該上表面2 1 1 9 200926389 貫穿至該下表面212，以供該些第一銲線 該下表面2 1 2位於該打線槽孔2 1 3之兩側 個複數第一接指214，該上表面211係形 二接指215。而該基板210係可為多層印 使該些第一接指214與該些第二接指215 該下表面212之外接墊（圖中未燴出，在 端子170之接合部位）。 該第一晶片2 2 0係設置於該基板2 1 〇 並具有一第一主動面221以及一相對之第 該第一主動面221係形成有複數個第一錦 位於該第一主動面221之中央區域，即 223為中央銲墊。其中，該第一晶片22〇 面221係朝向該基板210並使該些第一銲 於該打線槽孔213内。該些第一鲜線231 槽孔213並電性連接該第—晶片220之 223至該基板210之該些第一接指214， 片220與該基板210之電性互連。 該第二晶片240係具有一第二主動面 之第二背面242以及複數個形成於該第二 第二銲墊243。該第二晶片24〇之該第二 設於該第一晶片220之該第—背面222， 2 4 0係以背對背晶片堆疊方式設置於該 上’而使該第二主動面241係為朝上。請 示’該些第二銲墊243係位於該第二晶片 23 1之通過。 係形成有複數 成有複數個第 刷電路板，以 電性連接至在 第2圖中外接 之上表面2 11 一背面222， 墊223 ，其係 該些第一銲·塾 之該第一主動 墊223係對準 係通過該打線 該些第一鲜塾 達到該第一晶 2 4 1、一相對 主動面24 1之 背面242係貼 即該第二晶片 第一晶片220 參閱第3圖所 240之該第二 10 200926389 主動面24 1之中央區域，故該些第二銲墊243亦為中央 銲塾°較佳地，該第一晶片220與該第二晶片240係可 為實質相同之晶片’例如晶片尺寸、電性功能與銲墊配 置位置皆為相同，以減少晶片種類進而降低晶片之製造 成本與管理成本。該些第二銲線232係電性連接該第二 晶片240之該些第二銲墊243至該基板21〇之該些第二 接指2 1 5 ’達到該第二晶片24〇與該基板2 1 〇之電性互 連。因此，該些第一銲墊223與該些第二銲墊243皆為 中央型銲墊，並使該些第二銲線232長於該些第一銲線 231 〇 請參閱第2圖所示，該線凍結元件250係包覆該些 第二銲線232之一局部線段並黏附至該第二晶片240之 該第二主動面2 4 1上。這裡所指的「凍結」是指該線凍 結元件2 5 0在塗施時為液態或膠態而具有適當之流動 性，並在產品完成後為固態，以固著封住該些第二銲線 2 3 2。該線凍結元件2 5 0係可為液態塗佈之固化膠體， 具有熱固化性或光固化性’能包覆銲線線段之後更附著 於該第二晶片240之該第二主動面241。請參閱第4圖 所示’在本實施例中，該線凍結元件25〇係可為複數條 狀’並沿著該些第二銲墊243之排列方向黏附至該第二 晶片240之該第二主動面241上，具有打線後易於塗佈 之功效。請參閱第2圖所示，該些線凍結元件250係可 不覆蓋至該第一晶片220與該第二晶片24〇之側面以及 該基板210之該上表面211，即位於該些第二錄線232 11 200926389 之最南弧高處，以增加該些線凉沾_ /泉結το件250固化前的垂 重效果，藉以改變並固定該些坌_ λ 一卑一銲線232在第二晶片 2 4 0上之形狀。在該線凍結元仕 件250轉變成固態之後， 可以避免該些第二銲線23 2在拎垃 碎第二晶片240上產生沖 線與避免碰觸至該第二晶片^ * 之邊緣。 該模封膠體260係密封該此货 /劣第一銲線231、該些第 二銲線232、該第一晶片22〇、 也 第一晶片240以及該 線凍結元件2 5 0，以避免該背钒北 μ 對背堆疊之多晶片封裳構 造200之内部元件受到外界污 杂物污染。較佳地，該肚 線凍結元件2 5 0係不覆蓋該此货 一 &第二銲墊243，以使該此 線凍結元件2 5 0在條與條之μ μ ~ 間係形成有一上模流通道 2 6 1，其係對稱形成於該打線 ^ ⑽，以在模封時達上下模213之下模流通道 由該些條狀線珠結元件250形由千衡。在本實施例中， 吁具有-間隙，其係不小於之該上模流通道261係 « _ μ打線槽孔213之寬度。 Φ 具體而言，該背對背堆叠之 J之見度 <另包含有複數個外接端子27多晶片封裝構造200係 之該下表面212，以作為該背其係接合該基板 造20〇之輸出/輸入 堆疊之多晶片封裝構 ^ ^ Μ Φ Χ± #些外接端子270係可包 印刷電路板。在本實施例中， 接之一外部裝置如 含複數個銲球。 因此，本發明之該背對背 町使用實質相同的該第—日日 ®乏多阳片封裝構造200 雉疊，也因而不必鉍眛&日曰220與該第二晶片24〇做 个乂牦時費工地製 表作另一種周邊銲墊型之 12 200926389 晶片，不僅可降低晶片之製造成本也可使晶片 於控管。此外，亦可藉由該線凍結元件2 5 〇穩 二鲜線23 2,避免在封膠過程中該些第二銲線 沖線之現象或/及碰觸至該第二晶片240之第 241之邊緣，而引發短路或是損害該些第二銲 電性連接品質。 第5A至5H圖係用以說明前述背對背堆疊 封裝構造200之一具體製造方法。首先，請^ ® 圖所示，提供一基板210，該基板210係具有 2U、一下表面212以及一打線槽孔213，該下 係形成有複數個位於該打線槽孔2 1 3兩側之 214’該上表面211係形成有複數個第二接指 接著’請參閱第5B圖所示，設置一第一 於該基板210之該上表面211。其中該第一晶 以該第一主動面22 1朝下之方式貼設於該基相 ❹ 使該些第一銲墊223對準於該打線槽孔213户 該些第一銲墊223。接著，請參閱第5C圖所 (wire-bonding)形成複數個第一銲線23卜其係 線槽孔213並電性連接該第一晶片220之該些 223至該基板210之該些第一接指214。 在第一次電性連接後，請參閱第5D圖所开 背堆疊方式設置一第二晶片240於該第一晶> 也就是將該第二晶片240之一第二背面242貼 一晶片220之該第一背面222。其中，該第二 物料較易 固該些第 232產生 二主動面 線23 2之 之多晶片 ^閱第5A 一上表面 ‘表面212 第一接指 215 〇 晶片220 片220係 ί 210 ，並 !，以顯露 示，打線 穿過該打 第一銲墊 :，以背對 ί 220 上， 設於該第 -晶片2 4 0 13 200926389 係具有複數個第-雜 乐一銲墊243，其係形成至該 240之一第二主動 面241之中央區域。接著， 5 E圖所示，打錄jj,, 線形成複數個第二銲線232以 該第一 s曰片240之該些第二銲墊243至該基板 些第二接指215。丨中’該些第—銲塾223與 辉塾243皆$巾央型鲜塾，以使該些第二銲線 主動面24 1上。在本實施例中，該線凍結元件 為液態塗佈之固化膠體，以液態塗畫方式黏附 晶片240並加以熟化。例如，能以加熱或照射 適當之手段使該線凍結元件2 5 0轉變為固態。 結元件2 5 0在塗施時係可為勝稠態’又形成於 鲜線230之最南狐高處，提供一較佳垂重效果 正該些第二銲線230之形狀。在一較佳狀態， 銲線232在該第二晶片240之第二主動面241 呈接近水平，並在該第二晶片240之第二主動 邊緣能為大幅度彎曲。當該線凍結元件 2 5 0 態，能固定封住該些第二銲線2 3 2之易沖線絲 免在後續模封製程中產生沖線。 最後，請參閱第5G圖所示，形成一模封 於該基板210之該上表面211與該下表面21: 第二晶片 請參閱第 電性連接 2 1 〇之該 該些第二 232長於 一線凍結 25〇係先 至5亥第二 25〇係可 至該第二 紫外光等 當該線凍 該些第二 ，藉以修 該些第二 之上方概 面241之 轉變成固 段，以避 膠體260 :，用以密 該些第一銲線231» 之後’請參閱第5F及4圖所示，形成至少 元件250於該第二晶片240上，該線凍結元件 包覆該些第二銲線232之一局部線段，再黏附 ❹There are a plurality of LOC wafers to adhere the active surface of the first/wafer to the substrate. In the multi-chip package construction of the back-to-back stack described, it may additionally include a plurality of external terminals that engage the/lower surface of the substrate. In the foregoing multi-chip package construction of back-to-back stacks, the external terminals may comprise a plurality of solder balls. [Embodiment] According to a first embodiment of the present invention, a multi-chip package structure of a back-to-back stack is specifically disclosed. Referring to FIG. 2, a back-to-back stacked multi-chip package structure 200 mainly includes a substrate 210, a first wafer 220, a plurality of first bonding wires 231, a second wafer 24A, and a plurality of second bonding wires. 232. At least one line of freezing element 250 and a mold sealing body 260. The substrate 210 has an upper surface 211, a lower surface 212 and a wire slot 2 1 3 . The wire slot 2 1 3 extends from the upper surface 2 1 1 2009 200926389 to the lower surface 212 for the The lower surface 2 1 2 of the first bonding wires is located at a plurality of first fingers 214 on both sides of the wire slot 2 1 3 , and the upper surface 211 is formed by two fingers 215 . The substrate 210 can be multi-layer printed with the first contact 214 and the second contact 215 of the lower surface 212 (not shown in the figure, at the junction of the terminal 170). The first wafer 220 is disposed on the substrate 2 1 〇 and has a first active surface 221 and a first active surface 221 opposite to the first active surface 221 is formed on the first active surface 221 The central area, 223, is the center pad. The first surface 22 of the first wafer 22 faces the substrate 210 and the first portions are soldered into the wire slot 213. The first fresh wire 231 slot 213 is electrically connected to the first electrode 214 of the first wafer 220 to the first contact 214 of the substrate 210. The chip 220 is electrically connected to the substrate 210. The second wafer 240 has a second back surface 242 having a second active surface and a plurality of second pads 243 formed on the second surface. The second wafer 24 is disposed on the first back surface 222 of the first wafer 220, and the second back surface 222 is disposed on the upper side of the first wafer 220, and the second active surface 241 is upwardly disposed. . Please indicate that the second pads 243 are located in the second wafer 23 1 . Forming a plurality of plurality of brush circuit boards to electrically connect to the outer surface 2 11 and the back surface 222 in the second figure, the pad 223, which is the first active of the first solder joints The pad 223 is aligned to the first wafer 2 through the wire, and the back surface 242 of the opposite active surface 24 1 is attached to the second wafer 220. Referring to FIG. 3 The second 10 200926389 is the central area of the active surface 24 1 , so the second pads 243 are also central solder pads. Preferably, the first wafer 220 and the second wafer 240 are substantially identical wafers. For example, the wafer size, electrical function and pad placement position are the same to reduce the type of wafer and thus reduce the manufacturing cost and management cost of the wafer. The second bonding wires 232 are electrically connected to the second pads 243 of the second wafer 240 to the second contacts 2 1 5 ' of the substrate 21 to reach the second wafer 24 and the substrate 2 1 Electrical interconnection. Therefore, the first pads 223 and the second pads 243 are both central pads, and the second wires 232 are longer than the first wires 231. Please refer to FIG. 2, The wire freezing component 250 covers a partial line segment of the second bonding wires 232 and adheres to the second active surface 24 1 of the second wafer 240. As used herein, "freezing" means that the line freezing element 250 is liquid or colloidal at the time of application and has suitable fluidity, and is solid after completion of the product to secure the second welding. Line 2 3 2. The wire freezing member 250 can be a liquid-coated cured colloid having thermosetting or photocurable properties which can be adhered to the second active surface 241 of the second wafer 240 after being coated with the wire segment. Referring to FIG. 4, in the embodiment, the line freezing element 25 can be a plurality of strips and adhered to the second wafer 240 along the arrangement direction of the second pads 243. The second active surface 241 has the effect of being easily coated after the wire is applied. As shown in FIG. 2, the line freezing elements 250 may not cover the sides of the first wafer 220 and the second wafer 24 and the upper surface 211 of the substrate 210, that is, the second recording lines. 232 11 200926389 The southernmost arc height of the line, in order to increase the sag effect of the line _ / 泉 τ 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 250 2 4 0 shape. After the line freeze member 250 is turned into a solid state, the second bonding wires 23 2 can be prevented from generating a line on the mashed second wafer 240 and avoiding touching the edge of the second wafer. The molding compound 260 seals the inferior first bonding wire 231, the second bonding wires 232, the first wafer 22, the first wafer 240, and the wire freezing component 250 to avoid The internal components of the multi-wafer sealing structure 200 stacked on the back vanadium north μ are back-contaminated by external contaminants. Preferably, the belly freezing element 250 does not cover the first & second pad 243 such that the line freezing element 250 is formed between the strips and the strips The mold flow channel 261 is formed symmetrically on the wire (10) so that the mold flow passage below the upper and lower molds 213 during molding is formed by the strip-shaped beading elements 250. In the present embodiment, the lash has a gap which is not less than the width of the upper dies flow channel 261 « _ μ wire slot 213. Φ Specifically, the J-view of the back-to-back stack < additionally includes a plurality of external terminals 27 of the multi-chip package structure 200 of the lower surface 212 to serve as the output of the substrate to be bonded to the substrate. Input stacked multi-chip package structure ^ ^ Φ Φ Χ ± # Some external terminals 270 can be printed circuit boards. In this embodiment, one of the external devices includes a plurality of solder balls. Therefore, the back-to-back town of the present invention uses substantially the same first day-day® spent multi-yang package structure 200, and thus does not have to be used when the sundial 220 and the second wafer 24 are smashed. The cost of the construction of the table as another type of peripheral pad type 12 200926389 wafer, not only can reduce the manufacturing cost of the wafer can also be controlled by the wafer. In addition, the second freezing wire 23 2 can be stabilized by the wire freezing component 25 to avoid the phenomenon of the second wire bonding line during the sealing process and/or the 241 of the second wafer 240 being touched. The edge causes a short circuit or damages the quality of the second soldered connection. 5A to 5H are diagrams for explaining a specific manufacturing method of the aforementioned back-to-back stacked package structure 200. First, as shown in the figure, a substrate 210 is provided. The substrate 210 has a 2U, a lower surface 212, and a wire slot 213. The lower portion is formed with a plurality of 214 located on both sides of the wire slot 2 1 3 . The upper surface 211 is formed with a plurality of second fingers. Next, as shown in FIG. 5B, a first surface 211 of the substrate 210 is disposed. The first crystal is attached to the base layer with the first active surface 22 1 facing downwards. The first pads 223 are aligned with the first pads 223 of the wire slot 213. Next, referring to FIG. 5C, a plurality of first bonding wires 23 are formed, and the plurality of first bonding wires 23 are electrically connected to the first 223 of the first wafer 220 to the first of the substrate 210. Finger 214. After the first electrical connection, a second wafer 240 is disposed on the first crystal in the open stacking manner of FIG. 5D, that is, the second back surface 242 of the second wafer 240 is attached to the wafer 220. The first back surface 222. Wherein, the second material is relatively easy to solidify the plurality of wafers 232 to generate the second active surface line 23 2, the fifth surface, the upper surface 'surface 212, the first finger 215, the wafer 220, the sheet 220, ί 210, and! In order to reveal, the wire is passed through the first bonding pad: on the back side ί 220, and the first wafer 2 4 0 13 200926389 has a plurality of first-halo-lead pads 243, which are formed Up to a central region of the second active surface 241 of the 240. Next, as shown in FIG. 5E, the jj is recorded, and the plurality of second bonding wires 232 are formed by the second bonding pads 243 of the first s die 240 to the second bonding fingers 215 of the substrate. In the middle of the section, the first weld bead 223 and the illuminating 243 are both smear-shaped, so that the second weld line active faces 24 1 . In the present embodiment, the wire freezing member is a liquid-coated solidified gel, and the wafer 240 is adhered by liquid painting and cured. For example, the wire freezing member 250 can be converted to a solid state by heating or irradiation. The junction element 250 can be in a sturdy state when applied, and is formed at the southernmost fox height of the fresh line 230 to provide a preferred sag effect. The shape of the second bonding wire 230. In a preferred state, the bonding wire 232 is approximately horizontal on the second active surface 241 of the second wafer 240 and can be substantially curved at the second active edge of the second wafer 240. When the line freezes the element 250 state, the easy-to-wear wire of the second bonding wire 2 3 2 can be fixedly sealed to avoid punching in the subsequent molding process. Finally, as shown in FIG. 5G, the upper surface 211 and the lower surface 21 of the substrate 210 are formed: the second wafer is referred to as the electrical connection 2 1 , and the second 232 is longer than the first line. Freezing 25 先 first to 5 第二 second 25 可 to the second ultraviolet light, etc. when the line freezes the second, thereby repairing the second upper surface 241 into a solid segment to avoid colloid 260: after the first bonding wires 231» are sealed, as shown in FIGS. 5F and 4, at least the component 250 is formed on the second wafer 240, and the wire freezing component covers the second bonding wires 232 one of the local line segments, then stick to ❹
14 200926389 封該些第一銲線231、該些第二銲線232、該第一晶片 22〇、一第二晶片240以及該線凍結元件250。具體而 言’請參閱第5H圖所示，該背對背堆疊之多晶片封裝 構造200之製造方法係可另包含之步驟有：設置複數個 外接端子270以接合該基板210之該下表面212。 在本發明之第二具體實施例中，揭示另一種背對背 堆疊之多晶月封裝構造，請參閱第6圖所示，該背對背 堆疊之多晶片封裝構造300主要包含一基板310、一第 一晶片320、複數個第一銲線331、一第二晶片340、 複數個第二銲線3 3 2、至少一線凍結元件3 5 0以及一模 封膠體360«該基板310係具有一打線槽孔313，以供 該些第一銲線331通過。該第一晶片32〇係設置於該基 板310上並具有複數個第一銲墊323。在本實施例中， 該背對背堆疊之多晶片封裝構造300係可另包含有複數個 LOC黏晶膠帶38〇，以黏著該第一晶片320之一第一主 動面321至該基板31〇β該些第一銲線331係電性連接 該第一晶片320之該些第一銲墊323至該基板310。 該第二晶片3 4 0係以背對背堆疊方式設置於該第一 晶片320上並具有複數個第二銲墊343，該些第二銲墊 3斗3係位於該第二晶片34〇之一第二主動面341之中央 區域。該些第二銲線332係電性連接該第二晶片340之 該些第二銲墊343至該基板310。 該線束結元件350係包覆該些第二銲線332之一局 部線段並黏附至該第二晶片34〇之一第二主動面341 15 200926389 ❹14 200926389 The first bonding wires 231, the second bonding wires 232, the first wafer 22, a second wafer 240, and the line freezing member 250 are sealed. Specifically, referring to FIG. 5H, the method of fabricating the back-to-back stacked multi-chip package structure 200 can further include the steps of: providing a plurality of external terminals 270 to bond the lower surface 212 of the substrate 210. In a second embodiment of the present invention, another back-to-back stacked polycrystalline package structure is disclosed. Referring to FIG. 6, the back-to-back stacked multi-chip package structure 300 mainly includes a substrate 310 and a first wafer. 320, a plurality of first bonding wires 331, a second wafer 340, a plurality of second bonding wires 3 3 2, at least one wire freezing component 350 and a molding compound 360 «the substrate 310 has a wire slot 313 For the passage of the first bonding wires 331. The first wafer 32 is disposed on the substrate 310 and has a plurality of first pads 323. In this embodiment, the back-to-back stacked multi-chip package structure 300 may further include a plurality of LOC die-bonding tapes 38 黏 for adhering one of the first active faces 321 of the first die 320 to the substrate 31 〇β. The first bonding wires 331 are electrically connected to the first pads 323 of the first wafer 320 to the substrate 310 . The second wafer 340 is disposed on the first wafer 320 in a back-to-back stacking manner and has a plurality of second pads 343. The second pads 3 are located on the second wafer 34. The central area of the active surface 341. The second bonding wires 332 are electrically connected to the second pads 343 of the second wafer 340 to the substrate 310. The wire harnessing component 350 is wrapped around a partial line segment of the second bonding wires 332 and adhered to the second active surface of the second wafer 34. 341 15 200926389 ❹
上。請再參閱第6圖所示’在本實施例中，該線；束結元 件350係可包含有一線墩351以及一覆線物質352，其 中該線墩3 5 1係位於該些第二銲線3 3 2之下方，用以支 撐該些第二銲線332並定義該些第二銲線332被該覆線 物質352包覆之局部線段’可完全避免了該些第二銲線 3 3 2碰觸到該第二晶片3 4 0之可能性並限制了該覆線物 質3 5 2之形成區域。較佳地，該線缴3 51係可為 LOC(LeacUOn-Chip，引腳在晶片上型式）黏晶膠帶，在 該些第二銲線332形成之前，預先設置於該第二晶片 340上。該覆線物質352係可為液態環氧樹脂。該線墩 3 5 1此有效界疋所使用之線；東結元件3 5 〇之該覆線物質 3 52形成區域’避免該覆線物質352之溢流擴散。 該模封膠體360係密封該些第一銲線33丨、該些第 二銲線332、該第一晶片32〇、一第二晶片34〇以及該 線珠結元件350。該背對背堆昼之多晶片封装構造綱係 可另包含有複數個接合至該基板31〇之外接端子37〇。 請參閱第6圖所示，由於該些第一銲墊323與該些第二 銲墊343皆為中央型銲墊，故該些第二銲線332長於該 些第一銲線331，藉由該線凍結元件35〇包覆該些第二 銲線332在該第二晶片340上之懸空部位，以避免晶片 上沖線或/及碰觸晶片邊緣。因此，該背對背堆疊：多 晶片封裝構造300除了可使用相同種類之晶片來降低 晶片之製造成本與管控成本之外，並可解決銲線長短不 一造成的封裝缺陷。 16 200926389 以上所述’僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，本發明技術方案範圍當依 所附申請專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容’依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖：一種習知背對背堆疊之多晶片封裝構造之戴面 示意圖。 第2圖：依據本發明之第一具體實施例，一種背對背堆 疊之多晶片封装構造之截面示意圖。 第3圖：依據本發明之第一具體實施例，該背對背堆疊 之多晶片封裝構造中一第二晶片之第二主動面示 意圖。 第4圖：依據本發明之第一具體實施例，該背對背堆疊 之多晶片封裝構造中已設置第二晶片並形成有線 凍結元件之基板上表面示意圖。 第5A至5H圖：依據本發明之第一具體實施例，該背 對背堆叠之多晶片封裝構造在製程中該基板截面 示意圖。 第6圖：依據本發明之第二具體實施例，另一種背對背 堆疊之多晶片封裝構造截面示意圖。 17 200926389 【主要元件符號說明】 100背對背堆叠之多晶片封裝構造 1 1 Λ 甘上产 110基板 113打線槽孔 111上表面 112on. Referring to FIG. 6 again, in the embodiment, the line; the beam-binding element 350 can include a wire pier 351 and a wire covering material 352, wherein the wire pier 35 1 is located in the second welding. Below the line 3 3 2 , a portion of the second wire 332 that supports the second wire 332 and defines the second wire 352 to be covered by the wire covering material 352 can completely avoid the second wire 3 3 2 The possibility of touching the second wafer 300 and limiting the formation area of the line covering material 35. Preferably, the wire bonding module 51 can be a LOC (LeacUOn-Chip) type of die bonding tape, and is disposed on the second wafer 340 before the second bonding wires 332 are formed. The wire covering material 352 can be a liquid epoxy resin. The wire pier 3 5 1 is the line used for the effective boundary; the wire-bonding material 3 52 of the east junction element 3 52 forms a region to avoid overflow diffusion of the wire covering material 352. The molding compound 360 seals the first bonding wires 33, the second bonding wires 332, the first wafer 32, the second wafer 34, and the wire bonding component 350. The multi-chip package structure of the back-to-back stack may further comprise a plurality of external terminals 37 接合 bonded to the substrate 31. Referring to FIG. 6 , since the first pad 323 and the second pads 343 are both central pads, the second bonding wires 332 are longer than the first bonding wires 331 . The wire freezing component 35 covers the floating portions of the second bonding wires 332 on the second wafer 340 to avoid punching or/and touching the edge of the wafer. Therefore, the back-to-back stack: the multi-chip package structure 300 can use the same kind of wafers to reduce the manufacturing cost and the control cost of the wafer, and can solve the package defects caused by the length of the wire. 16 200926389 The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make a few changes or modifications to the equivalent embodiments by using the technical content disclosed above, but the content without departing from the technical solution of the present invention is made according to the technical essence of the present invention. Any simple modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view of a conventional multi-chip package structure in a back-to-back stack. Figure 2 is a cross-sectional view showing a multi-chip package structure of a back-to-back stack in accordance with a first embodiment of the present invention. Figure 3: In accordance with a first embodiment of the present invention, a second active surface of a second wafer in the multi-chip package construction of the back-to-back stack is shown. Fig. 4 is a schematic view showing the upper surface of a substrate in which a second wafer is formed and a wired freeze member is formed in the multi-chip package structure of the back-to-back stack according to the first embodiment of the present invention. 5A to 5H are views showing a cross-sectional view of the substrate in the process of the multi-chip package construction of the back-to-back stack according to the first embodiment of the present invention. Figure 6 is a cross-sectional view showing another multi-chip package structure of a back-to-back stack in accordance with a second embodiment of the present invention. 17 200926389 [Explanation of main component symbols] 100 multi-chip package structure of back-to-back stacking 1 1 甘 Gansu 110 substrate 113 wire slot 111 upper surface 112
❹ 120第一晶片 123中央銲墊 131第一銲線 140第二晶片 143周邊銲墊 160 200 210 213 220 223 231第一銲線 240第二晶片 243第二銲墊 250線凍結元件 121第一主動面 132第二銲線 1 4 1第二主動面 122 142 下表面 第一背面 第二背面 模封膠體 背對背堆疊之 基板 打線槽孔 第一晶片 第一銲塾 170外接端子 多晶片封裝構造 211上表面 214第一接指 221第一主動面 232第二銲線 241第二主動面 260模封膠髏 261上模流通道 270外接端子 300背對背堆疊之多晶片封裝構造 310基板 313打線槽孔 320第一晶片 321第一主動面 212 215 222 242 262 323 下表面 第二接指 第一背面 第二背面 下模流通道 第一銲墊 200926389 33 1 第一銲線 332 第二銲線 340 第二晶片 341 第二主動面 343第二銲墊 350 線康結元件 351 線墩 352 覆線物質 360 模封膠體 370 外接端子 380 LOC黏晶膠帶❹ 120 first wafer 123 central pad 131 first bonding wire 140 second wafer 143 peripheral pad 160 200 210 213 220 223 231 first bonding wire 240 second wafer 243 second bonding pad 250 line freezing element 121 first active Surface 132 second bonding wire 1 4 1 second active surface 122 142 lower surface first back second back molding encapsulant back-to-back stacked substrate wire slot first wafer first pad 170 external terminal multi-chip package structure 211 upper surface 214 first finger 221 first active surface 232 second bonding wire 241 second active surface 260 mold sealing glue 261 upper mold flow channel 270 external terminal 300 back-to-back stacked multi-chip package structure 310 substrate 313 wire slot 320 first Wafer 321 first active surface 212 215 222 242 262 323 lower surface second finger first back second second back lower mold channel first pad 200926389 33 1 first bonding wire 332 second bonding wire 340 second wafer 341 Two active surface 343 second soldering pad 350 line Kangjie component 351 line pier 352 covering material 360 mold sealing gel 370 external terminal 380 LOC adhesive tape
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