TW201114008A - Fabricating method of back-to-back chip assembly with flip-chip and wire-bonding connections and its structure - Google Patents
Fabricating method of back-to-back chip assembly with flip-chip and wire-bonding connections and its structure Download PDFInfo
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- TW201114008A TW201114008A TW098133489A TW98133489A TW201114008A TW 201114008 A TW201114008 A TW 201114008A TW 098133489 A TW098133489 A TW 098133489A TW 98133489 A TW98133489 A TW 98133489A TW 201114008 A TW201114008 A TW 201114008A
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
Description
201114008 六、發明說明: 【發明所屬之技術領域】 本發明係有關於多晶片半導體裝置,特別係有關於一 種覆晶打線連接之背對背晶片組合方法與構造。 【先前技術】 多晶片封裝(multi-chip package,MCP)技術普遍運用 於半導體封裝領域,基於半導體封裝實用需求,如將複 數個相同電性功能晶片封裝一體成具有更多記憶體容量 之多晶片模組,或者將複數個電性功能不同晶片封裝一 體成具有系統運算功能之系統封裝(system & package),且依晶片之型態不同須個別呈打線 (wire-bonding)與覆晶(flip_chip)加以封裝。 目前半導體產業中,由於覆晶(flip _chjp)技術具有較 佳的可靠度與性能,逐漸有取代打線(wire_b〇nding)技術 成為主流之趨勢。然而,因為打線技術能達到較高之產 忐,甚至發展出覆晶與打線技術並存的晶片堆疊技術, 以現有已知的覆晶加打線晶片堆疊技術,其製程是先覆 晶接合與填充底膠以完成下晶片之設置,再貼附上晶片 並作打線接合。因此,底膠會在基板上覆晶晶片周圍保 留一點膠寬度’而打線銲墊更設於點膠寬度之外的基板 外圍,以避免被底膠覆蓋,造成封裝體尺寸無法縮小, 而良率降低更提高了製造成本。 请參閱第1圖所示’一種習知的覆晶打線連接之背對 背晶片組合構造100,其係主要包含一基板11〇、一下晶 201114008 片120、一上晶片130、複數個銲線140、一底部填充膠 150以及一封膠體16(^該基板11〇係具有複數個凸塊接 墊1Π與複數個打線接指112,並且該基板no之上表 面另設有一防銲層113。該下晶片120係具有複數個凸 塊121,並且該些凸塊121係覆晶接合至該些凸塊接墊 111。該上晶片1 30係背對背貼附至該下晶片j 2〇之背 面’並以該些銲線140電性連接該上晶片13〇之銲墊13 j 於該些打線接指112。該底部填充膠15〇係設置於該下 晶片120之底部,以包覆該些凸塊121並保護該下晶片 120之主動面。該封膠體16〇係密封該上晶片13〇、該下 晶片12G與該底部填充膠丨.更具體地該覆晶打線 連接之背對背晶片組合構造1〇〇係依照如第2圖所示之 覆晶打線連接之背對背晶片組合方法所製成。該方法係 主要包含以下步驟:「提供基板」之步驟Η、「下晶片之 覆晶接合」之步驟12、「底膠填充」之步驟13、「背對背 堆疊上晶片」之步驟14、「上晶片之打線連接」之步驟 ^以及「形成封膠體」之步驟16。詳細而言步驟u 疋φζ·供該基板110,步趣βn ,驟12疋使該下晶片12〇 至該基板110。之播,舳,_止 _ 仃步驟13,將該底部填充膠150 填入該下晶片i 2〇之底部, 以保°隻这下晶片1 20之主動 面與密封該此凸地1〇1 21,但不可覆蓋到該些打線接指 =:之T14中,才將該上晶片―至該下 =行二:上。在完成步驟14後,才利用-打線技 術執盯步驟15,使該些鲜線140電性連接該上晶片130 201114008 與該基板110。最後,執行步驟16,於該基板11〇上形 成該封膠體160,以完成封裝製程。因此,習知是先執 行底膠填充再進行上晶片之打線連接,為了使打線製程 能順利進行,避免該底部填充膠15〇在填入時不可覆蓋 至該些打線接指11 2,故該基板11 〇必須要考慮到該底 部填充膠150所需要的點膠寬度,而將該打線接指ιΐ2 設置於點膠寬度之外的該基板110外圍,造成封裝體尺 寸無法縮小,增加了整體的製造成本。 ® 【發明内容】 本發明之主要目的係在於提供一種覆晶打線連接之 背對背晶片組合方法與構造,可保護基板上的打線銲點 以避免脫落。 ” 本發明之次一目的係在於提供一種覆晶打線連接之 背對背晶片組合方法與構造,基板周圍不需要預留供底 部填充膠形成之膠寬度,即使打線接指會被底部填充膠 • 所覆蓋也不會造成打線失敗,甚至更能增強可靠度與有 效地縮小封裝尺寸。 、 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種覆晶打線連接之背對背晶 片組合方法,主要包含有以下步驟:提供一基板其上 表面設有複數個凸塊接墊與複數個打線接指, M 一防 鮮層覆蓋該上表面,該防銲層係具有一導流開槽係同 時顯露該些凸塊接墊與該些打線接指。覆晶接合—= y 〇 下晶 至該基板,該下晶片係具有複數個凸塊,係接合至該 201114008 些凸塊接墊’卩電性連接該下晶片與該基板。背對背堆 m日μ該下晶片’該上晶片係具有複數個銲塾。 打線形成複數個銲線,係連接該些銲墊與該些打線接 才曰以電連接該上晶片與該基板。在上述的背對背堆 疊與打線㈣之後’形成—底部填充膝於該基板與該下 晶片之間,該底部填充膠係密封該些凸塊並填入該導流 P#槽内以覆蓋該些打線接指並局部密封該些辉線。本BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-wafer semiconductor device, and more particularly to a back-to-back wafer combination method and structure for a flip chip bonding. [Prior Art] Multi-chip package (MCP) technology is widely used in the field of semiconductor packaging. Based on the practical needs of semiconductor packages, such as packaging multiple identical functional functional chips into a multi-chip with more memory capacity. The module, or a plurality of electronic functions and different chip packages are integrated into a system package (system & package) having a system operation function, and must be individually wired-bonding and flip chip depending on the type of the chip (flip_chip) ) to be packaged. At present, in the semiconductor industry, due to the better reliability and performance of flip chip (flip _chjp) technology, there is a trend to replace wire_b〇nding technology. However, because the wire bonding technology can achieve higher production, and even develop a wafer stacking technology in which the flip chip and the wire bonding technology coexist, the conventionally known flip chip plus wire wafer stacking technology has a process of flip chip bonding and filling. The glue is used to complete the placement of the lower wafer, and the wafer is attached and bonded. Therefore, the primer will retain a little glue width around the flip chip on the substrate, and the wire bonding pad is placed on the periphery of the substrate outside the dispensing width to avoid being covered by the primer, so that the package size cannot be reduced. The reduction in the rate further increases the manufacturing cost. Referring to FIG. 1 , a conventional flip-chip bonding back-to-back wafer assembly structure 100 mainly includes a substrate 11 , a lower wafer 201114008 wafer 120 , an upper wafer 130 , a plurality of bonding wires 140 , and a The underfill 150 and the adhesive 16 (the substrate 11 has a plurality of bump pads 1 Π and a plurality of wire bonding fingers 112, and a solder resist layer 113 is further disposed on the surface of the substrate no. The 120 series has a plurality of bumps 121, and the bumps 121 are flip-chip bonded to the bump pads 111. The upper wafers 130 are attached back-to-back to the back surface of the lower wafer j 2〇 and The bonding wires 140 are electrically connected to the bonding pads 13 of the upper wafer 13 to the bonding wires 112. The underfill 15 is disposed at the bottom of the lower wafer 120 to cover the bumps 121. Protecting the active surface of the lower wafer 120. The encapsulant 16 is used to seal the upper wafer 13A, the lower wafer 12G and the underfill film. More specifically, the flip chip bonding back-to-back wafer assembly structure 1 Back-to-back wafer combination in accordance with flip chip bonding as shown in Figure 2 The method comprises the following steps: a step of "providing a substrate", a step 12 of "flip-chip bonding of the lower wafer", a step 13 of "primer filling", and a step of "stacking the wafer on the back-to-back" 14. The step of "bonding the upper wafer" and the step 16 of "forming the encapsulant". In detail, the step u 疋 φ ζ is supplied to the substrate 110, and the lower wafer 12 is slid to the The substrate 110 is broadcasted, 舳, _ _ 仃 step 13, the underfill 150 is filled into the bottom of the lower wafer i 2 , to protect only the active surface of the lower wafer 1 20 and seal the convex surface 1〇1 21, but can not be covered in the T14 of the wire-to-wire =: T14, the upper wafer - to the next = line 2: on. After completing step 14, only use the - wire technology to stare at step 15 The fresh wire 140 is electrically connected to the upper wafer 130 201114008 and the substrate 110. Finally, step 16 is performed to form the encapsulant 160 on the substrate 11 to complete the packaging process. Therefore, the conventional implementation is performed first. The underfill is filled and then the upper die is connected by a wire, in order to make the wire bonding process Smoothly, the underfill 15 15 is not covered to the wire bonding fingers 11 2 when filling, so the substrate 11 must take into account the required dispensing width of the underfill 150. The iv 2 is disposed on the periphery of the substrate 110 outside the dispensing width, so that the package size cannot be reduced, which increases the overall manufacturing cost. The main purpose of the present invention is to provide a back-to-back connection of a flip chip connection. The wafer assembly method and structure can protect the wire bonding pads on the substrate to avoid falling off. The second object of the present invention is to provide a back-to-back wafer combination method and structure for flip chip bonding, and no padding is required around the substrate. The width of the glue formed by the glue, even if the wire is connected by the underfill, will not cause the wire to fail, and even more enhance the reliability and effectively reduce the package size. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a back-to-back wafer assembly method for flip chip bonding, which mainly comprises the following steps: providing a substrate having a plurality of bump pads and a plurality of wire bonding fingers on an upper surface thereof, and an anti-fresh layer covering the upper surface The solder resist layer has a flow guiding groove system and simultaneously exposes the bump pads and the wire bonding fingers. Flip chip bonding -= y 〇 underlying the substrate, the lower wafer has a plurality of bumps bonded to the bump bumps of the 201114008, electrically connecting the lower wafer and the substrate. Back-to-back stack m day μ the lower wafer' The upper wafer has a plurality of solder fillets. The wire is formed into a plurality of bonding wires, and the bonding pads are connected to the wires to electrically connect the upper wafer and the substrate. After the back-to-back stacking and wire-bonding (4) described above, a bottom-filled knee is formed between the substrate and the lower wafer, and the underfill seals the bumps and fills the guide P# groove to cover the wires. Fingers are placed and partially sealed. this
發明另揭示依照上述組合方法所製成之構造。 本發明的目&及冑決其技術問題還可採用卩下技術 措施進一步實現。 在刚述之背對背晶片組合方法中,在該底部填充膠形 成之後,可另包冬+ , is之步驟為:形成一封膠體於該基板上, 以密封該上晶只、# π 片 該下晶片與該底部填充膠。 在前述之背斜ciiia ,, Λ 月對牙阳片組合方法中,該導流開槽係可為The invention further discloses a construction made in accordance with the above combined method. The object of the present invention and its technical problems can be further realized by adopting technical measures. In the back-to-back wafer assembly method just described, after the underfill is formed, the winter+ can be further included, the step of forming is to form a gel on the substrate to seal the upper crystal, the #π片. The wafer is filled with the underfill. In the foregoing anticline ciiia, Λ月的牙阳片组合方法, the diversion slotting system can be
連續或非連續之I , < &形’以使該防銲層在該下晶片之下方 形成為一防銲島塊。 在前述之哲#4· 3b。 π對彦晶片組合方法中,該導流開槽之外 緣係可為鑛齒# 蹄菌狀’以顯露該些打線接指。 在前述之昔谢· db。A continuous or discontinuous I, <&&' is such that the solder resist layer is formed as a solder resist island below the lower wafer. In the aforementioned Zhe #4·3b. In the π-Yan-Yan wafer combination method, the outer edge of the flow-guiding groove may be a mineral tooth-like shape to expose the wire-bonding fingers. In the foregoing, thank you db.
π對奇晶片組合方法中,該導流開槽係可J 多個槽孔,每一搞,· s 糟孔顯露至少一個凸塊接墊與至少一令 鄰近之打線接指。 在前述之背對背 迴焊接合之金屬桂 晶片組合方法中,該些凸塊係可為非 ’而該些凸塊與該些凸塊接墊之間係 以銲料連接。 201114008 n #胃上技術方案可以看出,本發明之覆晶打線連接之 _ 片汲合方法與構造,有以下優點與功效: β藉由先打線銲線再形成底部填充膠於基板與下晶 之間作為其中一技術手段,由於底部填充膠係密 :凸塊並填入導流開槽内,以覆蓋打線接指並局部 '、封銲線,故可保護基板上的打線銲點以避免脫落。 可藉由先打線銲線再形成底部填充膠於基板與下晶 片之間作為其中一技術手段,免除習知須考慮底部 填充膠之膠寬度問題’毋須擔心打線接指會被底部 填充膠所覆蓋而無法打線,故能有效地縮小封裝尺 寸。 二、可藉由防銲層之導流開槽與防銲島塊作為其中一技 術手段,由於導流開槽係為連續或非連續之環形, 以使防銲層在下晶片之下方形成為一防銲島塊故 有利於導引底部填充膠在下晶片周邊之流動。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例,然應 注意的是,該些圖示均為簡化之示意圖,僅以示意方法 來說明本發明之基本架構或實施方法,故僅顯示與本案 有關之元件與組合關係,圖t所顯示之元件並非以實朽 實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理,以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計,詳細之元件佈局可能更為複雜。 201114008 據本發明之一具體實施例,一種覆晶打線連接之背 對背片粗合方法舉例說明Μ 3圖之流程方塊圖與第 4 Α至4 G圖之开从并γ — * <凡件截面示意圖。該覆晶打線連接之背對 背曰曰片、’且σ方法根據第3圖,主要包含以下步驟:「提供 基板」之步驟21、「下晶片之覆晶接合」之步驟22、「背 對背堆疊上晶片,$半_ Γ , 」之步驟23、「上晶片之打線連接」之In the π-pair odd-wafer combination method, the flow-guiding grooving system can have a plurality of slots, and each of the s-holes reveals at least one bump pad and at least one adjacent wire-bonding finger. In the above-mentioned back-to-back-welded metal foil wafer bonding method, the bumps may be non-' and the bumps are soldered to the bump pads. 201114008 n #胃上技术方案 It can be seen that the method and structure of the flip chip bonding method of the present invention have the following advantages and effects: β, by first bonding a wire bonding wire to form an underfill glue on the substrate and the underlying crystal As one of the technical means, since the underfill is dense: the bump is filled in the diversion groove to cover the wire bonding finger and partially 'and the sealing wire, the wire bonding point on the substrate can be protected to avoid Fall off. By using a wire bonding wire to form an underfill between the substrate and the lower wafer as a technical means, it is necessary to avoid the problem of the width of the underfill rubber. It is necessary to worry that the wire bonding finger will be covered by the underfill rubber. It is impossible to wire, so it can effectively reduce the package size. Second, the guide layer of the solder resist layer and the anti-welding island block can be used as one of the technical means, since the flow guiding groove is continuous or discontinuous, so that the solder resist layer becomes a square under the lower wafer. The solder mask is advantageous for guiding the flow of the underfill on the periphery of the lower wafer. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which Therefore, only the components and combinations related to the case are shown. The components shown in Figure t are not drawn in proportion to the number, shape and size of the actual implementation. Some ratios of scales are exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. According to an embodiment of the present invention, a back-to-back sheet roughing method for a flip chip connection is illustrated by a flow block diagram of FIG. 3 and a fourth and fourth G map opening and γ — * < schematic diagram. The flip-chip bonding is back-to-back, and the σ method according to FIG. 3 mainly includes the following steps: step 21 of “providing the substrate”, step 22 of “flip-chip bonding of the lower wafer”, and “back-to-back stacking of the wafer” , $ half _ Γ , ” step 23, “on the wafer connection”
步驟24、「底膠填充 r ^ X 供兄」之步驟25以及「形成封膠體」之Step 24, Step 25 of "Bottom Filling r ^ X for Brother" and "Forming Sealant"
步驟 在各步驟上表現元件請參閱第4A至4Θ圖,說 明如下所示。 首先執行步驟21。請參閱第4八圖所示,提供一基 板21〇其上表φ 211設有複數個凸塊接墊川與複數 個打線接指2 1 3,並以一 ρ大名θ麻〇 , β» — ^ Μ 防鋅層214覆蓋該上表面211, 該防銲層2 14係具右—道古日日μ 、有導流開槽2 1 5,係同時顯露該些 凸塊接塾212與該歧打魂技, λ. , , j, —α深接知213。在本實施例中,該 導流開槽215係可為遠墙七、圭& 兩遷續或非連續之環形,以使該防銲 層214在該下晶片22〇之下方形成為一防銲島塊21 6(如 第6圖所示),以維持覆晶間隙與該基板21G的強度。因 此’在後續填勝製程中,該導流開槽215能夠導引底部 填充膠在該下晶片220周邊之流動並限制其往外擴散。 在-較佳實施例中,該防銲層214係可部分覆蓋至該些 打線接S 213之側邊,上述之「側邊」係指^線接 指213遠離相鄰之凸塊接墊212之一側。 執行步驟22。首先,如第 220。再請參閱第4C圖所示, 4B圖所示,提供一下晶片 覆晶接合該下晶片220至 201114008 該基板210,該下晶片220係具有複數個凸塊221,係接 合至該些凸塊接墊212,以電性連接該下晶片22〇與該 基板210»在本實施例中,該些凸塊221係可為非迴焊 接合之金屬柱,例如:可耐高溫不變形的金柱、銅柱等, 以解決習知凸塊以迴焊產生變形的橋接短路問題並能在 背對背堆疊與打線之後維持固定的底部填充空隙。具體 而言,該下晶片220之該些凸塊22丨與該基板21〇之該 些凸塊接塾212之間係以録料270連接。在一較佳實施 例中,如第4Β圖所示,該下晶片22〇之該些凸塊22ι 係可先附著該些銲料270’再直接對準接合至該基板21〇 上。 執行步驟23。請參閱第4D圖所示,背對背堆疊一上 晶片230至該下晶片220,該上晶片23〇係具有複數個 銲墊23 1 »在本實施例中,該上晶片23〇之尺寸係可不 大於該下晶片220之尺寸,並且該上晶片23〇係可藉由 一黏晶層232貼附至該下晶片22〇之背面。具體而言, 該黏晶層232係可不完全覆蓋該下晶片22〇之背面。在 一較佳實施例中,該黏晶層232係可依照製程需求選擇 形成於該上晶片230之背面或該下晶片22〇之背面。 執行步驟24。請參閱第4Ε圖所示,在尚未底膠填充 之前’打線形成複數個銲線240,係連接該些銲墊231 與該些打線接指213,以電性連接該上晶片23〇與該基 板210。由於在一較佳實施例中,該些凸塊221係可為 #迴焊接合之金屬柱,有一致的覆晶高度與足夠的打線 201114008 支樓力’能在未有底部填充膠之情況下,對該上晶片2 3 〇 進行打線作業。 執行步驟25。請參閱第4F圖所示,在上述的背對背 « 堆疊與打線步驟之後,形成一底部填充膠25〇於該基板 210與該下晶片220之間’該底部填充膠250係密封該 些凸塊221並填入該導流開槽215内,以覆蓋該些打線 接指213並局部密封該些銲線240。較佳地,由於該導 流開槽215能導引該底部填充膠250流動於該下晶片 _ 220之周邊’故可避免該底部填充膠250溢散至他處而 造成汙染》 最後,請參閲第4G圖所示,在該底部填充膠250形 成之後’可形成一封膠體260於該基板210上,以密封 該上晶片230、該下晶片220與該底部填充膠250。此外, 該封膠體260亦包覆該些銲線240,進一步地補強了該 些銲線240之結合力。該封膠體260可由模封方法形成。 • 在本發明中,由於該底部填充膠250係在該些銲線 240打線形成之後才填入該導流開槽215内,該底部填 充膠250除了填滿於該下晶片220以密封該些凸塊221 與該些凸塊接墊212,更藉由該導流開槽215可覆蓋於 該些打線接指213並局部包覆該些銲線24〇。因此,藉 由該底部填充膠25 0包覆並固定該些銲線240,可保護 該些銲線240之銲點,以防止在後續製程中發生該些銲 線240從銲點脫落之情況。此外,因為本發明是先完成 該上晶片230之打線步驟,再填入該底部填充膠250, 10 201114008 故可免除習知必須在基板周邊預留供形成該底部填充膠 250之膠寬度空間’該些打線接# 213會被該底部填充 膠250所覆蓋的結構不會有打線失敗的問題更能増強 可靠度與有效地縮小封裝尺寸。 本發明還揭示使用前述組合方法所製成之覆晶打線 連接之背對背晶片組合構造2〇〇舉例說明於第5圖。該 覆晶打線連接之背對背晶片組合構造係主要包含—基板 210、一下晶片220、一上晶片230、複數個銲線24〇以 及一底部填充膠250。該基板21〇之上表面211設有複 數個凸塊接墊212與複數個打線接指213,並以一防辉 層214覆蓋該上表面211,該防銲層214係具有一導流 開槽215,係同時顯露該些凸塊接墊212與該些打線接 指213。在一實施例中,該導流開槽215係可為連續或 非連續之環形。如第6圖所示,該導流開槽2丨5係為非 連續之環形,以使該防銲層214在該下晶片220之下方 形成為一防焊島塊216,故有利於導引該底部填充膠25〇 在該下晶片220周邊之流動,而不易溢散至他處而造成 汙染。並且,該防銲島塊216可被該防銲層214在非連 續之角隅處一體連接,以避免脫落。 該下晶片220係覆晶接合至該基板21〇,該下晶片220 係具有複數個凸塊221,係接合至該些凸塊接墊212,以 電性連接該下晶片220與該基板21〇。具體而言,該些 凸塊221係可為非迴焊接合之金屬柱,而該些凸塊22 i 與該些凸塊接墊212之間係以銲料2 7〇連接。更進一步 201114008 地’該上晶片230係背對背堆疊至該下晶片220 ’該上 晶片230係具有複數個銲墊231 »該些銲線240係連接 該些銲墊231與該些打線接指213,以電性連接該上晶 片230與該基板210。 該底部填充膠25 0係形成於該基板210與該下晶片 220之間,該底部填充膠250係密封該些凸塊221並填 入該導流開槽215内,以覆蓋該些打線接指213並局部 密封該些銲線240。此外,可另包含一封膠體260,係形 成於該基板210上,以密封該上晶片230、該下晶片220 與該底部填充膠250。 在一變化實施例中,如第7圖所示,該導流開槽21 5 之外側緣217係可為鋸齒狀,以顯露該些打線接指213。 詳細而言,該些打線接指213係可設置於該導流開槽2丄5 之外側緣217内。當填入該底部填充膠250之後,會自 然地流散至該導流開槽2 1 5内部,並填滿於該下晶片220 之底部。·由於該導流開槽2丨5係呈鋸齒狀,能與該底部 填充膠250之間產生較大的附著力,並縮小該底部填充 膠250的膠擴散面積,故可有效地防止該底部填充膠250 產生溢膠而造成汙染。在另一變化實施例中,如第8圖 所不,該導流開槽2 1 5係可為多個槽孔2 15 A ,每一槽孔 21 5A顯露至少一個凸塊接墊212與至少一個鄰近之打線 接指2 1 3。 以上所述’僅是本發明的較佳實施例而已,並非對本 發明作任何形式上的限制雖然本發明已以較佳實施例 12 201114008 揭露如上,然而並非用以限定本發明,任何熟悉本項技 術者,在不脫離本發明之技術範圍内,所作的任何簡單 修改、等效性變化與修飾’均仍屬於本發明的 内。 , 【圖式簡單說明】 第1圖:為習知的覆晶打線連接之背對背晶片組合構造 之戴面示意圖。 第2圖 為習知的覆晶打線連接之背對背晶片組合方法 之流程方塊圖。 第3圖 :據本發明之一具體實施例的覆晶打線連接之 者對背晶片組合方法之流程方塊圖。 第4A至4〇圖:依據本發明之一具體實施例在過程中之 元件截面示意圖。 第5圖=據本發明之一具體實施例的覆晶打線連接之 對背晶片組合構造之截面示意圖。 第6圖,據本發明之一具體實施例的覆晶打線連接之 背對背晶片組合構造繪示其基板與防銲層之上 視_ 〇 第7圖、依據本發明之一變化實施例的覆晶打線連接之 背蚜背晶片組合構造繪示其基板與防 視圖》 n 第8圖.依據本發明之另-變化實施例的覆晶打線連与 之背對f晶片Μ合構造繪示其基板與防鲜層4 上梘圖。 13 201114008 【主要元件符號說明】Procedure Refer to Figures 4A through 4 for the components to be represented at each step, as shown below. First, go to step 21. Referring to FIG. 4, a substrate 21 is provided. The upper surface φ 211 is provided with a plurality of bump pads and a plurality of wire fingers 2 1 3, and is numb with a ρ big name θ, β» — ^ Μ Zinc-proof layer 214 covers the upper surface 211, the solder resist layer 2 14 has a right-track ancient day μ, and a diversion slot 2 1 5, which simultaneously exposes the bump blocks 212 and the difference Souling skills, λ., , j, —α deep contact 213. In this embodiment, the flow guiding slot 215 can be a reciprocating or non-continuous ring of the far wall, the U.S. and the second, so that the solder resist layer 214 is squared under the lower wafer 22〇. The island block 21 6 (as shown in Fig. 6) maintains the gap between the flip chip and the substrate 21G. Therefore, in the subsequent filling process, the flow guiding groove 215 can guide the flow of the underfill on the periphery of the lower wafer 220 and restrict its outward diffusion. In the preferred embodiment, the solder resist layer 214 can partially cover the side of the wire bonding S 213. The "side" refers to the wire finger 213 away from the adjacent bump pad 212. One side. Go to Step 22. First, as in the 220th. Referring to FIG. 4C, as shown in FIG. 4B, the wafer is flip-chip bonded to the lower wafer 220 to 201114008. The lower wafer 220 has a plurality of bumps 221 bonded to the bumps. The pad 212 is electrically connected to the lower wafer 22 and the substrate 210. In the embodiment, the bumps 221 can be non-reflowed metal pillars, for example, gold pillars capable of withstanding high temperature and deformation. A copper post or the like is used to solve the problem of bridging short circuit in which the conventional bump is deformed by reflow and can maintain a fixed underfill gap after stacking and wire-bonding back-to-back. Specifically, the bumps 22 of the lower wafer 220 are connected to the bumps 212 of the substrate 21 by a recording material 270. In a preferred embodiment, as shown in FIG. 4, the bumps 22 of the lower wafer 22 may be attached to the solder 270' and then directly aligned to the substrate 21A. Go to Step 23. Referring to FIG. 4D, an upper wafer 230 is stacked back to back to the lower wafer 220. The upper wafer 23 has a plurality of pads 23 1 » In the embodiment, the size of the upper wafer 23 is not greater than The lower wafer 220 is sized and attached to the back side of the lower wafer 22 by a die attach layer 232. Specifically, the die layer 232 may not completely cover the back surface of the lower wafer 22 . In a preferred embodiment, the die layer 232 is formed on the back side of the upper wafer 230 or the back side of the lower wafer 22 in accordance with process requirements. Go to Step 24. Referring to FIG. 4, before the primer is filled, a plurality of bonding wires 240 are formed, and the bonding pads 231 and the bonding wires 213 are connected to electrically connect the upper wafer 23 and the substrate. 210. In a preferred embodiment, the bumps 221 can be #回焊合合金属柱, with a uniform flip-chip height and sufficient wire bonding 201114008, the building capacity can be in the absence of underfill , the upper wafer 2 3 〇 is wired. Go to Step 25. Referring to FIG. 4F, after the back-to-back «stacking and wire bonding steps described above, an underfill 25 is formed between the substrate 210 and the lower wafer 220. The underfill 250 seals the bumps 221 And filling the guiding groove 215 to cover the wire bonding fingers 213 and partially sealing the bonding wires 240. Preferably, since the flow guiding groove 215 can guide the underfill 250 to flow around the lower wafer _ 220, the underfill rubber 250 can be prevented from overflowing to other places and cause pollution. Finally, please refer to As shown in FIG. 4G, after the underfill 250 is formed, a gel 260 may be formed on the substrate 210 to seal the upper wafer 230, the lower wafer 220, and the underfill 250. In addition, the encapsulant 260 also covers the bonding wires 240 to further reinforce the bonding force of the bonding wires 240. The encapsulant 260 can be formed by a molding process. In the present invention, since the underfill 250 is filled into the flow guiding groove 215 after the bonding wires 240 are formed, the underfill 250 is filled in the lower wafer 220 to seal the holes. The bumps 221 and the bump pads 212 can cover the wire bonding fingers 213 and partially cover the wire bonding wires 24 by the guiding grooves 215. Therefore, by soldering and fixing the bonding wires 240 by the underfill 25 0, the solder joints of the bonding wires 240 can be protected to prevent the solder wires 240 from falling off from the soldering sites in a subsequent process. In addition, since the present invention completes the wire bonding step of the upper wafer 230 first, and then fills the underfill rubber 250, 10 201114008, it is possible to eliminate the need to reserve a glue width space for forming the underfill rubber 250 around the substrate. The structure in which the wire bonding #213 is covered by the underfill 250 does not have the problem of wire failure, and the reliability is reduced and the package size is effectively reduced. The present invention also discloses a back-to-back wafer assembly structure 2, which is formed by the above-described combination method, and is illustrated in Fig. 5. The flip chip bonded back-to-back wafer assembly structure mainly includes a substrate 210, a lower wafer 220, an upper wafer 230, a plurality of bonding wires 24A, and an underfill rubber 250. The upper surface 211 of the substrate 21 is provided with a plurality of bump pads 212 and a plurality of wire bonding fingers 213, and the upper surface 211 is covered by a anti-welding layer 214. The solder resist layer 214 has a flow guiding slot. 215, the bump pads 212 and the wire bonding fingers 213 are simultaneously exposed. In one embodiment, the flow guiding slot 215 can be a continuous or discontinuous ring. As shown in FIG. 6, the flow guiding groove 2丨5 is a discontinuous ring shape, so that the solder resist layer 214 is squared under the lower wafer 220 to form a solder resist island 216, which is advantageous for guiding. The underfill 25 流动 flows around the lower wafer 220 and does not easily spill over to other places to cause contamination. Moreover, the solder resist island 216 can be integrally joined by the solder resist layer 214 at non-continuous corners to avoid detachment. The lower wafer 220 is flip-chip bonded to the substrate 21A. The lower wafer 220 has a plurality of bumps 221 bonded to the bump pads 212 to electrically connect the lower wafer 220 and the substrate 21. . Specifically, the bumps 221 may be non-reflowed metal posts, and the bumps 22 i and the bump pads 212 are connected by solder. Further, 201114008, the upper wafer 230 is stacked back to back to the lower wafer 220. The upper wafer 230 has a plurality of pads 231. The bonding wires 240 are connected to the pads 231 and the bonding fingers 213. The upper wafer 230 and the substrate 210 are electrically connected. The underfill adhesive 25 is formed between the substrate 210 and the lower wafer 220. The underfill adhesive 250 seals the bumps 221 and fills the guiding slits 215 to cover the wire bonding fingers. 213 and partially seal the bonding wires 240. In addition, a glue 260 may be further formed on the substrate 210 to seal the upper wafer 230, the lower wafer 220 and the underfill 250. In a variant embodiment, as shown in FIG. 7, the outer edge 217 of the flow guiding slot 21 5 can be serrated to reveal the wire bonding fingers 213. In detail, the wire bonding fingers 213 can be disposed in the outer edge 217 of the flow guiding groove 2丄5. After the underfill 250 is filled, it naturally flows into the inside of the flow guiding groove 2 15 and fills the bottom of the lower wafer 220. Since the guide groove 2丨5 is serrated, a large adhesion can be generated between the underfill and the underfill 250, and the adhesive diffusion area of the underfill 250 is reduced, so that the bottom can be effectively prevented. Filler 250 produces spillage and contamination. In another variant embodiment, as shown in FIG. 8, the flow guiding slot 2 15 can be a plurality of slots 2 15 A , and each slot 21 5A exposes at least one bump pad 212 and at least A nearby wire is connected to 2 1 3 . The above description is only a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the invention has been disclosed above in the preferred embodiment 12 201114008, it is not intended to limit the invention, Any simple modifications, equivalent changes and modifications made by the skilled artisan will remain within the scope of the invention. [Simplified description of the drawings] Fig. 1 is a schematic view showing the wearable structure of a back-to-back wafer assembly structure of a conventional flip chip connection. Figure 2 is a flow block diagram of a conventional back-to-back wafer assembly method for flip chip bonding. Figure 3 is a block diagram showing the flow of a flip chip bonding method in accordance with an embodiment of the present invention. 4A to 4D are schematic cross-sectional views of elements in the process in accordance with an embodiment of the present invention. Fig. 5 is a schematic cross-sectional view showing a combined structure of a flip chip bonding according to a specific embodiment of the present invention. 6 is a diagram showing a back-to-back wafer assembly structure of a flip chip connection according to an embodiment of the present invention, showing a substrate and a solder resist layer thereon, and a flip chip according to a modified embodiment of the present invention. The back-and-back wafer combination structure of the wire connection shows the substrate and the anti-view view. FIG. 8 is a view showing the substrate and the flip-chip bonding structure according to another embodiment of the present invention. The anti-fresh layer 4 is on the map. 13 201114008 [Description of main component symbols]
步驟11 提供基板 步驟12 下晶片之覆晶接合 步驟13 底膠填充 步驟14 背對背堆疊上晶片 步轉1 5 上晶片之打線連接 步驟16 形成封膠體 步驟21 提供基板 步驟22 下晶片之覆晶接合 步驟23 背對背堆疊上晶片 步驟24 上晶片之打線連接 步驟25 底膠填充 步驟26 形成封膠體 100覆晶打線連接之背對背晶片組合構造 110基板 111 凸塊接墊 112 打 120 下晶片 130 上晶片 140 銲線 150 底 200 覆晶打線連接之背對 210 基板 211 上 213 打線接指 214 防 215A槽孔 216 防 220 下晶片 221 凸Step 11: Providing a flip chip bonding step of the wafer in step 12 of the substrate. Primer filling step 14 Wafer winding on the back-to-back stack 1 5 Wire bonding connection of the upper wafer Step 16 Forming the encapsulant Step 21 Providing the flip chip bonding step of the wafer in the step 22 of the substrate 23 Back-to-back stacking of wafers Step 24 Upper wafer bonding connection step 25 Primer filling step 26 Forming the encapsulant 100 flip-chip bonding back-to-back wafer assembly structure 110 substrate 111 bump pads 112 120 lower wafer 130 upper wafer 140 bonding wires 150 bottom 200 flip-chip connection back pair 210 substrate 211 on 213 wire connection finger 214 anti-215A slot 216 anti-220 lower wafer 221 convex
線接指 113防銲層 121凸塊 131 銲墊 部填充膠 160封膠體 背晶片組合構造 表面 212凸塊接墊 銲層 2 1 5導流開槽 鲜島塊 塊 14 201114008 230上晶片 240銲線 260封膠體 231銲墊 232黏晶層 2 5 0底部填充膠 270銲料Wire finger 113 solder mask 121 bump 131 pad pad filler 160 seal back wafer combination structure surface 212 bump pad solder layer 2 1 5 flow guiding slot fresh island block 14 201114008 230 wafer 240 wire bonding 260 seal 231 pad 232 adhesive layer 2 5 0 underfill 270 solder
1515
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TW098133489A TW201114008A (en) | 2009-10-02 | 2009-10-02 | Fabricating method of back-to-back chip assembly with flip-chip and wire-bonding connections and its structure |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI582916B (en) * | 2015-04-27 | 2017-05-11 | 南茂科技股份有限公司 | Multi chip package structure, wafer level chip package structure and manufacturing method thereof |
US10217702B2 (en) | 2012-06-21 | 2019-02-26 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming an embedded SoP fan-out package |
CN111498791A (en) * | 2020-04-30 | 2020-08-07 | 青岛歌尔微电子研究院有限公司 | Micro-electro-mechanical system packaging structure and manufacturing method thereof |
TWI812220B (en) * | 2021-08-30 | 2023-08-11 | 台灣積體電路製造股份有限公司 | Package structure and method for forming the same |
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2009
- 2009-10-02 TW TW098133489A patent/TW201114008A/en unknown
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Publication number | Priority date | Publication date | Assignee | Title |
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US10217702B2 (en) | 2012-06-21 | 2019-02-26 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming an embedded SoP fan-out package |
TWI582916B (en) * | 2015-04-27 | 2017-05-11 | 南茂科技股份有限公司 | Multi chip package structure, wafer level chip package structure and manufacturing method thereof |
US9653429B2 (en) | 2015-04-27 | 2017-05-16 | Chipmos Technologies Inc. | Multi-chip package structure having blocking structure, wafer level chip package structure having blocking structure and manufacturing process thereof |
CN111498791A (en) * | 2020-04-30 | 2020-08-07 | 青岛歌尔微电子研究院有限公司 | Micro-electro-mechanical system packaging structure and manufacturing method thereof |
TWI812220B (en) * | 2021-08-30 | 2023-08-11 | 台灣積體電路製造股份有限公司 | Package structure and method for forming the same |
US12014969B2 (en) | 2021-08-30 | 2024-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method for forming the same |
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